From nobody Mon Feb 9 11:33:48 2026 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 03BB9309F02; Fri, 31 Oct 2025 17:28:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.85.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761931696; cv=none; b=Fd4HC8j2DZk5zPoiHoWAbyZa0WUWiWfvZuE809AP0hNcLu64QvuruqKpfwBRs7SAGBeRGqjhHpnmAu4Bwfk91q45oBorAd1mOuJoTcddYasnrSxNe5CLfMjAiixTt08ymdRgyt40jRtcySEvrvh8jtXpiRaqSJuLsGOhD5v8MD8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761931696; c=relaxed/simple; bh=mX89eJtEOIjPqb5TiEEkJfU1H4NCQ2v2Gs/X8mYcvyA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=fF1Icdk8q23qbjBua/f3VdRYo5NSfeq8HncKxtFwIV8IxxC6LsyEB+j0FbymgEra4PgYZhTZ3LLg8jdxAQyXMpyYc3OqOZVmfrRfS1YcRUbWlE10MGzUk5xDhBsIGAjXSqZUXTMNgL7wpim0OCNcjQmP72JrDysa0OxMDNSziVE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=0mbD0KPT; arc=none smtp.client-ip=185.246.85.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="0mbD0KPT" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-03.galae.net (Postfix) with ESMTPS id 3706D4E4143C; Fri, 31 Oct 2025 17:28:12 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 0816960704; Fri, 31 Oct 2025 17:28:12 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 4C8051181800A; Fri, 31 Oct 2025 18:28:10 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1761931691; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=oHqEV/g7XFmkq0UzLPDeIwZV/fV2EtIfxTRhi9zC2G8=; b=0mbD0KPT1S8Q8Ue7MzvbGhBFxqwNL0QzL4nZpL1eCu8ne+RM5g7oXJQ81BjqMRAwz9sQNa 795Rb2z5UWU7jG0/k+L2EIsv6F3Np+Cu6v2t/7Vhk/DgLya4NtZpE3Cl4hEDJPGLqjtm7W qapdOmzpQLDdwqk2nJfCTlYNrqRkKSGnZbDJijg9cWfmyZn/e5bdworZewV8jnjaqOxIgf POLdpIv6/LQOZmCbIgvPc98ixwurVTCmdcZ/Ci2JrzwYeHKnYixxvaA3AoXnPm5fUbmftY QuVSl9E7peBkcYcaUV96Rmdlg5pfj1FecEqsfwtM+GVqJd0veK/WDajA5R5gqQ== From: Miquel Raynal Date: Fri, 31 Oct 2025 18:26:45 +0100 Subject: [PATCH 01/28] spi: spi-mem: Make the DTR command operation macro more suitable Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251031-winbond-v6-17-rc1-oddr-v1-1-be42de23ebf1@bootlin.com> References: <20251031-winbond-v6-17-rc1-oddr-v1-0-be42de23ebf1@bootlin.com> In-Reply-To: <20251031-winbond-v6-17-rc1-oddr-v1-0-be42de23ebf1@bootlin.com> To: Mark Brown , Richard Weinberger , Vignesh Raghavendra Cc: Tudor Ambarus , Pratyush Yadav , Thomas Petazzoni , Steam Lin , Santhosh Kumar K , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Miquel Raynal X-Mailer: b4 0.14.2 X-Last-TLS-Session-Version: TLSv1.3 In order to introduce DTR support in SPI NAND, a number of macros had to be created in the spi-mem layer. One of them remained unused at this point, SPI_MEM_DTR_OP_CMD. Being in the process of introducing octal DTR support now, experience shows that as-is the macro is not useful. In order to be really useful in octal DTR mode, the command opcode (one byte) must always be transmitted on the 8 data lines on both the rising and falling edge of the clock. Align the macro with the real needs by duplicating the opcode in the buffer and doubling its size. Signed-off-by: Miquel Raynal Reviewed-by: Tudor Ambarus --- include/linux/spi/spi-mem.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/include/linux/spi/spi-mem.h b/include/linux/spi/spi-mem.h index 82390712794c5a4dcef1319c19d74b77b6e1e724..81c9c7e793b6ab894675e0198d4= 12d84b8525c2e 100644 --- a/include/linux/spi/spi-mem.h +++ b/include/linux/spi/spi-mem.h @@ -20,10 +20,10 @@ .opcode =3D __opcode, \ } =20 -#define SPI_MEM_DTR_OP_CMD(__opcode, __buswidth) \ +#define SPI_MEM_DTR_OP_RPT_CMD(__opcode, __buswidth) \ { \ - .nbytes =3D 1, \ - .opcode =3D __opcode, \ + .nbytes =3D 2, \ + .opcode =3D __opcode | __opcode << 8, \ .buswidth =3D __buswidth, \ .dtr =3D true, \ } --=20 2.51.0 From nobody Mon Feb 9 11:33:48 2026 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 18711309EF4; Fri, 31 Oct 2025 17:28:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.171.202.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761931696; cv=none; b=kjPQGUN9MxA7e/SsRQW4pvMxEPMC6U60y+k+mhWhDEnD2AxtTuCKy0c4tUcqevUozdkQLoC5ZgOPsnIpxFLrgqOn5u5LSpCSMTUD+61aYMYEozvdrg6ECfPVDQDEPWZsnM1vDUqTgYVg8r7WkYQXqL60pqi2b+rUo15SexZqXtU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761931696; c=relaxed/simple; bh=Ll99UYQGGbu1eTDA6A1FqaugkPOuyw0NjihqNfzOht4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=b/W44wpc9Rq09xVo3QT7OwKtf/0ooBimGuzR1Lm1IPQaZLabhHz1+EQ+a0IYNTrQxCEeJ33Q1bmVyBT8NkStYT/QIZ6hx71SitJASbUmE96mvQyn7nCRMvqsOzQY2PL7F9IKyOo2sfuCFSu7ACXk7WfkLRiMDts7lUVsL3W6Wg4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=vvI4HU/g; arc=none smtp.client-ip=185.171.202.116 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="vvI4HU/g" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-04.galae.net (Postfix) with ESMTPS id B6C64C0E95A; Fri, 31 Oct 2025 17:27:52 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 477B860704; Fri, 31 Oct 2025 17:28:13 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 9AD781181800B; Fri, 31 Oct 2025 18:28:11 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1761931692; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=MQ2OSbA2wX7GpEne4dN3xY/3vjobyU3TcL9SV/CMJH8=; b=vvI4HU/grcaLTF2EgrEQqMZN9bpaAXWY9kU/ltufl/+RXDyc8UiYJSFIMOx971wR5+m+mr /QABjhbFEv4ePBgoNHVR2N6ddUH9WnFa5VkJJC9BJHzFGQU37w2MpQE8nPQXuSYqKVJxy2 /rJvT+fSBGXmFItqrda9qTNeJApBDcI5QZTN8G7TiTJ1D0+BpfSKYZACjPU3R4kDJG3DTA 21jLXXDmkN/Az90EQnn13I75WOxgp+gSlF7wrIQUAP0/vtsSZIt+qQPe5bJxz/VLZtu8yA D8erudFjW/vAZudPrgCii7M+0HwZXQyns2C3vYuwNhvQKW0ERiV9I44Z6wRMTg== From: Miquel Raynal Date: Fri, 31 Oct 2025 18:26:46 +0100 Subject: [PATCH 02/28] spi: spi-mem: Create a repeated address operation Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251031-winbond-v6-17-rc1-oddr-v1-2-be42de23ebf1@bootlin.com> References: <20251031-winbond-v6-17-rc1-oddr-v1-0-be42de23ebf1@bootlin.com> In-Reply-To: <20251031-winbond-v6-17-rc1-oddr-v1-0-be42de23ebf1@bootlin.com> To: Mark Brown , Richard Weinberger , Vignesh Raghavendra Cc: Tudor Ambarus , Pratyush Yadav , Thomas Petazzoni , Steam Lin , Santhosh Kumar K , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Miquel Raynal X-Mailer: b4 0.14.2 X-Last-TLS-Session-Version: TLSv1.3 In octal DTR mode, while the command opcode is *always* repeated, addresses may either be long enough to cover at least two bytes (in which case the existing macro works), or otherwise for single byte addresses, the byte must also be duplicated and sent twice: on each front of the clock. Create a macro for this common case. Signed-off-by: Miquel Raynal --- include/linux/spi/spi-mem.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/include/linux/spi/spi-mem.h b/include/linux/spi/spi-mem.h index 81c9c7e793b6ab894675e0198d412d84b8525c2e..e4db0924898ce5b17d2b6d42694= 95bb968db2871 100644 --- a/include/linux/spi/spi-mem.h +++ b/include/linux/spi/spi-mem.h @@ -43,6 +43,14 @@ .dtr =3D true, \ } =20 +#define SPI_MEM_DTR_OP_RPT_ADDR(__val, __buswidth) \ + { \ + .nbytes =3D 2, \ + .val =3D __val | __val << 8, \ + .buswidth =3D __buswidth, \ + .dtr =3D true, \ + } + #define SPI_MEM_OP_NO_ADDR { } =20 #define SPI_MEM_OP_DUMMY(__nbytes, __buswidth) \ --=20 2.51.0 From nobody Mon Feb 9 11:33:48 2026 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6A91E32143F for ; Fri, 31 Oct 2025 17:28:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.85.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761931699; cv=none; b=En/ebr73OX7zJtA4dYP3EsNI7fuKW1duiy2FKERgtdXNoeNCaH5Kfdl21oQoptbJ7MLSFI3rfienSI6Qtc7sKtrABtxxiv2XJUcJ2HvDnhm6MKRZOEI57JsFjICrjRJYBCXN14RVuPYnFGYUo+Qku4ZQLxzTEkYhX8IOfydR2NU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761931699; c=relaxed/simple; bh=D83udK3rkUXcu4imHlcUt7YguepdlZ70bccpPaQWIZI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=my5r59TJ+gnSrlQE7tz9OnoPIxVlnnOYkbq7G/SJmC40uvorMB74p8mFQ1AOiTjoloxSxV0kPSLYJTYLHwvw2B1Rp4Z3A7xy+G2hWTuHFBoV66aq2hBIR0bpg5w020VgE+azov10PfZcJo5haDPWdEljvKBI/xZ0ydDpYShlOXA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=jGqvtoEg; arc=none smtp.client-ip=185.246.85.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="jGqvtoEg" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-03.galae.net (Postfix) with ESMTPS id AB9554E41446; Fri, 31 Oct 2025 17:28:14 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 821FB60704; Fri, 31 Oct 2025 17:28:14 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id E31F011818466; Fri, 31 Oct 2025 18:28:12 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1761931693; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=Cd1E/3COSsZlzYl0nvZBhxDTb/M09zD1KDjitt7bE84=; b=jGqvtoEgGLnT2FvQCgdCkvNmT/ZZIAcSzIe3eAmD/fd49VWzBqmtx1ZAi5yAzMVIqGu+Kt MZXAKpC1Aak5V/prgzt8vtmQ+barP3b7XHNvOiYzGiLSqBnaZeHbahS0VBtk09usO596GW 8Wq/YPez7gHEO/lsb6JpLaqeey7Sq9cuJEPT5Ew9MwvbRss91lXdLeC2M4tkmRRz++6eGu wYzF4015/Ur39MQqXqOXpRz0GO20ZrzgZ2sbkYIZ0eO0tk+XaBrnWKMg8O+PrV1N3Jbsia +wuyzvp7gue4DN4KO6czR8S002NDd/KVa/uX9NFueknXukxZQ5vBjRqOJ3SCpQ== From: Miquel Raynal Date: Fri, 31 Oct 2025 18:26:47 +0100 Subject: [PATCH 03/28] spi: spi-mem: Limit octal DTR constraints to octal DTR situations Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251031-winbond-v6-17-rc1-oddr-v1-3-be42de23ebf1@bootlin.com> References: <20251031-winbond-v6-17-rc1-oddr-v1-0-be42de23ebf1@bootlin.com> In-Reply-To: <20251031-winbond-v6-17-rc1-oddr-v1-0-be42de23ebf1@bootlin.com> To: Mark Brown , Richard Weinberger , Vignesh Raghavendra Cc: Tudor Ambarus , Pratyush Yadav , Thomas Petazzoni , Steam Lin , Santhosh Kumar K , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Miquel Raynal X-Mailer: b4 0.14.2 X-Last-TLS-Session-Version: TLSv1.3 In this helper, any operation with a single DTR cycle (like 1S-1S-8D) is considered requiring a duplicated command opcode. This is wrong as this constraint only applies to octal DTR operations (8D-8D-8D). Narrow the application of this constraint to the concerned bus interface. Note: none of the possible XD-XD-XD pattern, with X being one of {1, 2, 4} would benefit from this check either as there is only in octal DTR mode that a single clock edge would be enough to transmit the full opcode. Make sure the constraint of expecting two bytes for the command is applied to the relevant bus interface. Signed-off-by: Miquel Raynal Reviewed-by: Tudor Ambarus --- drivers/spi/spi-mem.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c index 064b99204d9ac4bc233307609defa4fbbaf4534a..71e3eaf59df97cf6d04e6e67481= 0f12d037f384b 100644 --- a/drivers/spi/spi-mem.c +++ b/drivers/spi/spi-mem.c @@ -175,8 +175,19 @@ bool spi_mem_default_supports_op(struct spi_mem *mem, if (op->data.swap16 && !spi_mem_controller_is_capable(ctlr, swap16)) return false; =20 - if (op->cmd.nbytes !=3D 2) - return false; + /* Extra 8D-8D-8D limitations */ + if (op->cmd.dtr && op->cmd.buswidth =3D=3D 8) { + if (op->cmd.nbytes !=3D 2) + return false; + + if ((op->addr.nbytes % 2) || + (op->dummy.nbytes % 2) || + (op->data.nbytes % 2)) { + dev_err(&ctlr->dev, + "Even byte numbers not allowed in octal DTR operations\n"); + return false; + } + } } else { if (op->cmd.nbytes !=3D 1) return false; --=20 2.51.0 From nobody Mon Feb 9 11:33:48 2026 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 912E6322A28; Fri, 31 Oct 2025 17:28:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.85.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761931699; cv=none; b=bducprUWXlHp/+wnaIaNsA49mdF0F4MYTOeS+iP3Q4PTFHu+g4WrI34rUNkkP2XkerlKnbAl84++2i9f1ekWjwHyAp2Kc2qQILcyLU1evfhb0VgvhDiRIPytdLVughsLZMCLtBS5VUEXBwie4WDrFgc2X2R6xVtrBT3AN865wCI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761931699; c=relaxed/simple; bh=6b1R6dxIDY7X8ILKoHlOgTCQpmphyR+BSGWTVGsUv5o=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=kYaG39ptEG1RKdyBGbzymbHV9PcYtyr9Lu6KS+4k920t8oeCgqAzaouF0V53K0bVduNVyoqakTsSGnK3e1qNCAbsIkeR3QQFo5fLdKt6nPdJfM8JTHHogAnc/rPqCsheMEVwpAS+XWJhijgajX7gQRMklB6z9698MwZNkuDZJcE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=D9wXYUjt; arc=none smtp.client-ip=185.246.85.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="D9wXYUjt" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-03.galae.net (Postfix) with ESMTPS id 02EE84E41447; Fri, 31 Oct 2025 17:28:16 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id CD44060704; Fri, 31 Oct 2025 17:28:15 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 2C81511818007; Fri, 31 Oct 2025 18:28:14 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1761931695; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=IKJB1OCDKyocfIsQeZnwqEGivJeMVxUxOC96luFoKtE=; b=D9wXYUjtViGg2LSjRX1zVBy8SlAeLtMJ4AQoQdMrf24HMxh4/Zum5HZuq4v753py++w/P6 NkMglFwXcW08ph/fUybCqovGEX1FwAYKstCn7AX8FSCerG/CKLM8dHdBEkXhlVmETR29uQ uH+daxj1yBf3bLBiBFNqsFK23UFVa7A7y+b1BCRZBCmm6kxJ9O/Ur9Mhrjge7WP4lrfDHU FH0pB7YP8hpQW1AY9VU/63s8IHtYDObID+QgjSV4JWKDRa7OOHYpo/8d1gBHyKqNK76zk9 fuIJi7wW2ALGvZ5vNaiO1kqgpV27Sacmuo7VVoLfpPQ0sRxZT0a8s+tkTH4irQ== From: Miquel Raynal Date: Fri, 31 Oct 2025 18:26:48 +0100 Subject: [PATCH 04/28] mtd: spinand: Fix kernel doc Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251031-winbond-v6-17-rc1-oddr-v1-4-be42de23ebf1@bootlin.com> References: <20251031-winbond-v6-17-rc1-oddr-v1-0-be42de23ebf1@bootlin.com> In-Reply-To: <20251031-winbond-v6-17-rc1-oddr-v1-0-be42de23ebf1@bootlin.com> To: Mark Brown , Richard Weinberger , Vignesh Raghavendra Cc: Tudor Ambarus , Pratyush Yadav , Thomas Petazzoni , Steam Lin , Santhosh Kumar K , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Miquel Raynal X-Mailer: b4 0.14.2 X-Last-TLS-Session-Version: TLSv1.3 The @data buffer is 5 bytes, not 4, it has been extended for the need of devices with an extra ID bytes. Fixes: 34a956739d29 ("mtd: spinand: Add support for 5-byte IDs") Signed-off-by: Miquel Raynal Reviewed-by: Tudor Ambarus --- include/linux/mtd/spinand.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h index 927c10d7876958276a841a9f1278a74deeb89944..1c741145e49717169152854718f= 784e0e519ea92 100644 --- a/include/linux/mtd/spinand.h +++ b/include/linux/mtd/spinand.h @@ -287,7 +287,7 @@ struct spinand_device; =20 /** * struct spinand_id - SPI NAND id structure - * @data: buffer containing the id bytes. Currently 4 bytes large, but can + * @data: buffer containing the id bytes. Currently 5 bytes large, but can * be extended if required * @len: ID length */ --=20 2.51.0 From nobody Mon Feb 9 11:33:48 2026 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6FF4832AAB5 for ; Fri, 31 Oct 2025 17:28:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.171.202.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761931700; cv=none; b=iz6ggpMKnJ4pkm0vpiMAaUCgEdotPzq1ygOHaTF62N/xdn5WzzA6iwesJlPN/qh6afUQMGVCmux+Lh5HmZ3hTIiRlEDZUxtEFQe5nvnfoYr0Xemdeau5ZT99Bf9ScH+Atzy5f/UBMf+BJ0k55Lt6QdKy34r238eN/cYmJ1CS7LA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761931700; c=relaxed/simple; bh=IwvLnoMLU4bG0efPYGhK9TqWmO5drDF3tKFRE+kxHg0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=DI6MJIXrA1A/o4QHGvIRpnNbgnguILQaX7LPpOf6EqKYISaesC7QjkPc49nHeHjAS+WLMR/TeIwTUhsjSdRIflZ7bpE1IHVSHrZEBZ06myWXGLSsj+tzi3JXEaTbO7fZopNMkpXGQdf3l64CNAlAF0wNb9RsfIXUDAyTV3tfpYk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=ax0z1Sus; arc=none smtp.client-ip=185.171.202.116 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="ax0z1Sus" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-04.galae.net (Postfix) with ESMTPS id 7BB39C0E958; Fri, 31 Oct 2025 17:27:56 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 0BEC560704; Fri, 31 Oct 2025 17:28:17 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 7BD8F1181800A; Fri, 31 Oct 2025 18:28:15 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1761931696; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=q/W5OsQj0CIrKwA3ktIDzuIUiJU0LxRWvddRPMRjja0=; b=ax0z1SusDDh0MrZrcgp7sj0nbRFj0hAdv1pbn8SDe9RQAtVGGyU+wpaPFsihD0kt/edBdI RS2MsgDMgLyESKYt2qGjvCt7PHlxWC/4P9CixrJi5LbbLCVFQ/b4uZ3aBSd0Xe2DFU6eg0 o4p5X3pGqKQnKCfUbfdF/gxTjSwHQuEVjPjjv6v1oA01OnFEDTZKOpPi8JeUBwnZSPvUYt /rd+fbNp5KMioDzOz+QGrUh1w3ZarjCHh2mwB81avnBwwZk+VnEtl8N08ogN1UumlEsRPU GP3LboSkzgGu5XXpaBk3UGL+i70Ah36WDB2DaSZQq+7qpWCXYzoEeTcCpUsf7Q== From: Miquel Raynal Date: Fri, 31 Oct 2025 18:26:49 +0100 Subject: [PATCH 05/28] mtd: spinand: Add missing check Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251031-winbond-v6-17-rc1-oddr-v1-5-be42de23ebf1@bootlin.com> References: <20251031-winbond-v6-17-rc1-oddr-v1-0-be42de23ebf1@bootlin.com> In-Reply-To: <20251031-winbond-v6-17-rc1-oddr-v1-0-be42de23ebf1@bootlin.com> To: Mark Brown , Richard Weinberger , Vignesh Raghavendra Cc: Tudor Ambarus , Pratyush Yadav , Thomas Petazzoni , Steam Lin , Santhosh Kumar K , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Miquel Raynal X-Mailer: b4 0.14.2 X-Last-TLS-Session-Version: TLSv1.3 The update cache variant is mandatory, both read and write versions are being checked, but not this one. All chip drivers seem to implement this variant, so there should be no breakage. Signed-off-by: Miquel Raynal Reviewed-by: Tudor Ambarus --- The core has been like that since the begining, I do not think this patch should be backported, hence no Fixes tag. This barely qualifies as a fix anyway. --- drivers/mtd/nand/spi/core.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c index e748fa47ef7bffb7f443b37261d138b35eb4cc7a..9d4e82554dab07b676632155ae9= 4a706cf1177df 100644 --- a/drivers/mtd/nand/spi/core.c +++ b/drivers/mtd/nand/spi/core.c @@ -1431,6 +1431,9 @@ int spinand_match_and_init(struct spinand_device *spi= nand, =20 op =3D spinand_select_op_variant(spinand, info->op_variants.update_cache); + if (!op) + return -ENOTSUPP; + spinand->op_templates.update_cache =3D op; =20 return 0; --=20 2.51.0 From nobody Mon Feb 9 11:33:48 2026 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 292D8309EF4; Fri, 31 Oct 2025 17:28:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.84.56 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761931701; cv=none; b=oXI+Nco67l5fUswTzf+Rdbnz27SQqqiUYL0/foejA7+s/Vf9pLjGV7fB75L3pVnxUyiXnuPabQ7w9fplXpoQWUmm5hcy81mudw+4P0T8HCBH4MY8QdDFHPGB1PGZWkkUVhMxuwXPyiixDLuYQtFGITUzIT+ZAUM8C8cvo5rbhNQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761931701; c=relaxed/simple; bh=K31AbGtb6456muVxrIlDCmYc3I9jukAaBIq1mP4VODQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=A8CbGJjF8SG8qUyTBjfZq88fnuitxtzQ7W+I6tBucVKQk6qVugeaxmmtMxY3tDTMOYcTKaEbrHH+WyDOpws6nhxOsGgk0ha3x3WYrBlyrhorak1ltmwOt2WgN8TYbGVKA7k67scfmx98cJ6joI5OuM6H271EI1l0DY0HESZkfrk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=df5R4CGM; arc=none smtp.client-ip=185.246.84.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="df5R4CGM" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-02.galae.net (Postfix) with ESMTPS id 99B1B1A17C4; Fri, 31 Oct 2025 17:28:18 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 6ABFC60704; Fri, 31 Oct 2025 17:28:18 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id A31A11181800B; Fri, 31 Oct 2025 18:28:16 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1761931697; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=mLluG8puW16khAmDrjVJJH9/M5suelfU9smry8s1GdM=; b=df5R4CGMI5w+5S/Z1v/u2Gi7kUW5QflghJ+N20juWOd0iMxYA/KwG0RmviiS7FBA35ykd4 JM1hMETT2xQzj4vPBWlKZD4N8OXTZW7OhalguaA0xHUVKrpWpgaZgWD+O5EQbxLElZkLHE vKHwYZH49VuwvZY+tDHIxm98v62fdtKzZujGEIIN/JbQkCRlKIXnTHpBABlrG0QJn31rfZ Pv+ZY3WkzYtRn+1Pwao/z6tSyPNlNPe7iYCBxjFHPSvVLmIVoUNOXC/GCMjALPjWxmAuvc /IAN5400v4+OmsI3z9aPYui3NJoyhfP3UD/Z5p3cvCW+uip32lvV3cm1C3cIZQ== From: Miquel Raynal Date: Fri, 31 Oct 2025 18:26:50 +0100 Subject: [PATCH 06/28] mtd: spinand: Remove stale definitions Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251031-winbond-v6-17-rc1-oddr-v1-6-be42de23ebf1@bootlin.com> References: <20251031-winbond-v6-17-rc1-oddr-v1-0-be42de23ebf1@bootlin.com> In-Reply-To: <20251031-winbond-v6-17-rc1-oddr-v1-0-be42de23ebf1@bootlin.com> To: Mark Brown , Richard Weinberger , Vignesh Raghavendra Cc: Tudor Ambarus , Pratyush Yadav , Thomas Petazzoni , Steam Lin , Santhosh Kumar K , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Miquel Raynal X-Mailer: b4 0.14.2 X-Last-TLS-Session-Version: TLSv1.3 SPI NAND command values are directly included in the macros defining the ops. These are stale definitions, they are unused so drop them. Signed-off-by: Miquel Raynal Reviewed-by: Tudor Ambarus --- include/linux/mtd/spinand.h | 6 ------ 1 file changed, 6 deletions(-) diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h index 1c741145e49717169152854718f784e0e519ea92..731a3156b2577032e1f9a767044= f94aa262c3ec0 100644 --- a/include/linux/mtd/spinand.h +++ b/include/linux/mtd/spinand.h @@ -232,12 +232,6 @@ SPI_MEM_OP_NO_DUMMY, \ SPI_MEM_OP_DATA_OUT(len, buf, 8)) =20 -/** - * Standard SPI NAND flash commands - */ -#define SPINAND_CMD_PROG_LOAD_X4 0x32 -#define SPINAND_CMD_PROG_LOAD_RDM_DATA_X4 0x34 - /* feature register */ #define REG_BLOCK_LOCK 0xa0 #define BL_ALL_UNLOCKED 0x00 --=20 2.51.0 From nobody Mon Feb 9 11:33:48 2026 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 86D903164BC for ; Fri, 31 Oct 2025 17:28:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.84.56 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761931703; cv=none; b=AssrWpxDDdJe8sGl1n9aXYpTdYWyXbLRLEkj/LFtAH2FxyREVBGDRkC4hDEZV1gOq8yIPiXQkIaSCxJa/kuei3Nle5Cu+HJvIlqI8Eujo2ynj+s9/Ci5x2HMhGk0FYlvI2rQtKthj+/xSKzt8hjEH6frSqHgjo7kdT9JY42mVw0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761931703; c=relaxed/simple; bh=IpPFvCzVGIPQ3xyoVo+Bvmwy5JdjUpewmsRAMzScicI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ik/5AIqY39dHLtLb8qzytrM6SJ0FMR+GYdzVDcQ7upA+FZ90AsBw/1GJPIc0DdqnTEgCQulszYuqsIMhNJNsbN2zRv73czmcvWMt8Lr1SUWJBTlnA7KDJIpTjoOdqH45O37Z8saT9fR4fAmvv7Cq9RdmA3OYBWAeC33s4l0B1GE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=qPsj2AdS; arc=none smtp.client-ip=185.246.84.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="qPsj2AdS" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-02.galae.net (Postfix) with ESMTPS id 001311A17C2; Fri, 31 Oct 2025 17:28:19 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id C3C1260704; Fri, 31 Oct 2025 17:28:19 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 0E3CB11818466; Fri, 31 Oct 2025 18:28:17 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1761931699; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=YMq2Oulid+/ZQVRpF4JkTbc5d0mnCd8cN+kKX2PYD7Y=; b=qPsj2AdSwefrttBWTwJ1ayqmRCPISo0cpeRtPiZQNG94IkZbwRoSwb56jEVqoTDePSuj/v dqx8EmWFclZbh9bkRk2OcjdD+lz96eweN42MuDNrsCQd/de+kbrc+/TeyAezKeHPg0Q6Xy PGy23q9AfTRxd9oPCpXyiB21cPRBdpPihzKYAjkgkvut03QlsQ1PwZi9zHUZ+ocJbrAHG8 xgyevXzS5Qw4oBNf5Z8WlZ7OYOge6f7kv8rBexL59N1xTdkkkSsx8gT+ohadd675AXODwK 8Iqcaz7E4p8JJdehRIpMuGkGfXFhzPaLWY9pghjLT8YzwWU8rFLcXSuKoxzOyw== From: Miquel Raynal Date: Fri, 31 Oct 2025 18:26:51 +0100 Subject: [PATCH 07/28] mtd: spinand: Use standard return values Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251031-winbond-v6-17-rc1-oddr-v1-7-be42de23ebf1@bootlin.com> References: <20251031-winbond-v6-17-rc1-oddr-v1-0-be42de23ebf1@bootlin.com> In-Reply-To: <20251031-winbond-v6-17-rc1-oddr-v1-0-be42de23ebf1@bootlin.com> To: Mark Brown , Richard Weinberger , Vignesh Raghavendra Cc: Tudor Ambarus , Pratyush Yadav , Thomas Petazzoni , Steam Lin , Santhosh Kumar K , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Miquel Raynal X-Mailer: b4 0.14.2 X-Last-TLS-Session-Version: TLSv1.3 Replace -ENOTSUPP with -EOPNOTSUPP which is as relevant in this case but is standard. Signed-off-by: Miquel Raynal Reviewed-by: Tudor Ambarus --- drivers/mtd/nand/spi/core.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c index 9d4e82554dab07b676632155ae94a706cf1177df..e6ff5706a65bdd300ce59458467= 49afa59b2f12a 100644 --- a/drivers/mtd/nand/spi/core.c +++ b/drivers/mtd/nand/spi/core.c @@ -1418,28 +1418,28 @@ int spinand_match_and_init(struct spinand_device *s= pinand, op =3D spinand_select_op_variant(spinand, info->op_variants.read_cache); if (!op) - return -ENOTSUPP; + return -EOPNOTSUPP; =20 spinand->op_templates.read_cache =3D op; =20 op =3D spinand_select_op_variant(spinand, info->op_variants.write_cache); if (!op) - return -ENOTSUPP; + return -EOPNOTSUPP; =20 spinand->op_templates.write_cache =3D op; =20 op =3D spinand_select_op_variant(spinand, info->op_variants.update_cache); if (!op) - return -ENOTSUPP; + return -EOPNOTSUPP; =20 spinand->op_templates.update_cache =3D op; =20 return 0; } =20 - return -ENOTSUPP; + return -EOPNOTSUPP; } =20 static int spinand_detect(struct spinand_device *spinand) --=20 2.51.0 From nobody Mon Feb 9 11:33:48 2026 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C28F134CFA5; Fri, 31 Oct 2025 17:28:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.84.56 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761931704; cv=none; b=T4A6MhGjbtWKy8jTAKvElGPPmSvzMgR30puEydCJVObUL44qTO2qPOK/4mK4r9i5WbOo7OcE5FTx0rgSJFcueRju7hQwmUwH3TTo538cjIoLMjVU/Nn43Cf1fNzU/wttMnyTAQZEl96e7haejB5TJY7kdBQjW462I1w7qAWh1CY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761931704; c=relaxed/simple; bh=iyjcEJyUqoqMyrWzdnye4sanfH8zMTxSk+V2GY78ZOo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; 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Fri, 31 Oct 2025 17:28:21 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 5C31511818007; Fri, 31 Oct 2025 18:28:19 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1761931700; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=PvBKutAwa1m2PL4YRCKjf/u7MU2Ov+gYd6bI20RerpY=; b=s1KgbqGz4/ZSWyUN1Ji1Eg3iiyiO0nzxSSzCF4nggAHM01fvofsP1WXeqebUI7C6nxl6KE 0PALXDANdgKDBzIz1+sL+x1DYlkZvlSm1QBDeVdX2CBQe52BjZoXyVqSUdMAXfBD6kXZEi KzsdYPJblUz0fZy1YcypChw+Wo9ME3E8XLYCeyS/ID1xsgqBmD3+4Qdk4qp+szp9vKB5KK b19sQmsrbyKo4MA41tF2I0+uiphGi1CuGjKEq3nzPE892nq9a+e3yDdWHlAOWiM8iBtxQ6 Ay/pYSOZ8FoPVSm5GHhjARc9bCLpDL0VQ6QnrYkjE3+xzPMnqOBH74d1X/Y70w== From: Miquel Raynal Date: Fri, 31 Oct 2025 18:26:52 +0100 Subject: [PATCH 08/28] mtd: spinand: Decouple write enable and write disable operations Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251031-winbond-v6-17-rc1-oddr-v1-8-be42de23ebf1@bootlin.com> References: <20251031-winbond-v6-17-rc1-oddr-v1-0-be42de23ebf1@bootlin.com> In-Reply-To: <20251031-winbond-v6-17-rc1-oddr-v1-0-be42de23ebf1@bootlin.com> To: Mark Brown , Richard Weinberger , Vignesh Raghavendra Cc: Tudor Ambarus , Pratyush Yadav , Thomas Petazzoni , Steam Lin , Santhosh Kumar K , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Miquel Raynal X-Mailer: b4 0.14.2 X-Last-TLS-Session-Version: TLSv1.3 In order to introduce templates for all operations and not only for page helpers (in order to introduce octal DDR support), decouple the WR_EN and WR_DIS operations into two separate macros. Adapt the callers accordingly. There is no functional change. Signed-off-by: Miquel Raynal Reviewed-by: Tudor Ambarus --- drivers/mtd/nand/spi/core.c | 2 +- drivers/mtd/nand/spi/esmt.c | 2 +- drivers/mtd/nand/spi/micron.c | 2 +- include/linux/mtd/spinand.h | 10 ++++++++-- 4 files changed, 11 insertions(+), 5 deletions(-) diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c index e6ff5706a65bdd300ce5945846749afa59b2f12a..d215cefcba3f37057a2ba036d86= ae6638885a7f3 100644 --- a/drivers/mtd/nand/spi/core.c +++ b/drivers/mtd/nand/spi/core.c @@ -362,7 +362,7 @@ static void spinand_ondie_ecc_save_status(struct nand_d= evice *nand, u8 status) =20 int spinand_write_enable_op(struct spinand_device *spinand) { - struct spi_mem_op op =3D SPINAND_WR_EN_DIS_1S_0_0_OP(true); + struct spi_mem_op op =3D SPINAND_WR_EN_1S_0_0_OP; =20 return spi_mem_exec_op(spinand->spimem, &op); } diff --git a/drivers/mtd/nand/spi/esmt.c b/drivers/mtd/nand/spi/esmt.c index 9a9325c0bc49726b0421d77680684ae07560bf2e..f880c3b15ceab14676ab65f3d9e= 8530c713528c8 100644 --- a/drivers/mtd/nand/spi/esmt.c +++ b/drivers/mtd/nand/spi/esmt.c @@ -137,7 +137,7 @@ static int f50l1g41lb_user_otp_info(struct spinand_devi= ce *spinand, size_t len, static int f50l1g41lb_otp_lock(struct spinand_device *spinand, loff_t from, size_t len) { - struct spi_mem_op write_op =3D SPINAND_WR_EN_DIS_1S_0_0_OP(true); + struct spi_mem_op write_op =3D SPINAND_WR_EN_1S_0_0_OP; struct spi_mem_op exec_op =3D SPINAND_PROG_EXEC_1S_1S_0_OP(0); u8 status; int ret; diff --git a/drivers/mtd/nand/spi/micron.c b/drivers/mtd/nand/spi/micron.c index a49d7cb6a96da701ee981e677f414c57eabb2cec..b8130e04e8e798519ad38c58b55= 69935c1a447a2 100644 --- a/drivers/mtd/nand/spi/micron.c +++ b/drivers/mtd/nand/spi/micron.c @@ -251,7 +251,7 @@ static int mt29f2g01abagd_user_otp_info(struct spinand_= device *spinand, static int mt29f2g01abagd_otp_lock(struct spinand_device *spinand, loff_t = from, size_t len) { - struct spi_mem_op write_op =3D SPINAND_WR_EN_DIS_1S_0_0_OP(true); + struct spi_mem_op write_op =3D SPINAND_WR_EN_1S_0_0_OP; struct spi_mem_op exec_op =3D SPINAND_PROG_EXEC_1S_1S_0_OP(0); u8 status; int ret; diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h index 731a3156b2577032e1f9a767044f94aa262c3ec0..8c490a03b2e000bc18d692d72cf= d20b151db023c 100644 --- a/include/linux/mtd/spinand.h +++ b/include/linux/mtd/spinand.h @@ -26,8 +26,14 @@ SPI_MEM_OP_NO_DUMMY, \ SPI_MEM_OP_NO_DATA) =20 -#define SPINAND_WR_EN_DIS_1S_0_0_OP(enable) \ - SPI_MEM_OP(SPI_MEM_OP_CMD((enable) ? 0x06 : 0x04, 1), \ +#define SPINAND_WR_EN_1S_0_0_OP \ + SPI_MEM_OP(SPI_MEM_OP_CMD(0x06, 1), \ + SPI_MEM_OP_NO_ADDR, \ + SPI_MEM_OP_NO_DUMMY, \ + SPI_MEM_OP_NO_DATA) + +#define SPINAND_WR_DIS_1S_0_0_OP \ + SPI_MEM_OP(SPI_MEM_OP_CMD(0x04, 1), \ SPI_MEM_OP_NO_ADDR, \ SPI_MEM_OP_NO_DUMMY, \ SPI_MEM_OP_NO_DATA) --=20 2.51.0 From nobody Mon Feb 9 11:33:48 2026 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1013434D4DB; Fri, 31 Oct 2025 17:28:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.171.202.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761931706; cv=none; b=uCfQU43iI0umSvA3ItjCB3WRWKeSS64PGvG/rVCcxfDbaruGzPChcZzL0EtOXfw2MhNZhJJmb/ESrXTmRM9Gv3+MScOdyBj45kGymZ5k+gxiNtyPgP7whyQHR7PzrPfgWjWkTwJ+gOh8Hrz7n+gMOTsT2c/XRyKWkKVV5wjuqQ4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761931706; c=relaxed/simple; bh=qdvthG7Vi7hQFdOvT+ivnIhyG3J4sTYCjUbLhGubPo8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=RLYDFmoAfcwWbdDUBAUDKloG7YGwKZPMOvHrdViLZ6Cg91rMDiaqhCBMhvEF0HemmejfGKJjfnT5uRH+Va6BWqUMWdCT9j8rMX5Hydm9uBmO0heB3BE5MX0S7HIM49x9acTX0HM/dMbMibw5TsEKYIx2N4pbOnX/ZqZsU8Ilr/o= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=O0kyOun4; arc=none smtp.client-ip=185.171.202.116 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="O0kyOun4" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-04.galae.net (Postfix) with ESMTPS id 0167DC0E959; Fri, 31 Oct 2025 17:28:02 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 8608B60704; Fri, 31 Oct 2025 17:28:22 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id BC3CF1181800A; Fri, 31 Oct 2025 18:28:20 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1761931701; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=NIIPE8AFPeP5osbw/f33KrhgIWBKR4ROKxE3MEZAWO4=; b=O0kyOun4w5hAZ8dUflG9ocF/UJW2rYVknHSF6VfeevincXgycB8NWqZhAj4jNnAbpCEyOA ZJRXnSMsEMvCNt9u3lZnQJVjymWb4X/DPpAu8L/tqaFQrNAt51xKKeJ88uZCEC6aLaJp6T 1cgBsoVejLS1KbV+vlSYIdaVpAn0VHnKCdAYpWjsyRIK4BZ4O8Bxr2tuNVGaBbWf7Dny7Z kB103sX6a/vt4fm9DhV5kbbqdS3ToPhPI6ROtw/7DfTVcz1/hq4wINc+Ijyun1H1IC0Zq5 JIb/xiYh0B80oxny3noEK+e5+6U03YxggSFittqhj6S1KU7nWy8lQI+Pr0rk5Q== From: Miquel Raynal Date: Fri, 31 Oct 2025 18:26:53 +0100 Subject: [PATCH 09/28] mtd: spinand: Create an array of operation templates Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251031-winbond-v6-17-rc1-oddr-v1-9-be42de23ebf1@bootlin.com> References: <20251031-winbond-v6-17-rc1-oddr-v1-0-be42de23ebf1@bootlin.com> In-Reply-To: <20251031-winbond-v6-17-rc1-oddr-v1-0-be42de23ebf1@bootlin.com> To: Mark Brown , Richard Weinberger , Vignesh Raghavendra Cc: Tudor Ambarus , Pratyush Yadav , Thomas Petazzoni , Steam Lin , Santhosh Kumar K , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Miquel Raynal X-Mailer: b4 0.14.2 X-Last-TLS-Session-Version: TLSv1.3 Currently, the SPI NAND core implementation directly calls macros to get the various operations in shape. These macros are specific to the bus interface, currently only supporting the single SDR interface (any command following the 1S-XX-XX pattern). Introducing support for other bus interfaces (such as octal DTR) would mean that every user of these macros should become aware of the current bus interface and act accordingly, picking up and adapting to the current configuration. This would add quite a bit of boilerplate, be repetitive as well as error prone in case we miss one occurrence. Instead, let's create a table with all SPI NAND memory operations that are currently supported. We initialize them with the same single SDR _OP macros as before. This opens the possibility for users of the individual macros to make use of these templates instead. This way, when we will add another bus interface, we can just switch to another set of templates and all users will magically fill in their spi_mem_op structures with the correct ops. The existing read, write and update cache variants are also moved in this template array, which is barely noticeable by callers as we also add a structure member pointing to it. Signed-off-by: Miquel Raynal Reviewed-by: Tudor Ambarus --- drivers/mtd/nand/spi/core.c | 38 +++++++++++++++++++++++++++---------- drivers/mtd/nand/spi/winbond.c | 4 ++-- include/linux/mtd/spinand.h | 43 +++++++++++++++++++++++++++++++++-----= ---- 3 files changed, 64 insertions(+), 21 deletions(-) diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c index d215cefcba3f37057a2ba036d86ae6638885a7f3..11d3b28a14339282360a5ef12be= 715e532105e73 100644 --- a/drivers/mtd/nand/spi/core.c +++ b/drivers/mtd/nand/spi/core.c @@ -184,9 +184,9 @@ static int spinand_init_quad_enable(struct spinand_devi= ce *spinand) if (!(spinand->flags & SPINAND_HAS_QE_BIT)) return 0; =20 - if (spinand->op_templates.read_cache->data.buswidth =3D=3D 4 || - spinand->op_templates.write_cache->data.buswidth =3D=3D 4 || - spinand->op_templates.update_cache->data.buswidth =3D=3D 4) + if (spinand->op_templates->read_cache->data.buswidth =3D=3D 4 || + spinand->op_templates->write_cache->data.buswidth =3D=3D 4 || + spinand->op_templates->update_cache->data.buswidth =3D=3D 4) enable =3D true; =20 return spinand_upd_cfg(spinand, CFG_QUAD_ENABLE, @@ -1154,7 +1154,7 @@ static int spinand_create_dirmap(struct spinand_devic= e *spinand, info.offset =3D plane << fls(nand->memorg.pagesize); =20 info.length =3D nanddev_page_size(nand) + nanddev_per_page_oobsize(nand); - info.op_tmpl =3D *spinand->op_templates.update_cache; + info.op_tmpl =3D *spinand->op_templates->update_cache; desc =3D devm_spi_mem_dirmap_create(&spinand->spimem->spi->dev, spinand->spimem, &info); if (IS_ERR(desc)) @@ -1162,7 +1162,7 @@ static int spinand_create_dirmap(struct spinand_devic= e *spinand, =20 spinand->dirmaps[plane].wdesc =3D desc; =20 - info.op_tmpl =3D *spinand->op_templates.read_cache; + info.op_tmpl =3D *spinand->op_templates->read_cache; desc =3D spinand_create_rdesc(spinand, &info); if (IS_ERR(desc)) return PTR_ERR(desc); @@ -1177,7 +1177,7 @@ static int spinand_create_dirmap(struct spinand_devic= e *spinand, } =20 info.length =3D nanddev_page_size(nand) + nanddev_per_page_oobsize(nand); - info.op_tmpl =3D *spinand->op_templates.update_cache; + info.op_tmpl =3D *spinand->op_templates->update_cache; info.op_tmpl.data.ecc =3D true; desc =3D devm_spi_mem_dirmap_create(&spinand->spimem->spi->dev, spinand->spimem, &info); @@ -1186,7 +1186,7 @@ static int spinand_create_dirmap(struct spinand_devic= e *spinand, =20 spinand->dirmaps[plane].wdesc_ecc =3D desc; =20 - info.op_tmpl =3D *spinand->op_templates.read_cache; + info.op_tmpl =3D *spinand->op_templates->read_cache; info.op_tmpl.data.ecc =3D true; desc =3D spinand_create_rdesc(spinand, &info); if (IS_ERR(desc)) @@ -1322,6 +1322,22 @@ static void spinand_manufacturer_cleanup(struct spin= and_device *spinand) return spinand->manufacturer->ops->cleanup(spinand); } =20 +static void spinand_init_ssdr_templates(struct spinand_device *spinand) +{ + struct spinand_mem_ops *tmpl =3D &spinand->ssdr_op_templates; + + tmpl->reset =3D (struct spi_mem_op)SPINAND_RESET_1S_0_0_OP; + tmpl->readid =3D (struct spi_mem_op)SPINAND_READID_1S_1S_1S_OP(0, 0, NULL= , 0); + tmpl->wr_en =3D (struct spi_mem_op)SPINAND_WR_EN_1S_0_0_OP; + tmpl->wr_dis =3D (struct spi_mem_op)SPINAND_WR_DIS_1S_0_0_OP; + tmpl->set_feature =3D (struct spi_mem_op)SPINAND_SET_FEATURE_1S_1S_1S_OP(= 0, NULL); + tmpl->get_feature =3D (struct spi_mem_op)SPINAND_GET_FEATURE_1S_1S_1S_OP(= 0, NULL); + tmpl->blk_erase =3D (struct spi_mem_op)SPINAND_BLK_ERASE_1S_1S_0_OP(0); + tmpl->page_read =3D (struct spi_mem_op)SPINAND_PAGE_READ_1S_1S_0_OP(0); + tmpl->prog_exec =3D (struct spi_mem_op)SPINAND_PROG_EXEC_1S_1S_0_OP(0); + spinand->op_templates =3D &spinand->ssdr_op_templates; +} + static const struct spi_mem_op * spinand_select_op_variant(struct spinand_device *spinand, const struct spinand_op_variants *variants) @@ -1420,21 +1436,21 @@ int spinand_match_and_init(struct spinand_device *s= pinand, if (!op) return -EOPNOTSUPP; =20 - spinand->op_templates.read_cache =3D op; + spinand->ssdr_op_templates.read_cache =3D op; =20 op =3D spinand_select_op_variant(spinand, info->op_variants.write_cache); if (!op) return -EOPNOTSUPP; =20 - spinand->op_templates.write_cache =3D op; + spinand->ssdr_op_templates.write_cache =3D op; =20 op =3D spinand_select_op_variant(spinand, info->op_variants.update_cache); if (!op) return -EOPNOTSUPP; =20 - spinand->op_templates.update_cache =3D op; + spinand->ssdr_op_templates.update_cache =3D op; =20 return 0; } @@ -1549,6 +1565,8 @@ static int spinand_init(struct spinand_device *spinan= d) if (!spinand->scratchbuf) return -ENOMEM; =20 + spinand_init_ssdr_templates(spinand); + ret =3D spinand_detect(spinand); if (ret) goto err_free_bufs; diff --git a/drivers/mtd/nand/spi/winbond.c b/drivers/mtd/nand/spi/winbond.c index 4870b2d5edb2a1f8081b87bbe9de549c73272d7c..d5799c2df06520de6cb5c5b771c= eeb9d11ddf1fb 100644 --- a/drivers/mtd/nand/spi/winbond.c +++ b/drivers/mtd/nand/spi/winbond.c @@ -291,7 +291,7 @@ static int w25n0xjw_hs_cfg(struct spinand_device *spina= nd) u8 sr4; int ret; =20 - op =3D spinand->op_templates.read_cache; + op =3D spinand->op_templates->read_cache; if (op->cmd.dtr || op->addr.dtr || op->dummy.dtr || op->data.dtr) hs =3D false; else if (op->cmd.buswidth =3D=3D 1 && op->addr.buswidth =3D=3D 1 && @@ -355,7 +355,7 @@ static int w35n0xjw_vcr_cfg(struct spinand_device *spin= and) u8 io_mode; int ret; =20 - op =3D spinand->op_templates.read_cache; + op =3D spinand->op_templates->read_cache; =20 single =3D (op->cmd.buswidth =3D=3D 1 && op->addr.buswidth =3D=3D 1 && op= ->data.buswidth =3D=3D 1); dtr =3D (op->cmd.dtr || op->addr.dtr || op->data.dtr); diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h index 8c490a03b2e000bc18d692d72cfd20b151db023c..4afebaf5f0195b9bc617ea1f125= f637f76fff9f8 100644 --- a/include/linux/mtd/spinand.h +++ b/include/linux/mtd/spinand.h @@ -598,6 +598,36 @@ struct spinand_dirmap { struct spi_mem_dirmap_desc *rdesc_ecc; }; =20 +/** + * struct spinand_mem_ops - SPI NAND memory operations + * @reset: reset op template + * @readid: read ID op template + * @wr_en: write enable op template + * @wr_dis: write disable op template + * @set_feature: set feature op template + * @get_feature: get feature op template + * @blk_erase: blk erase op template + * @page_read: page read op template + * @prog_exec: prog exec op template + * @read_cache: read cache op template + * @write_cache: write cache op template + * @update_cache: update cache op template + */ +struct spinand_mem_ops { + struct spi_mem_op reset; + struct spi_mem_op readid; + struct spi_mem_op wr_en; + struct spi_mem_op wr_dis; + struct spi_mem_op set_feature; + struct spi_mem_op get_feature; + struct spi_mem_op blk_erase; + struct spi_mem_op page_read; + struct spi_mem_op prog_exec; + const struct spi_mem_op *read_cache; + const struct spi_mem_op *write_cache; + const struct spi_mem_op *update_cache; +}; + /** * struct spinand_device - SPI NAND device instance * @base: NAND device instance @@ -605,10 +635,8 @@ struct spinand_dirmap { * @lock: lock used to serialize accesses to the NAND * @id: NAND ID as returned by READ_ID * @flags: NAND flags - * @op_templates: various SPI mem op templates - * @op_templates.read_cache: read cache op template - * @op_templates.write_cache: write cache op template - * @op_templates.update_cache: update cache op template + * @ssdr_op_templates: Templates for all single SDR SPI mem operations + * @op_templates: Templates for all SPI mem operations * @select_target: select a specific target/die. Usually called before sen= ding * a command addressing a page or an eraseblock embedded in * this die. Only required if your chip exposes several dies @@ -642,11 +670,8 @@ struct spinand_device { struct spinand_id id; u32 flags; =20 - struct { - const struct spi_mem_op *read_cache; - const struct spi_mem_op *write_cache; - const struct spi_mem_op *update_cache; - } op_templates; + struct spinand_mem_ops ssdr_op_templates; + struct spinand_mem_ops *op_templates; =20 struct spinand_dirmap *dirmaps; =20 --=20 2.51.0 From nobody Mon Feb 9 11:33:48 2026 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3786C34D903 for ; Fri, 31 Oct 2025 17:28:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.171.202.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761931707; cv=none; b=LWPSBSa+zhCGME8kv1L4W/OZQ+5AR7Nb5hT6CXlQ/ivJ10STyO9Ciq71MmtCg1ynhyFALwqW9wka7Ydos4lN61HWc5D5MSKv2hIUZGgtHKS1kVxzmZSm0WtdGn83cyDi1hIDrDoffc+TMFoIX8UgRmr2N/qnjT5hYQ0hetrnJtI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761931707; c=relaxed/simple; bh=xgvo07V7Brp2WxQfVnrWJI348BV1HZRykOS2pUIwBKs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=BaZ9/uTZSgYIrYPHTYnvY8IN3KyLOIAdHqtSQU0yZHAxZMkcq6voPh5rIxjkMnT35O3/uE6UPIp8yV3gLKAWKm/OYHQXjSmGbYzE/a1hRrDZClCn2p+gS8agI60uPw38SuYvT5Eh62K1dBGQCOorutZTNEbOyOkXji+5KuHNL+0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=cNsTa4ZS; arc=none smtp.client-ip=185.171.202.116 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="cNsTa4ZS" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-04.galae.net (Postfix) with ESMTPS id 4F268C0E95A; Fri, 31 Oct 2025 17:28:03 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id D311C60704; Fri, 31 Oct 2025 17:28:23 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 2DCCC11818466; Fri, 31 Oct 2025 18:28:22 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1761931703; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=BxTI4mTo3h5fG4XfRzUyD/ZIDWRXmGLam2+xDEWaA4E=; b=cNsTa4ZSyBQampFuf7ovFnSu6bgNfSRGhy41h6viRI44Awe7DzvvZVbtYFRLn47W4vpj/K 2XM30byZjqSZrhQ4iHVmBesLOfNGKrHrNZGxfPb64pDrQ1uiyskLPuc2w5lpCSVrbBvXTU LOltk7LUMd5wT00ta5/yBM711HKPkt/aP9haD7YBFuts5CvRmelvUDAyT3Ufjcw6chLfqq WKLnfRJVSgSkLXIyYDRbD/42tvcKCgBS2bMe3jryHi/OiDek/Rox9gz1IjCKTKNAdNx4+V Y3In0+WXqnGB3L4pL/eygsyaLFVbe5wI50Wo5yU2wmKgu9SvMeTfKD+hGl7usg== From: Miquel Raynal Date: Fri, 31 Oct 2025 18:26:54 +0100 Subject: [PATCH 10/28] mtd: spinand: Make use of the operation templates through SPINAND_OP() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251031-winbond-v6-17-rc1-oddr-v1-10-be42de23ebf1@bootlin.com> References: <20251031-winbond-v6-17-rc1-oddr-v1-0-be42de23ebf1@bootlin.com> In-Reply-To: <20251031-winbond-v6-17-rc1-oddr-v1-0-be42de23ebf1@bootlin.com> To: Mark Brown , Richard Weinberger , Vignesh Raghavendra Cc: Tudor Ambarus , Pratyush Yadav , Thomas Petazzoni , Steam Lin , Santhosh Kumar K , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Miquel Raynal X-Mailer: b4 0.14.2 X-Last-TLS-Session-Version: TLSv1.3 Create a SPINAND_OP() macro to which we give the name of the operation we want. This macro retrieves the correct operation template based on the current bus interface (currently only single SDR, will soon be extended to octal DTR) and fills it with the usual parameters. This macro makes the transition from calling directly the low-level macros into using the (bus interface dependent) templates very smooth. Signed-off-by: Miquel Raynal Reviewed-by: Tudor Ambarus --- drivers/mtd/nand/spi/core.c | 26 ++++++------- drivers/mtd/nand/spi/winbond.c | 3 +- include/linux/mtd/spinand.h | 87 ++++++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 102 insertions(+), 14 deletions(-) diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c index 11d3b28a14339282360a5ef12be715e532105e73..d4f46a17f77e15ac0ab26397e88= d37119636b003 100644 --- a/drivers/mtd/nand/spi/core.c +++ b/drivers/mtd/nand/spi/core.c @@ -22,8 +22,8 @@ =20 int spinand_read_reg_op(struct spinand_device *spinand, u8 reg, u8 *val) { - struct spi_mem_op op =3D SPINAND_GET_FEATURE_1S_1S_1S_OP(reg, - spinand->scratchbuf); + struct spi_mem_op op =3D SPINAND_OP(spinand, get_feature, + reg, spinand->scratchbuf); int ret; =20 ret =3D spi_mem_exec_op(spinand->spimem, &op); @@ -36,8 +36,8 @@ int spinand_read_reg_op(struct spinand_device *spinand, u= 8 reg, u8 *val) =20 int spinand_write_reg_op(struct spinand_device *spinand, u8 reg, u8 val) { - struct spi_mem_op op =3D SPINAND_SET_FEATURE_1S_1S_1S_OP(reg, - spinand->scratchbuf); + struct spi_mem_op op =3D SPINAND_OP(spinand, set_feature, + reg, spinand->scratchbuf); =20 *spinand->scratchbuf =3D val; return spi_mem_exec_op(spinand->spimem, &op); @@ -362,7 +362,7 @@ static void spinand_ondie_ecc_save_status(struct nand_d= evice *nand, u8 status) =20 int spinand_write_enable_op(struct spinand_device *spinand) { - struct spi_mem_op op =3D SPINAND_WR_EN_1S_0_0_OP; + struct spi_mem_op op =3D SPINAND_OP(spinand, wr_en); =20 return spi_mem_exec_op(spinand->spimem, &op); } @@ -372,7 +372,7 @@ static int spinand_load_page_op(struct spinand_device *= spinand, { struct nand_device *nand =3D spinand_to_nand(spinand); unsigned int row =3D nanddev_pos_to_row(nand, &req->pos); - struct spi_mem_op op =3D SPINAND_PAGE_READ_1S_1S_0_OP(row); + struct spi_mem_op op =3D SPINAND_OP(spinand, page_read, row); =20 return spi_mem_exec_op(spinand->spimem, &op); } @@ -527,7 +527,7 @@ static int spinand_program_op(struct spinand_device *sp= inand, { struct nand_device *nand =3D spinand_to_nand(spinand); unsigned int row =3D nanddev_pos_to_row(nand, &req->pos); - struct spi_mem_op op =3D SPINAND_PROG_EXEC_1S_1S_0_OP(row); + struct spi_mem_op op =3D SPINAND_OP(spinand, prog_exec, row); =20 return spi_mem_exec_op(spinand->spimem, &op); } @@ -537,7 +537,7 @@ static int spinand_erase_op(struct spinand_device *spin= and, { struct nand_device *nand =3D spinand_to_nand(spinand); unsigned int row =3D nanddev_pos_to_row(nand, pos); - struct spi_mem_op op =3D SPINAND_BLK_ERASE_1S_1S_0_OP(row); + struct spi_mem_op op =3D SPINAND_OP(spinand, blk_erase, row); =20 return spi_mem_exec_op(spinand->spimem, &op); } @@ -557,8 +557,8 @@ static int spinand_erase_op(struct spinand_device *spin= and, int spinand_wait(struct spinand_device *spinand, unsigned long initial_del= ay_us, unsigned long poll_delay_us, u8 *s) { - struct spi_mem_op op =3D SPINAND_GET_FEATURE_1S_1S_1S_OP(REG_STATUS, - spinand->scratchbuf); + struct spi_mem_op op =3D SPINAND_OP(spinand, get_feature, + REG_STATUS, spinand->scratchbuf); u8 status; int ret; =20 @@ -591,8 +591,8 @@ int spinand_wait(struct spinand_device *spinand, unsign= ed long initial_delay_us, static int spinand_read_id_op(struct spinand_device *spinand, u8 naddr, u8 ndummy, u8 *buf) { - struct spi_mem_op op =3D SPINAND_READID_1S_1S_1S_OP( - naddr, ndummy, spinand->scratchbuf, SPINAND_MAX_ID_LEN); + struct spi_mem_op op =3D SPINAND_OP(spinand, readid, + naddr, ndummy, spinand->scratchbuf, SPINAND_MAX_ID_LEN); int ret; =20 ret =3D spi_mem_exec_op(spinand->spimem, &op); @@ -604,7 +604,7 @@ static int spinand_read_id_op(struct spinand_device *sp= inand, u8 naddr, =20 static int spinand_reset_op(struct spinand_device *spinand) { - struct spi_mem_op op =3D SPINAND_RESET_1S_0_0_OP; + struct spi_mem_op op =3D SPINAND_OP(spinand, reset); int ret; =20 ret =3D spi_mem_exec_op(spinand->spimem, &op); diff --git a/drivers/mtd/nand/spi/winbond.c b/drivers/mtd/nand/spi/winbond.c index d5799c2df06520de6cb5c5b771ceeb9d11ddf1fb..bfec5d037f25b81a3c90feba666= fe8283a41ddb1 100644 --- a/drivers/mtd/nand/spi/winbond.c +++ b/drivers/mtd/nand/spi/winbond.c @@ -251,7 +251,8 @@ static int w25n02kv_ecc_get_status(struct spinand_devic= e *spinand, { struct nand_device *nand =3D spinand_to_nand(spinand); u8 mbf =3D 0; - struct spi_mem_op op =3D SPINAND_GET_FEATURE_1S_1S_1S_OP(0x30, spinand->s= cratchbuf); + struct spi_mem_op op =3D SPINAND_OP(spinand, get_feature, + 0x30, spinand->scratchbuf); =20 switch (status & STATUS_ECC_MASK) { case STATUS_ECC_NO_BITFLIPS: diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h index 4afebaf5f0195b9bc617ea1f125f637f76fff9f8..a8fd04a67cfa9925bd68c57539d= 86e0816b76274 100644 --- a/include/linux/mtd/spinand.h +++ b/include/linux/mtd/spinand.h @@ -701,6 +701,93 @@ struct spinand_device { unsigned int retry_mode); }; =20 +static inline struct spi_mem_op +spinand_fill_reset_op(struct spinand_device *spinand) +{ + return spinand->op_templates->reset; +} + +static inline struct spi_mem_op +spinand_fill_readid_op(struct spinand_device *spinand, + u8 naddr, u8 ndummy, void *buf, unsigned int len) +{ + struct spi_mem_op op =3D spinand->op_templates->readid; + + op.addr.nbytes =3D naddr; + op.dummy.nbytes =3D ndummy; + op.data.buf.in =3D buf; + op.data.nbytes =3D len; + + return op; +} + +static inline struct spi_mem_op +spinand_fill_wr_en_op(struct spinand_device *spinand) +{ + return spinand->op_templates->wr_en; +} + +static inline struct spi_mem_op +spinand_fill_wr_dis_op(struct spinand_device *spinand) +{ + return spinand->op_templates->wr_dis; +} + +static inline struct spi_mem_op +spinand_fill_set_feature_op(struct spinand_device *spinand, u64 reg, const= void *valptr) +{ + struct spi_mem_op op =3D spinand->op_templates->set_feature; + + op.addr.val =3D reg; + op.data.buf.out =3D valptr; + + return op; +} + +static inline struct spi_mem_op +spinand_fill_get_feature_op(struct spinand_device *spinand, u64 reg, void = *valptr) +{ + struct spi_mem_op op =3D spinand->op_templates->get_feature; + + op.addr.val =3D reg; + op.data.buf.in =3D valptr; + + return op; +} + +static inline struct spi_mem_op +spinand_fill_blk_erase_op(struct spinand_device *spinand, u64 addr) +{ + struct spi_mem_op op =3D spinand->op_templates->blk_erase; + + op.addr.val =3D addr; + + return op; +} + +static inline struct spi_mem_op +spinand_fill_page_read_op(struct spinand_device *spinand, u64 addr) +{ + struct spi_mem_op op =3D spinand->op_templates->page_read; + + op.addr.val =3D addr; + + return op; +} + +static inline struct spi_mem_op +spinand_fill_prog_exec_op(struct spinand_device *spinand, u64 addr) +{ + struct spi_mem_op op =3D spinand->op_templates->prog_exec; + + op.addr.val =3D addr; + + return op; +} + +#define SPINAND_OP(spinand, op_name, ...) \ + spinand_fill_ ## op_name ## _op(spinand, ##__VA_ARGS__) + /** * mtd_to_spinand() - Get the SPI NAND device attached to an MTD instance * @mtd: MTD instance --=20 2.51.0 From nobody Mon Feb 9 11:33:48 2026 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CFD9934DB60 for ; Fri, 31 Oct 2025 17:28:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="Bpj7xOTE" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-02.galae.net (Postfix) with ESMTPS id 3C8491A17C4 for ; Fri, 31 Oct 2025 17:28:25 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 0DE4660704; Fri, 31 Oct 2025 17:28:25 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 79E221181800B; Fri, 31 Oct 2025 18:28:23 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1761931704; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=De7gBmjTI9KAJwGNKuzLWU3Oj2vrG8Kq519OwAayKsY=; b=Bpj7xOTEWd3bCrNKkoYBh3dnBIrJ1WALpYpR0/E4fonag/pfwZAEx6K5DTbK01TOwnIY8/ Ze6R+ubl0CZ+TuP0kjj47OuSl86v0emsefdn2Ot2EzPDbluXT+2Lu5eJ8OY0/sHZTnYQUS Fo6+++0JBIhn9xp9tz8FmguCKSk7ja0VFA/SR9jB0ljb6LN5tuaJDw490C8ymDX1vsGoSJ CUq9SlbUqQH3fg+sWnrfLxi2huY7Qpj5xZXigmcIvkgth0z4KNdreFbEwbKlJustNIor6h 0mYVuSFDoc1I5oJUr73/+hX/5Qh6lbJnBHLEPKGOtQsrAfKIBga3Qe8S4Ti5TA== From: Miquel Raynal Date: Fri, 31 Oct 2025 18:26:55 +0100 Subject: [PATCH 11/28] mtd: spinand: Convert vendor drivers to SPINAND_OP() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251031-winbond-v6-17-rc1-oddr-v1-11-be42de23ebf1@bootlin.com> References: <20251031-winbond-v6-17-rc1-oddr-v1-0-be42de23ebf1@bootlin.com> In-Reply-To: <20251031-winbond-v6-17-rc1-oddr-v1-0-be42de23ebf1@bootlin.com> To: Mark Brown , Richard Weinberger , Vignesh Raghavendra Cc: Tudor Ambarus , Pratyush Yadav , Thomas Petazzoni , Steam Lin , Santhosh Kumar K , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Miquel Raynal X-Mailer: b4 0.14.2 X-Last-TLS-Session-Version: TLSv1.3 This macro allows to silently switch bus interfaces, use it outside of the core in all places that can be trivially converted. At this stage there is no functional change expected, until octal DTR support gets added. Signed-off-by: Miquel Raynal --- drivers/mtd/nand/spi/esmt.c | 4 ++-- drivers/mtd/nand/spi/gigadevice.c | 8 ++++---- drivers/mtd/nand/spi/macronix.c | 4 ++-- drivers/mtd/nand/spi/micron.c | 8 ++++---- drivers/mtd/nand/spi/toshiba.c | 3 ++- 5 files changed, 14 insertions(+), 13 deletions(-) diff --git a/drivers/mtd/nand/spi/esmt.c b/drivers/mtd/nand/spi/esmt.c index f880c3b15ceab14676ab65f3d9e8530c713528c8..ba95e589e12fb4d934a0cd3746c= 7b286897ffe92 100644 --- a/drivers/mtd/nand/spi/esmt.c +++ b/drivers/mtd/nand/spi/esmt.c @@ -137,8 +137,8 @@ static int f50l1g41lb_user_otp_info(struct spinand_devi= ce *spinand, size_t len, static int f50l1g41lb_otp_lock(struct spinand_device *spinand, loff_t from, size_t len) { - struct spi_mem_op write_op =3D SPINAND_WR_EN_1S_0_0_OP; - struct spi_mem_op exec_op =3D SPINAND_PROG_EXEC_1S_1S_0_OP(0); + struct spi_mem_op write_op =3D SPINAND_OP(spinand, wr_en); + struct spi_mem_op exec_op =3D SPINAND_OP(spinand, prog_exec, 0); u8 status; int ret; =20 diff --git a/drivers/mtd/nand/spi/gigadevice.c b/drivers/mtd/nand/spi/gigad= evice.c index 72ad36c9a12693caf863b0d172d4a1f2ac4d5ecd..e4380208edd09445c44a29bb7dd= 2012a0bb1a1b0 100644 --- a/drivers/mtd/nand/spi/gigadevice.c +++ b/drivers/mtd/nand/spi/gigadevice.c @@ -266,8 +266,8 @@ static int gd5fxgq4uexxg_ecc_get_status(struct spinand_= device *spinand, u8 status) { u8 status2; - struct spi_mem_op op =3D SPINAND_GET_FEATURE_1S_1S_1S_OP(GD5FXGQXXEXXG_RE= G_STATUS2, - spinand->scratchbuf); + struct spi_mem_op op =3D SPINAND_OP(spinand, get_feature, + GD5FXGQXXEXXG_REG_STATUS2, spinand->scratchbuf); int ret; =20 switch (status & STATUS_ECC_MASK) { @@ -309,8 +309,8 @@ static int gd5fxgq5xexxg_ecc_get_status(struct spinand_= device *spinand, u8 status) { u8 status2; - struct spi_mem_op op =3D SPINAND_GET_FEATURE_1S_1S_1S_OP(GD5FXGQXXEXXG_RE= G_STATUS2, - spinand->scratchbuf); + struct spi_mem_op op =3D SPINAND_OP(spinand, get_feature, + GD5FXGQXXEXXG_REG_STATUS2, spinand->scratchbuf); int ret; =20 switch (status & STATUS_ECC_MASK) { diff --git a/drivers/mtd/nand/spi/macronix.c b/drivers/mtd/nand/spi/macroni= x.c index edf63b9996cf029fffa4948566c7afda77d97cee..143cc120bdec1300f8fe60e951c= 4da9174668677 100644 --- a/drivers/mtd/nand/spi/macronix.c +++ b/drivers/mtd/nand/spi/macronix.c @@ -148,8 +148,8 @@ static int macronix_set_cont_read(struct spinand_device= *spinand, bool enable) static int macronix_set_read_retry(struct spinand_device *spinand, unsigned int retry_mode) { - struct spi_mem_op op =3D SPINAND_SET_FEATURE_1S_1S_1S_OP(MACRONIX_FEATURE= _ADDR_READ_RETRY, - spinand->scratchbuf); + struct spi_mem_op op =3D SPINAND_OP(spinand, set_feature, + MACRONIX_FEATURE_ADDR_READ_RETRY, spinand->scratchbuf); =20 *spinand->scratchbuf =3D retry_mode; return spi_mem_exec_op(spinand->spimem, &op); diff --git a/drivers/mtd/nand/spi/micron.c b/drivers/mtd/nand/spi/micron.c index b8130e04e8e798519ad38c58b5569935c1a447a2..36f6cbbd7462c0c5c208a28acae= 6e64e1af954da 100644 --- a/drivers/mtd/nand/spi/micron.c +++ b/drivers/mtd/nand/spi/micron.c @@ -137,8 +137,8 @@ static const struct mtd_ooblayout_ops micron_4_ooblayou= t =3D { static int micron_select_target(struct spinand_device *spinand, unsigned int target) { - struct spi_mem_op op =3D SPINAND_SET_FEATURE_1S_1S_1S_OP(MICRON_DIE_SELEC= T_REG, - spinand->scratchbuf); + struct spi_mem_op op =3D SPINAND_OP(spinand, set_feature, + MICRON_DIE_SELECT_REG, spinand->scratchbuf); =20 if (target > 1) return -EINVAL; @@ -251,8 +251,8 @@ static int mt29f2g01abagd_user_otp_info(struct spinand_= device *spinand, static int mt29f2g01abagd_otp_lock(struct spinand_device *spinand, loff_t = from, size_t len) { - struct spi_mem_op write_op =3D SPINAND_WR_EN_1S_0_0_OP; - struct spi_mem_op exec_op =3D SPINAND_PROG_EXEC_1S_1S_0_OP(0); + struct spi_mem_op write_op =3D SPINAND_OP(spinand, wr_en); + struct spi_mem_op exec_op =3D SPINAND_OP(spinand, prog_exec, 0); u8 status; int ret; =20 diff --git a/drivers/mtd/nand/spi/toshiba.c b/drivers/mtd/nand/spi/toshiba.c index 6530257ac0beddf8b9e5a9591c5f5ccc4803c003..ef649162ee680c2d7db9dc9332e= 705265bc8f234 100644 --- a/drivers/mtd/nand/spi/toshiba.c +++ b/drivers/mtd/nand/spi/toshiba.c @@ -73,7 +73,8 @@ static int tx58cxgxsxraix_ecc_get_status(struct spinand_d= evice *spinand, { struct nand_device *nand =3D spinand_to_nand(spinand); u8 mbf =3D 0; - struct spi_mem_op op =3D SPINAND_GET_FEATURE_1S_1S_1S_OP(0x30, spinand->s= cratchbuf); + struct spi_mem_op op =3D SPINAND_OP(spinand, get_feature, + 0x30, spinand->scratchbuf); =20 switch (status & STATUS_ECC_MASK) { case STATUS_ECC_NO_BITFLIPS: --=20 2.51.0 From nobody Mon Feb 9 11:33:48 2026 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0ED5734DCE6 for ; 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bh=jv1QAVetYv+kcwEdo8dQ+dRsDCLD1VFydP/2jra5dV0=; b=RDm77a5+ViA3+FA61T1BqPeY3a93LpZKgl/UxpqC6/BRo74xapkI3+wodHs7QQJX+8Ed2c mbVBNyeiF/XugST1XsO0/R9TbIAGIyD3EIP5XpB51rZpBt6mor+m7yjn2KU6Rcb7CW0ott F2c8iyu0af8g3/AGYdmirCFoGWtncwXjJcVFeTsbcyQgnUZSN0mhiOv16UqNtV0wV7QLjN 5cRY0Td+sKBZotjGsFLaKOh6q9FuN7V7yzeczqDyOew5VSbnF3IrrqV78BTA16KFVn/OHG wCpcPp91zJZQU6finFtuoa3w3nIiUKtQDOpmee3FNmay6h/kiClMqDOn3W1g9Q== From: Miquel Raynal Date: Fri, 31 Oct 2025 18:26:56 +0100 Subject: [PATCH 12/28] mtd: spinand: macronix: Convert vendor specific operation to SPINAND_OP() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251031-winbond-v6-17-rc1-oddr-v1-12-be42de23ebf1@bootlin.com> References: <20251031-winbond-v6-17-rc1-oddr-v1-0-be42de23ebf1@bootlin.com> In-Reply-To: <20251031-winbond-v6-17-rc1-oddr-v1-0-be42de23ebf1@bootlin.com> To: Mark Brown , Richard Weinberger , Vignesh Raghavendra Cc: Tudor Ambarus , Pratyush Yadav , Thomas Petazzoni , Steam Lin , Santhosh Kumar K , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Miquel Raynal X-Mailer: b4 0.14.2 X-Last-TLS-Session-Version: TLSv1.3 Macronix chips require a vendor specific operation to read the ECC status register. Instead of defining this op only in the function that needs it, hiding it from the core, make it a proper define like all other spi-mem operations, and implement the necessary spinand_fill_*_op() helper to make the SPINAND_OP() macro work. This way we can use it from any function without any extra handling outside of this helper when we will convert the core to support octal DDR busses. Signed-off-by: Miquel Raynal Reviewed-by: Tudor Ambarus --- drivers/mtd/nand/spi/macronix.c | 20 +++++++++++++++----- 1 file changed, 15 insertions(+), 5 deletions(-) diff --git a/drivers/mtd/nand/spi/macronix.c b/drivers/mtd/nand/spi/macroni= x.c index 143cc120bdec1300f8fe60e951c4da9174668677..a847ea8f49a8a7005405f6083a4= aaac942974998 100644 --- a/drivers/mtd/nand/spi/macronix.c +++ b/drivers/mtd/nand/spi/macronix.c @@ -41,6 +41,18 @@ static SPINAND_OP_VARIANTS(update_cache_variants, SPINAND_PROG_LOAD_1S_1S_4S_OP(false, 0, NULL, 0), SPINAND_PROG_LOAD_1S_1S_1S_OP(false, 0, NULL, 0)); =20 +#define SPINAND_MACRONIX_READ_ECCSR_1S_0_1S(buf) \ + SPI_MEM_OP(SPI_MEM_OP_CMD(0x7c, 1), \ + SPI_MEM_OP_NO_ADDR, \ + SPI_MEM_OP_DUMMY(1, 1), \ + SPI_MEM_OP_DATA_IN(1, buf, 1)) + +static struct spi_mem_op +spinand_fill_macronix_read_eccsr_op(struct spinand_device *spinand, void *= valptr) +{ + return (struct spi_mem_op)SPINAND_MACRONIX_READ_ECCSR_1S_0_1S(valptr); +} + static int mx35lfxge4ab_ooblayout_ecc(struct mtd_info *mtd, int section, struct mtd_oob_region *region) { @@ -67,12 +79,10 @@ static const struct mtd_ooblayout_ops mx35lfxge4ab_oobl= ayout =3D { static int macronix_get_eccsr(struct spinand_device *spinand, u8 *eccsr) { struct macronix_priv *priv =3D spinand->priv; - struct spi_mem_op op =3D SPI_MEM_OP(SPI_MEM_OP_CMD(0x7c, 1), - SPI_MEM_OP_NO_ADDR, - SPI_MEM_OP_DUMMY(1, 1), - SPI_MEM_OP_DATA_IN(1, eccsr, 1)); + struct spi_mem_op op =3D SPINAND_OP(spinand, macronix_read_eccsr, eccsr); + int ret; =20 - int ret =3D spi_mem_exec_op(spinand->spimem, &op); + ret =3D spi_mem_exec_op(spinand->spimem, &op); if (ret) return ret; =20 --=20 2.51.0 From nobody Mon Feb 9 11:33:48 2026 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6705534E770; Fri, 31 Oct 2025 17:28:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.171.202.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761931711; cv=none; b=qje5PsJ22tAR+zoJeUqURxuV4bOtfHdDQKgeLUxhHis0jAPZdMlBTdLebB6m9Y7LU7epfAt5QyplTrKZ2kB7ldLOmKWMb/RVvc+tK3uuWDy8YQwXc0IZ/JXs3C7hcpf5o9Sk2GxOKBV1unAtQg2pbsAU5oV2ErRYnQ4e1JwHt9A= ARC-Message-Signature: i=1; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251031-winbond-v6-17-rc1-oddr-v1-13-be42de23ebf1@bootlin.com> References: <20251031-winbond-v6-17-rc1-oddr-v1-0-be42de23ebf1@bootlin.com> In-Reply-To: <20251031-winbond-v6-17-rc1-oddr-v1-0-be42de23ebf1@bootlin.com> To: Mark Brown , Richard Weinberger , Vignesh Raghavendra Cc: Tudor Ambarus , Pratyush Yadav , Thomas Petazzoni , Steam Lin , Santhosh Kumar K , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Miquel Raynal X-Mailer: b4 0.14.2 X-Last-TLS-Session-Version: TLSv1.3 Winbond W25N* chips require a vendor specific operation to select the target. Instead of defining this op only in the function that needs it, hiding it from the core, make it a proper define like all other spi-mem operations, and implement the necessary spinand_fill_*_op() helper to make the SPINAND_OP() macro work. This way we can use it from any function without any extra handling outside of this helper when we will convert the core to support octal DDR busses. Signed-off-by: Miquel Raynal Reviewed-by: Tudor Ambarus --- drivers/mtd/nand/spi/winbond.c | 20 ++++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) diff --git a/drivers/mtd/nand/spi/winbond.c b/drivers/mtd/nand/spi/winbond.c index bfec5d037f25b81a3c90feba666fe8283a41ddb1..dde59f8f63f511a298a43a5b43f= e07c1d726f179 100644 --- a/drivers/mtd/nand/spi/winbond.c +++ b/drivers/mtd/nand/spi/winbond.c @@ -87,6 +87,18 @@ static SPINAND_OP_VARIANTS(update_cache_variants, SPINAND_PROG_LOAD_1S_1S_4S_OP(false, 0, NULL, 0), SPINAND_PROG_LOAD_1S_1S_1S_OP(false, 0, NULL, 0)); =20 +#define SPINAND_WINBOND_SELECT_TARGET_1S_0_1S(buf) \ + SPI_MEM_OP(SPI_MEM_OP_CMD(0xc2, 1), \ + SPI_MEM_OP_NO_ADDR, \ + SPI_MEM_OP_NO_DUMMY, \ + SPI_MEM_OP_DATA_OUT(1, buf, 1)) + +static struct spi_mem_op +spinand_fill_winbond_select_target_op(struct spinand_device *spinand, void= *valptr) +{ + return (struct spi_mem_op)SPINAND_WINBOND_SELECT_TARGET_1S_0_1S(valptr); +} + static int w25m02gv_ooblayout_ecc(struct mtd_info *mtd, int section, struct mtd_oob_region *region) { @@ -119,12 +131,8 @@ static const struct mtd_ooblayout_ops w25m02gv_ooblayo= ut =3D { static int w25m02gv_select_target(struct spinand_device *spinand, unsigned int target) { - struct spi_mem_op op =3D SPI_MEM_OP(SPI_MEM_OP_CMD(0xc2, 1), - SPI_MEM_OP_NO_ADDR, - SPI_MEM_OP_NO_DUMMY, - SPI_MEM_OP_DATA_OUT(1, - spinand->scratchbuf, - 1)); + struct spi_mem_op op =3D SPINAND_OP(spinand, winbond_select_target, + spinand->scratchbuf); =20 *spinand->scratchbuf =3D target; return spi_mem_exec_op(spinand->spimem, &op); --=20 2.51.0 From nobody Mon Feb 9 11:33:48 2026 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A941034EF0B; Fri, 31 Oct 2025 17:28:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.84.56 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761931712; cv=none; b=AvBCIjxzCKwQ5OWWLjW+8FuLUl67xZ7cjOUvQ3EPEnzALY6J1oBeeYkJ4U9gwe99UIT0FFMtrJI5wfyBrbdBmZ9mebXRpvNi40zqsyLM3uFVxXTEr4rCpQAb6gIHeq/FVtxLfdIPWs49/Rn1uWOcvH2Y/+skWpprY3ZbPR6p+qg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761931712; c=relaxed/simple; bh=07EOgXth6XkPkHWngakcKndxm5s+WUTbZtg+4rzo0eQ=; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251031-winbond-v6-17-rc1-oddr-v1-14-be42de23ebf1@bootlin.com> References: <20251031-winbond-v6-17-rc1-oddr-v1-0-be42de23ebf1@bootlin.com> In-Reply-To: <20251031-winbond-v6-17-rc1-oddr-v1-0-be42de23ebf1@bootlin.com> To: Mark Brown , Richard Weinberger , Vignesh Raghavendra Cc: Tudor Ambarus , Pratyush Yadav , Thomas Petazzoni , Steam Lin , Santhosh Kumar K , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Miquel Raynal X-Mailer: b4 0.14.2 X-Last-TLS-Session-Version: TLSv1.3 Winbond W35N* chips require a vendor specific operation to write their VCR register (a configuration register, typically used for tuning the number of dummy cycles and switching to a different bus interface). Instead of defining this op only in the function that needs it, hiding it from the core, make it a proper define like all other spi-mem operations, and implement the necessary spinand_fill_*_op() helper to make the SPINAND_OP() macro work. This way we can use it from any function without any extra handling outside of this helper when we will convert the core to support octal DDR busses. Signed-off-by: Miquel Raynal Reviewed-by: Tudor Ambarus --- drivers/mtd/nand/spi/winbond.c | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) diff --git a/drivers/mtd/nand/spi/winbond.c b/drivers/mtd/nand/spi/winbond.c index dde59f8f63f511a298a43a5b43fe07c1d726f179..3003ad7e83ee8f553ec82a03264= 22916c0ed794c 100644 --- a/drivers/mtd/nand/spi/winbond.c +++ b/drivers/mtd/nand/spi/winbond.c @@ -87,6 +87,18 @@ static SPINAND_OP_VARIANTS(update_cache_variants, SPINAND_PROG_LOAD_1S_1S_4S_OP(false, 0, NULL, 0), SPINAND_PROG_LOAD_1S_1S_1S_OP(false, 0, NULL, 0)); =20 +#define SPINAND_WINBOND_WRITE_VCR_1S_1S_1S(reg, buf) \ + SPI_MEM_OP(SPI_MEM_OP_CMD(0x81, 1), \ + SPI_MEM_OP_ADDR(3, reg, 1), \ + SPI_MEM_OP_NO_DUMMY, \ + SPI_MEM_OP_DATA_OUT(1, buf, 1)) + +static struct spi_mem_op +spinand_fill_winbond_write_vcr_op(struct spinand_device *spinand, u8 reg, = void *valptr) +{ + return (struct spi_mem_op)SPINAND_WINBOND_WRITE_VCR_1S_1S_1S(reg, valptr); +} + #define SPINAND_WINBOND_SELECT_TARGET_1S_0_1S(buf) \ SPI_MEM_OP(SPI_MEM_OP_CMD(0xc2, 1), \ SPI_MEM_OP_NO_ADDR, \ @@ -329,11 +341,8 @@ static int w25n0xjw_hs_cfg(struct spinand_device *spin= and) =20 static int w35n0xjw_write_vcr(struct spinand_device *spinand, u8 reg, u8 v= al) { - struct spi_mem_op op =3D - SPI_MEM_OP(SPI_MEM_OP_CMD(0x81, 1), - SPI_MEM_OP_ADDR(3, reg, 1), - SPI_MEM_OP_NO_DUMMY, - SPI_MEM_OP_DATA_OUT(1, spinand->scratchbuf, 1)); + struct spi_mem_op op =3D SPINAND_OP(spinand, winbond_write_vcr, + reg, spinand->scratchbuf); int ret; =20 *spinand->scratchbuf =3D val; --=20 2.51.0 From nobody Mon Feb 9 11:33:48 2026 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E213334F27D for ; Fri, 31 Oct 2025 17:28:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.84.56 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761931713; cv=none; b=oKNZDjdqSGdUFo1Yh+E9FQtxizCxVlQjx+CgJkdPc66XTxxo5GpcsoPKFH9offwUiiea0Dj3IXBhqQxaphPeuEIcmeNbAACAby0N/JMrR/LsU6w0O9FsV+FpaSag4nt5oKpy2zxOco0gbb0ih4tTSZPGj4hjG4ze3qUryGEtGc0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761931713; c=relaxed/simple; bh=SwofGuta5o6W85LlbaSEKjS7hlS8I8TpmVta/kJFyr8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; 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Fri, 31 Oct 2025 17:28:30 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id C039411818007; Fri, 31 Oct 2025 18:28:28 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1761931709; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=ZnZdiNJPbIqvHm/HDag2fb8foKcg/2VPHnNDy+534Sc=; b=gpthj2FszYm3wOTAqiSK3W+RfJBtylUVIZ+zV2ruI3xuhvmtaMrXhuh1XzdpXJsAHq+R1o 89HHVe7LwxFqaQtm2lv/PCN7OSQ2UNeeX07xooxQ9mFgz7moCStfaOwJCXraDPze8FPCP5 Y+80heOSuOgs3I2tDYLWGCNACHSVw2IZV0rG5DICtcoo5Kke4mNRBVZ1eN3Tcem3tbc+n4 gmAkF7E7zQ/LP1DjWcpgG3QaQzwCIQlkqIqbUtKzC2WE+qVF74XUVFQVEemEK6s6eA0yVi U4MzWcqcBUU7ayKKvKgmE8VORtMuM3g5m/HJM6lvaDDHO3L3X/4NVy4D8405UA== From: Miquel Raynal Date: Fri, 31 Oct 2025 18:26:59 +0100 Subject: [PATCH 15/28] mtd: spinand: List vendor specific operations and make sure they are supported Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251031-winbond-v6-17-rc1-oddr-v1-15-be42de23ebf1@bootlin.com> References: <20251031-winbond-v6-17-rc1-oddr-v1-0-be42de23ebf1@bootlin.com> In-Reply-To: <20251031-winbond-v6-17-rc1-oddr-v1-0-be42de23ebf1@bootlin.com> To: Mark Brown , Richard Weinberger , Vignesh Raghavendra Cc: Tudor Ambarus , Pratyush Yadav , Thomas Petazzoni , Steam Lin , Santhosh Kumar K , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Miquel Raynal X-Mailer: b4 0.14.2 X-Last-TLS-Session-Version: TLSv1.3 It is probably safe to expect that all SPI controller drivers will ever support all the most basic SPI NAND operations, such as write enable, register reads, page program, block erases, etc. However, what about vendor specific operations? So far nobody complained about it, but as we are about to introduce octal DTR support, and as none of the SPI NAND instruction set is defined in any standard, we must remain careful about these extra operations. One way to make sure we do not blindly get ourselves in strange situations with vendor commands failing silently is to make the check once for all, while probing the chip. However at this stage we have no such list, so let's add the necessary infrastructure to allow: - registering vendor operations, - checking they are actually supported when appropriate. Signed-off-by: Miquel Raynal --- drivers/mtd/nand/spi/core.c | 26 ++++++++++++++++++++++++++ include/linux/mtd/spinand.h | 5 +++++ 2 files changed, 31 insertions(+) diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c index d4f46a17f77e15ac0ab26397e88d37119636b003..7c01516c6b6acb41d2cc080d6fb= aaa5ace661602 100644 --- a/drivers/mtd/nand/spi/core.c +++ b/drivers/mtd/nand/spi/core.c @@ -1338,6 +1338,27 @@ static void spinand_init_ssdr_templates(struct spina= nd_device *spinand) spinand->op_templates =3D &spinand->ssdr_op_templates; } =20 +static int spinand_support_vendor_ops(struct spinand_device *spinand, + const struct spinand_info *info) +{ + int i; + + /* + * The vendor ops array is only used in order to verify this chip and all= its memory + * operations are supported. If we see patterns emerging, we could ideall= y name these + * operations and define them at the SPI NAND core level instead. + * For now, this only serves as a sanity check. + */ + for (i =3D 0; i < info->vendor_ops->nops; i++) { + const struct spi_mem_op *op =3D &info->vendor_ops->ops[i]; + + if (!spi_mem_supports_op(spinand->spimem, op)) + return -EOPNOTSUPP; + } + + return 0; +} + static const struct spi_mem_op * spinand_select_op_variant(struct spinand_device *spinand, const struct spinand_op_variants *variants) @@ -1407,6 +1428,7 @@ int spinand_match_and_init(struct spinand_device *spi= nand, u8 *id =3D spinand->id.data; struct nand_device *nand =3D spinand_to_nand(spinand); unsigned int i; + int ret; =20 for (i =3D 0; i < table_size; i++) { const struct spinand_info *info =3D &table[i]; @@ -1452,6 +1474,10 @@ int spinand_match_and_init(struct spinand_device *sp= inand, =20 spinand->ssdr_op_templates.update_cache =3D op; =20 + ret =3D spinand_support_vendor_ops(spinand, info); + if (ret) + return ret; + return 0; } =20 diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h index a8fd04a67cfa9925bd68c57539d86e0816b76274..0565cdeb3f7b652699d420a8c05= c3fe53fcc2253 100644 --- a/include/linux/mtd/spinand.h +++ b/include/linux/mtd/spinand.h @@ -492,6 +492,7 @@ struct spinand_user_otp { * @op_variants.read_cache: variants of the read-cache operation * @op_variants.write_cache: variants of the write-cache operation * @op_variants.update_cache: variants of the update-cache operation + * @vendor_ops: vendor specific operations * @select_target: function used to select a target/die. Required only for * multi-die chips * @configure_chip: Align the chip configuration with the core settings @@ -516,6 +517,7 @@ struct spinand_info { const struct spinand_op_variants *write_cache; const struct spinand_op_variants *update_cache; } op_variants; + const struct spinand_op_variants *vendor_ops; int (*select_target)(struct spinand_device *spinand, unsigned int target); int (*configure_chip)(struct spinand_device *spinand); @@ -542,6 +544,9 @@ struct spinand_info { .update_cache =3D __update, \ } =20 +#define SPINAND_INFO_VENDOR_OPS(__ops) \ + .vendor_ops =3D __ops + #define SPINAND_ECCINFO(__ooblayout, __get_status) \ .eccinfo =3D { \ .ooblayout =3D __ooblayout, \ --=20 2.51.0 From nobody Mon Feb 9 11:33:48 2026 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 42E8234FF79 for ; Fri, 31 Oct 2025 17:28:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.85.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761931717; cv=none; b=kX4z7csCtBi3q9MZJ3DNGJEoR/OgiFFHv4+xtDgY4JlaV4oitPf+IQ+qmTd8p0a7pzhB3ZXv/GD/tT4+U1B7tBmJc8i0rr+p2/59iAFHwbmkIQmX48P7DL5y87WPF0MT6UbRCsIriwNqZ+LiWDJBN2WVsy+ZgYbWzjUiHIg+TEI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761931717; c=relaxed/simple; bh=s9QP08vtkGDYwazwgqrfFxRGwX8EU+BTdFOQiiYeVRo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=V3uRMVafhqZrmtcwBc1mY9taI03XM02vbgLf3W5G6hwOJQ0wHQQNjI7l8rCEWc4SNF+sfSpwYk1jGw4+qtxQJWfHUKeqfZqB7TkJUDOL8zZx80Je4TIzbvNz0yRcOv5i4QyLhTpvAYo7/IdNBw30DxvyctHiss91dMRabZsZruQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=RD+p5LMi; arc=none smtp.client-ip=185.246.85.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="RD+p5LMi" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-03.galae.net (Postfix) with ESMTPS id D28B94E41446; Fri, 31 Oct 2025 17:28:31 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id A829160704; Fri, 31 Oct 2025 17:28:31 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 176E21181800A; Fri, 31 Oct 2025 18:28:30 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1761931711; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=SSScNc/ZTYByCMEF9q858dnRFAdSrotGIfTOHWGCemk=; b=RD+p5LMiV31QgnitgyjquqxiAyyuIQfYCl7nXRnzvC2LANs0sSmkqRx4xlfjHbGnFZ0CoQ /iV0N8qk3ji+C+YXK468xQBh6sXnVJpMJsEIU3QPP6G6jCZCBUMFRA1v9EbC0ct61TXHIr NWnq6PAYWI2enYSBP/VuIKLM3mQ9bsvKPN0I6SkLDFAyvXqnvkpMHr5prucSHYrIEbsFjl Bghd1fQ93xZu1bLVPijRSg8Qic7GLdmkcVJUC7J8tSybaV5kFibC2wGEypckFk/hR5ULeU 9K9bTwUGFKJ9zACa22v0DBP2wM0Y4Re9uX46aPd1Bi0mrfJCXeteNAwMcAnkMA== From: Miquel Raynal Date: Fri, 31 Oct 2025 18:27:00 +0100 Subject: [PATCH 16/28] mtd: spinand: macronix: Register vendor specific operation Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251031-winbond-v6-17-rc1-oddr-v1-16-be42de23ebf1@bootlin.com> References: <20251031-winbond-v6-17-rc1-oddr-v1-0-be42de23ebf1@bootlin.com> In-Reply-To: <20251031-winbond-v6-17-rc1-oddr-v1-0-be42de23ebf1@bootlin.com> To: Mark Brown , Richard Weinberger , Vignesh Raghavendra Cc: Tudor Ambarus , Pratyush Yadav , Thomas Petazzoni , Steam Lin , Santhosh Kumar K , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Miquel Raynal X-Mailer: b4 0.14.2 X-Last-TLS-Session-Version: TLSv1.3 Provide the Macronix specific "read ECC status register" operation so that the core can verify if it is supported by the controller before using it. Signed-off-by: Miquel Raynal --- drivers/mtd/nand/spi/macronix.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/drivers/mtd/nand/spi/macronix.c b/drivers/mtd/nand/spi/macroni= x.c index a847ea8f49a8a7005405f6083a4aaac942974998..6b7cbcc6e2872d3369b8eb765de= de05c7299c896 100644 --- a/drivers/mtd/nand/spi/macronix.c +++ b/drivers/mtd/nand/spi/macronix.c @@ -47,6 +47,9 @@ static SPINAND_OP_VARIANTS(update_cache_variants, SPI_MEM_OP_DUMMY(1, 1), \ SPI_MEM_OP_DATA_IN(1, buf, 1)) =20 +static SPINAND_OP_VARIANTS(macronix_ops, + SPINAND_MACRONIX_READ_ECCSR_1S_0_1S(NULL)); + static struct spi_mem_op spinand_fill_macronix_read_eccsr_op(struct spinand_device *spinand, void *= valptr) { @@ -174,6 +177,7 @@ static const struct spinand_info macronix_spinand_table= [] =3D { &write_cache_variants, &update_cache_variants), SPINAND_HAS_QE_BIT, + SPINAND_INFO_VENDOR_OPS(¯onix_ops), SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, macronix_ecc_get_status)), SPINAND_INFO("MX35LF2GE4AB", @@ -195,6 +199,7 @@ static const struct spinand_info macronix_spinand_table= [] =3D { &write_cache_variants, &update_cache_variants), SPINAND_HAS_QE_BIT, + SPINAND_INFO_VENDOR_OPS(¯onix_ops), SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, macronix_ecc_get_status), SPINAND_CONT_READ(macronix_set_cont_read), @@ -208,6 +213,7 @@ static const struct spinand_info macronix_spinand_table= [] =3D { &write_cache_variants, &update_cache_variants), SPINAND_HAS_QE_BIT, + SPINAND_INFO_VENDOR_OPS(¯onix_ops), SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, macronix_ecc_get_status), SPINAND_CONT_READ(macronix_set_cont_read), @@ -278,6 +284,7 @@ static const struct spinand_info macronix_spinand_table= [] =3D { &write_cache_variants, &update_cache_variants), SPINAND_HAS_QE_BIT, + SPINAND_INFO_VENDOR_OPS(¯onix_ops), SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, macronix_ecc_get_status)), SPINAND_INFO("MX31UF1GE4BC", @@ -288,6 +295,7 @@ static const struct spinand_info macronix_spinand_table= [] =3D { &write_cache_variants, &update_cache_variants), SPINAND_HAS_QE_BIT, + SPINAND_INFO_VENDOR_OPS(¯onix_ops), SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, macronix_ecc_get_status)), =20 @@ -301,6 +309,7 @@ static const struct spinand_info macronix_spinand_table= [] =3D { SPINAND_HAS_QE_BIT | SPINAND_HAS_PROG_PLANE_SELECT_BIT | SPINAND_HAS_READ_PLANE_SELECT_BIT, + SPINAND_INFO_VENDOR_OPS(¯onix_ops), SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, macronix_ecc_get_status)), SPINAND_INFO("MX35UF4G24AD", @@ -312,6 +321,7 @@ static const struct spinand_info macronix_spinand_table= [] =3D { &update_cache_variants), SPINAND_HAS_QE_BIT | SPINAND_HAS_PROG_PLANE_SELECT_BIT, + SPINAND_INFO_VENDOR_OPS(¯onix_ops), SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, macronix_ecc_get_status), SPINAND_READ_RETRY(MACRONIX_NUM_READ_RETRY_MODES, @@ -324,6 +334,7 @@ static const struct spinand_info macronix_spinand_table= [] =3D { &write_cache_variants, &update_cache_variants), SPINAND_HAS_QE_BIT, + SPINAND_INFO_VENDOR_OPS(¯onix_ops), SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, macronix_ecc_get_status), SPINAND_READ_RETRY(MACRONIX_NUM_READ_RETRY_MODES, @@ -336,6 +347,7 @@ static const struct spinand_info macronix_spinand_table= [] =3D { &write_cache_variants, &update_cache_variants), SPINAND_HAS_QE_BIT, + SPINAND_INFO_VENDOR_OPS(¯onix_ops), SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, macronix_ecc_get_status), SPINAND_CONT_READ(macronix_set_cont_read), @@ -351,6 +363,7 @@ static const struct spinand_info macronix_spinand_table= [] =3D { SPINAND_HAS_QE_BIT | SPINAND_HAS_PROG_PLANE_SELECT_BIT | SPINAND_HAS_READ_PLANE_SELECT_BIT, + SPINAND_INFO_VENDOR_OPS(¯onix_ops), SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, macronix_ecc_get_status)), SPINAND_INFO("MX35UF2G24AD", @@ -362,6 +375,7 @@ static const struct spinand_info macronix_spinand_table= [] =3D { &update_cache_variants), SPINAND_HAS_QE_BIT | SPINAND_HAS_PROG_PLANE_SELECT_BIT, + SPINAND_INFO_VENDOR_OPS(¯onix_ops), SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, macronix_ecc_get_status), SPINAND_READ_RETRY(MACRONIX_NUM_READ_RETRY_MODES, @@ -374,6 +388,7 @@ static const struct spinand_info macronix_spinand_table= [] =3D { &write_cache_variants, &update_cache_variants), SPINAND_HAS_QE_BIT, + SPINAND_INFO_VENDOR_OPS(¯onix_ops), SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, macronix_ecc_get_status), SPINAND_READ_RETRY(MACRONIX_NUM_READ_RETRY_MODES, @@ -386,6 +401,7 @@ static const struct spinand_info macronix_spinand_table= [] =3D { &write_cache_variants, &update_cache_variants), SPINAND_HAS_QE_BIT, + SPINAND_INFO_VENDOR_OPS(¯onix_ops), SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, macronix_ecc_get_status), SPINAND_CONT_READ(macronix_set_cont_read), @@ -399,6 +415,7 @@ static const struct spinand_info macronix_spinand_table= [] =3D { &write_cache_variants, &update_cache_variants), SPINAND_HAS_QE_BIT, + SPINAND_INFO_VENDOR_OPS(¯onix_ops), SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, macronix_ecc_get_status), SPINAND_CONT_READ(macronix_set_cont_read)), @@ -410,6 +427,7 @@ static const struct spinand_info macronix_spinand_table= [] =3D { &write_cache_variants, &update_cache_variants), SPINAND_HAS_QE_BIT, + SPINAND_INFO_VENDOR_OPS(¯onix_ops), SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, macronix_ecc_get_status)), SPINAND_INFO("MX35UF1G24AD", @@ -420,6 +438,7 @@ static const struct spinand_info macronix_spinand_table= [] =3D { &write_cache_variants, &update_cache_variants), SPINAND_HAS_QE_BIT, + SPINAND_INFO_VENDOR_OPS(¯onix_ops), SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, macronix_ecc_get_status), SPINAND_READ_RETRY(MACRONIX_NUM_READ_RETRY_MODES, @@ -432,6 +451,7 @@ static const struct spinand_info macronix_spinand_table= [] =3D { &write_cache_variants, &update_cache_variants), SPINAND_HAS_QE_BIT, + SPINAND_INFO_VENDOR_OPS(¯onix_ops), SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, macronix_ecc_get_status), SPINAND_CONT_READ(macronix_set_cont_read), @@ -445,6 +465,7 @@ static const struct spinand_info macronix_spinand_table= [] =3D { &write_cache_variants, &update_cache_variants), SPINAND_HAS_QE_BIT, + SPINAND_INFO_VENDOR_OPS(¯onix_ops), SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, macronix_ecc_get_status), SPINAND_CONT_READ(macronix_set_cont_read)), @@ -456,6 +477,7 @@ static const struct spinand_info macronix_spinand_table= [] =3D { &write_cache_variants, &update_cache_variants), SPINAND_HAS_QE_BIT, + SPINAND_INFO_VENDOR_OPS(¯onix_ops), SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, macronix_ecc_get_status)), SPINAND_INFO("MX3UF2GE4BC", @@ -466,6 +488,7 @@ static const struct spinand_info macronix_spinand_table= [] =3D { &write_cache_variants, &update_cache_variants), SPINAND_HAS_QE_BIT, + SPINAND_INFO_VENDOR_OPS(¯onix_ops), SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, macronix_ecc_get_status)), }; --=20 2.51.0 From nobody Mon Feb 9 11:33:48 2026 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No 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+0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1761931712; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=o9wIzIvZiwRUNi0x5RrTd6dDilzMRTH2lHz86yrV8Lw=; b=LDNV5w1lANS5nYtNjr1I5p7kB/z3pWHD38yKtMCCHsO2u4uEbsKvdnLSsEfDOeq/9WQH21 w+FIA7SLXadznmJiif0B3U2MqTmZpzZUuZVGc2LusMHMyYpsXK8k2LSNV9XaW4HItAX+7y y9m6hTwQMXA1v6ict7ZW+nhKcW+ixNLaOlgtyRnVaBFapQ2PmdfAj8hixvoDcfNoXc18RQ VAgCDZpG4mAryhbsOD8WOsSiF8ZOBfl6xIuSlg0odP7vVBvU3p+chIf3y4Y9iC13n7ZCVu VaDdFdSp0xeXP5gskJBhAIa5OlC0c8OwCZ+VNA+M8o0JlrtOEjje9dUF65MylQ== From: Miquel Raynal Date: Fri, 31 Oct 2025 18:27:01 +0100 Subject: [PATCH 17/28] mtd: spinand: winbond: Register W25N vendor specific operation Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251031-winbond-v6-17-rc1-oddr-v1-17-be42de23ebf1@bootlin.com> References: <20251031-winbond-v6-17-rc1-oddr-v1-0-be42de23ebf1@bootlin.com> In-Reply-To: <20251031-winbond-v6-17-rc1-oddr-v1-0-be42de23ebf1@bootlin.com> To: Mark Brown , Richard Weinberger , Vignesh Raghavendra Cc: Tudor Ambarus , Pratyush Yadav , Thomas Petazzoni , Steam Lin , Santhosh Kumar K , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Miquel Raynal X-Mailer: b4 0.14.2 X-Last-TLS-Session-Version: TLSv1.3 Provide the Winbond W25N specific "select target" operation to let the core verify it is supported by the controller before using it. Signed-off-by: Miquel Raynal --- drivers/mtd/nand/spi/winbond.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/mtd/nand/spi/winbond.c b/drivers/mtd/nand/spi/winbond.c index 3003ad7e83ee8f553ec82a0326422916c0ed794c..36053f35ee5e84eb355343443a2= 8d274cf7ea5c3 100644 --- a/drivers/mtd/nand/spi/winbond.c +++ b/drivers/mtd/nand/spi/winbond.c @@ -105,6 +105,9 @@ spinand_fill_winbond_write_vcr_op(struct spinand_device= *spinand, u8 reg, void * SPI_MEM_OP_NO_DUMMY, \ SPI_MEM_OP_DATA_OUT(1, buf, 1)) =20 +static SPINAND_OP_VARIANTS(winbond_w25_ops, + SPINAND_WINBOND_SELECT_TARGET_1S_0_1S(NULL)); + static struct spi_mem_op spinand_fill_winbond_select_target_op(struct spinand_device *spinand, void= *valptr) { @@ -497,6 +500,7 @@ static const struct spinand_info winbond_spinand_table[= ] =3D { &write_cache_variants, &update_cache_variants), 0, + SPINAND_INFO_VENDOR_OPS(&winbond_w25_ops), SPINAND_ECCINFO(&w25m02gv_ooblayout, NULL), SPINAND_SELECT_TARGET(w25m02gv_select_target)), SPINAND_INFO("W25N02JW", /* high-speed 1.8V */ --=20 2.51.0 From nobody Mon Feb 9 11:33:48 2026 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F063D350A01 for ; Fri, 31 Oct 2025 17:28:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.84.56 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761931717; cv=none; b=lHnxkiW2txKyFaaeN7MgwWef/epRXNE0nfhyFiWZWwlCpp0wpOHgqlGXwedDADS5goKpAOpPRYhvGaml3jdgxzHTwSn1VVgcOVA6RPqLAupoYjWHCAwZUwGzTFMrD+dlPkX089JEBF9HoFqK7zzJcpKUzh4w+7OZWuWN4n1N2kI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761931717; c=relaxed/simple; bh=BcT58DCMpYImSfCLXscwx0J/YNnF0Oe9IqpvZNcgQ78=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=COIwpSOLeaGhq9j/Jk4SYwz4GQVrbFjP0qCOPgspkj1Iyqi4fyL1ZFvPeJQCQAudcVAtq9d6wImh+Z8g2XqHFs7+qBqmWEFsNKcnTBkji325XM05xAqk0ylvVAq6g4WYtCXcFHx0hZdRgSPK1hbOWkN0rkd2ilnKxhKnNIfgGZw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=UEe5WHxT; arc=none smtp.client-ip=185.246.84.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="UEe5WHxT" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-02.galae.net (Postfix) with ESMTPS id 9D80C1A17C2; Fri, 31 Oct 2025 17:28:34 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 7461360704; Fri, 31 Oct 2025 17:28:34 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id A938211818466; Fri, 31 Oct 2025 18:28:32 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1761931713; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=qLn8pqGpyg4U7OLjWyRrfWQycUAFq+5725pA6nA01gM=; b=UEe5WHxTMWNUU4sVtZJCYJu6Mgx3Z7Fcdlhkt0JsnLfHxQPyeTuP7KXuMD5arq8/mWdo95 4/QFu7UYGaPOYcbWh5NYEIOtRY9N76+ZDZw2YIwior6GT6Td4xU4YIhA14Fo5v6Cb73BTT yWms+2/LBhlpVdl8SDCxgYsiRBC3h9QyJh/gYc0xxngoqMw61s3tAMYXxEMrGPl8MwssBT J9uX6M4FZNnA7F7+ndzl2Yk2K7+YlAXa13JnA9JC+sOpoA+vFUHDMEay7yME4roDBsaZy1 y52H258HZf+jgJxxEFxstc4pNJ6L+PUQOQkHH94HQaH1HFNwFsF6rzimSfzcEg== From: Miquel Raynal Date: Fri, 31 Oct 2025 18:27:02 +0100 Subject: [PATCH 18/28] mtd: spinand: winbond: Register W35N vendor specific operation Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251031-winbond-v6-17-rc1-oddr-v1-18-be42de23ebf1@bootlin.com> References: <20251031-winbond-v6-17-rc1-oddr-v1-0-be42de23ebf1@bootlin.com> In-Reply-To: <20251031-winbond-v6-17-rc1-oddr-v1-0-be42de23ebf1@bootlin.com> To: Mark Brown , Richard Weinberger , Vignesh Raghavendra Cc: Tudor Ambarus , Pratyush Yadav , Thomas Petazzoni , Steam Lin , Santhosh Kumar K , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Miquel Raynal X-Mailer: b4 0.14.2 X-Last-TLS-Session-Version: TLSv1.3 Provide the Winbond W35N specific "write VCR register" operation to let the core verify it is supported by the controller before using it. Signed-off-by: Miquel Raynal --- drivers/mtd/nand/spi/winbond.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/mtd/nand/spi/winbond.c b/drivers/mtd/nand/spi/winbond.c index 36053f35ee5e84eb355343443a28d274cf7ea5c3..1c13dba08369c48ca26381c634a= bcea4e7360f30 100644 --- a/drivers/mtd/nand/spi/winbond.c +++ b/drivers/mtd/nand/spi/winbond.c @@ -93,6 +93,9 @@ static SPINAND_OP_VARIANTS(update_cache_variants, SPI_MEM_OP_NO_DUMMY, \ SPI_MEM_OP_DATA_OUT(1, buf, 1)) =20 +static SPINAND_OP_VARIANTS(winbond_w35_ops, + SPINAND_WINBOND_WRITE_VCR_1S_1S_1S(0, NULL)); + static struct spi_mem_op spinand_fill_winbond_write_vcr_op(struct spinand_device *spinand, u8 reg, = void *valptr) { @@ -469,6 +472,7 @@ static const struct spinand_info winbond_spinand_table[= ] =3D { &write_cache_octal_variants, &update_cache_octal_variants), 0, + SPINAND_INFO_VENDOR_OPS(&winbond_w35_ops), SPINAND_ECCINFO(&w35n01jw_ooblayout, NULL), SPINAND_CONFIGURE_CHIP(w35n0xjw_vcr_cfg)), SPINAND_INFO("W35N02JW", /* 1.8V */ @@ -479,6 +483,7 @@ static const struct spinand_info winbond_spinand_table[= ] =3D { &write_cache_octal_variants, &update_cache_octal_variants), 0, + SPINAND_INFO_VENDOR_OPS(&winbond_w35_ops), SPINAND_ECCINFO(&w35n01jw_ooblayout, NULL), SPINAND_CONFIGURE_CHIP(w35n0xjw_vcr_cfg)), SPINAND_INFO("W35N04JW", /* 1.8V */ @@ -489,6 +494,7 @@ static const struct spinand_info winbond_spinand_table[= ] =3D { &write_cache_octal_variants, &update_cache_octal_variants), 0, + SPINAND_INFO_VENDOR_OPS(&winbond_w35_ops), SPINAND_ECCINFO(&w35n01jw_ooblayout, NULL), SPINAND_CONFIGURE_CHIP(w35n0xjw_vcr_cfg)), /* 2G-bit densities */ --=20 2.51.0 From nobody Mon Feb 9 11:33:48 2026 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CC624350A3D; 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bh=5pi4CcvcO27jDmf/e7y4SHnPB/Y88k3Vae3Xm2yNuow=; b=Gk/w51kCU/8d4KkH+9PASySJzs9qCVlS7IgkATDswIySEf3g5XXTHBoIm3aAPcd+KhFtSU n3mJNRowcOMb58j+hXlbBDah4ACTL7v80ILDeN8NZkTHbjMHnlep3h3m1HQRRAIGDRNBxT cbzYcNgqTXu0kGbQ7cSiGv5xCZdittHtcOwnSyBEz6QnbaGJQijElzAIy/QwEGqx7kKtBy B454EXMpQabzAiSQMe9ZJHK4XP6KGXGjOT4saGINarKf/oNYFwunUhA3KEbHk5G6SV5IoH Ea8U76zlUZR/CYl4UrLL3PpgFA2+93IfiJAw13nYvBxwN843pT7cTj0qDF8fZA== From: Miquel Raynal Date: Fri, 31 Oct 2025 18:27:03 +0100 Subject: [PATCH 19/28] mtd: spinand: winbond: Fix style Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251031-winbond-v6-17-rc1-oddr-v1-19-be42de23ebf1@bootlin.com> References: <20251031-winbond-v6-17-rc1-oddr-v1-0-be42de23ebf1@bootlin.com> In-Reply-To: <20251031-winbond-v6-17-rc1-oddr-v1-0-be42de23ebf1@bootlin.com> To: Mark Brown , Richard Weinberger , Vignesh Raghavendra Cc: Tudor Ambarus , Pratyush Yadav , Thomas Petazzoni , Steam Lin , Santhosh Kumar K , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Miquel Raynal X-Mailer: b4 0.14.2 X-Last-TLS-Session-Version: TLSv1.3 Add a missing new line in the middle of the driver. Signed-off-by: Miquel Raynal --- drivers/mtd/nand/spi/winbond.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mtd/nand/spi/winbond.c b/drivers/mtd/nand/spi/winbond.c index 1c13dba08369c48ca26381c634abcea4e7360f30..7eade2251f7b5b2a96c0a7528ca= 6d64ba6d8233e 100644 --- a/drivers/mtd/nand/spi/winbond.c +++ b/drivers/mtd/nand/spi/winbond.c @@ -408,6 +408,7 @@ static int w35n0xjw_vcr_cfg(struct spinand_device *spin= and) default: return -EINVAL; } + ret =3D w35n0xjw_write_vcr(spinand, W35N01JW_VCR_DUMMY_CLOCK_REG, dummy_c= ycles); if (ret) return ret; --=20 2.51.0 From nobody Mon Feb 9 11:33:48 2026 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 09A0B351FB9; Fri, 31 Oct 2025 17:28:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.85.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761931720; cv=none; b=rITdJdgTkAUk58gfaJIXSYSeFjwHRdrQsBAIHNffzLkxJxBr8g4P2ah1Ahq15ukzByzUq9FcT1D2oG4IuazQfN1yRd7S/RQhYrX/bRFH9x0k0FkUpH1dJHKSvDASlSKoHeA957fblRXQ7uFeEC4KUC1CvZ62jbqwmFa6kZhL2Ps= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761931720; c=relaxed/simple; bh=UZHRF27En+zsCs8vMqc7Q9eAF5nNS57+m2aqEESwh/0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=lvNm59RDmjP0y2ElnTfAFLk2Wo8OzTRFu7lBmmFAn7OA3uLtYIwqqNue2md73Cd6E4pTBBMOvU1LSsImi7ZeBy8bfMGPbl4508/Z0EQqNsLNzIh6GLfQpyLJ/LV/G4JG4HkcbBDxgNskNcVBNs/1xKuP1f+AKJ7iPJo77gn4U2M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=rwSz6Vkb; arc=none smtp.client-ip=185.246.85.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="rwSz6Vkb" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-03.galae.net (Postfix) with ESMTPS id A8FA94E41434; Fri, 31 Oct 2025 17:28:37 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 8043E60704; Fri, 31 Oct 2025 17:28:37 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 07F311181800B; Fri, 31 Oct 2025 18:28:35 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1761931716; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=YwdHq0kXuW83TPzSi0AdbC2T+tsymu7wdChzedkkepA=; b=rwSz6VkbJ8BeEwaHaLBJ4x9IeS5VgVVviBj3M0h1uoTERcC83xmMtIGaJdC80qe/dHwSc3 CmcpbJSAEQcq2W36x/GefC4omRghnWshMWt8+t0qAZTqEt5L+TkLTLhRCee5DX6J9DpFzH uKXWbUgLH5Hgrpc5cjRv7kb0E1lK5OrbRhKtS8hU0A3Tk6lKkX/JN721RqQXVuEvmeWw/Q /zI4iQBi4ousSCGPE0I3bUT0bYd4bLXuIxf6K8yqmj1OuJXsA3dsypgXQv+RHb9U1wFzsI RsWmY526HllUZCu7CIVeYLg2Z2eGgWeQeIRVI+Wn848DavF7rrItrIfoW60Mkw== From: Miquel Raynal Date: Fri, 31 Oct 2025 18:27:04 +0100 Subject: [PATCH 20/28] mtd: spinand: winbond: Rename IO_MODE register macro Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251031-winbond-v6-17-rc1-oddr-v1-20-be42de23ebf1@bootlin.com> References: <20251031-winbond-v6-17-rc1-oddr-v1-0-be42de23ebf1@bootlin.com> In-Reply-To: <20251031-winbond-v6-17-rc1-oddr-v1-0-be42de23ebf1@bootlin.com> To: Mark Brown , Richard Weinberger , Vignesh Raghavendra Cc: Tudor Ambarus , Pratyush Yadav , Thomas Petazzoni , Steam Lin , Santhosh Kumar K , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Miquel Raynal X-Mailer: b4 0.14.2 X-Last-TLS-Session-Version: TLSv1.3 Suffix the macro name with *_REG to align with the rest of the driver. Signed-off-by: Miquel Raynal --- drivers/mtd/nand/spi/winbond.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/nand/spi/winbond.c b/drivers/mtd/nand/spi/winbond.c index 7eade2251f7b5b2a96c0a7528ca6d64ba6d8233e..b169636376835157c64bce17a4f= 32549e1c1eb9f 100644 --- a/drivers/mtd/nand/spi/winbond.c +++ b/drivers/mtd/nand/spi/winbond.c @@ -22,7 +22,7 @@ #define W25N0XJW_SR4 0xD0 #define W25N0XJW_SR4_HS BIT(2) =20 -#define W35N01JW_VCR_IO_MODE 0x00 +#define W35N01JW_VCR_IO_MODE_REG 0x00 #define W35N01JW_VCR_IO_MODE_SINGLE_SDR 0xFF #define W35N01JW_VCR_IO_MODE_OCTAL_SDR 0xDF #define W35N01JW_VCR_IO_MODE_OCTAL_DDR_DS 0xE7 @@ -392,7 +392,7 @@ static int w35n0xjw_vcr_cfg(struct spinand_device *spin= and) else return -EINVAL; =20 - ret =3D w35n0xjw_write_vcr(spinand, W35N01JW_VCR_IO_MODE, io_mode); + ret =3D w35n0xjw_write_vcr(spinand, W35N01JW_VCR_IO_MODE_REG, io_mode); if (ret) return ret; =20 --=20 2.51.0 From nobody Mon Feb 9 11:33:48 2026 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9C1EB354AEB for ; Fri, 31 Oct 2025 17:28:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.84.56 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761931722; cv=none; b=NM1jRpg94NyomUX0f8Vug4ZXeziW5jV5+eScqJAjdlKjAqxxWGCdWSBvInzdc75nVv+Uel3oAVmXFBrafTMCXHhptxegaB+qwa1qsXAyAdNv6JT0yMsPxDI7X5J1YTlIMWzReedzLPFneqxI3PfnSuTZLoa34HaajJBDI8LQ6aA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761931722; c=relaxed/simple; bh=R0YmQeghSKw5PoxKOG0myWRRdHkSep5Ke0+SMyuX6Bk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=WeD91X/K60QyJjg4Df1TKilX42dTOCq1AmqnDNhtNOfTkEhYje/Ygy47UQcrz6LDCnrUUvqtRggmsAcQz2ScIhBulZtQ2iiOcnoevE51toaysl7H2ksnEMEmHSC0r8Ztcxb/moeuTpk/sXQhb2Xgt3K7JHwrFJ6UqRlBf9JR2Cw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=Lqri9Bfp; arc=none smtp.client-ip=185.246.84.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="Lqri9Bfp" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-02.galae.net (Postfix) with ESMTPS id 31AE71A17C6; Fri, 31 Oct 2025 17:28:39 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 08ED260704; Fri, 31 Oct 2025 17:28:39 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 34D801181800A; Fri, 31 Oct 2025 18:28:37 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1761931718; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=ex2SptpuBK+4RMrw2hKUubiMGuwo3pULUp58RhXWy8w=; b=Lqri9Bfp6SGJi9VpPmHo/57DgqJdOMKyMulKxVXHIi3QC4AAF79B6F+8ZLKit4C8ASo7UO K1n8kNY/vTq2dvQjXPSHjfVGANKoIHExxrMZ6qlLB2sJE8pjMiAFgIGs8ETRUxPVdfEAcy ql3ge0KV8xxAE+YpANVrKMS4b0D/ufEWgHk9XR3mArK78+2j210ME00om8M3PTL9lVkg3M 3gGRPJitvJpAmjRlajBIVaVMRSp1zOWz+odGXPbCr4ws8J4uZOH4/b8/yxbasn9gQLZHdS oNYFsTk4PSMxPiF/FuiCGpPyGn8+nYI1taPrBekYVqcI+TaYGsWkPAWkvjpkJQ== From: Miquel Raynal Date: Fri, 31 Oct 2025 18:27:05 +0100 Subject: [PATCH 21/28] mtd: spinand: winbond: Configure the IO mode after the dummy cycles Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251031-winbond-v6-17-rc1-oddr-v1-21-be42de23ebf1@bootlin.com> References: <20251031-winbond-v6-17-rc1-oddr-v1-0-be42de23ebf1@bootlin.com> In-Reply-To: <20251031-winbond-v6-17-rc1-oddr-v1-0-be42de23ebf1@bootlin.com> To: Mark Brown , Richard Weinberger , Vignesh Raghavendra Cc: Tudor Ambarus , Pratyush Yadav , Thomas Petazzoni , Steam Lin , Santhosh Kumar K , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Miquel Raynal X-Mailer: b4 0.14.2 X-Last-TLS-Session-Version: TLSv1.3 When we will change the bus interface, the action that actually performs the transition is the IO mode register write. This means after the IO mode register write, we should use the new bus interface. But the ->configure_chip() hook itself is not responsible of making this change official, it is the caller that must act according to the return value. Reorganize this helper to first configure the dummy cycles before possibly switching to another bus interface. Signed-off-by: Miquel Raynal --- drivers/mtd/nand/spi/winbond.c | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/drivers/mtd/nand/spi/winbond.c b/drivers/mtd/nand/spi/winbond.c index b169636376835157c64bce17a4f32549e1c1eb9f..1d79a8ae79206af7d823018c460= 3b3bd36a0dd88 100644 --- a/drivers/mtd/nand/spi/winbond.c +++ b/drivers/mtd/nand/spi/winbond.c @@ -381,21 +381,6 @@ static int w35n0xjw_vcr_cfg(struct spinand_device *spi= nand) =20 op =3D spinand->op_templates->read_cache; =20 - single =3D (op->cmd.buswidth =3D=3D 1 && op->addr.buswidth =3D=3D 1 && op= ->data.buswidth =3D=3D 1); - dtr =3D (op->cmd.dtr || op->addr.dtr || op->data.dtr); - if (single && !dtr) - io_mode =3D W35N01JW_VCR_IO_MODE_SINGLE_SDR; - else if (!single && !dtr) - io_mode =3D W35N01JW_VCR_IO_MODE_OCTAL_SDR; - else if (!single && dtr) - io_mode =3D W35N01JW_VCR_IO_MODE_OCTAL_DDR; - else - return -EINVAL; - - ret =3D w35n0xjw_write_vcr(spinand, W35N01JW_VCR_IO_MODE_REG, io_mode); - if (ret) - return ret; - dummy_cycles =3D ((op->dummy.nbytes * 8) / op->dummy.buswidth) / (op->dum= my.dtr ? 2 : 1); switch (dummy_cycles) { case 8: @@ -413,6 +398,21 @@ static int w35n0xjw_vcr_cfg(struct spinand_device *spi= nand) if (ret) return ret; =20 + single =3D (op->cmd.buswidth =3D=3D 1 && op->addr.buswidth =3D=3D 1 && op= ->data.buswidth =3D=3D 1); + dtr =3D (op->cmd.dtr && op->addr.dtr && op->data.dtr); + if (single && !dtr) + io_mode =3D W35N01JW_VCR_IO_MODE_SINGLE_SDR; + else if (!single && !dtr) + io_mode =3D W35N01JW_VCR_IO_MODE_OCTAL_SDR; + else if (!single && dtr) + io_mode =3D W35N01JW_VCR_IO_MODE_OCTAL_DDR; + else + return -EINVAL; + + ret =3D w35n0xjw_write_vcr(spinand, W35N01JW_VCR_IO_MODE_REG, io_mode); + if (ret) + return ret; + return 0; } =20 --=20 2.51.0 From nobody Mon Feb 9 11:33:48 2026 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 96B8E35504A for ; Fri, 31 Oct 2025 17:28:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.171.202.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761931723; cv=none; b=A9Yh2QC+uXAdvIy7ObMdFrHGR7804NmpyPJrpxOnfvuricaQAU06SbEQGEju9sYoVNAojATbgUnj/HqLh54nVyrVQDXetB8dZPgxxHVtiJgEHNKoakGhwknpoh3xuq5xj65F1GRDdU9FxbV/UhhKWebjf62ZpZ1iCqR7R/VdLDA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761931723; c=relaxed/simple; bh=iX+n9HzY/YkNmOzBAg84DXwptwGF3y7LQxR8/FtomhA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=iimk1gKdPjXzqxXGxSr7PMX1+X6wXB+gOy1X4rQ3eMbKD/7/c0Mcc1KFVbNvCJm2SZurG3rTKXMzp6c9B+V5PqcdTI4lkeupIJBzJey4Zti0ca0ln8GLPTvGMruDgerbytkUEal6EW8BA1lx6VymcVhxtYXDzIXl2W7uhstyVlY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=hqNZ/wsU; arc=none smtp.client-ip=185.171.202.116 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="hqNZ/wsU" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-04.galae.net (Postfix) with ESMTPS id A9A5AC0E959; Fri, 31 Oct 2025 17:28:19 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 3ACC160704; Fri, 31 Oct 2025 17:28:40 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id B053A11818007; Fri, 31 Oct 2025 18:28:38 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1761931719; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=0TkMp9aMwcsGosTWrhdTtxz4Lwc7YIxnivcDZ+k6Uqo=; b=hqNZ/wsUGkTKZq0riG/RmSnnIu+QPPr5pXIU6713zaYh/NXlRythOCClzvCx1gGf3gP5dh yuDeya8OSJEaPvBDjz9H7XBH6q3G92VWEGDKFegdGjw8rY7TydMlKET3/ntMuEmC8Moqx3 5GvTE+YcEf0nwT2FSO5G3gFnVLKnH2g998eTODG+mg2ILBDdv+x0dKwxoCNp8CuJRd6s01 U7K9wgK6oNMpFuXhFBxa2+ZLzLGRmG9mTCPMHWA2O1974jWEPBk1YDGcotII5jhekKbfbK bn51RrZRAgPew1eXsdTJN+9Hc6WAMsXJzpRRDASkSIpU1SEo1zlzeFZqsgBfqA== From: Miquel Raynal Date: Fri, 31 Oct 2025 18:27:06 +0100 Subject: [PATCH 22/28] mtd: spinand: Gather all the bus interface steps in one single function Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251031-winbond-v6-17-rc1-oddr-v1-22-be42de23ebf1@bootlin.com> References: <20251031-winbond-v6-17-rc1-oddr-v1-0-be42de23ebf1@bootlin.com> In-Reply-To: <20251031-winbond-v6-17-rc1-oddr-v1-0-be42de23ebf1@bootlin.com> To: Mark Brown , Richard Weinberger , Vignesh Raghavendra Cc: Tudor Ambarus , Pratyush Yadav , Thomas Petazzoni , Steam Lin , Santhosh Kumar K , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Miquel Raynal X-Mailer: b4 0.14.2 X-Last-TLS-Session-Version: TLSv1.3 Writing the quad enable bit in one helper and doing the chip configuration in another does not make much sense from a bus interface setup point of view. Instead, let's create a broader helper which is going to be in charge of all the bus configuration steps at once. This will specifically allow to transition to octal DDR mode, and even fallback to quad (if suppoorted) or single mode otherwise. Signed-off-by: Miquel Raynal --- drivers/mtd/nand/spi/core.c | 62 +++++++++++++++++++++++++++--------------= ---- 1 file changed, 37 insertions(+), 25 deletions(-) diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c index 7c01516c6b6acb41d2cc080d6fbaaa5ace661602..caf549617f369ada2c1712e863e= 563ae547ca0e6 100644 --- a/drivers/mtd/nand/spi/core.c +++ b/drivers/mtd/nand/spi/core.c @@ -177,18 +177,9 @@ static int spinand_init_cfg_cache(struct spinand_devic= e *spinand) return 0; } =20 -static int spinand_init_quad_enable(struct spinand_device *spinand) +static int spinand_init_quad_enable(struct spinand_device *spinand, + bool enable) { - bool enable =3D false; - - if (!(spinand->flags & SPINAND_HAS_QE_BIT)) - return 0; - - if (spinand->op_templates->read_cache->data.buswidth =3D=3D 4 || - spinand->op_templates->write_cache->data.buswidth =3D=3D 4 || - spinand->op_templates->update_cache->data.buswidth =3D=3D 4) - enable =3D true; - return spinand_upd_cfg(spinand, CFG_QUAD_ENABLE, enable ? CFG_QUAD_ENABLE : 0); } @@ -1306,12 +1297,6 @@ static int spinand_manufacturer_init(struct spinand_= device *spinand) return ret; } =20 - if (spinand->configure_chip) { - ret =3D spinand->configure_chip(spinand); - if (ret) - return ret; - } - return 0; } =20 @@ -1517,6 +1502,31 @@ static int spinand_detect(struct spinand_device *spi= nand) return 0; } =20 +static int spinand_configure_chip(struct spinand_device *spinand) +{ + bool quad_enable =3D false; + int ret; + + if (spinand->flags & SPINAND_HAS_QE_BIT) { + if (spinand->ssdr_op_templates.read_cache->data.buswidth =3D=3D 4 || + spinand->ssdr_op_templates.write_cache->data.buswidth =3D=3D 4 || + spinand->ssdr_op_templates.update_cache->data.buswidth =3D=3D 4) + quad_enable =3D true; + } + + ret =3D spinand_init_quad_enable(spinand, quad_enable); + if (ret) + return ret; + + if (spinand->configure_chip) { + ret =3D spinand->configure_chip(spinand); + if (ret) + return ret; + } + + return ret; +} + static int spinand_init_flash(struct spinand_device *spinand) { struct device *dev =3D &spinand->spimem->spi->dev; @@ -1527,10 +1537,6 @@ static int spinand_init_flash(struct spinand_device = *spinand) if (ret) return ret; =20 - ret =3D spinand_init_quad_enable(spinand); - if (ret) - return ret; - ret =3D spinand_upd_cfg(spinand, CFG_OTP_ENABLE, 0); if (ret) return ret; @@ -1543,19 +1549,25 @@ static int spinand_init_flash(struct spinand_device= *spinand) return ret; } =20 + ret =3D spinand_configure_chip(spinand); + if (ret) + goto manuf_cleanup; + /* After power up, all blocks are locked, so unlock them here. */ for (i =3D 0; i < nand->memorg.ntargets; i++) { ret =3D spinand_select_target(spinand, i); if (ret) - break; + goto manuf_cleanup; =20 ret =3D spinand_lock_block(spinand, BL_ALL_UNLOCKED); if (ret) - break; + goto manuf_cleanup; } =20 - if (ret) - spinand_manufacturer_cleanup(spinand); + return 0; + +manuf_cleanup: + spinand_manufacturer_cleanup(spinand); =20 return ret; } --=20 2.51.0 From nobody Mon Feb 9 11:33:48 2026 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9A3C435580D for ; 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arc=none smtp.client-ip=185.171.202.116 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="OQU8H40z" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-04.galae.net (Postfix) with ESMTPS id DE62CC0E95A; Fri, 31 Oct 2025 17:28:20 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 6A9AB60704; Fri, 31 Oct 2025 17:28:41 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id DB15C1181800B; Fri, 31 Oct 2025 18:28:39 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1761931720; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=dDe4j5e1a+Bm1K5ZQ2VOjxbCwe35OfOvHUNHbqYEBCM=; b=OQU8H40zhHDYyzpyBy35Qe++qVhY8HighZjajGJghAuu4atrS+eNn2O2JBTc4ACXcYTz5/ 2ua93PkmSv17jrw7i9lq/knC8bQtCvkoiLC+MKZq3iCDizD2yzgJz2qgSBG9hoKA8pYMvx ZBOQ9gpmwKclyA7hOlCiwQNH9VtXDcfk92oKOnAR87vYXwiyr5VTgFbJ/qmSeYlVZyKC+t d79SLWKyIUSEEeOQxF0unF2JMpWGixWuttehktjYeq/xV+ZqButVQtpFIqhGEWESGAUSu9 kOVMCmKOw76BjYRzH5u8pgcAkKS7Rs7yTBAhPmoRtpX6QDw9Lt2IppeEFllG3g== From: Miquel Raynal Date: Fri, 31 Oct 2025 18:27:07 +0100 Subject: [PATCH 23/28] mtd: spinand: Add support for setting a bus interface Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251031-winbond-v6-17-rc1-oddr-v1-23-be42de23ebf1@bootlin.com> References: <20251031-winbond-v6-17-rc1-oddr-v1-0-be42de23ebf1@bootlin.com> In-Reply-To: <20251031-winbond-v6-17-rc1-oddr-v1-0-be42de23ebf1@bootlin.com> To: Mark Brown , Richard Weinberger , Vignesh Raghavendra Cc: Tudor Ambarus , Pratyush Yadav , Thomas Petazzoni , Steam Lin , Santhosh Kumar K , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Miquel Raynal X-Mailer: b4 0.14.2 X-Last-TLS-Session-Version: TLSv1.3 Create a bus interface enumeration, currently only containing the one we support: SSDR, for single SDR, so any operation whose command is sent over a single data line in SDR mode, ie. any operation matching 1S-XX-XX. The main spinand_device structure gets a new parameter to store this enumeration, for now unused. Of course it is set to SSDR during the SSDR templates initialization to further clarify the state we are in at the moment. This member is subject to be used to know in which bus configuration we and be updated by the core when we switch to faster mode(s). Signed-off-by: Miquel Raynal --- drivers/mtd/nand/spi/core.c | 1 + include/linux/mtd/spinand.h | 10 ++++++++++ 2 files changed, 11 insertions(+) diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c index caf549617f369ada2c1712e863e563ae547ca0e6..fc7263fad7afbd084ecf015dd1d= 764d6683b46a8 100644 --- a/drivers/mtd/nand/spi/core.c +++ b/drivers/mtd/nand/spi/core.c @@ -1321,6 +1321,7 @@ static void spinand_init_ssdr_templates(struct spinan= d_device *spinand) tmpl->page_read =3D (struct spi_mem_op)SPINAND_PAGE_READ_1S_1S_0_OP(0); tmpl->prog_exec =3D (struct spi_mem_op)SPINAND_PROG_EXEC_1S_1S_0_OP(0); spinand->op_templates =3D &spinand->ssdr_op_templates; + spinand->bus_iface =3D SSDR; } =20 static int spinand_support_vendor_ops(struct spinand_device *spinand, diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h index 0565cdeb3f7b652699d420a8c05c3fe53fcc2253..7d059956c81a3a6fd337bab43fb= 4f1130997ab0f 100644 --- a/include/linux/mtd/spinand.h +++ b/include/linux/mtd/spinand.h @@ -480,6 +480,14 @@ struct spinand_user_otp { const struct spinand_user_otp_ops *ops; }; =20 +/** + * enum spinand_bus_interface - SPI NAND bus interface types + * @SSDR: Bus configuration supporting all 1S-XX-XX operations, including = dual and quad + */ +enum spinand_bus_interface { + SSDR, +}; + /** * struct spinand_info - Structure used to describe SPI NAND chips * @model: model name @@ -642,6 +650,7 @@ struct spinand_mem_ops { * @flags: NAND flags * @ssdr_op_templates: Templates for all single SDR SPI mem operations * @op_templates: Templates for all SPI mem operations + * @bus_iface: Current bus interface * @select_target: select a specific target/die. Usually called before sen= ding * a command addressing a page or an eraseblock embedded in * this die. Only required if your chip exposes several dies @@ -677,6 +686,7 @@ struct spinand_device { =20 struct spinand_mem_ops ssdr_op_templates; struct spinand_mem_ops *op_templates; + enum spinand_bus_interface bus_iface; =20 struct spinand_dirmap *dirmaps; =20 --=20 2.51.0 From nobody Mon Feb 9 11:33:48 2026 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 39B283557E0; Fri, 31 Oct 2025 17:28:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.171.202.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761931726; cv=none; b=U+39e3vM3VUPH8Ujr3aCkmAquDtXf6F+4ORsOKuA3TdMkWBmnul4f27qsEMRCBjkzTR2IeWOT3q+AvH/NB1/HcD7etbhK9+M1v22SKNrWMh2xMiDdb16JgMfultwM6/y9SETFY+S27MFDf2vwJkab9ht6GCaTkOgFyvReNQwGYc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761931726; c=relaxed/simple; bh=TNoYEQnBFh3gP20Y4ao1hqraCmPr6wCjj5wqZ3Qi4yM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=RlwCP3fTewKbJTlPAPde1iBVGp5Z1HNOZA/38BsOroiwzUvzOqlvVlEbYDmK639LOx41gYEqv182GLbpXb9aPbhifKBse6iWD1O8j7RgIMqLUWnbvYK63rP63R5gXLahVit2Bvm3flCbiNPGDgmJoKJQDbff2T5u2WCvWq6+Ghs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=DIRu8ElF; arc=none smtp.client-ip=185.171.202.116 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="DIRu8ElF" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-04.galae.net (Postfix) with ESMTPS id 3F794C0E958; Fri, 31 Oct 2025 17:28:22 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id C377360704; Fri, 31 Oct 2025 17:28:42 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 165131181800A; Fri, 31 Oct 2025 18:28:41 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1761931722; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=FbpwgQnTShOmE9iJ48pWQGNuCt29TUQkvkRo0eiMaAQ=; b=DIRu8ElFiW438LrY4NcGm9oQrY4vcnzVQZPDi4iKKpm7/ZB5O8TtTmVe6jmnVn8enww1hF TgcfgIcqEJOfcxL9Zo84uvwVL8K578F/R+u40MqpF1FKPWjQrSvVCJRiaWVfbUQ6mppSwl JZHPJLSgvZsKqQA56q8FR8atFup6k9Ez/FhMA4uYEB1EytTfKHJjmZ/Hbx1clnU/p8kEW0 29UVz8Y/carl6Ts2izQDq5ExeOOIMwBMAOVYQ2tk1iwezo+jv9gLjMEKE4KXr2YnhoB/3B KmpW2mJREmWKk6fnIPk3Ig1Vw7MkueGWUz8ZBAIK3Os9Sc+zn/icIiZDKS6GGQ== From: Miquel Raynal Date: Fri, 31 Oct 2025 18:27:08 +0100 Subject: [PATCH 24/28] mtd: spinand: Propagate the bus interface across core helpers Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251031-winbond-v6-17-rc1-oddr-v1-24-be42de23ebf1@bootlin.com> References: <20251031-winbond-v6-17-rc1-oddr-v1-0-be42de23ebf1@bootlin.com> In-Reply-To: <20251031-winbond-v6-17-rc1-oddr-v1-0-be42de23ebf1@bootlin.com> To: Mark Brown , Richard Weinberger , Vignesh Raghavendra Cc: Tudor Ambarus , Pratyush Yadav , Thomas Petazzoni , Steam Lin , Santhosh Kumar K , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Miquel Raynal X-Mailer: b4 0.14.2 X-Last-TLS-Session-Version: TLSv1.3 For now all drivers provide SSDR variants only. When we add support for ODTR modes, there will be a need to differentiate the type of variant we target as well as the need to check if we support one or the other type of operations. Pass this parameter to lower level helpers, which for now is unused, in order to simplify the patch introducing ODTR support. Signed-off-by: Miquel Raynal --- drivers/mtd/nand/spi/core.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c index fc7263fad7afbd084ecf015dd1d764d6683b46a8..0d98cc1d987e1f6387f6bb243cd= 3720949b01b0b 100644 --- a/drivers/mtd/nand/spi/core.c +++ b/drivers/mtd/nand/spi/core.c @@ -1325,7 +1325,8 @@ static void spinand_init_ssdr_templates(struct spinan= d_device *spinand) } =20 static int spinand_support_vendor_ops(struct spinand_device *spinand, - const struct spinand_info *info) + const struct spinand_info *info, + enum spinand_bus_interface iface) { int i; =20 @@ -1346,7 +1347,7 @@ static int spinand_support_vendor_ops(struct spinand_= device *spinand, } =20 static const struct spi_mem_op * -spinand_select_op_variant(struct spinand_device *spinand, +spinand_select_op_variant(struct spinand_device *spinand, enum spinand_bus= _interface iface, const struct spinand_op_variants *variants) { struct nand_device *nand =3D spinand_to_nand(spinand); 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bh=1AlxpEmOzkdHU55IN1x55ULPTzeTpk4t+gKIBhPki5c=; b=vJNmRXNz3oDvVJ1FnQQieTAov+RBMej4MMh2r2w4tS3K/b6clMI6/YalgI8CUvhCt0DB3B GXopmiFUpwXfQ6se8A3WdbUVSPTnqqXPSZC+2ETRwiBpmBQgmNuFduM/9nHY5AlnTUW1SY 2hjjC24hDbfYF6LZzmoBfr4wA7Rd2uVszF4M8lyGh0s9gVzD1tP3geXxETHMa0JfKr/cI2 QLvZakIoEUvKAbER94qALH59ikc5fR6UP7OI1ThE5S9G9yWveGwmL0kWFA0UR922jkSuOn S8inmMdlfEHkvC8OM3yDZQodIXvY3XFfuGwjpl2SwJVVoiv5JmsUkPMaBLvqaA== From: Miquel Raynal Date: Fri, 31 Oct 2025 18:27:09 +0100 Subject: [PATCH 25/28] mtd: spinand: Give the bus interface to the configuration helper Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251031-winbond-v6-17-rc1-oddr-v1-25-be42de23ebf1@bootlin.com> References: <20251031-winbond-v6-17-rc1-oddr-v1-0-be42de23ebf1@bootlin.com> In-Reply-To: <20251031-winbond-v6-17-rc1-oddr-v1-0-be42de23ebf1@bootlin.com> To: Mark Brown , Richard Weinberger , Vignesh Raghavendra Cc: Tudor Ambarus , Pratyush Yadav , Thomas Petazzoni , Steam Lin , Santhosh Kumar K , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Miquel Raynal X-Mailer: b4 0.14.2 X-Last-TLS-Session-Version: TLSv1.3 The chip configuration hook is the one responsible to actually switch the switch between bus interfaces. It is natural to give it the bus interface we expect with a new parameter. For now the only value we can give is SSDR, but this is subject to change in the future, so add a bit of extra logic in the implementations of this callback to make sure both the core and the chip driver are aligned on the request. Signed-off-by: Miquel Raynal --- drivers/mtd/nand/spi/core.c | 2 +- drivers/mtd/nand/spi/winbond.c | 28 +++++++++++++++++++++------- include/linux/mtd/spinand.h | 6 ++++-- 3 files changed, 26 insertions(+), 10 deletions(-) diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c index 0d98cc1d987e1f6387f6bb243cd3720949b01b0b..044a84d7b47bf08a14f2310b971= cdc85267b0fd2 100644 --- a/drivers/mtd/nand/spi/core.c +++ b/drivers/mtd/nand/spi/core.c @@ -1521,7 +1521,7 @@ static int spinand_configure_chip(struct spinand_devi= ce *spinand) return ret; =20 if (spinand->configure_chip) { - ret =3D spinand->configure_chip(spinand); + ret =3D spinand->configure_chip(spinand, SSDR); if (ret) return ret; } diff --git a/drivers/mtd/nand/spi/winbond.c b/drivers/mtd/nand/spi/winbond.c index 1d79a8ae79206af7d823018c4603b3bd36a0dd88..419f4303a0dc7518017e2bd4225= 84813dca14d48 100644 --- a/drivers/mtd/nand/spi/winbond.c +++ b/drivers/mtd/nand/spi/winbond.c @@ -311,13 +311,17 @@ static int w25n02kv_ecc_get_status(struct spinand_dev= ice *spinand, return -EINVAL; } =20 -static int w25n0xjw_hs_cfg(struct spinand_device *spinand) +static int w25n0xjw_hs_cfg(struct spinand_device *spinand, + enum spinand_bus_interface iface) { const struct spi_mem_op *op; bool hs; u8 sr4; int ret; =20 + if (iface !=3D SSDR) + return -EOPNOTSUPP; + op =3D spinand->op_templates->read_cache; if (op->cmd.dtr || op->addr.dtr || op->dummy.dtr || op->data.dtr) hs =3D false; @@ -371,17 +375,25 @@ static int w35n0xjw_write_vcr(struct spinand_device *= spinand, u8 reg, u8 val) return 0; } =20 -static int w35n0xjw_vcr_cfg(struct spinand_device *spinand) +static int w35n0xjw_vcr_cfg(struct spinand_device *spinand, + enum spinand_bus_interface iface) { - const struct spi_mem_op *op; + const struct spi_mem_op *ref_op; unsigned int dummy_cycles; bool dtr, single; u8 io_mode; int ret; =20 - op =3D spinand->op_templates->read_cache; + switch (iface) { + case SSDR: + ref_op =3D spinand->ssdr_op_templates.read_cache; + break; + default: + return -EOPNOTSUPP; + }; =20 - dummy_cycles =3D ((op->dummy.nbytes * 8) / op->dummy.buswidth) / (op->dum= my.dtr ? 2 : 1); + dummy_cycles =3D ((ref_op->dummy.nbytes * 8) / ref_op->dummy.buswidth) / + (ref_op->dummy.dtr ? 2 : 1); switch (dummy_cycles) { case 8: case 12: @@ -398,8 +410,10 @@ static int w35n0xjw_vcr_cfg(struct spinand_device *spi= nand) if (ret) return ret; =20 - single =3D (op->cmd.buswidth =3D=3D 1 && op->addr.buswidth =3D=3D 1 && op= ->data.buswidth =3D=3D 1); - dtr =3D (op->cmd.dtr && op->addr.dtr && op->data.dtr); + single =3D (ref_op->cmd.buswidth =3D=3D 1 && + ref_op->addr.buswidth =3D=3D 1 && + ref_op->data.buswidth =3D=3D 1); + dtr =3D (ref_op->cmd.dtr && ref_op->addr.dtr && ref_op->data.dtr); if (single && !dtr) io_mode =3D W35N01JW_VCR_IO_MODE_SINGLE_SDR; else if (!single && !dtr) diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h index 7d059956c81a3a6fd337bab43fb4f1130997ab0f..94348344208861c9e1ca36bd86e= 206225cbbd816 100644 --- a/include/linux/mtd/spinand.h +++ b/include/linux/mtd/spinand.h @@ -528,7 +528,8 @@ struct spinand_info { const struct spinand_op_variants *vendor_ops; int (*select_target)(struct spinand_device *spinand, unsigned int target); - int (*configure_chip)(struct spinand_device *spinand); + int (*configure_chip)(struct spinand_device *spinand, + enum spinand_bus_interface iface); int (*set_cont_read)(struct spinand_device *spinand, bool enable); struct spinand_fact_otp fact_otp; @@ -703,7 +704,8 @@ struct spinand_device { const struct spinand_manufacturer *manufacturer; void *priv; =20 - int (*configure_chip)(struct spinand_device *spinand); + int (*configure_chip)(struct spinand_device *spinand, + enum spinand_bus_interface iface); bool cont_read_possible; int (*set_cont_read)(struct spinand_device *spinand, bool enable); --=20 2.51.0 From nobody Mon Feb 9 11:33:48 2026 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 746AD3559F7 for ; Fri, 31 Oct 2025 17:28:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="W+sBhqYb" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-04.galae.net (Postfix) with ESMTPS id 9BAAFC0E95A; Fri, 31 Oct 2025 17:28:24 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 2C41160704; Fri, 31 Oct 2025 17:28:45 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 8471311818466; Fri, 31 Oct 2025 18:28:43 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1761931724; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=r4QdbcFBCx7yyVZucPnXkIWsxV+Bp5ag9tk3sEn1mAA=; b=W+sBhqYbh0YnF2BOR9j6yWodY+F0iL6iTI1C89zODzGruf9oYX65k7aEjAwT6FyBp7qLfI laKGbTNXjRpOr8Re7HQbifnYuH7DuxZK37+BWqoLUab9vpIOpNqBKhpN1DMb9S+8lOX132 IbEPn+FdZhD5W5kNykWUNlrCKjCscdS4DNmeJpAKZ7x2K9ioYXxSrAz32dhqb5L5vlZ7qY l9urCVerHBXFWMu5tUgMBwBW6dAPdLjSd9Gvgi5v92xgTmassmRLZBGzld4ZkG1DqvoaZs 246LY/1+aQ3zB4n+Jn6t6N/7xbjUNV9DMZb2hDpdGn9pnc3XAottbEdN60D5Hg== From: Miquel Raynal Date: Fri, 31 Oct 2025 18:27:10 +0100 Subject: [PATCH 26/28] mtd: spinand: Warn if using SSDR-only vendor commands in a non SSDR mode Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251031-winbond-v6-17-rc1-oddr-v1-26-be42de23ebf1@bootlin.com> References: <20251031-winbond-v6-17-rc1-oddr-v1-0-be42de23ebf1@bootlin.com> In-Reply-To: <20251031-winbond-v6-17-rc1-oddr-v1-0-be42de23ebf1@bootlin.com> To: Mark Brown , Richard Weinberger , Vignesh Raghavendra Cc: Tudor Ambarus , Pratyush Yadav , Thomas Petazzoni , Steam Lin , Santhosh Kumar K , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Miquel Raynal X-Mailer: b4 0.14.2 X-Last-TLS-Session-Version: TLSv1.3 Both Macronix and Winbond have chip specific operations which are SSDR only. Trying to use them in an ODTR setup will fail and doing this is a pure software bug. Warn explicitly in this case. Signed-off-by: Miquel Raynal --- drivers/mtd/nand/spi/macronix.c | 2 ++ drivers/mtd/nand/spi/winbond.c | 2 ++ 2 files changed, 4 insertions(+) diff --git a/drivers/mtd/nand/spi/macronix.c b/drivers/mtd/nand/spi/macroni= x.c index 6b7cbcc6e2872d3369b8eb765dede05c7299c896..84be5e0402b5db8787178dc0a39= 901b938b0d2e1 100644 --- a/drivers/mtd/nand/spi/macronix.c +++ b/drivers/mtd/nand/spi/macronix.c @@ -53,6 +53,8 @@ static SPINAND_OP_VARIANTS(macronix_ops, static struct spi_mem_op spinand_fill_macronix_read_eccsr_op(struct spinand_device *spinand, void *= valptr) { + WARN_ON_ONCE(spinand->bus_iface !=3D SSDR); + return (struct spi_mem_op)SPINAND_MACRONIX_READ_ECCSR_1S_0_1S(valptr); } =20 diff --git a/drivers/mtd/nand/spi/winbond.c b/drivers/mtd/nand/spi/winbond.c index 419f4303a0dc7518017e2bd422584813dca14d48..90e4ece00cf5e727df87cb2367d= 9f85a2a6759bb 100644 --- a/drivers/mtd/nand/spi/winbond.c +++ b/drivers/mtd/nand/spi/winbond.c @@ -114,6 +114,8 @@ static SPINAND_OP_VARIANTS(winbond_w25_ops, static struct spi_mem_op spinand_fill_winbond_select_target_op(struct spinand_device *spinand, void= *valptr) { + WARN_ON_ONCE(spinand->bus_iface !=3D SSDR); + return (struct spi_mem_op)SPINAND_WINBOND_SELECT_TARGET_1S_0_1S(valptr); } =20 --=20 2.51.0 From nobody Mon Feb 9 11:33:48 2026 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AF9ED357700 for ; Fri, 31 Oct 2025 17:28:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.171.202.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761931730; cv=none; b=g2d3DYgMGoayKAG5N174OQYz0adkXj/VQ/U3s15vAfzH4F0H60nhPYVIzT/Y5m34HdLtlvfsUxL1TrSPMF7sI4LGHn+K6mgFnFwQn0GumRWtDlVvgqWie7xUKIS0/CGiTz9bjJkufK3eTLCKaLt14qZO9NRKMjHfvbEEn7neMCI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761931730; c=relaxed/simple; bh=0QoCBi/fXwAOetc/HsMS9hKOZdz2Nb/4WzXABWE7lxg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; 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Fri, 31 Oct 2025 17:28:46 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id C85501181800A; Fri, 31 Oct 2025 18:28:44 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1761931725; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=X001T6lzyDCorrIZ61+vmoecBHaTsVDzNT1CiH+QftQ=; b=ZBkKa4IBO+LaTZKpqiGY0u9cCP0sNFTa03C0T5uJlsgK6t1DX8oOY7EnB/cbIKuuWnPBmL 7tKn6QPwaKrJQpOmhsCiTYHCxZ00AJP348Uj3El9qtv3o6DaLtOSYP5pVwUi3fBJ4Zkhr6 6lGSzg5Tj86D2C8xxsbJtFHfBbTvAeYMob0HlnoTekEEd5KNSh59WaUrrgBJhksuOnIYnH s3DGlQk1x2OQez3FHR8VAF5OuhItasERYqGZpgCOnzCiFilnHOkunr4nFYmRwiweCCO/rh RSwWF2xHei+p9zEmK145zH5Fqovh2dwWSsDNWbB803sUz9sn/jFlfe5astTXDQ== From: Miquel Raynal Date: Fri, 31 Oct 2025 18:27:11 +0100 Subject: [PATCH 27/28] mtd: spinand: Add octal DTR support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251031-winbond-v6-17-rc1-oddr-v1-27-be42de23ebf1@bootlin.com> References: <20251031-winbond-v6-17-rc1-oddr-v1-0-be42de23ebf1@bootlin.com> In-Reply-To: <20251031-winbond-v6-17-rc1-oddr-v1-0-be42de23ebf1@bootlin.com> To: Mark Brown , Richard Weinberger , Vignesh Raghavendra Cc: Tudor Ambarus , Pratyush Yadav , Thomas Petazzoni , Steam Lin , Santhosh Kumar K , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Miquel Raynal X-Mailer: b4 0.14.2 X-Last-TLS-Session-Version: TLSv1.3 Create a new bus interface named ODTR for "octal DTR", which matches the following pattern: 8D-8D-8D. Add octal DTR support for all the existing core operations. Add a second set of templates for this bus interface. Give the possibility for drivers to register their read, write and update cache variants as well as their vendor specific operations. Check the SPI controller driver supports all the octal DTR commands that we might need before switching to the ODTR bus interface. Make the switch by calling ->configure_chip() with the ODTR parameter. Fallback in case this step fails. If someone ever attempts to suspend a chip in octal DTR mode, there are changes that it will loose its configuration at resume. Prevent any problem by explicitly switching back to SSDR while suspending. Note: there is a limitation in the current approach, page I/Os are not available as the dirmaps will be created for the ODTR bus interface if that option is supported and not switched back to SSDR during suspend. Switching them is possible but would be costly and would not bring anything as right after resuming we will switch again to ODTR. In case this capability is used for debug, developpers should mind to destroy and recreate suitable direct mappings. Finally, as a side effect, we increase the buffer for reading IDs to 6. No device at this point returns 6 bytes, but we support 5 bytes IDs, which means in octal DTR mode we have no other choice than reading an even number of bytes, hence 6. Signed-off-by: Miquel Raynal --- drivers/mtd/nand/spi/core.c | 134 ++++++++++++++++++++++++++++++++++++++++= +++- include/linux/mtd/spinand.h | 85 +++++++++++++++++++++++++++- 2 files changed, 216 insertions(+), 3 deletions(-) diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c index 044a84d7b47bf08a14f2310b971cdc85267b0fd2..49ee03a7252b8bc16e894b33293= e2fd67046bf3b 100644 --- a/drivers/mtd/nand/spi/core.c +++ b/drivers/mtd/nand/spi/core.c @@ -1307,6 +1307,11 @@ static void spinand_manufacturer_cleanup(struct spin= and_device *spinand) return spinand->manufacturer->ops->cleanup(spinand); } =20 +static bool spinand_op_is_odtr(const struct spi_mem_op *op) +{ + return op->cmd.dtr && op->cmd.buswidth =3D=3D 8; +} + static void spinand_init_ssdr_templates(struct spinand_device *spinand) { struct spinand_mem_ops *tmpl =3D &spinand->ssdr_op_templates; @@ -1339,6 +1344,10 @@ static int spinand_support_vendor_ops(struct spinand= _device *spinand, for (i =3D 0; i < info->vendor_ops->nops; i++) { const struct spi_mem_op *op =3D &info->vendor_ops->ops[i]; =20 + if ((iface =3D=3D SSDR && spinand_op_is_odtr(op)) || + (iface =3D=3D ODTR && !spinand_op_is_odtr(op))) + continue; + if (!spi_mem_supports_op(spinand->spimem, op)) return -EOPNOTSUPP; } @@ -1346,6 +1355,49 @@ static int spinand_support_vendor_ops(struct spinand= _device *spinand, return 0; } =20 +static int spinand_init_odtr_instruction_set(struct spinand_device *spinan= d) +{ + struct spinand_mem_ops *tmpl =3D &spinand->odtr_op_templates; + + tmpl->reset =3D (struct spi_mem_op)SPINAND_RESET_8D_0_0_OP; + if (!spi_mem_supports_op(spinand->spimem, &tmpl->reset)) + return -EOPNOTSUPP; + + tmpl->readid =3D (struct spi_mem_op)SPINAND_READID_8D_8D_8D_OP(0, 0, NULL= , 0); + if (!spi_mem_supports_op(spinand->spimem, &tmpl->readid)) + return -EOPNOTSUPP; + + tmpl->wr_en =3D (struct spi_mem_op)SPINAND_WR_EN_8D_0_0_OP; + if (!spi_mem_supports_op(spinand->spimem, &tmpl->wr_en)) + return -EOPNOTSUPP; + + tmpl->wr_dis =3D (struct spi_mem_op)SPINAND_WR_DIS_8D_0_0_OP; + if (!spi_mem_supports_op(spinand->spimem, &tmpl->wr_dis)) + return -EOPNOTSUPP; + + tmpl->set_feature =3D (struct spi_mem_op)SPINAND_SET_FEATURE_8D_8D_8D_OP(= 0, NULL); + if (!spi_mem_supports_op(spinand->spimem, &tmpl->set_feature)) + return -EOPNOTSUPP; + + tmpl->get_feature =3D (struct spi_mem_op)SPINAND_GET_FEATURE_8D_8D_8D_OP(= 0, NULL); + if (!spi_mem_supports_op(spinand->spimem, &tmpl->get_feature)) + return -EOPNOTSUPP; + + tmpl->blk_erase =3D (struct spi_mem_op)SPINAND_BLK_ERASE_8D_8D_0_OP(0); + if (!spi_mem_supports_op(spinand->spimem, &tmpl->blk_erase)) + return -EOPNOTSUPP; + + tmpl->page_read =3D (struct spi_mem_op)SPINAND_PAGE_READ_8D_8D_0_OP(0); + if (!spi_mem_supports_op(spinand->spimem, &tmpl->page_read)) + return -EOPNOTSUPP; + + tmpl->prog_exec =3D (struct spi_mem_op)SPINAND_PROG_EXEC_8D_8D_0_OP(0); + if (!spi_mem_supports_op(spinand->spimem, &tmpl->prog_exec)) + return -EOPNOTSUPP; + + return 0; +} + static const struct spi_mem_op * spinand_select_op_variant(struct spinand_device *spinand, enum spinand_bus= _interface iface, const struct spinand_op_variants *variants) @@ -1361,6 +1413,10 @@ spinand_select_op_variant(struct spinand_device *spi= nand, enum spinand_bus_inter unsigned int nbytes; int ret; =20 + if ((iface =3D=3D SSDR && spinand_op_is_odtr(&op)) || + (iface =3D=3D ODTR && !spinand_op_is_odtr(&op))) + continue; + nbytes =3D nanddev_per_page_oobsize(nand) + nanddev_page_size(nand); =20 @@ -1440,6 +1496,8 @@ int spinand_match_and_init(struct spinand_device *spi= nand, spinand->read_retries =3D table[i].read_retries; spinand->set_read_retry =3D table[i].set_read_retry; =20 + /* I/O variants selection with single-spi SDR commands */ + op =3D spinand_select_op_variant(spinand, SSDR, info->op_variants.read_cache); if (!op) @@ -1465,6 +1523,28 @@ int spinand_match_and_init(struct spinand_device *sp= inand, if (ret) return ret; =20 + /* I/O variants selection with octo-spi DDR commands (optional) */ + + ret =3D spinand_init_odtr_instruction_set(spinand); + if (ret) + return 0; + + ret =3D spinand_support_vendor_ops(spinand, info, ODTR); + if (ret) + return 0; + + op =3D spinand_select_op_variant(spinand, ODTR, + info->op_variants.read_cache); + spinand->odtr_op_templates.read_cache =3D op; + + op =3D spinand_select_op_variant(spinand, ODTR, + info->op_variants.write_cache); + spinand->odtr_op_templates.write_cache =3D op; + + op =3D spinand_select_op_variant(spinand, ODTR, + info->op_variants.update_cache); + spinand->odtr_op_templates.update_cache =3D op; + return 0; } =20 @@ -1506,9 +1586,34 @@ static int spinand_detect(struct spinand_device *spi= nand) =20 static int spinand_configure_chip(struct spinand_device *spinand) { - bool quad_enable =3D false; + bool odtr =3D false, quad_enable =3D false; int ret; =20 + if (spinand->odtr_op_templates.read_cache && + spinand->odtr_op_templates.write_cache && + spinand->odtr_op_templates.update_cache) + odtr =3D true; + + if (odtr) { + if (!spinand->configure_chip) + goto try_ssdr; + + /* ODTR bus interface configuration happens here */ + ret =3D spinand->configure_chip(spinand, ODTR); + if (ret) { + spinand->odtr_op_templates.read_cache =3D NULL; + spinand->odtr_op_templates.write_cache =3D NULL; + spinand->odtr_op_templates.update_cache =3D NULL; + goto try_ssdr; + } + + spinand->op_templates =3D &spinand->odtr_op_templates; + spinand->bus_iface =3D ODTR; + + return 0; + } + +try_ssdr: if (spinand->flags & SPINAND_HAS_QE_BIT) { if (spinand->ssdr_op_templates.read_cache->data.buswidth =3D=3D 4 || spinand->ssdr_op_templates.write_cache->data.buswidth =3D=3D 4 || @@ -1590,6 +1695,32 @@ static void spinand_mtd_resume(struct mtd_info *mtd) spinand_ecc_enable(spinand, false); } =20 +static int spinand_mtd_suspend(struct mtd_info *mtd) +{ + struct spinand_device *spinand =3D mtd_to_spinand(mtd); + int ret; + + /* + * Return to SSDR interface in the suspend path to make sure the + * reset operation is correctly processed upon resume. + * + * Note: Once back in SSDR mode, every operation but the page helpers + * (dirmap based I/O accessors) will work. Page accesses would require + * destroying and recreating the dirmaps twice to work, which would be + * impacting for no reason, as this is just a transitional state. + */ + if (spinand->bus_iface =3D=3D ODTR) { + ret =3D spinand->configure_chip(spinand, SSDR); + if (ret) + return ret; + + spinand->op_templates =3D &spinand->ssdr_op_templates; + spinand->bus_iface =3D SSDR; + } + + return 0; +} + static int spinand_init(struct spinand_device *spinand) { struct device *dev =3D &spinand->spimem->spi->dev; @@ -1659,6 +1790,7 @@ static int spinand_init(struct spinand_device *spinan= d) mtd->_block_isreserved =3D spinand_mtd_block_isreserved; mtd->_erase =3D spinand_mtd_erase; mtd->_max_bad_blocks =3D nanddev_mtd_max_bad_blocks; + mtd->_suspend =3D spinand_mtd_suspend; mtd->_resume =3D spinand_mtd_resume; =20 if (spinand_user_otp_size(spinand) || spinand_fact_otp_size(spinand)) { diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h index 94348344208861c9e1ca36bd86e206225cbbd816..eb8ae164b3aa21398636e347fbf= 810d49d62ff7d 100644 --- a/include/linux/mtd/spinand.h +++ b/include/linux/mtd/spinand.h @@ -238,6 +238,77 @@ SPI_MEM_OP_NO_DUMMY, \ SPI_MEM_OP_DATA_OUT(len, buf, 8)) =20 +/** + * Octal DDR SPI NAND flash operations + */ + +#define SPINAND_RESET_8D_0_0_OP \ + SPI_MEM_OP(SPI_MEM_DTR_OP_RPT_CMD(0xff, 8), \ + SPI_MEM_OP_NO_ADDR, \ + SPI_MEM_OP_NO_DUMMY, \ + SPI_MEM_OP_NO_DATA) + +#define SPINAND_READID_8D_8D_8D_OP(naddr, ndummy, buf, len) \ + SPI_MEM_OP(SPI_MEM_DTR_OP_RPT_CMD(0x9f, 8), \ + SPI_MEM_DTR_OP_ADDR(naddr, 0, 8), \ + SPI_MEM_DTR_OP_DUMMY(ndummy, 8), \ + SPI_MEM_DTR_OP_DATA_IN(len, buf, 8)) + +#define SPINAND_WR_EN_8D_0_0_OP \ + SPI_MEM_OP(SPI_MEM_DTR_OP_RPT_CMD(0x06, 8), \ + SPI_MEM_OP_NO_ADDR, \ + SPI_MEM_OP_NO_DUMMY, \ + SPI_MEM_OP_NO_DATA) + +#define SPINAND_WR_DIS_8D_0_0_OP \ + SPI_MEM_OP(SPI_MEM_DTR_OP_RPT_CMD(0x04, 8), \ + SPI_MEM_OP_NO_ADDR, \ + SPI_MEM_OP_NO_DUMMY, \ + SPI_MEM_OP_NO_DATA) + +#define SPINAND_SET_FEATURE_8D_8D_8D_OP(reg, valptr) \ + SPI_MEM_OP(SPI_MEM_DTR_OP_RPT_CMD(0x1f, 8), \ + SPI_MEM_DTR_OP_RPT_ADDR(reg, 8), \ + SPI_MEM_OP_NO_DUMMY, \ + SPI_MEM_DTR_OP_DATA_OUT(2, valptr, 8)) + +#define SPINAND_GET_FEATURE_8D_8D_8D_OP(reg, valptr) \ + SPI_MEM_OP(SPI_MEM_DTR_OP_RPT_CMD(0x0f, 8), \ + SPI_MEM_DTR_OP_RPT_ADDR(reg, 8), \ + SPI_MEM_DTR_OP_DUMMY(14, 8), \ + SPI_MEM_DTR_OP_DATA_IN(2, valptr, 8)) + +#define SPINAND_BLK_ERASE_8D_8D_0_OP(addr) \ + SPI_MEM_OP(SPI_MEM_DTR_OP_RPT_CMD(0xd8, 8), \ + SPI_MEM_DTR_OP_ADDR(2, addr, 8), \ + SPI_MEM_OP_NO_DUMMY, \ + SPI_MEM_OP_NO_DATA) + +#define SPINAND_PAGE_READ_8D_8D_0_OP(addr) \ + SPI_MEM_OP(SPI_MEM_DTR_OP_RPT_CMD(0x13, 8), \ + SPI_MEM_DTR_OP_ADDR(2, addr, 8), \ + SPI_MEM_OP_NO_DUMMY, \ + SPI_MEM_OP_NO_DATA) + +#define SPINAND_PAGE_READ_FROM_CACHE_8D_8D_8D_OP(addr, ndummy, buf, len, f= req) \ + SPI_MEM_OP(SPI_MEM_DTR_OP_RPT_CMD(0x9d, 8), \ + SPI_MEM_DTR_OP_ADDR(2, addr, 8), \ + SPI_MEM_DTR_OP_DUMMY(ndummy, 8), \ + SPI_MEM_DTR_OP_DATA_IN(len, buf, 8), \ + SPI_MEM_OP_MAX_FREQ(freq)) + +#define SPINAND_PROG_EXEC_8D_8D_0_OP(addr) \ + SPI_MEM_OP(SPI_MEM_DTR_OP_RPT_CMD(0x10, 8), \ + SPI_MEM_DTR_OP_ADDR(2, addr, 8), \ + SPI_MEM_OP_NO_DUMMY, \ + SPI_MEM_OP_NO_DATA) + +#define SPINAND_PROG_LOAD_8D_8D_8D_OP(reset, addr, buf, len) \ + SPI_MEM_OP(SPI_MEM_DTR_OP_RPT_CMD((reset ? 0xc2 : 0xc4), 8), \ + SPI_MEM_DTR_OP_ADDR(2, addr, 8), \ + SPI_MEM_OP_NO_DUMMY, \ + SPI_MEM_DTR_OP_DATA_OUT(len, buf, 8)) + /* feature register */ #define REG_BLOCK_LOCK 0xa0 #define BL_ALL_UNLOCKED 0x00 @@ -261,7 +332,7 @@ struct spinand_op; struct spinand_device; =20 -#define SPINAND_MAX_ID_LEN 5 +#define SPINAND_MAX_ID_LEN 6 /* * For erase, write and read operation, we got the following timings : * tBERS (erase) 1ms to 4ms @@ -287,7 +358,7 @@ struct spinand_device; =20 /** * struct spinand_id - SPI NAND id structure - * @data: buffer containing the id bytes. Currently 5 bytes large, but can + * @data: buffer containing the id bytes. Currently 6 bytes large, but can * be extended if required * @len: ID length */ @@ -483,9 +554,11 @@ struct spinand_user_otp { /** * enum spinand_bus_interface - SPI NAND bus interface types * @SSDR: Bus configuration supporting all 1S-XX-XX operations, including = dual and quad + * @ODTR: Bus configuration supporting only 8D-8D-8D operations */ enum spinand_bus_interface { SSDR, + ODTR, }; =20 /** @@ -650,6 +723,7 @@ struct spinand_mem_ops { * @id: NAND ID as returned by READ_ID * @flags: NAND flags * @ssdr_op_templates: Templates for all single SDR SPI mem operations + * @odtr_op_templates: Templates for all octal DTR SPI mem operations * @op_templates: Templates for all SPI mem operations * @bus_iface: Current bus interface * @select_target: select a specific target/die. Usually called before sen= ding @@ -686,6 +760,7 @@ struct spinand_device { u32 flags; =20 struct spinand_mem_ops ssdr_op_templates; + struct spinand_mem_ops odtr_op_templates; struct spinand_mem_ops *op_templates; enum spinand_bus_interface bus_iface; =20 @@ -755,6 +830,9 @@ spinand_fill_set_feature_op(struct spinand_device *spin= and, u64 reg, const void { struct spi_mem_op op =3D spinand->op_templates->set_feature; =20 + if (op.cmd.dtr && op.cmd.buswidth =3D=3D 8) + reg |=3D reg << 8; + op.addr.val =3D reg; op.data.buf.out =3D valptr; =20 @@ -766,6 +844,9 @@ spinand_fill_get_feature_op(struct spinand_device *spin= and, u64 reg, void *valpt { struct spi_mem_op op =3D spinand->op_templates->get_feature; =20 + if (op.cmd.dtr && op.cmd.buswidth =3D=3D 8) + reg |=3D reg << 8; + op.addr.val =3D reg; op.data.buf.in =3D valptr; =20 --=20 2.51.0 From nobody Mon Feb 9 11:33:48 2026 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1F3CB35773E for ; Fri, 31 Oct 2025 17:28:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.85.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761931730; cv=none; b=re3KdGpQW7MEjyAqYZB8sf0BPke8ex8Tzek6Mn1tXwq8/8Yj2Ni3Xdak2EFLvu+1c7mgxyy301+L1B9t8mn5A3/+vuVsPI3hFqLnRsOxYyxbSax0KX9AYSHYSRStNQq776o/p6cqBy9+bdBH6NZ/zidSBohVEW1BTAqKPAffNRA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761931730; c=relaxed/simple; bh=e9FC+3UzvkjqWZ+ix07WU+iFe6vTYQmUx/syuc42dF0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=CrfwMQ9yzX8qPOGDKN04x6J6k/fjn18hL0RRoMV+9RA2Ri1wc+vd+0ZE4/wRm1oMoFY6dhTnkI6WC1dAIZFtwzqc68oHMFjwBhtuoFZxdPICpIBIzcVzKKfT88QHWho/bEX8WGBDg6v/YKAQObyzuDUk6CJP6lOTBDcUxiTF+Oc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=Vncpdjk7; arc=none smtp.client-ip=185.246.85.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="Vncpdjk7" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-03.galae.net (Postfix) with ESMTPS id A91594E4143F; Fri, 31 Oct 2025 17:28:47 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 7F16360704; Fri, 31 Oct 2025 17:28:47 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 0D1F011818007; Fri, 31 Oct 2025 18:28:45 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1761931726; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=Yqsm5byi+NRPnRhNkd8UBM/Bmv6Ofu8I+HrZRoBLCI0=; b=Vncpdjk72ik/OAK7vIr+QdHzNB7KIZeweosE6fE9DJRk/oLB1X2XDCYOzOdCCSK7hpuIJS 6pbUX//afKCvZVnkDCtmN480fbGITJFS/X2fVGGEDckMaE+2dntQvo+l9D3s74DEZf7AzJ KCm76pLqqO3+GxlXoCczI+Sf1Qp4sKr75ZGhRqGgSw5A5aXNHanWDRuxmbJgTjeBEG4PZb 3pVYOMO95HZOL2m+R+dAgC8w/0EkYOpZnRlQ+qN64e2R/OgqmN7xwAc22vQ48pKZm8EYke 1LePAD795uNNNyBM64E7koiaGE23wn5NwasJkrKAqBJKA0V9vW1QPU9f90vg/g== From: Miquel Raynal Date: Fri, 31 Oct 2025 18:27:12 +0100 Subject: [PATCH 28/28] mtd: spinand: winbond: W35N octal DTR support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251031-winbond-v6-17-rc1-oddr-v1-28-be42de23ebf1@bootlin.com> References: <20251031-winbond-v6-17-rc1-oddr-v1-0-be42de23ebf1@bootlin.com> In-Reply-To: <20251031-winbond-v6-17-rc1-oddr-v1-0-be42de23ebf1@bootlin.com> To: Mark Brown , Richard Weinberger , Vignesh Raghavendra Cc: Tudor Ambarus , Pratyush Yadav , Thomas Petazzoni , Steam Lin , Santhosh Kumar K , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Miquel Raynal X-Mailer: b4 0.14.2 X-Last-TLS-Session-Version: TLSv1.3 Extend the support for the W35N chip family by supporting the ODTR bus interface. The chip is capable to run in this mode, which brings a significant performance improvement. 1S-8S-8S: # flash_speed /dev/mtd0 -c1 -d eraseblock write speed is 7529 KiB/s eraseblock read speed is 15058 KiB/s 8D-8D-8D: # flash_speed /dev/mtd0 -c1 -d eraseblock write speed is 9481 KiB/s eraseblock read speed is 23272 KiB/s This is +55% read speed and +26% write speed with the same hardware. Tests have been conducted with a TI AM62A7 using the Cadence quad SPI controller. Signed-off-by: Miquel Raynal --- drivers/mtd/nand/spi/winbond.c | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/nand/spi/winbond.c b/drivers/mtd/nand/spi/winbond.c index 90e4ece00cf5e727df87cb2367d9f85a2a6759bb..8430ae307be0fefded8e2710940= 3a59b9b17b089 100644 --- a/drivers/mtd/nand/spi/winbond.c +++ b/drivers/mtd/nand/spi/winbond.c @@ -36,6 +36,8 @@ */ =20 static SPINAND_OP_VARIANTS(read_cache_octal_variants, + SPINAND_PAGE_READ_FROM_CACHE_8D_8D_8D_OP(0, 24, NULL, 0, 120 * HZ_PER_MH= Z), + SPINAND_PAGE_READ_FROM_CACHE_8D_8D_8D_OP(0, 16, NULL, 0, 86 * HZ_PER_MHZ= ), SPINAND_PAGE_READ_FROM_CACHE_1S_1D_8D_OP(0, 3, NULL, 0, 120 * HZ_PER_MHZ= ), SPINAND_PAGE_READ_FROM_CACHE_1S_1D_8D_OP(0, 2, NULL, 0, 105 * HZ_PER_MHZ= ), SPINAND_PAGE_READ_FROM_CACHE_1S_8S_8S_OP(0, 20, NULL, 0, 0), @@ -48,11 +50,13 @@ static SPINAND_OP_VARIANTS(read_cache_octal_variants, SPINAND_PAGE_READ_FROM_CACHE_1S_1S_1S_OP(0, 1, NULL, 0, 0)); =20 static SPINAND_OP_VARIANTS(write_cache_octal_variants, + SPINAND_PROG_LOAD_8D_8D_8D_OP(true, 0, NULL, 0), SPINAND_PROG_LOAD_1S_8S_8S_OP(true, 0, NULL, 0), SPINAND_PROG_LOAD_1S_1S_8S_OP(0, NULL, 0), SPINAND_PROG_LOAD_1S_1S_1S_OP(true, 0, NULL, 0)); =20 static SPINAND_OP_VARIANTS(update_cache_octal_variants, + SPINAND_PROG_LOAD_8D_8D_8D_OP(false, 0, NULL, 0), SPINAND_PROG_LOAD_1S_8S_8S_OP(false, 0, NULL, 0), SPINAND_PROG_LOAD_1S_1S_1S_OP(false, 0, NULL, 0)); =20 @@ -93,13 +97,22 @@ static SPINAND_OP_VARIANTS(update_cache_variants, SPI_MEM_OP_NO_DUMMY, \ SPI_MEM_OP_DATA_OUT(1, buf, 1)) =20 +#define SPINAND_WINBOND_WRITE_VCR_8D_8D_8D(reg, buf) \ + SPI_MEM_OP(SPI_MEM_DTR_OP_RPT_CMD(0x81, 8), \ + SPI_MEM_DTR_OP_ADDR(4, reg, 8), \ + SPI_MEM_OP_NO_DUMMY, \ + SPI_MEM_DTR_OP_DATA_OUT(2, buf, 8)) + static SPINAND_OP_VARIANTS(winbond_w35_ops, - SPINAND_WINBOND_WRITE_VCR_1S_1S_1S(0, NULL)); + SPINAND_WINBOND_WRITE_VCR_1S_1S_1S(0, NULL), + SPINAND_WINBOND_WRITE_VCR_8D_8D_8D(0, NULL)); =20 static struct spi_mem_op spinand_fill_winbond_write_vcr_op(struct spinand_device *spinand, u8 reg, = void *valptr) { - return (struct spi_mem_op)SPINAND_WINBOND_WRITE_VCR_1S_1S_1S(reg, valptr); + return (spinand->bus_iface =3D=3D SSDR) ? + (struct spi_mem_op)SPINAND_WINBOND_WRITE_VCR_1S_1S_1S(reg, valptr) : + (struct spi_mem_op)SPINAND_WINBOND_WRITE_VCR_8D_8D_8D(reg, valptr); } =20 #define SPINAND_WINBOND_SELECT_TARGET_1S_0_1S(buf) \ @@ -390,6 +403,9 @@ static int w35n0xjw_vcr_cfg(struct spinand_device *spin= and, case SSDR: ref_op =3D spinand->ssdr_op_templates.read_cache; break; + case ODTR: + ref_op =3D spinand->odtr_op_templates.read_cache; + break; default: return -EOPNOTSUPP; }; --=20 2.51.0