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Fri, 31 Oct 2025 03:02:50 -0700 (PDT) Received: from hu-tdas-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7a7db0a0219sm1609360b3a.37.2025.10.31.03.02.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 31 Oct 2025 03:02:50 -0700 (PDT) From: Taniya Das Date: Fri, 31 Oct 2025 15:32:25 +0530 Subject: [PATCH] clk: qcom: tcsrcc-glymur: Update register offsets for clock refs Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251031-tcsrcc_glymur-v1-1-0efb031f0ac5@oss.qualcomm.com> X-B4-Tracking: v=1; b=H4sIADCJBGkC/6tWKk4tykwtVrJSqFYqSi3LLM7MzwNyDHUUlJIzE vPSU3UzU4B8JSMDI1NDA2MD3ZLk4qLk5Pj0nMrc0iLdlBQDC0MLU/OUJBMzJaCegqLUtMwKsHn RsbW1AGXx2H9fAAAA X-Change-ID: 20251030-tcsrcc_glymur-dd081857db46 To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Abel Vesa , Dmitry Baryshkov Cc: Rajendra Nayak , Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Taniya Das X-Mailer: b4 0.15-dev-aa3f6 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDMxMDA5MSBTYWx0ZWRfXzOwl+jx+bdMG ZpL3tua5tQTHXiB8N09Gj60T6Nt4fPchawyGapXSKHSMMOaqUiGa+Z5pgWvKdYo3Tyd7CMLmaK9 rs3vpsSRi0rqCKiZQbkWnd/kE2Wj+fOzYjUDTVKmEm1+Gm5TrNSyt+Irq4ILB8RwNx8fhXIHDMp sm3SctNslwndl0jiC6NqqSongNmxZDDaMhaZPTUIW04QfOTz/ZHPlbB4XmdmNQZMLHeGwlbEnXU BjkLOPEQZENicvMp9EW1OxfwXttxhLF0K8jE5KL9ZNi9YthIlwnp4sR92dSGChvnbTcUMiLIuFe oZ7nEPBIjEjFDEB0CSKEGrFe1SC9Kuf4+QcRInpgaL6lcnvukCxgCfWY21RHDRU4Vjt7QC3NbB5 Mp3safDdSNci7f4kmpJ8WHMnGyJs8Q== X-Authority-Analysis: v=2.4 cv=Q8PfIo2a c=1 sm=1 tr=0 ts=6904894c cx=c_pps a=WW5sKcV1LcKqjgzy2JUPuA==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=x6icFKpwvdMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=fnDjtfwCBqzf7SSwl4wA:9 a=QEXdDO2ut3YA:10 a=OpyuDcXvxspvyRM73sMx:22 X-Proofpoint-ORIG-GUID: idmL8kY41-RH1B19xgVKbV4-4UbsJjus X-Proofpoint-GUID: idmL8kY41-RH1B19xgVKbV4-4UbsJjus X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-10-31_02,2025-10-29_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 priorityscore=1501 adultscore=0 malwarescore=0 suspectscore=0 spamscore=0 lowpriorityscore=0 impostorscore=0 phishscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2510310091 Update the register offsets for all the clock ref branches to match the new address mapping in the TCSR subsystem. Fixes: 2c1d6ce4f3da ("clk: qcom: Add TCSR clock driver for Glymur SoC") Signed-off-by: Taniya Das Reviewed-by: Abel Vesa Tested-by: Jagadeesh Kona --- drivers/clk/qcom/tcsrcc-glymur.c | 54 ++++++++++++++++++++----------------= ---- 1 file changed, 27 insertions(+), 27 deletions(-) diff --git a/drivers/clk/qcom/tcsrcc-glymur.c b/drivers/clk/qcom/tcsrcc-gly= mur.c index c1f8b6d10b7fd6eaef0149843594fc7eb6a620ec..215bc2ac548da83aec23921ef9a= 4bd59b6b307bc 100644 --- a/drivers/clk/qcom/tcsrcc-glymur.c +++ b/drivers/clk/qcom/tcsrcc-glymur.c @@ -28,10 +28,10 @@ enum { }; =20 static struct clk_branch tcsr_edp_clkref_en =3D { - .halt_reg =3D 0x1c, + .halt_reg =3D 0x60, .halt_check =3D BRANCH_HALT_DELAY, .clkr =3D { - .enable_reg =3D 0x1c, + .enable_reg =3D 0x60, .enable_mask =3D BIT(0), .hw.init =3D &(const struct clk_init_data) { .name =3D "tcsr_edp_clkref_en", @@ -45,10 +45,10 @@ static struct clk_branch tcsr_edp_clkref_en =3D { }; =20 static struct clk_branch tcsr_pcie_1_clkref_en =3D { - .halt_reg =3D 0x4, + .halt_reg =3D 0x48, .halt_check =3D BRANCH_HALT_DELAY, .clkr =3D { - .enable_reg =3D 0x4, + .enable_reg =3D 0x48, .enable_mask =3D BIT(0), .hw.init =3D &(const struct clk_init_data) { .name =3D "tcsr_pcie_1_clkref_en", @@ -62,10 +62,10 @@ static struct clk_branch tcsr_pcie_1_clkref_en =3D { }; =20 static struct clk_branch tcsr_pcie_2_clkref_en =3D { - .halt_reg =3D 0x8, + .halt_reg =3D 0x4c, .halt_check =3D BRANCH_HALT_DELAY, .clkr =3D { - .enable_reg =3D 0x8, + .enable_reg =3D 0x4c, .enable_mask =3D BIT(0), .hw.init =3D &(const struct clk_init_data) { .name =3D "tcsr_pcie_2_clkref_en", @@ -79,10 +79,10 @@ static struct clk_branch tcsr_pcie_2_clkref_en =3D { }; =20 static struct clk_branch tcsr_pcie_3_clkref_en =3D { - .halt_reg =3D 0x10, + .halt_reg =3D 0x54, .halt_check =3D BRANCH_HALT_DELAY, .clkr =3D { - .enable_reg =3D 0x10, + .enable_reg =3D 0x54, .enable_mask =3D BIT(0), .hw.init =3D &(const struct clk_init_data) { .name =3D "tcsr_pcie_3_clkref_en", @@ -96,10 +96,10 @@ static struct clk_branch tcsr_pcie_3_clkref_en =3D { }; =20 static struct clk_branch tcsr_pcie_4_clkref_en =3D { - .halt_reg =3D 0x14, + .halt_reg =3D 0x58, .halt_check =3D BRANCH_HALT_DELAY, .clkr =3D { - .enable_reg =3D 0x14, + .enable_reg =3D 0x58, .enable_mask =3D BIT(0), .hw.init =3D &(const struct clk_init_data) { .name =3D "tcsr_pcie_4_clkref_en", @@ -113,10 +113,10 @@ static struct clk_branch tcsr_pcie_4_clkref_en =3D { }; =20 static struct clk_branch tcsr_usb2_1_clkref_en =3D { - .halt_reg =3D 0x28, + .halt_reg =3D 0x6c, .halt_check =3D BRANCH_HALT_DELAY, .clkr =3D { - .enable_reg =3D 0x28, + .enable_reg =3D 0x6c, .enable_mask =3D BIT(0), .hw.init =3D &(const struct clk_init_data) { .name =3D "tcsr_usb2_1_clkref_en", @@ -130,10 +130,10 @@ static struct clk_branch tcsr_usb2_1_clkref_en =3D { }; =20 static struct clk_branch tcsr_usb2_2_clkref_en =3D { - .halt_reg =3D 0x2c, + .halt_reg =3D 0x70, .halt_check =3D BRANCH_HALT_DELAY, .clkr =3D { - .enable_reg =3D 0x2c, + .enable_reg =3D 0x70, .enable_mask =3D BIT(0), .hw.init =3D &(const struct clk_init_data) { .name =3D "tcsr_usb2_2_clkref_en", @@ -147,10 +147,10 @@ static struct clk_branch tcsr_usb2_2_clkref_en =3D { }; =20 static struct clk_branch tcsr_usb2_3_clkref_en =3D { - .halt_reg =3D 0x30, + .halt_reg =3D 0x74, .halt_check =3D BRANCH_HALT_DELAY, .clkr =3D { - .enable_reg =3D 0x30, + .enable_reg =3D 0x74, .enable_mask =3D BIT(0), .hw.init =3D &(const struct clk_init_data) { .name =3D "tcsr_usb2_3_clkref_en", @@ -164,10 +164,10 @@ static struct clk_branch tcsr_usb2_3_clkref_en =3D { }; =20 static struct clk_branch tcsr_usb2_4_clkref_en =3D { - .halt_reg =3D 0x44, + .halt_reg =3D 0x88, .halt_check =3D BRANCH_HALT_DELAY, .clkr =3D { - .enable_reg =3D 0x44, + .enable_reg =3D 0x88, .enable_mask =3D BIT(0), .hw.init =3D &(const struct clk_init_data) { .name =3D "tcsr_usb2_4_clkref_en", @@ -181,10 +181,10 @@ static struct clk_branch tcsr_usb2_4_clkref_en =3D { }; =20 static struct clk_branch tcsr_usb3_0_clkref_en =3D { - .halt_reg =3D 0x20, + .halt_reg =3D 0x64, .halt_check =3D BRANCH_HALT_DELAY, .clkr =3D { - .enable_reg =3D 0x20, + .enable_reg =3D 0x64, .enable_mask =3D BIT(0), .hw.init =3D &(const struct clk_init_data) { .name =3D "tcsr_usb3_0_clkref_en", @@ -198,10 +198,10 @@ static struct clk_branch tcsr_usb3_0_clkref_en =3D { }; =20 static struct clk_branch tcsr_usb3_1_clkref_en =3D { - .halt_reg =3D 0x24, + .halt_reg =3D 0x68, .halt_check =3D BRANCH_HALT_DELAY, .clkr =3D { - .enable_reg =3D 0x24, + .enable_reg =3D 0x68, .enable_mask =3D BIT(0), .hw.init =3D &(const struct clk_init_data) { .name =3D "tcsr_usb3_1_clkref_en", @@ -215,10 +215,10 @@ static struct clk_branch tcsr_usb3_1_clkref_en =3D { }; =20 static struct clk_branch tcsr_usb4_1_clkref_en =3D { - .halt_reg =3D 0x0, + .halt_reg =3D 0x44, .halt_check =3D BRANCH_HALT_DELAY, .clkr =3D { - .enable_reg =3D 0x0, + .enable_reg =3D 0x44, .enable_mask =3D BIT(0), .hw.init =3D &(const struct clk_init_data) { .name =3D "tcsr_usb4_1_clkref_en", @@ -232,10 +232,10 @@ static struct clk_branch tcsr_usb4_1_clkref_en =3D { }; =20 static struct clk_branch tcsr_usb4_2_clkref_en =3D { - .halt_reg =3D 0x18, + .halt_reg =3D 0x5c, .halt_check =3D BRANCH_HALT_DELAY, .clkr =3D { - .enable_reg =3D 0x18, + .enable_reg =3D 0x5c, .enable_mask =3D BIT(0), .hw.init =3D &(const struct clk_init_data) { .name =3D "tcsr_usb4_2_clkref_en", @@ -268,7 +268,7 @@ static const struct regmap_config tcsr_cc_glymur_regmap= _config =3D { .reg_bits =3D 32, .reg_stride =3D 4, .val_bits =3D 32, - .max_register =3D 0x44, + .max_register =3D 0x94, .fast_io =3D true, }; =20 --- base-commit: 131f3d9446a6075192cdd91f197989d98302faa6 change-id: 20251030-tcsrcc_glymur-dd081857db46 Best regards, --=20 Taniya Das