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Reviewed-by: Rob Herring (Arm) Acked-by: Manivannan Sadhasivam Signed-off-by: Krishna Chaitanya Chundru --- .../devicetree/bindings/pci/toshiba,tc9563.yaml | 178 +++++++++++++++++= ++++ 1 file changed, 178 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/toshiba,tc9563.yaml b/Do= cumentation/devicetree/bindings/pci/toshiba,tc9563.yaml new file mode 100644 index 0000000000000000000000000000000000000000..a957a4bc38d6c91a13797f848b0= e2faa64eb02f5 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/toshiba,tc9563.yaml @@ -0,0 +1,178 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/toshiba,tc9563.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Toshiba TC9563 PCIe switch + +maintainers: + - rishna Chaitanya Chundru + +description: | + Toshiba TC9563 PCIe switch has one upstream and three downstream ports. + The 3rd downstream port has integrated endpoint device of Ethernet MAC. + Other two downstream ports are supposed to connect to external device. + + The TC9563 PCIe switch can be configured through I2C interface before + PCIe link is established to change FTS, ASPM related entry delays, + tx amplitude etc for better power efficiency and functionality. + +properties: + compatible: + enum: + - pci1179,0623 + + reg: + maxItems: 1 + + resx-gpios: + maxItems: 1 + description: + GPIO controlling the RESX# pin. + + vdd18-supply: true + + vdd09-supply: true + + vddc-supply: true + + vddio1-supply: true + + vddio2-supply: true + + vddio18-supply: true + + i2c-parent: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: + A phandle to the parent I2C node and the slave address of the device + used to do configure tc9563 to change FTS, tx amplitude etc. + items: + - description: Phandle to the I2C controller node + - description: I2C slave address + +patternProperties: + "^pcie@[1-3],0$": + description: + child nodes describing the internal downstream ports + the tc9563 switch. + type: object + allOf: + - $ref: "#/$defs/tc9563-node" + - $ref: /schemas/pci/pci-pci-bridge.yaml# + unevaluatedProperties: false + +$defs: + tc9563-node: + type: object + + properties: + toshiba,tx-amplitude-microvolt: + description: + Change Tx Margin setting for low power consumption. + + toshiba,no-dfe-support: + type: boolean + description: + Disable DFE (Decision Feedback Equalizer), which mitigates + intersymbol interference and some reflections caused by impedanc= e mismatches. + +required: + - resx-gpios + - vdd18-supply + - vdd09-supply + - vddc-supply + - vddio1-supply + - vddio2-supply + - vddio18-supply + - i2c-parent + +allOf: + - $ref: "#/$defs/tc9563-node" + - $ref: /schemas/pci/pci-bus-common.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + + pcie { + #address-cells =3D <3>; + #size-cells =3D <2>; + + pcie@0 { + device_type =3D "pci"; + reg =3D <0x0 0x0 0x0 0x0 0x0>; + + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges; + bus-range =3D <0x01 0xff>; + + pcie@0,0 { + compatible =3D "pci1179,0623"; + + reg =3D <0x10000 0x0 0x0 0x0 0x0>; + device_type =3D "pci"; + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges; + bus-range =3D <0x02 0xff>; + + i2c-parent =3D <&qup_i2c 0x77>; + + vdd18-supply =3D <&vdd>; + vdd09-supply =3D <&vdd>; + vddc-supply =3D <&vdd>; + vddio1-supply =3D <&vdd>; + vddio2-supply =3D <&vdd>; + vddio18-supply =3D <&vdd>; + + resx-gpios =3D <&gpio 1 GPIO_ACTIVE_LOW>; + + pcie@1,0 { + compatible =3D "pciclass,0604"; + reg =3D <0x20800 0x0 0x0 0x0 0x0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + device_type =3D "pci"; + ranges; + bus-range =3D <0x03 0xff>; + + toshiba,no-dfe-support; + }; + + pcie@2,0 { + compatible =3D "pciclass,0604"; + reg =3D <0x21000 0x0 0x0 0x0 0x0>; + #address-cells =3D <3>; + #size-cells =3D <2>; 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When the PCI bridge is found, its child DT nodes will be scanned and pwrctrl devices will be created if needed. By the time pwrctrl driver probe gets called link training is already enabled by controller driver. Certain devices like TC956x which uses PCI pwrctl framework needs to configure the device before PCI link is up. As the controller driver already enables link training as part of its probe, the moment device is powered on, controller and device participates in the link training and link can come up immediately and may not have time to configure the device. So we need to stop the link training by using assert_perst() by asserting the PERST# and de-assert the PERST# after device is configured. Signed-off-by: Krishna Chaitanya Chundru --- include/linux/pci.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/linux/pci.h b/include/linux/pci.h index d1fdf81fbe1e427aecbc951fa3fdf65c20450b05..ed5dac663e96e3a6ad2edffffc9= fa8b348d0a677 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -829,6 +829,7 @@ struct pci_ops { void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int whe= re); int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size,= u32 *val); int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size= , u32 val); + int (*assert_perst)(struct pci_bus *bus, bool assert); }; =20 /* --=20 2.34.1 From nobody Sun Feb 8 10:44:09 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A4313346E55 for ; Fri, 31 Oct 2025 11:12:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Signed-off-by: Krishna Chaitanya Chundru --- drivers/pci/controller/dwc/pcie-designware.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/con= troller/dwc/pcie-designware.h index e995f692a1ecd10130d3be3358827f801811387f..99a02f052e1c8410573ecd44340= a9ba4f822e979 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -485,6 +485,7 @@ struct dw_pcie_ops { enum dw_pcie_ltssm (*get_ltssm)(struct dw_pcie *pcie); int (*start_link)(struct dw_pcie *pcie); void (*stop_link)(struct dw_pcie *pcie); + int (*assert_perst)(struct dw_pcie *pcie, bool assert); }; =20 struct debugfs_info { @@ -787,6 +788,14 @@ static inline void dw_pcie_stop_link(struct dw_pcie *p= ci) pci->ops->stop_link(pci); } =20 +static inline int dw_pcie_assert_perst(struct dw_pcie *pci, bool assert) +{ + if (pci->ops && pci->ops->assert_perst) + return pci->ops->assert_perst(pci, assert); + + return 0; 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Signed-off-by: Krishna Chaitanya Chundru --- drivers/pci/controller/dwc/pcie-designware-host.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pc= i/controller/dwc/pcie-designware-host.c index 20c9333bcb1c4812e2fd96047a49944574df1e6f..b56dd1d51fa4f03931942dc9da6= 49bef8859f192 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -842,10 +842,19 @@ void __iomem *dw_pcie_own_conf_map_bus(struct pci_bus= *bus, unsigned int devfn, } EXPORT_SYMBOL_GPL(dw_pcie_own_conf_map_bus); =20 +static int dw_pcie_op_assert_perst(struct pci_bus *bus, bool assert) +{ + struct dw_pcie_rp *pp =3D bus->sysdata; + struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); + + return dw_pcie_assert_perst(pci, assert); +} + static struct pci_ops dw_pcie_ops =3D { .map_bus =3D dw_pcie_own_conf_map_bus, .read =3D pci_generic_config_read, .write =3D pci_generic_config_write, + .assert_perst =3D dw_pcie_op_assert_perst, }; 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Such devices use this function op to assert the PERST# before configuring the device and once the configuration is done they de-assert the PERST#. Signed-off-by: Krishna Chaitanya Chundru --- drivers/pci/controller/dwc/pcie-qcom.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controlle= r/dwc/pcie-qcom.c index 805edbbfe7eba496bc99ca82051dee43d240f359..cdc605b44e19e17319c39933f22= d0b7710c5e9ef 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -696,6 +696,18 @@ static int qcom_pcie_post_init_1_0_0(struct qcom_pcie = *pcie) return 0; } =20 +static int qcom_pcie_assert_perst(struct dw_pcie *pci, bool assert) +{ + struct qcom_pcie *pcie =3D to_qcom_pcie(pci); + + if (assert) + qcom_ep_reset_assert(pcie); + else + qcom_ep_reset_deassert(pcie); + + return 0; +} + static void qcom_pcie_2_3_2_ltssm_enable(struct qcom_pcie *pcie) { u32 val; @@ -1516,6 +1528,7 @@ static const struct qcom_pcie_cfg cfg_fw_managed =3D { static const struct dw_pcie_ops dw_pcie_ops =3D { .link_up =3D qcom_pcie_link_up, .start_link =3D qcom_pcie_start_link, + .assert_perst =3D qcom_pcie_assert_perst, }; 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To one of the downstream ports integrated ethernet MAC is connected as endpoint device. Other two downstream ports are supposed to connect to external device. One Host can connect to TC9563 by upstream port. TC9563 switch needs to be configured after powering on and before the PCIe link was up. The PCIe controller driver already enables link training at the host side even before this driver probe happens, due to this when driver enables power to the switch it participates in the link training and PCIe link may come up before configuring the switch through I2C. Once the link is up the configuration done through I2C will not have any effect. To prevent the host from participating in link training, disable link training on the host side to ensure the link does not come up before the switch is configured via I2C. Based on dt property and type of the port, tc9563 is configured through I2C. Reviewed-by: Bjorn Andersson Reviewed-by: Bartosz Golaszewski Signed-off-by: Krishna Chaitanya Chundru --- drivers/pci/pwrctrl/Kconfig | 14 + drivers/pci/pwrctrl/Makefile | 2 + drivers/pci/pwrctrl/pci-pwrctrl-tc9563.c | 649 +++++++++++++++++++++++++++= ++++ 3 files changed, 665 insertions(+) diff --git a/drivers/pci/pwrctrl/Kconfig b/drivers/pci/pwrctrl/Kconfig index 6956c18548114ce12247b560f1ef159eb7e90b10..b43fdf052d376e14e9481d6dd97= e89db3a48ca69 100644 --- a/drivers/pci/pwrctrl/Kconfig +++ b/drivers/pci/pwrctrl/Kconfig @@ -22,6 +22,20 @@ config PCI_PWRCTRL_SLOT PCI slots. The voltage regulators powering the rails of the PCI slots are expected to be defined in the devicetree node of the PCI bridge. =20 +config PCI_PWRCTRL_TC9563 + tristate "PCI Power Control driver for TC9563 PCIe switch" + select PCI_PWRCTRL + default m if ARCH_QCOM + help + Say Y here to enable the PCI Power Control driver of TC9563 PCIe + switch. + + This driver enables power and configures the TC9563 PCIe switch + through i2c. TC9563 is a PCIe switch which has one upstream and three + downstream ports. To one of the downstream ports integrated ethernet + MAC is connected as endpoint device. Other two downstream ports are + supposed to connect to external device. + # deprecated config HAVE_PWRCTL bool diff --git a/drivers/pci/pwrctrl/Makefile b/drivers/pci/pwrctrl/Makefile index a4e5808d7850ceb0ca272731e5539e1dfc564e43..13b02282106c2bdbf884f487534= f7466047c7fcf 100644 --- a/drivers/pci/pwrctrl/Makefile +++ b/drivers/pci/pwrctrl/Makefile @@ -7,3 +7,5 @@ obj-$(CONFIG_PCI_PWRCTRL_PWRSEQ) +=3D pci-pwrctrl-pwrseq.o =20 obj-$(CONFIG_PCI_PWRCTRL_SLOT) +=3D pci-pwrctrl-slot.o pci-pwrctrl-slot-y :=3D slot.o + +obj-$(CONFIG_PCI_PWRCTRL_TC9563) +=3D pci-pwrctrl-tc9563.o diff --git a/drivers/pci/pwrctrl/pci-pwrctrl-tc9563.c b/drivers/pci/pwrctrl= /pci-pwrctrl-tc9563.c new file mode 100644 index 0000000000000000000000000000000000000000..8f5247df1344a66509f5e0dd67d= 07d63b3588df2 --- /dev/null +++ b/drivers/pci/pwrctrl/pci-pwrctrl-tc9563.c @@ -0,0 +1,649 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../pci.h" + +#define TC9563_GPIO_CONFIG 0x801208 +#define TC9563_RESET_GPIO 0x801210 + +#define TC9563_PORT_L0S_DELAY 0x82496c +#define TC9563_PORT_L1_DELAY 0x824970 + +#define TC9563_EMBEDDED_ETH_DELAY 0x8200d8 +#define TC9563_ETH_L1_DELAY_MASK GENMASK(27, 18) +#define TC9563_ETH_L1_DELAY_VALUE(x) FIELD_PREP(TC9563_ETH_L1_DELAY_MASK, = x) +#define TC9563_ETH_L0S_DELAY_MASK GENMASK(17, 13) +#define TC9563_ETH_L0S_DELAY_VALUE(x) FIELD_PREP(TC9563_ETH_L0S_DELAY_MASK= , x) + +#define TC9563_NFTS_2_5_GT 0x824978 +#define TC9563_NFTS_5_GT 0x82497c + +#define TC9563_PORT_LANE_ACCESS_ENABLE 0x828000 + +#define TC9563_PHY_RATE_CHANGE_OVERRIDE 0x828040 +#define TC9563_PHY_RATE_CHANGE 0x828050 + +#define TC9563_TX_MARGIN 0x828234 + +#define TC9563_DFE_ENABLE 0x828a04 +#define TC9563_DFE_EQ0_MODE 0x828a08 +#define TC9563_DFE_EQ1_MODE 0x828a0c +#define TC9563_DFE_EQ2_MODE 0x828a14 +#define TC9563_DFE_PD_MASK 0x828254 + +#define TC9563_PORT_SELECT 0x82c02c +#define TC9563_PORT_ACCESS_ENABLE 0x82c030 + +#define TC9563_POWER_CONTROL 0x82b09c +#define TC9563_POWER_CONTROL_OVREN 0x82b2c8 + +#define TC9563_GPIO_MASK 0xfffffff3 +#define TC9563_GPIO_DEASSERT_BITS 0xc /* Bits to clear for GPIO deassert = */ + +#define TC9563_TX_MARGIN_MIN_UA 400000 + +/* + * From TC9563 PORSYS rev 0.2, figure 1.1 POR boot sequence + * wait for 10ms for the internal osc frequency to stabilize. + */ +#define TC9563_OSC_STAB_DELAY_US (10 * USEC_PER_MSEC) + +#define TC9563_L0S_L1_DELAY_UNIT_NS 256 /* Each unit represents 256 nanos= econds */ + +struct tc9563_pwrctrl_reg_setting { + unsigned int offset; + unsigned int val; +}; + +enum tc9563_pwrctrl_ports { + TC9563_USP, + TC9563_DSP1, + TC9563_DSP2, + TC9563_DSP3, + TC9563_ETHERNET, + TC9563_MAX +}; + +struct tc9563_pwrctrl_cfg { + u32 l0s_delay; + u32 l1_delay; + u32 tx_amp; + u8 nfts[2]; /* GEN1 & GEN2 */ + bool disable_dfe; + bool disable_port; +}; + +#define TC9563_PWRCTL_MAX_SUPPLY 6 + +static const char *const tc9563_supply_names[TC9563_PWRCTL_MAX_SUPPLY] =3D= { + "vddc", + "vdd18", + "vdd09", + "vddio1", + "vddio2", + "vddio18", +}; + +struct tc9563_pwrctrl_ctx { + struct regulator_bulk_data supplies[TC9563_PWRCTL_MAX_SUPPLY]; + struct tc9563_pwrctrl_cfg cfg[TC9563_MAX]; + struct gpio_desc *reset_gpio; + struct i2c_adapter *adapter; + struct i2c_client *client; + struct pci_pwrctrl pwrctrl; +}; + +/* + * downstream port power off sequence, hardcoding the address + * as we don't know register names for these register offsets. + */ +static const struct tc9563_pwrctrl_reg_setting common_pwroff_seq[] =3D { + {0x82900c, 0x1}, + {0x829010, 0x1}, + {0x829018, 0x0}, + {0x829020, 0x1}, + {0x82902c, 0x1}, + {0x829030, 0x1}, + {0x82903c, 0x1}, + {0x829058, 0x0}, + {0x82905c, 0x1}, + {0x829060, 0x1}, + {0x8290cc, 0x1}, + {0x8290d0, 0x1}, + {0x8290d8, 0x1}, + {0x8290e0, 0x1}, + {0x8290e8, 0x1}, + {0x8290ec, 0x1}, + {0x8290f4, 0x1}, + {0x82910c, 0x1}, + {0x829110, 0x1}, + {0x829114, 0x1}, +}; + +static const struct tc9563_pwrctrl_reg_setting dsp1_pwroff_seq[] =3D { + {TC9563_PORT_ACCESS_ENABLE, 0x2}, + {TC9563_PORT_LANE_ACCESS_ENABLE, 0x3}, + {TC9563_POWER_CONTROL, 0x014f4804}, + {TC9563_POWER_CONTROL_OVREN, 0x1}, + {TC9563_PORT_ACCESS_ENABLE, 0x4}, +}; + +static const struct tc9563_pwrctrl_reg_setting dsp2_pwroff_seq[] =3D { + {TC9563_PORT_ACCESS_ENABLE, 0x8}, + {TC9563_PORT_LANE_ACCESS_ENABLE, 0x1}, + {TC9563_POWER_CONTROL, 0x014f4804}, + {TC9563_POWER_CONTROL_OVREN, 0x1}, + {TC9563_PORT_ACCESS_ENABLE, 0x8}, +}; + +/* + * Since all transfers are initiated by the probe, no locks are necessary, + * as there are no concurrent calls. + */ +static int tc9563_pwrctrl_i2c_write(struct i2c_client *client, + u32 reg_addr, u32 reg_val) +{ + struct i2c_msg msg; + u8 msg_buf[7]; + int ret; + + msg.addr =3D client->addr; + msg.len =3D 7; + msg.flags =3D 0; + + /* Big Endian for reg addr */ + put_unaligned_be24(reg_addr, &msg_buf[0]); + + /* Little Endian for reg val */ + put_unaligned_le32(reg_val, &msg_buf[3]); + + msg.buf =3D msg_buf; + ret =3D i2c_transfer(client->adapter, &msg, 1); + return ret =3D=3D 1 ? 0 : ret; +} + +static int tc9563_pwrctrl_i2c_read(struct i2c_client *client, + u32 reg_addr, u32 *reg_val) +{ + struct i2c_msg msg[2]; + u8 wr_data[3]; + u32 rd_data; + int ret; + + msg[0].addr =3D client->addr; + msg[0].len =3D 3; + msg[0].flags =3D 0; + + /* Big Endian for reg addr */ + put_unaligned_be24(reg_addr, &wr_data[0]); + + msg[0].buf =3D wr_data; + + msg[1].addr =3D client->addr; + msg[1].len =3D 4; + msg[1].flags =3D I2C_M_RD; + + msg[1].buf =3D (u8 *)&rd_data; + + ret =3D i2c_transfer(client->adapter, &msg[0], 2); + if (ret =3D=3D 2) { + *reg_val =3D get_unaligned_le32(&rd_data); + return 0; + } + + /* If only one message successfully completed, return -EIO */ + return ret =3D=3D 1 ? -EIO : ret; +} + +static int tc9563_pwrctrl_i2c_bulk_write(struct i2c_client *client, + const struct tc9563_pwrctrl_reg_setting *seq, int len) +{ + int ret, i; + + for (i =3D 0; i < len; i++) { + ret =3D tc9563_pwrctrl_i2c_write(client, seq[i].offset, seq[i].val); + if (ret) + return ret; + } + + return 0; +} + +static int tc9563_pwrctrl_disable_port(struct tc9563_pwrctrl_ctx *ctx, + enum tc9563_pwrctrl_ports port) +{ + struct tc9563_pwrctrl_cfg *cfg =3D &ctx->cfg[port]; + const struct tc9563_pwrctrl_reg_setting *seq; + int ret, len; + + if (!cfg->disable_port) + return 0; + + if (port =3D=3D TC9563_DSP1) { + seq =3D dsp1_pwroff_seq; + len =3D ARRAY_SIZE(dsp1_pwroff_seq); + } else { + seq =3D dsp2_pwroff_seq; + len =3D ARRAY_SIZE(dsp2_pwroff_seq); + } + + ret =3D tc9563_pwrctrl_i2c_bulk_write(ctx->client, seq, len); + if (ret) + return ret; + + return tc9563_pwrctrl_i2c_bulk_write(ctx->client, + common_pwroff_seq, ARRAY_SIZE(common_pwroff_seq)); +} + +static int tc9563_pwrctrl_set_l0s_l1_entry_delay(struct tc9563_pwrctrl_ctx= *ctx, + enum tc9563_pwrctrl_ports port, bool is_l1, u32 ns) +{ + u32 rd_val, units; + int ret; + + if (ns < TC9563_L0S_L1_DELAY_UNIT_NS) + return 0; + + /* convert to units of 256ns */ + units =3D ns / TC9563_L0S_L1_DELAY_UNIT_NS; + + if (port =3D=3D TC9563_ETHERNET) { + ret =3D tc9563_pwrctrl_i2c_read(ctx->client, TC9563_EMBEDDED_ETH_DELAY, = &rd_val); + if (ret) + return ret; + + if (is_l1) + rd_val =3D u32_replace_bits(rd_val, units, TC9563_ETH_L1_DELAY_MASK); + else + rd_val =3D u32_replace_bits(rd_val, units, TC9563_ETH_L0S_DELAY_MASK); + + return tc9563_pwrctrl_i2c_write(ctx->client, TC9563_EMBEDDED_ETH_DELAY, = rd_val); + } + + ret =3D tc9563_pwrctrl_i2c_write(ctx->client, TC9563_PORT_SELECT, BIT(por= t)); + if (ret) + return ret; + + return tc9563_pwrctrl_i2c_write(ctx->client, + is_l1 ? TC9563_PORT_L1_DELAY : TC9563_PORT_L0S_DELAY, units); +} + +static int tc9563_pwrctrl_set_tx_amplitude(struct tc9563_pwrctrl_ctx *ctx, + enum tc9563_pwrctrl_ports port) +{ + u32 amp =3D ctx->cfg[port].tx_amp; + int port_access; + + if (amp < TC9563_TX_MARGIN_MIN_UA) + return 0; + + /* txmargin =3D (Amp(uV) - 400000) / 3125 */ + amp =3D (amp - TC9563_TX_MARGIN_MIN_UA) / 3125; + + switch (port) { + case TC9563_USP: + port_access =3D 0x1; + break; + case TC9563_DSP1: + port_access =3D 0x2; + break; + case TC9563_DSP2: + port_access =3D 0x8; + break; + default: + return -EINVAL; + }; + + struct tc9563_pwrctrl_reg_setting tx_amp_seq[] =3D { + {TC9563_PORT_ACCESS_ENABLE, port_access}, + {TC9563_PORT_LANE_ACCESS_ENABLE, 0x3}, + {TC9563_TX_MARGIN, amp}, + }; + + return tc9563_pwrctrl_i2c_bulk_write(ctx->client, tx_amp_seq, ARRAY_SIZE(= tx_amp_seq)); +} + +static int tc9563_pwrctrl_disable_dfe(struct tc9563_pwrctrl_ctx *ctx, + enum tc9563_pwrctrl_ports port) +{ + struct tc9563_pwrctrl_cfg *cfg =3D &ctx->cfg[port]; + int port_access, lane_access =3D 0x3; + u32 phy_rate =3D 0x21; + + if (!cfg->disable_dfe) + return 0; + + switch (port) { + case TC9563_USP: + phy_rate =3D 0x1; + port_access =3D 0x1; + break; + case TC9563_DSP1: + port_access =3D 0x2; + break; + case TC9563_DSP2: + port_access =3D 0x8; + lane_access =3D 0x1; + break; + default: + return -EINVAL; + }; + + struct tc9563_pwrctrl_reg_setting disable_dfe_seq[] =3D { + {TC9563_PORT_ACCESS_ENABLE, port_access}, + {TC9563_PORT_LANE_ACCESS_ENABLE, lane_access}, + {TC9563_DFE_ENABLE, 0x0}, + {TC9563_DFE_EQ0_MODE, 0x411}, + {TC9563_DFE_EQ1_MODE, 0x11}, + {TC9563_DFE_EQ2_MODE, 0x11}, + {TC9563_DFE_PD_MASK, 0x7}, + {TC9563_PHY_RATE_CHANGE_OVERRIDE, 0x10}, + {TC9563_PHY_RATE_CHANGE, phy_rate}, + {TC9563_PHY_RATE_CHANGE, 0x0}, + {TC9563_PHY_RATE_CHANGE_OVERRIDE, 0x0}, + }; + + return tc9563_pwrctrl_i2c_bulk_write(ctx->client, + disable_dfe_seq, ARRAY_SIZE(disable_dfe_seq)); +} + +static int tc9563_pwrctrl_set_nfts(struct tc9563_pwrctrl_ctx *ctx, + enum tc9563_pwrctrl_ports port) +{ + u8 *nfts =3D ctx->cfg[port].nfts; + struct tc9563_pwrctrl_reg_setting nfts_seq[] =3D { + {TC9563_NFTS_2_5_GT, nfts[0]}, + {TC9563_NFTS_5_GT, nfts[1]}, + }; + int ret; + + if (!nfts[0]) + return 0; + + ret =3D tc9563_pwrctrl_i2c_write(ctx->client, TC9563_PORT_SELECT, BIT(po= rt)); + if (ret) + return ret; + + return tc9563_pwrctrl_i2c_bulk_write(ctx->client, nfts_seq, ARRAY_SIZE(nf= ts_seq)); +} + +static int tc9563_pwrctrl_assert_deassert_reset(struct tc9563_pwrctrl_ctx = *ctx, bool deassert) +{ + int ret, val; + + ret =3D tc9563_pwrctrl_i2c_write(ctx->client, TC9563_GPIO_CONFIG, TC9563_= GPIO_MASK); + if (ret) + return ret; + + val =3D deassert ? TC9563_GPIO_DEASSERT_BITS : 0; + + return tc9563_pwrctrl_i2c_write(ctx->client, TC9563_RESET_GPIO, val); +} + +static int tc9563_pwrctrl_parse_device_dt(struct tc9563_pwrctrl_ctx *ctx, = struct device_node *node, + enum tc9563_pwrctrl_ports port) +{ + struct tc9563_pwrctrl_cfg *cfg =3D &ctx->cfg[port]; + int ret; + + + /* Disable port if the status of the port is disabled. */ + if (!of_device_is_available(node)) { + cfg->disable_port =3D true; + return 0; + }; + + ret =3D of_property_read_u32(node, "aspm-l0s-entry-delay-ns", &cfg->l0s_d= elay); + if (ret && ret !=3D -EINVAL) + return ret; + + ret =3D of_property_read_u32(node, "aspm-l1-entry-delay-ns", &cfg->l1_del= ay); + if (ret && ret !=3D -EINVAL) + return ret; + + ret =3D of_property_read_u32(node, "qcom,tx-amplitude-microvolt", &cfg->t= x_amp); + if (ret && ret !=3D -EINVAL) + return ret; + + ret =3D of_property_read_u8_array(node, "n-fts", cfg->nfts, ARRAY_SIZE(cf= g->nfts)); + if (ret && ret !=3D -EINVAL) + return ret; + + cfg->disable_dfe =3D of_property_read_bool(node, "qcom,no-dfe-support"); + + return 0; +} + +static void tc9563_pwrctrl_power_off(struct tc9563_pwrctrl_ctx *ctx) +{ + gpiod_set_value(ctx->reset_gpio, 1); + + regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies); +} + +static int tc9563_pwrctrl_bring_up(struct tc9563_pwrctrl_ctx *ctx) +{ + struct tc9563_pwrctrl_cfg *cfg; + int ret, i; + + ret =3D regulator_bulk_enable(ARRAY_SIZE(ctx->supplies), ctx->supplies); + if (ret < 0) + return dev_err_probe(ctx->pwrctrl.dev, ret, "cannot enable regulators\n"= ); + + gpiod_set_value(ctx->reset_gpio, 0); + + fsleep(TC9563_OSC_STAB_DELAY_US); + + ret =3D tc9563_pwrctrl_assert_deassert_reset(ctx, false); + if (ret) + goto power_off; + + for (i =3D 0; i < TC9563_MAX; i++) { + cfg =3D &ctx->cfg[i]; + ret =3D tc9563_pwrctrl_disable_port(ctx, i); + if (ret) { + dev_err(ctx->pwrctrl.dev, "Disabling port failed\n"); + goto power_off; + } + + ret =3D tc9563_pwrctrl_set_l0s_l1_entry_delay(ctx, i, false, cfg->l0s_de= lay); + if (ret) { + dev_err(ctx->pwrctrl.dev, "Setting L0s entry delay failed\n"); + goto power_off; + } + + ret =3D tc9563_pwrctrl_set_l0s_l1_entry_delay(ctx, i, true, cfg->l1_dela= y); + if (ret) { + dev_err(ctx->pwrctrl.dev, "Setting L1 entry delay failed\n"); + goto power_off; + } + + ret =3D tc9563_pwrctrl_set_tx_amplitude(ctx, i); + if (ret) { + dev_err(ctx->pwrctrl.dev, "Setting Tx amplitude failed\n"); + goto power_off; + } + + ret =3D tc9563_pwrctrl_set_nfts(ctx, i); + if (ret) { + dev_err(ctx->pwrctrl.dev, "Setting N_FTS failed\n"); + goto power_off; + } + + ret =3D tc9563_pwrctrl_disable_dfe(ctx, i); + if (ret) { + dev_err(ctx->pwrctrl.dev, "Disabling DFE failed\n"); + goto power_off; + } + } + + ret =3D tc9563_pwrctrl_assert_deassert_reset(ctx, true); + if (!ret) + return 0; + +power_off: + tc9563_pwrctrl_power_off(ctx); + return ret; +} + +static int tc9563_pwrctrl_probe(struct platform_device *pdev) +{ + struct pci_host_bridge *bridge =3D to_pci_host_bridge(pdev->dev.parent); + struct pci_bus *bus =3D bridge->bus; + struct device *dev =3D &pdev->dev; + enum tc9563_pwrctrl_ports port; + struct tc9563_pwrctrl_ctx *ctx; + struct device_node *i2c_node; + int ret, addr; + + ctx =3D devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); + if (!ctx) + return -ENOMEM; + + ret =3D of_property_read_u32_index(pdev->dev.of_node, "i2c-parent", 1, &a= ddr); + if (ret) + return dev_err_probe(dev, ret, "Failed to read i2c-parent property\n"); + + i2c_node =3D of_parse_phandle(dev->of_node, "i2c-parent", 0); + ctx->adapter =3D of_find_i2c_adapter_by_node(i2c_node); + of_node_put(i2c_node); + if (!ctx->adapter) + return dev_err_probe(dev, -EPROBE_DEFER, "Failed to find I2C adapter\n"); + + ctx->client =3D i2c_new_dummy_device(ctx->adapter, addr); + if (IS_ERR(ctx->client)) { + dev_err(dev, "Failed to create I2C client\n"); + i2c_put_adapter(ctx->adapter); + return PTR_ERR(ctx->client); + } + + for (int i =3D 0; i < ARRAY_SIZE(tc9563_supply_names); i++) + ctx->supplies[i].supply =3D tc9563_supply_names[i]; + + ret =3D devm_regulator_bulk_get(dev, TC9563_PWRCTL_MAX_SUPPLY, ctx->suppl= ies); + if (ret) { + dev_err_probe(dev, ret, "failed to get supply regulator\n"); + goto remove_i2c; + } + + ctx->reset_gpio =3D devm_gpiod_get(dev, "resx", GPIOD_OUT_HIGH); + if (IS_ERR(ctx->reset_gpio)) { + ret =3D dev_err_probe(dev, PTR_ERR(ctx->reset_gpio), "failed to get resx= GPIO\n"); + goto remove_i2c; + } + + pci_pwrctrl_init(&ctx->pwrctrl, dev); + + port =3D TC9563_USP; + ret =3D tc9563_pwrctrl_parse_device_dt(ctx, pdev->dev.of_node, port); + if (ret) { + dev_err(dev, "failed to parse device tree properties: %d\n", ret); + goto remove_i2c; + } + + /* + * Downstream ports are always children of the upstream port. + * The first node represents DSP1, the second node represents DSP2, and s= o on. + */ + for_each_child_of_node_scoped(pdev->dev.of_node, child) { + port++; + ret =3D tc9563_pwrctrl_parse_device_dt(ctx, child, port); + if (ret) + break; + /* Embedded ethernet device are under DSP3 */ + if (port =3D=3D TC9563_DSP3) { + for_each_child_of_node_scoped(child, child1) { + port++; + ret =3D tc9563_pwrctrl_parse_device_dt(ctx, child1, port); + if (ret) + break; + } + } + } + if (ret) { + dev_err(dev, "failed to parse device tree properties: %d\n", ret); + goto remove_i2c; + } + + if (bridge->ops->assert_perst) { + ret =3D bridge->ops->assert_perst(bus, true); + if (ret) + goto remove_i2c; + } + + ret =3D tc9563_pwrctrl_bring_up(ctx); + if (ret) + goto remove_i2c; + + if (bridge->ops->assert_perst) { + ret =3D bridge->ops->assert_perst(bus, false); + if (ret) + goto power_off; + } + + ret =3D devm_pci_pwrctrl_device_set_ready(dev, &ctx->pwrctrl); + if (ret) + goto power_off; + + platform_set_drvdata(pdev, ctx); + + return 0; + +power_off: + tc9563_pwrctrl_power_off(ctx); +remove_i2c: + i2c_unregister_device(ctx->client); + i2c_put_adapter(ctx->adapter); + return ret; +} + +static void tc9563_pwrctrl_remove(struct platform_device *pdev) +{ + struct tc9563_pwrctrl_ctx *ctx =3D platform_get_drvdata(pdev); + + tc9563_pwrctrl_power_off(ctx); + i2c_unregister_device(ctx->client); + i2c_put_adapter(ctx->adapter); +} + +static const struct of_device_id tc9563_pwrctrl_of_match[] =3D { + { .compatible =3D "pci1179,0623"}, + { } +}; +MODULE_DEVICE_TABLE(of, tc9563_pwrctrl_of_match); + +static struct platform_driver tc9563_pwrctrl_driver =3D { + .driver =3D { + .name =3D "pwrctrl-tc9563", + .of_match_table =3D tc9563_pwrctrl_of_match, + .probe_type =3D PROBE_PREFER_ASYNCHRONOUS, + }, + .probe =3D tc9563_pwrctrl_probe, + .remove =3D tc9563_pwrctrl_remove, +}; +module_platform_driver(tc9563_pwrctrl_driver); + +MODULE_AUTHOR("Krishna chaitanya chundru "); +MODULE_DESCRIPTION("TC956x power control driver"); +MODULE_LICENSE("GPL"); --=20 2.34.1 From nobody Sun Feb 8 10:44:09 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BC38A347BAD for ; Fri, 31 Oct 2025 11:12:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; 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Two embedded Ethernet devices are present on one of the downstream ports. As all these ports are present in the node represent the downstream ports and embedded endpoints. Power to the TC9563 is supplied through two LDO regulators, controlled by two GPIOs, which are added as fixed regulators. Configure the TC9563 through I2C. Reviewed-by: Bjorn Andersson Acked-by: Manivannan Sadhasivam Reviewed-by: Dmitry Baryshkov Signed-off-by: Krishna Chaitanya Chundru --- arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 128 +++++++++++++++++++++++= ++++ arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 +- 2 files changed, 129 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot= /dts/qcom/qcs6490-rb3gen2.dts index 18cea8812001421456dc85547c3c711e2c42182a..6aa49519508a2f88afa23f8f801= 5f986c0a5b84e 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts @@ -262,6 +262,30 @@ vph_pwr: vph-pwr-regulator { regulator-max-microvolt =3D <3700000>; }; =20 + vdd_ntn_0p9: regulator-vdd-ntn-0p9 { + compatible =3D "regulator-fixed"; + regulator-name =3D "VDD_NTN_0P9"; + gpio =3D <&pm8350c_gpios 2 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt =3D <899400>; + regulator-max-microvolt =3D <899400>; + enable-active-high; + pinctrl-0 =3D <&ntn_0p9_en>; + pinctrl-names =3D "default"; + regulator-enable-ramp-delay =3D <4300>; + }; + + vdd_ntn_1p8: regulator-vdd-ntn-1p8 { + compatible =3D "regulator-fixed"; + regulator-name =3D "VDD_NTN_1P8"; + gpio =3D <&pm8350c_gpios 3 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + enable-active-high; + pinctrl-0 =3D <&ntn_1p8_en>; + pinctrl-names =3D "default"; + regulator-enable-ramp-delay =3D <10000>; + }; + wcn6750-pmu { compatible =3D "qcom,wcn6750-pmu"; pinctrl-0 =3D <&bt_en>; @@ -843,6 +867,78 @@ &pcie1_phy { status =3D "okay"; }; =20 +&pcie1_port0 { + pcie@0,0 { + compatible =3D "pci1179,0623"; + reg =3D <0x10000 0x0 0x0 0x0 0x0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + + device_type =3D "pci"; + ranges; + bus-range =3D <0x2 0xff>; + + vddc-supply =3D <&vdd_ntn_0p9>; + vdd18-supply =3D <&vdd_ntn_1p8>; + vdd09-supply =3D <&vdd_ntn_0p9>; + vddio1-supply =3D <&vdd_ntn_1p8>; + vddio2-supply =3D <&vdd_ntn_1p8>; + vddio18-supply =3D <&vdd_ntn_1p8>; + + i2c-parent =3D <&i2c0 0x77>; + + resx-gpios =3D <&pm8350c_gpios 1 GPIO_ACTIVE_LOW>; + + pinctrl-0 =3D <&tc9563_rsex_n>; + pinctrl-names =3D "default"; + + pcie@1,0 { + reg =3D <0x20800 0x0 0x0 0x0 0x0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + + device_type =3D "pci"; + ranges; + bus-range =3D <0x3 0xff>; + }; + + pcie@2,0 { + reg =3D <0x21000 0x0 0x0 0x0 0x0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + + device_type =3D "pci"; + ranges; + bus-range =3D <0x4 0xff>; + }; + + pcie@3,0 { + reg =3D <0x21800 0x0 0x0 0x0 0x0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + device_type =3D "pci"; + ranges; + bus-range =3D <0x5 0xff>; + + pci@0,0 { + reg =3D <0x50000 0x0 0x0 0x0 0x0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + device_type =3D "pci"; + ranges; + }; + + pci@0,1 { + reg =3D <0x50100 0x0 0x0 0x0 0x0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + device_type =3D "pci"; + ranges; + }; + }; + }; +}; + &pm7325_gpios { kypd_vol_up_n: kypd-vol-up-n-state { pins =3D "gpio6"; @@ -1119,6 +1215,38 @@ right_spkr: speaker@0,2 { }; }; =20 +&pm8350c_gpios { + ntn_0p9_en: ntn-0p9-en-state { + pins =3D "gpio2"; + function =3D "normal"; + + bias-disable; + input-disable; + output-enable; + power-source =3D <0>; + }; + + ntn_1p8_en: ntn-1p8-en-state { + pins =3D "gpio3"; + function =3D "normal"; + + bias-disable; + input-disable; + output-enable; + power-source =3D <0>; + }; + + tc9563_rsex_n: tc9563-resx-state { + pins =3D "gpio1"; + function =3D "normal"; + + bias-disable; + input-disable; + output-enable; + power-source =3D <0>; + }; +}; + &tlmm { gpio-reserved-ranges =3D <32 2>, /* ADSP */ <48 4>; /* NFC */ diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qco= m/sc7280.dtsi index 4b04dea57ec8cc652e37f1d93c410404adaadd5d..23cf2c8c72b0bab67467e4b60cd= 57a3e658efa68 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -2424,7 +2424,7 @@ pcie1: pcie@1c08000 { =20 status =3D "disabled"; =20 - pcie@0 { + pcie1_port0: pcie@0 { device_type =3D "pci"; reg =3D <0x0 0x0 0x0 0x0 0x0>; bus-range =3D <0x01 0xff>; --=20 2.34.1