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This gives more flexibility and also allows us to drop the .num_links member, saving from possible errors related to it being not set or set incorrectly. Signed-off-by: Dmitry Baryshkov --- drivers/interconnect/qcom/sdm845.c | 774 ++++++++++++++++++---------------= ---- drivers/interconnect/qcom/sdm845.h | 140 ------- 2 files changed, 381 insertions(+), 533 deletions(-) diff --git a/drivers/interconnect/qcom/sdm845.c b/drivers/interconnect/qcom= /sdm845.c index 855802be93fea1d999bc8a885f36c3c318e1d86d..83d7a611cdf72d4b1cc17f86455= 106574a13cc9b 100644 --- a/drivers/interconnect/qcom/sdm845.c +++ b/drivers/interconnect/qcom/sdm845.c @@ -14,1251 +14,1231 @@ =20 #include "bcm-voter.h" #include "icc-rpmh.h" -#include "sdm845.h" + +static struct qcom_icc_node qhm_a1noc_cfg; +static struct qcom_icc_node qhm_qup1; +static struct qcom_icc_node qhm_tsif; +static struct qcom_icc_node xm_sdc2; +static struct qcom_icc_node xm_sdc4; +static struct qcom_icc_node xm_ufs_card; +static struct qcom_icc_node xm_ufs_mem; +static struct qcom_icc_node xm_pcie_0; +static struct qcom_icc_node qhm_a2noc_cfg; +static struct qcom_icc_node qhm_qdss_bam; +static struct qcom_icc_node qhm_qup2; +static struct qcom_icc_node qnm_cnoc; +static struct qcom_icc_node qxm_crypto; +static struct qcom_icc_node qxm_ipa; +static struct qcom_icc_node xm_pcie3_1; +static struct qcom_icc_node xm_qdss_etr; +static struct qcom_icc_node xm_usb3_0; +static struct qcom_icc_node xm_usb3_1; +static struct qcom_icc_node qxm_camnoc_hf0_uncomp; +static struct qcom_icc_node qxm_camnoc_hf1_uncomp; +static struct qcom_icc_node qxm_camnoc_sf_uncomp; +static struct qcom_icc_node qhm_spdm; +static struct qcom_icc_node qhm_tic; +static struct qcom_icc_node qnm_snoc; +static struct qcom_icc_node xm_qdss_dap; +static struct qcom_icc_node qhm_cnoc; +static struct qcom_icc_node acm_l3; +static struct qcom_icc_node pm_gnoc_cfg; +static struct qcom_icc_node llcc_mc; +static struct qcom_icc_node acm_tcu; +static struct qcom_icc_node qhm_memnoc_cfg; +static struct qcom_icc_node qnm_apps; +static struct qcom_icc_node qnm_mnoc_hf; +static struct qcom_icc_node qnm_mnoc_sf; +static struct qcom_icc_node qnm_snoc_gc; +static struct qcom_icc_node qnm_snoc_sf; +static struct qcom_icc_node qxm_gpu; +static struct qcom_icc_node qhm_mnoc_cfg; +static struct qcom_icc_node qxm_camnoc_hf0; +static struct qcom_icc_node qxm_camnoc_hf1; +static struct qcom_icc_node qxm_camnoc_sf; +static struct qcom_icc_node qxm_mdp0; +static struct qcom_icc_node qxm_mdp1; +static struct qcom_icc_node qxm_rot; +static struct qcom_icc_node qxm_venus0; +static struct qcom_icc_node qxm_venus1; +static struct qcom_icc_node qxm_venus_arm9; +static struct qcom_icc_node qhm_snoc_cfg; +static struct qcom_icc_node qnm_aggre1_noc; +static struct qcom_icc_node qnm_aggre2_noc; +static struct qcom_icc_node qnm_gladiator_sodv; +static struct qcom_icc_node qnm_memnoc; +static struct qcom_icc_node qnm_pcie_anoc; +static struct qcom_icc_node qxm_pimem; +static struct qcom_icc_node xm_gic; +static struct qcom_icc_node qns_a1noc_snoc; +static struct qcom_icc_node srvc_aggre1_noc; +static struct qcom_icc_node qns_pcie_a1noc_snoc; +static struct qcom_icc_node qns_a2noc_snoc; +static struct qcom_icc_node qns_pcie_snoc; +static struct qcom_icc_node srvc_aggre2_noc; +static struct qcom_icc_node qns_camnoc_uncomp; +static struct qcom_icc_node qhs_a1_noc_cfg; +static struct qcom_icc_node qhs_a2_noc_cfg; +static struct qcom_icc_node qhs_aop; +static struct qcom_icc_node qhs_aoss; +static struct qcom_icc_node qhs_camera_cfg; +static struct qcom_icc_node qhs_clk_ctl; +static struct qcom_icc_node qhs_compute_dsp_cfg; +static struct qcom_icc_node qhs_cpr_cx; +static struct qcom_icc_node qhs_crypto0_cfg; +static struct qcom_icc_node qhs_dcc_cfg; +static struct qcom_icc_node qhs_ddrss_cfg; +static struct qcom_icc_node qhs_display_cfg; +static struct qcom_icc_node qhs_glm; +static struct qcom_icc_node qhs_gpuss_cfg; +static struct qcom_icc_node qhs_imem_cfg; +static struct qcom_icc_node qhs_ipa; +static struct qcom_icc_node qhs_mnoc_cfg; +static struct qcom_icc_node qhs_pcie0_cfg; +static struct qcom_icc_node qhs_pcie_gen3_cfg; +static struct qcom_icc_node qhs_pdm; +static struct qcom_icc_node qhs_phy_refgen_south; +static struct qcom_icc_node qhs_pimem_cfg; +static struct qcom_icc_node qhs_prng; +static struct qcom_icc_node qhs_qdss_cfg; +static struct qcom_icc_node qhs_qupv3_north; +static struct qcom_icc_node qhs_qupv3_south; +static struct qcom_icc_node qhs_sdc2; +static struct qcom_icc_node qhs_sdc4; +static struct qcom_icc_node qhs_snoc_cfg; +static struct qcom_icc_node qhs_spdm; +static struct qcom_icc_node qhs_spss_cfg; +static struct qcom_icc_node qhs_tcsr; +static struct qcom_icc_node qhs_tlmm_north; +static struct qcom_icc_node qhs_tlmm_south; +static struct qcom_icc_node qhs_tsif; +static struct qcom_icc_node qhs_ufs_card_cfg; +static struct qcom_icc_node qhs_ufs_mem_cfg; +static struct qcom_icc_node qhs_usb3_0; +static struct qcom_icc_node qhs_usb3_1; +static struct qcom_icc_node qhs_venus_cfg; +static struct qcom_icc_node qhs_vsense_ctrl_cfg; +static struct qcom_icc_node qns_cnoc_a2noc; +static struct qcom_icc_node srvc_cnoc; +static struct qcom_icc_node qhs_llcc; +static struct qcom_icc_node qhs_memnoc; +static struct qcom_icc_node qns_gladiator_sodv; +static struct qcom_icc_node qns_gnoc_memnoc; +static struct qcom_icc_node srvc_gnoc; +static struct qcom_icc_node ebi; +static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg; +static struct qcom_icc_node qns_apps_io; +static struct qcom_icc_node qns_llcc; +static struct qcom_icc_node qns_memnoc_snoc; +static struct qcom_icc_node srvc_memnoc; +static struct qcom_icc_node qns2_mem_noc; +static struct qcom_icc_node qns_mem_noc_hf; +static struct qcom_icc_node srvc_mnoc; +static struct qcom_icc_node qhs_apss; +static struct qcom_icc_node qns_cnoc; +static struct qcom_icc_node qns_memnoc_gc; +static struct qcom_icc_node qns_memnoc_sf; +static struct qcom_icc_node qxs_imem; +static struct qcom_icc_node qxs_pcie; +static struct qcom_icc_node qxs_pcie_gen3; +static struct qcom_icc_node qxs_pimem; +static struct qcom_icc_node srvc_snoc; +static struct qcom_icc_node xs_qdss_stm; +static struct qcom_icc_node xs_sys_tcu_cfg; =20 static struct qcom_icc_node qhm_a1noc_cfg =3D { .name =3D "qhm_a1noc_cfg", - .id =3D SDM845_MASTER_A1NOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SDM845_SLAVE_SERVICE_A1NOC }, + .link_nodes =3D { &srvc_aggre1_noc }, }; =20 static struct qcom_icc_node qhm_qup1 =3D { .name =3D "qhm_qup1", - .id =3D SDM845_MASTER_BLSP_1, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SDM845_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node qhm_tsif =3D { .name =3D "qhm_tsif", - .id =3D SDM845_MASTER_TSIF, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SDM845_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node xm_sdc2 =3D { .name =3D "xm_sdc2", - .id =3D SDM845_MASTER_SDCC_2, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SDM845_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node xm_sdc4 =3D { .name =3D "xm_sdc4", - .id =3D SDM845_MASTER_SDCC_4, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SDM845_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node xm_ufs_card =3D { .name =3D "xm_ufs_card", - .id =3D SDM845_MASTER_UFS_CARD, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SDM845_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node xm_ufs_mem =3D { .name =3D "xm_ufs_mem", - .id =3D SDM845_MASTER_UFS_MEM, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SDM845_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node xm_pcie_0 =3D { .name =3D "xm_pcie_0", - .id =3D SDM845_MASTER_PCIE_0, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SDM845_SLAVE_ANOC_PCIE_A1NOC_SNOC }, + .link_nodes =3D { &qns_pcie_a1noc_snoc }, }; =20 static struct qcom_icc_node qhm_a2noc_cfg =3D { .name =3D "qhm_a2noc_cfg", - .id =3D SDM845_MASTER_A2NOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SDM845_SLAVE_SERVICE_A2NOC }, + .link_nodes =3D { &srvc_aggre2_noc }, }; =20 static struct qcom_icc_node qhm_qdss_bam =3D { .name =3D "qhm_qdss_bam", - .id =3D SDM845_MASTER_QDSS_BAM, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SDM845_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qhm_qup2 =3D { .name =3D "qhm_qup2", - .id =3D SDM845_MASTER_BLSP_2, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SDM845_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qnm_cnoc =3D { .name =3D "qnm_cnoc", - .id =3D SDM845_MASTER_CNOC_A2NOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SDM845_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qxm_crypto =3D { .name =3D "qxm_crypto", - .id =3D SDM845_MASTER_CRYPTO, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SDM845_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qxm_ipa =3D { .name =3D "qxm_ipa", - .id =3D SDM845_MASTER_IPA, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SDM845_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node xm_pcie3_1 =3D { .name =3D "xm_pcie3_1", - .id =3D SDM845_MASTER_PCIE_1, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SDM845_SLAVE_ANOC_PCIE_SNOC }, + .link_nodes =3D { &qns_pcie_snoc }, }; =20 static struct qcom_icc_node xm_qdss_etr =3D { .name =3D "xm_qdss_etr", - .id =3D SDM845_MASTER_QDSS_ETR, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SDM845_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node xm_usb3_0 =3D { .name =3D "xm_usb3_0", - .id =3D SDM845_MASTER_USB3_0, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SDM845_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node xm_usb3_1 =3D { .name =3D "xm_usb3_1", - .id =3D SDM845_MASTER_USB3_1, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SDM845_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qxm_camnoc_hf0_uncomp =3D { .name =3D "qxm_camnoc_hf0_uncomp", - .id =3D SDM845_MASTER_CAMNOC_HF0_UNCOMP, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SDM845_SLAVE_CAMNOC_UNCOMP }, + .link_nodes =3D { &qns_camnoc_uncomp }, }; =20 static struct qcom_icc_node qxm_camnoc_hf1_uncomp =3D { .name =3D "qxm_camnoc_hf1_uncomp", - .id =3D SDM845_MASTER_CAMNOC_HF1_UNCOMP, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SDM845_SLAVE_CAMNOC_UNCOMP }, + .link_nodes =3D { &qns_camnoc_uncomp }, }; =20 static struct qcom_icc_node qxm_camnoc_sf_uncomp =3D { .name =3D "qxm_camnoc_sf_uncomp", - .id =3D SDM845_MASTER_CAMNOC_SF_UNCOMP, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SDM845_SLAVE_CAMNOC_UNCOMP }, + .link_nodes =3D { &qns_camnoc_uncomp }, }; =20 static struct qcom_icc_node qhm_spdm =3D { .name =3D "qhm_spdm", - .id =3D SDM845_MASTER_SPDM, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SDM845_SLAVE_CNOC_A2NOC }, + .link_nodes =3D { &qns_cnoc_a2noc }, }; =20 static struct qcom_icc_node qhm_tic =3D { .name =3D "qhm_tic", - .id =3D SDM845_MASTER_TIC, .channels =3D 1, .buswidth =3D 4, .num_links =3D 43, - .links =3D { SDM845_SLAVE_A1NOC_CFG, - SDM845_SLAVE_A2NOC_CFG, - SDM845_SLAVE_AOP, - SDM845_SLAVE_AOSS, - SDM845_SLAVE_CAMERA_CFG, - SDM845_SLAVE_CLK_CTL, - SDM845_SLAVE_CDSP_CFG, - SDM845_SLAVE_RBCPR_CX_CFG, - SDM845_SLAVE_CRYPTO_0_CFG, - SDM845_SLAVE_DCC_CFG, - SDM845_SLAVE_CNOC_DDRSS, - SDM845_SLAVE_DISPLAY_CFG, - SDM845_SLAVE_GLM, - SDM845_SLAVE_GFX3D_CFG, - SDM845_SLAVE_IMEM_CFG, - SDM845_SLAVE_IPA_CFG, - SDM845_SLAVE_CNOC_MNOC_CFG, - SDM845_SLAVE_PCIE_0_CFG, - SDM845_SLAVE_PCIE_1_CFG, - SDM845_SLAVE_PDM, - SDM845_SLAVE_SOUTH_PHY_CFG, - SDM845_SLAVE_PIMEM_CFG, - SDM845_SLAVE_PRNG, - SDM845_SLAVE_QDSS_CFG, - SDM845_SLAVE_BLSP_2, - SDM845_SLAVE_BLSP_1, - SDM845_SLAVE_SDCC_2, - SDM845_SLAVE_SDCC_4, - SDM845_SLAVE_SNOC_CFG, - SDM845_SLAVE_SPDM_WRAPPER, - SDM845_SLAVE_SPSS_CFG, - SDM845_SLAVE_TCSR, - SDM845_SLAVE_TLMM_NORTH, - SDM845_SLAVE_TLMM_SOUTH, - SDM845_SLAVE_TSIF, - SDM845_SLAVE_UFS_CARD_CFG, - SDM845_SLAVE_UFS_MEM_CFG, - SDM845_SLAVE_USB3_0, - SDM845_SLAVE_USB3_1, - SDM845_SLAVE_VENUS_CFG, - SDM845_SLAVE_VSENSE_CTRL_CFG, - SDM845_SLAVE_CNOC_A2NOC, - SDM845_SLAVE_SERVICE_CNOC - }, + .link_nodes =3D { &qhs_a1_noc_cfg, + &qhs_a2_noc_cfg, + &qhs_aop, + &qhs_aoss, + &qhs_camera_cfg, + &qhs_clk_ctl, + &qhs_compute_dsp_cfg, + &qhs_cpr_cx, + &qhs_crypto0_cfg, + &qhs_dcc_cfg, + &qhs_ddrss_cfg, + &qhs_display_cfg, + &qhs_glm, + &qhs_gpuss_cfg, + &qhs_imem_cfg, + &qhs_ipa, + &qhs_mnoc_cfg, + &qhs_pcie0_cfg, + &qhs_pcie_gen3_cfg, + &qhs_pdm, + &qhs_phy_refgen_south, + &qhs_pimem_cfg, + &qhs_prng, + &qhs_qdss_cfg, + &qhs_qupv3_north, + &qhs_qupv3_south, + &qhs_sdc2, + &qhs_sdc4, + &qhs_snoc_cfg, + &qhs_spdm, + &qhs_spss_cfg, + &qhs_tcsr, + &qhs_tlmm_north, + &qhs_tlmm_south, + &qhs_tsif, + &qhs_ufs_card_cfg, + &qhs_ufs_mem_cfg, + &qhs_usb3_0, + &qhs_usb3_1, + &qhs_venus_cfg, + &qhs_vsense_ctrl_cfg, + &qns_cnoc_a2noc, + &srvc_cnoc }, }; =20 static struct qcom_icc_node qnm_snoc =3D { .name =3D "qnm_snoc", - .id =3D SDM845_MASTER_SNOC_CNOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 42, - .links =3D { SDM845_SLAVE_A1NOC_CFG, - SDM845_SLAVE_A2NOC_CFG, - SDM845_SLAVE_AOP, - SDM845_SLAVE_AOSS, - SDM845_SLAVE_CAMERA_CFG, - SDM845_SLAVE_CLK_CTL, - SDM845_SLAVE_CDSP_CFG, - SDM845_SLAVE_RBCPR_CX_CFG, - SDM845_SLAVE_CRYPTO_0_CFG, - SDM845_SLAVE_DCC_CFG, - SDM845_SLAVE_CNOC_DDRSS, - SDM845_SLAVE_DISPLAY_CFG, - SDM845_SLAVE_GLM, - SDM845_SLAVE_GFX3D_CFG, - SDM845_SLAVE_IMEM_CFG, - SDM845_SLAVE_IPA_CFG, - SDM845_SLAVE_CNOC_MNOC_CFG, - SDM845_SLAVE_PCIE_0_CFG, - SDM845_SLAVE_PCIE_1_CFG, - SDM845_SLAVE_PDM, - SDM845_SLAVE_SOUTH_PHY_CFG, - SDM845_SLAVE_PIMEM_CFG, - SDM845_SLAVE_PRNG, - SDM845_SLAVE_QDSS_CFG, - SDM845_SLAVE_BLSP_2, - SDM845_SLAVE_BLSP_1, - SDM845_SLAVE_SDCC_2, - SDM845_SLAVE_SDCC_4, - SDM845_SLAVE_SNOC_CFG, - SDM845_SLAVE_SPDM_WRAPPER, - SDM845_SLAVE_SPSS_CFG, - SDM845_SLAVE_TCSR, - SDM845_SLAVE_TLMM_NORTH, - SDM845_SLAVE_TLMM_SOUTH, - SDM845_SLAVE_TSIF, - SDM845_SLAVE_UFS_CARD_CFG, - SDM845_SLAVE_UFS_MEM_CFG, - SDM845_SLAVE_USB3_0, - SDM845_SLAVE_USB3_1, - SDM845_SLAVE_VENUS_CFG, - SDM845_SLAVE_VSENSE_CTRL_CFG, - SDM845_SLAVE_SERVICE_CNOC - }, + .link_nodes =3D { &qhs_a1_noc_cfg, + &qhs_a2_noc_cfg, + &qhs_aop, + &qhs_aoss, + &qhs_camera_cfg, + &qhs_clk_ctl, + &qhs_compute_dsp_cfg, + &qhs_cpr_cx, + &qhs_crypto0_cfg, + &qhs_dcc_cfg, + &qhs_ddrss_cfg, + &qhs_display_cfg, + &qhs_glm, + &qhs_gpuss_cfg, + &qhs_imem_cfg, + &qhs_ipa, + &qhs_mnoc_cfg, + &qhs_pcie0_cfg, + &qhs_pcie_gen3_cfg, + &qhs_pdm, + &qhs_phy_refgen_south, + &qhs_pimem_cfg, + &qhs_prng, + &qhs_qdss_cfg, + &qhs_qupv3_north, + &qhs_qupv3_south, + &qhs_sdc2, + &qhs_sdc4, + &qhs_snoc_cfg, + &qhs_spdm, + &qhs_spss_cfg, + &qhs_tcsr, + &qhs_tlmm_north, + &qhs_tlmm_south, + &qhs_tsif, + &qhs_ufs_card_cfg, + &qhs_ufs_mem_cfg, + &qhs_usb3_0, + &qhs_usb3_1, + &qhs_venus_cfg, + &qhs_vsense_ctrl_cfg, + &srvc_cnoc }, }; =20 static struct qcom_icc_node xm_qdss_dap =3D { .name =3D "xm_qdss_dap", - .id =3D SDM845_MASTER_QDSS_DAP, .channels =3D 1, .buswidth =3D 8, .num_links =3D 43, - .links =3D { SDM845_SLAVE_A1NOC_CFG, - SDM845_SLAVE_A2NOC_CFG, - SDM845_SLAVE_AOP, - SDM845_SLAVE_AOSS, - SDM845_SLAVE_CAMERA_CFG, - SDM845_SLAVE_CLK_CTL, - SDM845_SLAVE_CDSP_CFG, - SDM845_SLAVE_RBCPR_CX_CFG, - SDM845_SLAVE_CRYPTO_0_CFG, - SDM845_SLAVE_DCC_CFG, - SDM845_SLAVE_CNOC_DDRSS, - SDM845_SLAVE_DISPLAY_CFG, - SDM845_SLAVE_GLM, - SDM845_SLAVE_GFX3D_CFG, - SDM845_SLAVE_IMEM_CFG, - SDM845_SLAVE_IPA_CFG, - SDM845_SLAVE_CNOC_MNOC_CFG, - SDM845_SLAVE_PCIE_0_CFG, - SDM845_SLAVE_PCIE_1_CFG, - SDM845_SLAVE_PDM, - SDM845_SLAVE_SOUTH_PHY_CFG, - SDM845_SLAVE_PIMEM_CFG, - SDM845_SLAVE_PRNG, - SDM845_SLAVE_QDSS_CFG, - SDM845_SLAVE_BLSP_2, - SDM845_SLAVE_BLSP_1, - SDM845_SLAVE_SDCC_2, - SDM845_SLAVE_SDCC_4, - SDM845_SLAVE_SNOC_CFG, - SDM845_SLAVE_SPDM_WRAPPER, - SDM845_SLAVE_SPSS_CFG, - SDM845_SLAVE_TCSR, - SDM845_SLAVE_TLMM_NORTH, - SDM845_SLAVE_TLMM_SOUTH, - SDM845_SLAVE_TSIF, - SDM845_SLAVE_UFS_CARD_CFG, - SDM845_SLAVE_UFS_MEM_CFG, - SDM845_SLAVE_USB3_0, - SDM845_SLAVE_USB3_1, - SDM845_SLAVE_VENUS_CFG, - SDM845_SLAVE_VSENSE_CTRL_CFG, - SDM845_SLAVE_CNOC_A2NOC, - SDM845_SLAVE_SERVICE_CNOC - }, + .link_nodes =3D { &qhs_a1_noc_cfg, + &qhs_a2_noc_cfg, + &qhs_aop, + &qhs_aoss, + &qhs_camera_cfg, + &qhs_clk_ctl, + &qhs_compute_dsp_cfg, + &qhs_cpr_cx, + &qhs_crypto0_cfg, + &qhs_dcc_cfg, + &qhs_ddrss_cfg, + &qhs_display_cfg, + &qhs_glm, + &qhs_gpuss_cfg, + &qhs_imem_cfg, + &qhs_ipa, + &qhs_mnoc_cfg, + &qhs_pcie0_cfg, + &qhs_pcie_gen3_cfg, + &qhs_pdm, + &qhs_phy_refgen_south, + &qhs_pimem_cfg, + &qhs_prng, + &qhs_qdss_cfg, + &qhs_qupv3_north, + &qhs_qupv3_south, + &qhs_sdc2, + &qhs_sdc4, + &qhs_snoc_cfg, + &qhs_spdm, + &qhs_spss_cfg, + &qhs_tcsr, + &qhs_tlmm_north, + &qhs_tlmm_south, + &qhs_tsif, + &qhs_ufs_card_cfg, + &qhs_ufs_mem_cfg, + &qhs_usb3_0, + &qhs_usb3_1, + &qhs_venus_cfg, + &qhs_vsense_ctrl_cfg, + &qns_cnoc_a2noc, + &srvc_cnoc }, }; =20 static struct qcom_icc_node qhm_cnoc =3D { .name =3D "qhm_cnoc", - .id =3D SDM845_MASTER_CNOC_DC_NOC, .channels =3D 1, .buswidth =3D 4, .num_links =3D 2, - .links =3D { SDM845_SLAVE_LLCC_CFG, - SDM845_SLAVE_MEM_NOC_CFG - }, + .link_nodes =3D { &qhs_llcc, + &qhs_memnoc }, }; =20 static struct qcom_icc_node acm_l3 =3D { .name =3D "acm_l3", - .id =3D SDM845_MASTER_APPSS_PROC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 3, - .links =3D { SDM845_SLAVE_GNOC_SNOC, - SDM845_SLAVE_GNOC_MEM_NOC, - SDM845_SLAVE_SERVICE_GNOC - }, + .link_nodes =3D { &qns_gladiator_sodv, + &qns_gnoc_memnoc, + &srvc_gnoc }, }; =20 static struct qcom_icc_node pm_gnoc_cfg =3D { .name =3D "pm_gnoc_cfg", - .id =3D SDM845_MASTER_GNOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SDM845_SLAVE_SERVICE_GNOC }, + .link_nodes =3D { &srvc_gnoc }, }; =20 static struct qcom_icc_node llcc_mc =3D { .name =3D "llcc_mc", - .id =3D SDM845_MASTER_LLCC, .channels =3D 4, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SDM845_SLAVE_EBI1 }, + .link_nodes =3D { &ebi }, }; =20 static struct qcom_icc_node acm_tcu =3D { .name =3D "acm_tcu", - .id =3D SDM845_MASTER_TCU_0, .channels =3D 1, .buswidth =3D 8, .num_links =3D 3, - .links =3D { SDM845_SLAVE_MEM_NOC_GNOC, - SDM845_SLAVE_LLCC, - SDM845_SLAVE_MEM_NOC_SNOC - }, + .link_nodes =3D { &qns_apps_io, + &qns_llcc, + &qns_memnoc_snoc }, }; =20 static struct qcom_icc_node qhm_memnoc_cfg =3D { .name =3D "qhm_memnoc_cfg", - .id =3D SDM845_MASTER_MEM_NOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 2, - .links =3D { SDM845_SLAVE_MSS_PROC_MS_MPU_CFG, - SDM845_SLAVE_SERVICE_MEM_NOC - }, + .link_nodes =3D { &qhs_mdsp_ms_mpu_cfg, + &srvc_memnoc }, }; =20 static struct qcom_icc_node qnm_apps =3D { .name =3D "qnm_apps", - .id =3D SDM845_MASTER_GNOC_MEM_NOC, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SDM845_SLAVE_LLCC }, + .link_nodes =3D { &qns_llcc }, }; =20 static struct qcom_icc_node qnm_mnoc_hf =3D { .name =3D "qnm_mnoc_hf", - .id =3D SDM845_MASTER_MNOC_HF_MEM_NOC, .channels =3D 2, .buswidth =3D 32, .num_links =3D 2, - .links =3D { SDM845_SLAVE_MEM_NOC_GNOC, - SDM845_SLAVE_LLCC - }, + .link_nodes =3D { &qns_apps_io, + &qns_llcc }, }; =20 static struct qcom_icc_node qnm_mnoc_sf =3D { .name =3D "qnm_mnoc_sf", - .id =3D SDM845_MASTER_MNOC_SF_MEM_NOC, .channels =3D 1, .buswidth =3D 32, .num_links =3D 3, - .links =3D { SDM845_SLAVE_MEM_NOC_GNOC, - SDM845_SLAVE_LLCC, - SDM845_SLAVE_MEM_NOC_SNOC - }, + .link_nodes =3D { &qns_apps_io, + &qns_llcc, + &qns_memnoc_snoc }, }; =20 static struct qcom_icc_node qnm_snoc_gc =3D { .name =3D "qnm_snoc_gc", - .id =3D SDM845_MASTER_SNOC_GC_MEM_NOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SDM845_SLAVE_LLCC }, + .link_nodes =3D { &qns_llcc }, }; =20 static struct qcom_icc_node qnm_snoc_sf =3D { .name =3D "qnm_snoc_sf", - .id =3D SDM845_MASTER_SNOC_SF_MEM_NOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 2, - .links =3D { SDM845_SLAVE_MEM_NOC_GNOC, - SDM845_SLAVE_LLCC - }, + .link_nodes =3D { &qns_apps_io, + &qns_llcc }, }; =20 static struct qcom_icc_node qxm_gpu =3D { .name =3D "qxm_gpu", - .id =3D SDM845_MASTER_GFX3D, .channels =3D 2, .buswidth =3D 32, .num_links =3D 3, - .links =3D { SDM845_SLAVE_MEM_NOC_GNOC, - SDM845_SLAVE_LLCC, - SDM845_SLAVE_MEM_NOC_SNOC - }, + .link_nodes =3D { &qns_apps_io, + &qns_llcc, + &qns_memnoc_snoc }, }; =20 static struct qcom_icc_node qhm_mnoc_cfg =3D { .name =3D "qhm_mnoc_cfg", - .id =3D SDM845_MASTER_CNOC_MNOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SDM845_SLAVE_SERVICE_MNOC }, + .link_nodes =3D { &srvc_mnoc }, }; =20 static struct qcom_icc_node qxm_camnoc_hf0 =3D { .name =3D "qxm_camnoc_hf0", - .id =3D SDM845_MASTER_CAMNOC_HF0, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SDM845_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_hf }, }; =20 static struct qcom_icc_node qxm_camnoc_hf1 =3D { .name =3D "qxm_camnoc_hf1", - .id =3D SDM845_MASTER_CAMNOC_HF1, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SDM845_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_hf }, }; =20 static struct qcom_icc_node qxm_camnoc_sf =3D { .name =3D "qxm_camnoc_sf", - .id =3D SDM845_MASTER_CAMNOC_SF, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SDM845_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns2_mem_noc }, }; =20 static struct qcom_icc_node qxm_mdp0 =3D { .name =3D "qxm_mdp0", - .id =3D SDM845_MASTER_MDP0, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SDM845_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_hf }, }; =20 static struct qcom_icc_node qxm_mdp1 =3D { .name =3D "qxm_mdp1", - .id =3D SDM845_MASTER_MDP1, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SDM845_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_hf }, }; =20 static struct qcom_icc_node qxm_rot =3D { .name =3D "qxm_rot", - .id =3D SDM845_MASTER_ROTATOR, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SDM845_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns2_mem_noc }, }; =20 static struct qcom_icc_node qxm_venus0 =3D { .name =3D "qxm_venus0", - .id =3D SDM845_MASTER_VIDEO_P0, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SDM845_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns2_mem_noc }, }; =20 static struct qcom_icc_node qxm_venus1 =3D { .name =3D "qxm_venus1", - .id =3D SDM845_MASTER_VIDEO_P1, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SDM845_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns2_mem_noc }, }; =20 static struct qcom_icc_node qxm_venus_arm9 =3D { .name =3D "qxm_venus_arm9", - .id =3D SDM845_MASTER_VIDEO_PROC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SDM845_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns2_mem_noc }, }; =20 static struct qcom_icc_node qhm_snoc_cfg =3D { .name =3D "qhm_snoc_cfg", - .id =3D SDM845_MASTER_SNOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SDM845_SLAVE_SERVICE_SNOC }, + .link_nodes =3D { &srvc_snoc }, }; =20 static struct qcom_icc_node qnm_aggre1_noc =3D { .name =3D "qnm_aggre1_noc", - .id =3D SDM845_MASTER_A1NOC_SNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 6, - .links =3D { SDM845_SLAVE_APPSS, - SDM845_SLAVE_SNOC_CNOC, - SDM845_SLAVE_SNOC_MEM_NOC_SF, - SDM845_SLAVE_IMEM, - SDM845_SLAVE_PIMEM, - SDM845_SLAVE_QDSS_STM - }, + .link_nodes =3D { &qhs_apss, + &qns_cnoc, + &qns_memnoc_sf, + &qxs_imem, + &qxs_pimem, + &xs_qdss_stm }, }; =20 static struct qcom_icc_node qnm_aggre2_noc =3D { .name =3D "qnm_aggre2_noc", - .id =3D SDM845_MASTER_A2NOC_SNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 9, - .links =3D { SDM845_SLAVE_APPSS, - SDM845_SLAVE_SNOC_CNOC, - SDM845_SLAVE_SNOC_MEM_NOC_SF, - SDM845_SLAVE_IMEM, - SDM845_SLAVE_PCIE_0, - SDM845_SLAVE_PCIE_1, - SDM845_SLAVE_PIMEM, - SDM845_SLAVE_QDSS_STM, - SDM845_SLAVE_TCU - }, + .link_nodes =3D { &qhs_apss, + &qns_cnoc, + &qns_memnoc_sf, + &qxs_imem, + &qxs_pcie, + &qxs_pcie_gen3, + &qxs_pimem, + &xs_qdss_stm, + &xs_sys_tcu_cfg }, }; =20 static struct qcom_icc_node qnm_gladiator_sodv =3D { .name =3D "qnm_gladiator_sodv", - .id =3D SDM845_MASTER_GNOC_SNOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 8, - .links =3D { SDM845_SLAVE_APPSS, - SDM845_SLAVE_SNOC_CNOC, - SDM845_SLAVE_IMEM, - SDM845_SLAVE_PCIE_0, - SDM845_SLAVE_PCIE_1, - SDM845_SLAVE_PIMEM, - SDM845_SLAVE_QDSS_STM, - SDM845_SLAVE_TCU - }, + .link_nodes =3D { &qhs_apss, + &qns_cnoc, + &qxs_imem, + &qxs_pcie, + &qxs_pcie_gen3, + &qxs_pimem, + &xs_qdss_stm, + &xs_sys_tcu_cfg }, }; =20 static struct qcom_icc_node qnm_memnoc =3D { .name =3D "qnm_memnoc", - .id =3D SDM845_MASTER_MEM_NOC_SNOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 5, - .links =3D { SDM845_SLAVE_APPSS, - SDM845_SLAVE_SNOC_CNOC, - SDM845_SLAVE_IMEM, - SDM845_SLAVE_PIMEM, - SDM845_SLAVE_QDSS_STM - }, + .link_nodes =3D { &qhs_apss, + &qns_cnoc, + &qxs_imem, + &qxs_pimem, + &xs_qdss_stm }, }; =20 static struct qcom_icc_node qnm_pcie_anoc =3D { .name =3D "qnm_pcie_anoc", - .id =3D SDM845_MASTER_ANOC_PCIE_SNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 5, - .links =3D { SDM845_SLAVE_APPSS, - SDM845_SLAVE_SNOC_CNOC, - SDM845_SLAVE_SNOC_MEM_NOC_SF, - SDM845_SLAVE_IMEM, - SDM845_SLAVE_QDSS_STM - }, + .link_nodes =3D { &qhs_apss, + &qns_cnoc, + &qns_memnoc_sf, + &qxs_imem, + &xs_qdss_stm }, }; =20 static struct qcom_icc_node qxm_pimem =3D { .name =3D "qxm_pimem", - .id =3D SDM845_MASTER_PIMEM, .channels =3D 1, .buswidth =3D 8, .num_links =3D 2, - .links =3D { SDM845_SLAVE_SNOC_MEM_NOC_GC, - SDM845_SLAVE_IMEM - }, + .link_nodes =3D { &qns_memnoc_gc, + &qxs_imem }, }; =20 static struct qcom_icc_node xm_gic =3D { .name =3D "xm_gic", - .id =3D SDM845_MASTER_GIC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 2, - .links =3D { SDM845_SLAVE_SNOC_MEM_NOC_GC, - SDM845_SLAVE_IMEM - }, + .link_nodes =3D { &qns_memnoc_gc, + &qxs_imem }, }; =20 static struct qcom_icc_node qns_a1noc_snoc =3D { .name =3D "qns_a1noc_snoc", - .id =3D SDM845_SLAVE_A1NOC_SNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SDM845_MASTER_A1NOC_SNOC }, + .link_nodes =3D { &qnm_aggre1_noc }, }; =20 static struct qcom_icc_node srvc_aggre1_noc =3D { .name =3D "srvc_aggre1_noc", - .id =3D SDM845_SLAVE_SERVICE_A1NOC, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 1, - .links =3D { 0 }, }; =20 static struct qcom_icc_node qns_pcie_a1noc_snoc =3D { .name =3D "qns_pcie_a1noc_snoc", - .id =3D SDM845_SLAVE_ANOC_PCIE_A1NOC_SNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SDM845_MASTER_ANOC_PCIE_SNOC }, + .link_nodes =3D { &qnm_pcie_anoc }, }; =20 static struct qcom_icc_node qns_a2noc_snoc =3D { .name =3D "qns_a2noc_snoc", - .id =3D SDM845_SLAVE_A2NOC_SNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SDM845_MASTER_A2NOC_SNOC }, + .link_nodes =3D { &qnm_aggre2_noc }, }; =20 static struct qcom_icc_node qns_pcie_snoc =3D { .name =3D "qns_pcie_snoc", - .id =3D SDM845_SLAVE_ANOC_PCIE_SNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SDM845_MASTER_ANOC_PCIE_SNOC }, + .link_nodes =3D { &qnm_pcie_anoc }, }; =20 static struct qcom_icc_node srvc_aggre2_noc =3D { .name =3D "srvc_aggre2_noc", - .id =3D SDM845_SLAVE_SERVICE_A2NOC, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qns_camnoc_uncomp =3D { .name =3D "qns_camnoc_uncomp", - .id =3D SDM845_SLAVE_CAMNOC_UNCOMP, .channels =3D 1, .buswidth =3D 32, }; =20 static struct qcom_icc_node qhs_a1_noc_cfg =3D { .name =3D "qhs_a1_noc_cfg", - .id =3D SDM845_SLAVE_A1NOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SDM845_MASTER_A1NOC_CFG }, + .link_nodes =3D { &qhm_a1noc_cfg }, }; =20 static struct qcom_icc_node qhs_a2_noc_cfg =3D { .name =3D "qhs_a2_noc_cfg", - .id =3D SDM845_SLAVE_A2NOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SDM845_MASTER_A2NOC_CFG }, + .link_nodes =3D { &qhm_a2noc_cfg }, }; =20 static struct qcom_icc_node qhs_aop =3D { .name =3D "qhs_aop", - .id =3D SDM845_SLAVE_AOP, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_aoss =3D { .name =3D "qhs_aoss", - .id =3D SDM845_SLAVE_AOSS, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_camera_cfg =3D { .name =3D "qhs_camera_cfg", - .id =3D SDM845_SLAVE_CAMERA_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_clk_ctl =3D { .name =3D "qhs_clk_ctl", - .id =3D SDM845_SLAVE_CLK_CTL, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_compute_dsp_cfg =3D { .name =3D "qhs_compute_dsp_cfg", - .id =3D SDM845_SLAVE_CDSP_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_cpr_cx =3D { .name =3D "qhs_cpr_cx", - .id =3D SDM845_SLAVE_RBCPR_CX_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_crypto0_cfg =3D { .name =3D "qhs_crypto0_cfg", - .id =3D SDM845_SLAVE_CRYPTO_0_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_dcc_cfg =3D { .name =3D "qhs_dcc_cfg", - .id =3D SDM845_SLAVE_DCC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SDM845_MASTER_CNOC_DC_NOC }, + .link_nodes =3D { &qhm_cnoc }, }; =20 static struct qcom_icc_node qhs_ddrss_cfg =3D { .name =3D "qhs_ddrss_cfg", - .id =3D SDM845_SLAVE_CNOC_DDRSS, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_display_cfg =3D { .name =3D "qhs_display_cfg", - .id =3D SDM845_SLAVE_DISPLAY_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_glm =3D { .name =3D "qhs_glm", - .id =3D SDM845_SLAVE_GLM, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_gpuss_cfg =3D { .name =3D "qhs_gpuss_cfg", - .id =3D SDM845_SLAVE_GFX3D_CFG, .channels =3D 1, .buswidth =3D 8, }; =20 static struct qcom_icc_node qhs_imem_cfg =3D { .name =3D "qhs_imem_cfg", - .id =3D SDM845_SLAVE_IMEM_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_ipa =3D { .name =3D "qhs_ipa", - .id =3D SDM845_SLAVE_IPA_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_mnoc_cfg =3D { .name =3D "qhs_mnoc_cfg", - .id =3D SDM845_SLAVE_CNOC_MNOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SDM845_MASTER_CNOC_MNOC_CFG }, + .link_nodes =3D { &qhm_mnoc_cfg }, }; =20 static struct qcom_icc_node qhs_pcie0_cfg =3D { .name =3D "qhs_pcie0_cfg", - .id =3D SDM845_SLAVE_PCIE_0_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_pcie_gen3_cfg =3D { .name =3D "qhs_pcie_gen3_cfg", - .id =3D SDM845_SLAVE_PCIE_1_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_pdm =3D { .name =3D "qhs_pdm", - .id =3D SDM845_SLAVE_PDM, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_phy_refgen_south =3D { .name =3D "qhs_phy_refgen_south", - .id =3D SDM845_SLAVE_SOUTH_PHY_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_pimem_cfg =3D { .name =3D "qhs_pimem_cfg", - .id =3D SDM845_SLAVE_PIMEM_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_prng =3D { .name =3D "qhs_prng", - .id =3D SDM845_SLAVE_PRNG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_qdss_cfg =3D { .name =3D "qhs_qdss_cfg", - .id =3D SDM845_SLAVE_QDSS_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_qupv3_north =3D { .name =3D "qhs_qupv3_north", - .id =3D SDM845_SLAVE_BLSP_2, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_qupv3_south =3D { .name =3D "qhs_qupv3_south", - .id =3D SDM845_SLAVE_BLSP_1, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_sdc2 =3D { .name =3D "qhs_sdc2", - .id =3D SDM845_SLAVE_SDCC_2, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_sdc4 =3D { .name =3D "qhs_sdc4", - .id =3D SDM845_SLAVE_SDCC_4, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_snoc_cfg =3D { .name =3D "qhs_snoc_cfg", - .id =3D SDM845_SLAVE_SNOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SDM845_MASTER_SNOC_CFG }, + .link_nodes =3D { &qhm_snoc_cfg }, }; =20 static struct qcom_icc_node qhs_spdm =3D { .name =3D "qhs_spdm", - .id =3D SDM845_SLAVE_SPDM_WRAPPER, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_spss_cfg =3D { .name =3D "qhs_spss_cfg", - .id =3D SDM845_SLAVE_SPSS_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_tcsr =3D { .name =3D "qhs_tcsr", - .id =3D SDM845_SLAVE_TCSR, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_tlmm_north =3D { .name =3D "qhs_tlmm_north", - .id =3D SDM845_SLAVE_TLMM_NORTH, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_tlmm_south =3D { .name =3D "qhs_tlmm_south", - .id =3D SDM845_SLAVE_TLMM_SOUTH, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_tsif =3D { .name =3D "qhs_tsif", - .id =3D SDM845_SLAVE_TSIF, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_ufs_card_cfg =3D { .name =3D "qhs_ufs_card_cfg", - .id =3D SDM845_SLAVE_UFS_CARD_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_ufs_mem_cfg =3D { .name =3D "qhs_ufs_mem_cfg", - .id =3D SDM845_SLAVE_UFS_MEM_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_usb3_0 =3D { .name =3D "qhs_usb3_0", - .id =3D SDM845_SLAVE_USB3_0, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_usb3_1 =3D { .name =3D "qhs_usb3_1", - .id =3D SDM845_SLAVE_USB3_1, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_venus_cfg =3D { .name =3D "qhs_venus_cfg", - .id =3D SDM845_SLAVE_VENUS_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_vsense_ctrl_cfg =3D { .name =3D "qhs_vsense_ctrl_cfg", - .id =3D SDM845_SLAVE_VSENSE_CTRL_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qns_cnoc_a2noc =3D { .name =3D "qns_cnoc_a2noc", - .id =3D SDM845_SLAVE_CNOC_A2NOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SDM845_MASTER_CNOC_A2NOC }, + .link_nodes =3D { &qnm_cnoc }, }; =20 static struct qcom_icc_node srvc_cnoc =3D { .name =3D "srvc_cnoc", - .id =3D SDM845_SLAVE_SERVICE_CNOC, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_llcc =3D { .name =3D "qhs_llcc", - .id =3D SDM845_SLAVE_LLCC_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_memnoc =3D { .name =3D "qhs_memnoc", - .id =3D SDM845_SLAVE_MEM_NOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SDM845_MASTER_MEM_NOC_CFG }, + .link_nodes =3D { &qhm_memnoc_cfg }, }; =20 static struct qcom_icc_node qns_gladiator_sodv =3D { .name =3D "qns_gladiator_sodv", - .id =3D SDM845_SLAVE_GNOC_SNOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SDM845_MASTER_GNOC_SNOC }, + .link_nodes =3D { &qnm_gladiator_sodv }, }; =20 static struct qcom_icc_node qns_gnoc_memnoc =3D { .name =3D "qns_gnoc_memnoc", - .id =3D SDM845_SLAVE_GNOC_MEM_NOC, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SDM845_MASTER_GNOC_MEM_NOC }, + .link_nodes =3D { &qnm_apps }, }; =20 static struct qcom_icc_node srvc_gnoc =3D { .name =3D "srvc_gnoc", - .id =3D SDM845_SLAVE_SERVICE_GNOC, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node ebi =3D { .name =3D "ebi", - .id =3D SDM845_SLAVE_EBI1, .channels =3D 4, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg =3D { .name =3D "qhs_mdsp_ms_mpu_cfg", - .id =3D SDM845_SLAVE_MSS_PROC_MS_MPU_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qns_apps_io =3D { .name =3D "qns_apps_io", - .id =3D SDM845_SLAVE_MEM_NOC_GNOC, .channels =3D 1, .buswidth =3D 32, }; =20 static struct qcom_icc_node qns_llcc =3D { .name =3D "qns_llcc", - .id =3D SDM845_SLAVE_LLCC, .channels =3D 4, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SDM845_MASTER_LLCC }, + .link_nodes =3D { &llcc_mc }, }; =20 static struct qcom_icc_node qns_memnoc_snoc =3D { .name =3D "qns_memnoc_snoc", - .id =3D SDM845_SLAVE_MEM_NOC_SNOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SDM845_MASTER_MEM_NOC_SNOC }, + .link_nodes =3D { &qnm_memnoc }, }; =20 static struct qcom_icc_node srvc_memnoc =3D { .name =3D "srvc_memnoc", - .id =3D SDM845_SLAVE_SERVICE_MEM_NOC, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qns2_mem_noc =3D { .name =3D "qns2_mem_noc", - .id =3D SDM845_SLAVE_MNOC_SF_MEM_NOC, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SDM845_MASTER_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qnm_mnoc_sf }, }; =20 static struct qcom_icc_node qns_mem_noc_hf =3D { .name =3D "qns_mem_noc_hf", - .id =3D SDM845_SLAVE_MNOC_HF_MEM_NOC, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SDM845_MASTER_MNOC_HF_MEM_NOC }, + .link_nodes =3D { &qnm_mnoc_hf }, }; =20 static struct qcom_icc_node srvc_mnoc =3D { .name =3D "srvc_mnoc", - .id =3D SDM845_SLAVE_SERVICE_MNOC, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_apss =3D { .name =3D "qhs_apss", - .id =3D SDM845_SLAVE_APPSS, .channels =3D 1, .buswidth =3D 8, }; =20 static struct qcom_icc_node qns_cnoc =3D { .name =3D "qns_cnoc", - .id =3D SDM845_SLAVE_SNOC_CNOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SDM845_MASTER_SNOC_CNOC }, + .link_nodes =3D { &qnm_snoc }, }; =20 static struct qcom_icc_node qns_memnoc_gc =3D { .name =3D "qns_memnoc_gc", - .id =3D SDM845_SLAVE_SNOC_MEM_NOC_GC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SDM845_MASTER_SNOC_GC_MEM_NOC }, + .link_nodes =3D { &qnm_snoc_gc }, }; =20 static struct qcom_icc_node qns_memnoc_sf =3D { .name =3D "qns_memnoc_sf", - .id =3D SDM845_SLAVE_SNOC_MEM_NOC_SF, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SDM845_MASTER_SNOC_SF_MEM_NOC }, + .link_nodes =3D { &qnm_snoc_sf }, }; =20 static struct qcom_icc_node qxs_imem =3D { .name =3D "qxs_imem", - .id =3D SDM845_SLAVE_IMEM, .channels =3D 1, .buswidth =3D 8, }; =20 static struct qcom_icc_node qxs_pcie =3D { .name =3D "qxs_pcie", - .id =3D SDM845_SLAVE_PCIE_0, .channels =3D 1, .buswidth =3D 8, }; =20 static struct qcom_icc_node qxs_pcie_gen3 =3D { .name =3D "qxs_pcie_gen3", - .id =3D SDM845_SLAVE_PCIE_1, .channels =3D 1, .buswidth =3D 8, }; =20 static struct qcom_icc_node qxs_pimem =3D { .name =3D "qxs_pimem", - .id =3D SDM845_SLAVE_PIMEM, .channels =3D 1, .buswidth =3D 8, }; =20 static struct qcom_icc_node srvc_snoc =3D { .name =3D "srvc_snoc", - .id =3D SDM845_SLAVE_SERVICE_SNOC, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node xs_qdss_stm =3D { .name =3D "xs_qdss_stm", - .id =3D SDM845_SLAVE_QDSS_STM, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node xs_sys_tcu_cfg =3D { .name =3D "xs_sys_tcu_cfg", - .id =3D SDM845_SLAVE_TCU, .channels =3D 1, .buswidth =3D 8, }; @@ -1534,6 +1514,7 @@ static struct qcom_icc_node * const aggre1_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sdm845_aggre1_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D aggre1_noc_nodes, .num_nodes =3D ARRAY_SIZE(aggre1_noc_nodes), .bcms =3D aggre1_noc_bcms, @@ -1563,6 +1544,7 @@ static struct qcom_icc_node * const aggre2_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sdm845_aggre2_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D aggre2_noc_nodes, .num_nodes =3D ARRAY_SIZE(aggre2_noc_nodes), .bcms =3D aggre2_noc_bcms, @@ -1624,6 +1606,7 @@ static struct qcom_icc_node * const config_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sdm845_config_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D config_noc_nodes, .num_nodes =3D ARRAY_SIZE(config_noc_nodes), .bcms =3D config_noc_bcms, @@ -1640,6 +1623,7 @@ static struct qcom_icc_node * const dc_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sdm845_dc_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D dc_noc_nodes, .num_nodes =3D ARRAY_SIZE(dc_noc_nodes), .bcms =3D dc_noc_bcms, @@ -1658,6 +1642,7 @@ static struct qcom_icc_node * const gladiator_noc_nod= es[] =3D { }; =20 static const struct qcom_icc_desc sdm845_gladiator_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D gladiator_noc_nodes, .num_nodes =3D ARRAY_SIZE(gladiator_noc_nodes), .bcms =3D gladiator_noc_bcms, @@ -1693,6 +1678,7 @@ static struct qcom_icc_node * const mem_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sdm845_mem_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D mem_noc_nodes, .num_nodes =3D ARRAY_SIZE(mem_noc_nodes), .bcms =3D mem_noc_bcms, @@ -1727,6 +1713,7 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sdm845_mmss_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D mmss_noc_nodes, .num_nodes =3D ARRAY_SIZE(mmss_noc_nodes), .bcms =3D mmss_noc_bcms, @@ -1773,6 +1760,7 @@ static struct qcom_icc_node * const system_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sdm845_system_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D system_noc_nodes, .num_nodes =3D ARRAY_SIZE(system_noc_nodes), .bcms =3D system_noc_bcms, diff --git a/drivers/interconnect/qcom/sdm845.h b/drivers/interconnect/qcom= /sdm845.h deleted file mode 100644 index bc7e425ce9852288da16c49345e77f6374267365..000000000000000000000000000= 0000000000000 --- a/drivers/interconnect/qcom/sdm845.h +++ /dev/null @@ -1,140 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2020, The Linux Foundation. All rights reserved. - */ - -#ifndef __DRIVERS_INTERCONNECT_QCOM_SDM845_H__ -#define __DRIVERS_INTERCONNECT_QCOM_SDM845_H__ - -#define SDM845_MASTER_A1NOC_CFG 1 -#define SDM845_MASTER_BLSP_1 2 -#define SDM845_MASTER_TSIF 3 -#define SDM845_MASTER_SDCC_2 4 -#define SDM845_MASTER_SDCC_4 5 -#define SDM845_MASTER_UFS_CARD 6 -#define SDM845_MASTER_UFS_MEM 7 -#define SDM845_MASTER_PCIE_0 8 -#define SDM845_MASTER_A2NOC_CFG 9 -#define SDM845_MASTER_QDSS_BAM 10 -#define SDM845_MASTER_BLSP_2 11 -#define SDM845_MASTER_CNOC_A2NOC 12 -#define SDM845_MASTER_CRYPTO 13 -#define SDM845_MASTER_IPA 14 -#define SDM845_MASTER_PCIE_1 15 -#define SDM845_MASTER_QDSS_ETR 16 -#define SDM845_MASTER_USB3_0 17 -#define SDM845_MASTER_USB3_1 18 -#define SDM845_MASTER_CAMNOC_HF0_UNCOMP 19 -#define SDM845_MASTER_CAMNOC_HF1_UNCOMP 20 -#define SDM845_MASTER_CAMNOC_SF_UNCOMP 21 -#define SDM845_MASTER_SPDM 22 -#define SDM845_MASTER_TIC 23 -#define SDM845_MASTER_SNOC_CNOC 24 -#define SDM845_MASTER_QDSS_DAP 25 -#define SDM845_MASTER_CNOC_DC_NOC 26 -#define SDM845_MASTER_APPSS_PROC 27 -#define SDM845_MASTER_GNOC_CFG 28 -#define SDM845_MASTER_LLCC 29 -#define SDM845_MASTER_TCU_0 30 -#define SDM845_MASTER_MEM_NOC_CFG 31 -#define SDM845_MASTER_GNOC_MEM_NOC 32 -#define SDM845_MASTER_MNOC_HF_MEM_NOC 33 -#define SDM845_MASTER_MNOC_SF_MEM_NOC 34 -#define SDM845_MASTER_SNOC_GC_MEM_NOC 35 -#define SDM845_MASTER_SNOC_SF_MEM_NOC 36 -#define SDM845_MASTER_GFX3D 37 -#define SDM845_MASTER_CNOC_MNOC_CFG 38 -#define SDM845_MASTER_CAMNOC_HF0 39 -#define SDM845_MASTER_CAMNOC_HF1 40 -#define SDM845_MASTER_CAMNOC_SF 41 -#define SDM845_MASTER_MDP0 42 -#define SDM845_MASTER_MDP1 43 -#define SDM845_MASTER_ROTATOR 44 -#define SDM845_MASTER_VIDEO_P0 45 -#define SDM845_MASTER_VIDEO_P1 46 -#define SDM845_MASTER_VIDEO_PROC 47 -#define SDM845_MASTER_SNOC_CFG 48 -#define SDM845_MASTER_A1NOC_SNOC 49 -#define SDM845_MASTER_A2NOC_SNOC 50 -#define SDM845_MASTER_GNOC_SNOC 51 -#define SDM845_MASTER_MEM_NOC_SNOC 52 -#define SDM845_MASTER_ANOC_PCIE_SNOC 53 -#define SDM845_MASTER_PIMEM 54 -#define SDM845_MASTER_GIC 55 -#define SDM845_SLAVE_A1NOC_SNOC 56 -#define SDM845_SLAVE_SERVICE_A1NOC 57 -#define SDM845_SLAVE_ANOC_PCIE_A1NOC_SNOC 58 -#define SDM845_SLAVE_A2NOC_SNOC 59 -#define SDM845_SLAVE_ANOC_PCIE_SNOC 60 -#define SDM845_SLAVE_SERVICE_A2NOC 61 -#define SDM845_SLAVE_CAMNOC_UNCOMP 62 -#define SDM845_SLAVE_A1NOC_CFG 63 -#define SDM845_SLAVE_A2NOC_CFG 64 -#define SDM845_SLAVE_AOP 65 -#define SDM845_SLAVE_AOSS 66 -#define SDM845_SLAVE_CAMERA_CFG 67 -#define SDM845_SLAVE_CLK_CTL 68 -#define SDM845_SLAVE_CDSP_CFG 69 -#define SDM845_SLAVE_RBCPR_CX_CFG 70 -#define SDM845_SLAVE_CRYPTO_0_CFG 71 -#define SDM845_SLAVE_DCC_CFG 72 -#define SDM845_SLAVE_CNOC_DDRSS 73 -#define SDM845_SLAVE_DISPLAY_CFG 74 -#define SDM845_SLAVE_GLM 75 -#define SDM845_SLAVE_GFX3D_CFG 76 -#define SDM845_SLAVE_IMEM_CFG 77 -#define SDM845_SLAVE_IPA_CFG 78 -#define SDM845_SLAVE_CNOC_MNOC_CFG 79 -#define SDM845_SLAVE_PCIE_0_CFG 80 -#define SDM845_SLAVE_PCIE_1_CFG 81 -#define SDM845_SLAVE_PDM 82 -#define SDM845_SLAVE_SOUTH_PHY_CFG 83 -#define SDM845_SLAVE_PIMEM_CFG 84 -#define SDM845_SLAVE_PRNG 85 -#define SDM845_SLAVE_QDSS_CFG 86 -#define SDM845_SLAVE_BLSP_2 87 -#define SDM845_SLAVE_BLSP_1 88 -#define SDM845_SLAVE_SDCC_2 89 -#define SDM845_SLAVE_SDCC_4 90 -#define SDM845_SLAVE_SNOC_CFG 91 -#define SDM845_SLAVE_SPDM_WRAPPER 92 -#define SDM845_SLAVE_SPSS_CFG 93 -#define SDM845_SLAVE_TCSR 94 -#define SDM845_SLAVE_TLMM_NORTH 95 -#define SDM845_SLAVE_TLMM_SOUTH 96 -#define SDM845_SLAVE_TSIF 97 -#define SDM845_SLAVE_UFS_CARD_CFG 98 -#define SDM845_SLAVE_UFS_MEM_CFG 99 -#define SDM845_SLAVE_USB3_0 100 -#define SDM845_SLAVE_USB3_1 101 -#define SDM845_SLAVE_VENUS_CFG 102 -#define SDM845_SLAVE_VSENSE_CTRL_CFG 103 -#define SDM845_SLAVE_CNOC_A2NOC 104 -#define SDM845_SLAVE_SERVICE_CNOC 105 -#define SDM845_SLAVE_LLCC_CFG 106 -#define SDM845_SLAVE_MEM_NOC_CFG 107 -#define SDM845_SLAVE_GNOC_SNOC 108 -#define SDM845_SLAVE_GNOC_MEM_NOC 109 -#define SDM845_SLAVE_SERVICE_GNOC 110 -#define SDM845_SLAVE_EBI1 111 -#define SDM845_SLAVE_MSS_PROC_MS_MPU_CFG 112 -#define SDM845_SLAVE_MEM_NOC_GNOC 113 -#define SDM845_SLAVE_LLCC 114 -#define SDM845_SLAVE_MEM_NOC_SNOC 115 -#define SDM845_SLAVE_SERVICE_MEM_NOC 116 -#define SDM845_SLAVE_MNOC_SF_MEM_NOC 117 -#define SDM845_SLAVE_MNOC_HF_MEM_NOC 118 -#define SDM845_SLAVE_SERVICE_MNOC 119 -#define SDM845_SLAVE_APPSS 120 -#define SDM845_SLAVE_SNOC_CNOC 121 -#define SDM845_SLAVE_SNOC_MEM_NOC_GC 122 -#define SDM845_SLAVE_SNOC_MEM_NOC_SF 123 -#define SDM845_SLAVE_IMEM 124 -#define SDM845_SLAVE_PCIE_0 125 -#define SDM845_SLAVE_PCIE_1 126 -#define SDM845_SLAVE_PIMEM 127 -#define SDM845_SLAVE_SERVICE_SNOC 128 -#define SDM845_SLAVE_QDSS_STM 129 -#define SDM845_SLAVE_TCU 130 - -#endif /* __DRIVERS_INTERCONNECT_QCOM_SDM845_H__ */ --=20 2.47.3