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This gives more flexibility and also allows us to drop the .num_links member, saving from possible errors related to it being not set or set incorrectly. Signed-off-by: Dmitry Baryshkov --- drivers/interconnect/qcom/sm8750.c | 616 ++++++++++++++-------------------= ---- 1 file changed, 230 insertions(+), 386 deletions(-) diff --git a/drivers/interconnect/qcom/sm8750.c b/drivers/interconnect/qcom= /sm8750.c index 69bc22222075280365eb419f1ad140d1aa4e752d..a46c1553ce0fd13b99a7d327eb5= 75b232bc36509 100644 --- a/drivers/interconnect/qcom/sm8750.c +++ b/drivers/interconnect/qcom/sm8750.c @@ -14,1181 +14,1011 @@ #include "bcm-voter.h" #include "icc-rpmh.h" =20 -#define SM8750_MASTER_GPU_TCU 0 -#define SM8750_MASTER_SYS_TCU 1 -#define SM8750_MASTER_APPSS_PROC 2 -#define SM8750_MASTER_LLCC 3 -#define SM8750_MASTER_QDSS_BAM 4 -#define SM8750_MASTER_QSPI_0 5 -#define SM8750_MASTER_QUP_1 6 -#define SM8750_MASTER_QUP_2 7 -#define SM8750_MASTER_A1NOC_SNOC 8 -#define SM8750_MASTER_A2NOC_SNOC 9 -#define SM8750_MASTER_CAMNOC_HF 10 -#define SM8750_MASTER_CAMNOC_NRT_ICP_SF 11 -#define SM8750_MASTER_CAMNOC_RT_CDM_SF 12 -#define SM8750_MASTER_CAMNOC_SF 13 -#define SM8750_MASTER_GEM_NOC_CNOC 14 -#define SM8750_MASTER_GEM_NOC_PCIE_SNOC 15 -#define SM8750_MASTER_GFX3D 16 -#define SM8750_MASTER_LPASS_GEM_NOC 17 -#define SM8750_MASTER_LPASS_LPINOC 18 -#define SM8750_MASTER_LPIAON_NOC 19 -#define SM8750_MASTER_LPASS_PROC 20 -#define SM8750_MASTER_MDP 21 -#define SM8750_MASTER_MSS_PROC 22 -#define SM8750_MASTER_MNOC_HF_MEM_NOC 23 -#define SM8750_MASTER_MNOC_SF_MEM_NOC 24 -#define SM8750_MASTER_CDSP_PROC 25 -#define SM8750_MASTER_COMPUTE_NOC 26 -#define SM8750_MASTER_ANOC_PCIE_GEM_NOC 27 -#define SM8750_MASTER_SNOC_SF_MEM_NOC 28 -#define SM8750_MASTER_UBWC_P 29 -#define SM8750_MASTER_CDSP_HCP 30 -#define SM8750_MASTER_VIDEO_CV_PROC 31 -#define SM8750_MASTER_VIDEO_EVA 32 -#define SM8750_MASTER_VIDEO_MVP 33 -#define SM8750_MASTER_VIDEO_V_PROC 34 -#define SM8750_MASTER_CNOC_CFG 35 -#define SM8750_MASTER_CNOC_MNOC_CFG 36 -#define SM8750_MASTER_PCIE_ANOC_CFG 37 -#define SM8750_MASTER_QUP_CORE_0 38 -#define SM8750_MASTER_QUP_CORE_1 39 -#define SM8750_MASTER_QUP_CORE_2 40 -#define SM8750_MASTER_CRYPTO 41 -#define SM8750_MASTER_IPA 42 -#define SM8750_MASTER_QUP_3 43 -#define SM8750_MASTER_SOCCP_AGGR_NOC 44 -#define SM8750_MASTER_SP 45 -#define SM8750_MASTER_GIC 46 -#define SM8750_MASTER_PCIE_0 47 -#define SM8750_MASTER_QDSS_ETR 48 -#define SM8750_MASTER_QDSS_ETR_1 49 -#define SM8750_MASTER_SDCC_2 50 -#define SM8750_MASTER_SDCC_4 51 -#define SM8750_MASTER_UFS_MEM 52 -#define SM8750_MASTER_USB3_0 53 -#define SM8750_SLAVE_UBWC_P 54 -#define SM8750_SLAVE_EBI1 55 -#define SM8750_SLAVE_AHB2PHY_SOUTH 56 -#define SM8750_SLAVE_AHB2PHY_NORTH 57 -#define SM8750_SLAVE_AOSS 58 -#define SM8750_SLAVE_CAMERA_CFG 59 -#define SM8750_SLAVE_CLK_CTL 60 -#define SM8750_SLAVE_CRYPTO_0_CFG 61 -#define SM8750_SLAVE_DISPLAY_CFG 62 -#define SM8750_SLAVE_EVA_CFG 63 -#define SM8750_SLAVE_GFX3D_CFG 64 -#define SM8750_SLAVE_I2C 65 -#define SM8750_SLAVE_I3C_IBI0_CFG 66 -#define SM8750_SLAVE_I3C_IBI1_CFG 67 -#define SM8750_SLAVE_IMEM_CFG 68 -#define SM8750_SLAVE_IPA_CFG 69 -#define SM8750_SLAVE_IPC_ROUTER_CFG 70 -#define SM8750_SLAVE_CNOC_MSS 71 -#define SM8750_SLAVE_PCIE_CFG 72 -#define SM8750_SLAVE_PRNG 73 -#define SM8750_SLAVE_QDSS_CFG 74 -#define SM8750_SLAVE_QSPI_0 75 -#define SM8750_SLAVE_QUP_3 76 -#define SM8750_SLAVE_QUP_1 77 -#define SM8750_SLAVE_QUP_2 78 -#define SM8750_SLAVE_SDCC_2 79 -#define SM8750_SLAVE_SDCC_4 80 -#define SM8750_SLAVE_SOCCP 81 -#define SM8750_SLAVE_SPSS_CFG 82 -#define SM8750_SLAVE_TCSR 83 -#define SM8750_SLAVE_TLMM 84 -#define SM8750_SLAVE_TME_CFG 85 -#define SM8750_SLAVE_UFS_MEM_CFG 86 -#define SM8750_SLAVE_USB3_0 87 -#define SM8750_SLAVE_VENUS_CFG 88 -#define SM8750_SLAVE_VSENSE_CTRL_CFG 89 -#define SM8750_SLAVE_A1NOC_SNOC 90 -#define SM8750_SLAVE_A2NOC_SNOC 91 -#define SM8750_SLAVE_APPSS 92 -#define SM8750_SLAVE_GEM_NOC_CNOC 93 -#define SM8750_SLAVE_SNOC_GEM_NOC_SF 94 -#define SM8750_SLAVE_LLCC 95 -#define SM8750_SLAVE_LPASS_GEM_NOC 96 -#define SM8750_SLAVE_LPIAON_NOC_LPASS_AG_NOC 97 -#define SM8750_SLAVE_LPICX_NOC_LPIAON_NOC 98 -#define SM8750_SLAVE_MNOC_HF_MEM_NOC 99 -#define SM8750_SLAVE_MNOC_SF_MEM_NOC 100 -#define SM8750_SLAVE_CDSP_MEM_NOC 101 -#define SM8750_SLAVE_MEM_NOC_PCIE_SNOC 102 -#define SM8750_SLAVE_ANOC_PCIE_GEM_NOC 103 -#define SM8750_SLAVE_CNOC_CFG 104 -#define SM8750_SLAVE_DDRSS_CFG 105 -#define SM8750_SLAVE_CNOC_MNOC_CFG 106 -#define SM8750_SLAVE_PCIE_ANOC_CFG 107 -#define SM8750_SLAVE_QUP_CORE_0 108 -#define SM8750_SLAVE_QUP_CORE_1 109 -#define SM8750_SLAVE_QUP_CORE_2 110 -#define SM8750_SLAVE_BOOT_IMEM 111 -#define SM8750_SLAVE_IMEM 112 -#define SM8750_SLAVE_BOOT_IMEM_2 113 -#define SM8750_SLAVE_SERVICE_CNOC 114 -#define SM8750_SLAVE_SERVICE_MNOC 115 -#define SM8750_SLAVE_SERVICE_PCIE_ANOC 116 -#define SM8750_SLAVE_PCIE_0 117 -#define SM8750_SLAVE_QDSS_STM 118 -#define SM8750_SLAVE_TCU 119 +static struct qcom_icc_node qhm_qspi; +static struct qcom_icc_node qhm_qup1; +static struct qcom_icc_node qxm_qup02; +static struct qcom_icc_node xm_sdc4; +static struct qcom_icc_node xm_ufs_mem; +static struct qcom_icc_node xm_usb3_0; +static struct qcom_icc_node qhm_qdss_bam; +static struct qcom_icc_node qhm_qup2; +static struct qcom_icc_node qxm_crypto; +static struct qcom_icc_node qxm_ipa; +static struct qcom_icc_node qxm_soccp; +static struct qcom_icc_node qxm_sp; +static struct qcom_icc_node xm_qdss_etr_0; +static struct qcom_icc_node xm_qdss_etr_1; +static struct qcom_icc_node xm_sdc2; +static struct qcom_icc_node qup0_core_master; +static struct qcom_icc_node qup1_core_master; +static struct qcom_icc_node qup2_core_master; +static struct qcom_icc_node qsm_cfg; +static struct qcom_icc_node qnm_gemnoc_cnoc; +static struct qcom_icc_node qnm_gemnoc_pcie; +static struct qcom_icc_node alm_gpu_tcu; +static struct qcom_icc_node alm_sys_tcu; +static struct qcom_icc_node chm_apps; +static struct qcom_icc_node qnm_gpu; +static struct qcom_icc_node qnm_lpass_gemnoc; +static struct qcom_icc_node qnm_mdsp; +static struct qcom_icc_node qnm_mnoc_hf; +static struct qcom_icc_node qnm_mnoc_sf; +static struct qcom_icc_node qnm_nsp_gemnoc; +static struct qcom_icc_node qnm_pcie; +static struct qcom_icc_node qnm_snoc_sf; +static struct qcom_icc_node qnm_ubwc_p; +static struct qcom_icc_node xm_gic; +static struct qcom_icc_node qnm_lpiaon_noc; +static struct qcom_icc_node qnm_lpass_lpinoc; +static struct qcom_icc_node qnm_lpinoc_dsp_qns4m; +static struct qcom_icc_node llcc_mc; +static struct qcom_icc_node qnm_camnoc_hf; +static struct qcom_icc_node qnm_camnoc_nrt_icp_sf; +static struct qcom_icc_node qnm_camnoc_rt_cdm_sf; +static struct qcom_icc_node qnm_camnoc_sf; +static struct qcom_icc_node qnm_mdp; +static struct qcom_icc_node qnm_vapss_hcp; +static struct qcom_icc_node qnm_video_cv_cpu; +static struct qcom_icc_node qnm_video_eva; +static struct qcom_icc_node qnm_video_mvp; +static struct qcom_icc_node qnm_video_v_cpu; +static struct qcom_icc_node qsm_mnoc_cfg; +static struct qcom_icc_node qnm_nsp; +static struct qcom_icc_node qsm_pcie_anoc_cfg; +static struct qcom_icc_node xm_pcie3; +static struct qcom_icc_node qnm_aggre1_noc; +static struct qcom_icc_node qnm_aggre2_noc; +static struct qcom_icc_node qns_a1noc_snoc; +static struct qcom_icc_node qns_a2noc_snoc; +static struct qcom_icc_node qup0_core_slave; +static struct qcom_icc_node qup1_core_slave; +static struct qcom_icc_node qup2_core_slave; +static struct qcom_icc_node qhs_ahb2phy0; +static struct qcom_icc_node qhs_ahb2phy1; +static struct qcom_icc_node qhs_camera_cfg; +static struct qcom_icc_node qhs_clk_ctl; +static struct qcom_icc_node qhs_crypto0_cfg; +static struct qcom_icc_node qhs_display_cfg; +static struct qcom_icc_node qhs_eva_cfg; +static struct qcom_icc_node qhs_gpuss_cfg; +static struct qcom_icc_node qhs_i2c; +static struct qcom_icc_node qhs_i3c_ibi0_cfg; +static struct qcom_icc_node qhs_i3c_ibi1_cfg; +static struct qcom_icc_node qhs_imem_cfg; +static struct qcom_icc_node qhs_mss_cfg; +static struct qcom_icc_node qhs_pcie_cfg; +static struct qcom_icc_node qhs_prng; +static struct qcom_icc_node qhs_qdss_cfg; +static struct qcom_icc_node qhs_qspi; +static struct qcom_icc_node qhs_qup02; +static struct qcom_icc_node qhs_qup1; +static struct qcom_icc_node qhs_qup2; +static struct qcom_icc_node qhs_sdc2; +static struct qcom_icc_node qhs_sdc4; +static struct qcom_icc_node qhs_spss_cfg; +static struct qcom_icc_node qhs_tcsr; +static struct qcom_icc_node qhs_tlmm; +static struct qcom_icc_node qhs_ufs_mem_cfg; +static struct qcom_icc_node qhs_usb3_0; +static struct qcom_icc_node qhs_venus_cfg; +static struct qcom_icc_node qhs_vsense_ctrl_cfg; +static struct qcom_icc_node qss_mnoc_cfg; +static struct qcom_icc_node qss_pcie_anoc_cfg; +static struct qcom_icc_node xs_qdss_stm; +static struct qcom_icc_node xs_sys_tcu_cfg; +static struct qcom_icc_node qhs_aoss; +static struct qcom_icc_node qhs_ipa; +static struct qcom_icc_node qhs_ipc_router; +static struct qcom_icc_node qhs_soccp; +static struct qcom_icc_node qhs_tme_cfg; +static struct qcom_icc_node qns_apss; +static struct qcom_icc_node qss_cfg; +static struct qcom_icc_node qss_ddrss_cfg; +static struct qcom_icc_node qxs_boot_imem; +static struct qcom_icc_node qxs_imem; +static struct qcom_icc_node qxs_modem_boot_imem; +static struct qcom_icc_node srvc_cnoc_main; +static struct qcom_icc_node xs_pcie; +static struct qcom_icc_node chs_ubwc_p; +static struct qcom_icc_node qns_gem_noc_cnoc; +static struct qcom_icc_node qns_llcc; +static struct qcom_icc_node qns_pcie; +static struct qcom_icc_node qns_lpass_ag_noc_gemnoc; +static struct qcom_icc_node qns_lpass_aggnoc; +static struct qcom_icc_node qns_lpi_aon_noc; +static struct qcom_icc_node ebi; +static struct qcom_icc_node qns_mem_noc_hf; +static struct qcom_icc_node qns_mem_noc_sf; +static struct qcom_icc_node srvc_mnoc; +static struct qcom_icc_node qns_nsp_gemnoc; +static struct qcom_icc_node qns_pcie_mem_noc; +static struct qcom_icc_node srvc_pcie_aggre_noc; +static struct qcom_icc_node qns_gemnoc_sf; =20 static struct qcom_icc_node qhm_qspi =3D { .name =3D "qhm_qspi", - .id =3D SM8750_MASTER_QSPI_0, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8750_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node qhm_qup1 =3D { .name =3D "qhm_qup1", - .id =3D SM8750_MASTER_QUP_1, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8750_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node qxm_qup02 =3D { .name =3D "qxm_qup02", - .id =3D SM8750_MASTER_QUP_3, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8750_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node xm_sdc4 =3D { .name =3D "xm_sdc4", - .id =3D SM8750_MASTER_SDCC_4, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8750_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node xm_ufs_mem =3D { .name =3D "xm_ufs_mem", - .id =3D SM8750_MASTER_UFS_MEM, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM8750_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node xm_usb3_0 =3D { .name =3D "xm_usb3_0", - .id =3D SM8750_MASTER_USB3_0, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8750_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node qhm_qdss_bam =3D { .name =3D "qhm_qdss_bam", - .id =3D SM8750_MASTER_QDSS_BAM, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8750_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qhm_qup2 =3D { .name =3D "qhm_qup2", - .id =3D SM8750_MASTER_QUP_2, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8750_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qxm_crypto =3D { .name =3D "qxm_crypto", - .id =3D SM8750_MASTER_CRYPTO, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8750_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qxm_ipa =3D { .name =3D "qxm_ipa", - .id =3D SM8750_MASTER_IPA, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8750_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qxm_soccp =3D { .name =3D "qxm_soccp", - .id =3D SM8750_MASTER_SOCCP_AGGR_NOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8750_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qxm_sp =3D { .name =3D "qxm_sp", - .id =3D SM8750_MASTER_SP, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8750_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node xm_qdss_etr_0 =3D { .name =3D "xm_qdss_etr_0", - .id =3D SM8750_MASTER_QDSS_ETR, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8750_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node xm_qdss_etr_1 =3D { .name =3D "xm_qdss_etr_1", - .id =3D SM8750_MASTER_QDSS_ETR_1, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8750_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node xm_sdc2 =3D { .name =3D "xm_sdc2", - .id =3D SM8750_MASTER_SDCC_2, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8750_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qup0_core_master =3D { .name =3D "qup0_core_master", - .id =3D SM8750_MASTER_QUP_CORE_0, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8750_SLAVE_QUP_CORE_0 }, + .link_nodes =3D { &qup0_core_slave }, }; =20 static struct qcom_icc_node qup1_core_master =3D { .name =3D "qup1_core_master", - .id =3D SM8750_MASTER_QUP_CORE_1, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8750_SLAVE_QUP_CORE_1 }, + .link_nodes =3D { &qup1_core_slave }, }; =20 static struct qcom_icc_node qup2_core_master =3D { .name =3D "qup2_core_master", - .id =3D SM8750_MASTER_QUP_CORE_2, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8750_SLAVE_QUP_CORE_2 }, + .link_nodes =3D { &qup2_core_slave }, }; =20 static struct qcom_icc_node qsm_cfg =3D { .name =3D "qsm_cfg", - .id =3D SM8750_MASTER_CNOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 33, - .links =3D { SM8750_SLAVE_AHB2PHY_SOUTH, SM8750_SLAVE_AHB2PHY_NORTH, - SM8750_SLAVE_CAMERA_CFG, SM8750_SLAVE_CLK_CTL, - SM8750_SLAVE_CRYPTO_0_CFG, SM8750_SLAVE_DISPLAY_CFG, - SM8750_SLAVE_EVA_CFG, SM8750_SLAVE_GFX3D_CFG, - SM8750_SLAVE_I2C, SM8750_SLAVE_I3C_IBI0_CFG, - SM8750_SLAVE_I3C_IBI1_CFG, SM8750_SLAVE_IMEM_CFG, - SM8750_SLAVE_CNOC_MSS, SM8750_SLAVE_PCIE_CFG, - SM8750_SLAVE_PRNG, SM8750_SLAVE_QDSS_CFG, - SM8750_SLAVE_QSPI_0, SM8750_SLAVE_QUP_3, - SM8750_SLAVE_QUP_1, SM8750_SLAVE_QUP_2, - SM8750_SLAVE_SDCC_2, SM8750_SLAVE_SDCC_4, - SM8750_SLAVE_SPSS_CFG, SM8750_SLAVE_TCSR, - SM8750_SLAVE_TLMM, SM8750_SLAVE_UFS_MEM_CFG, - SM8750_SLAVE_USB3_0, SM8750_SLAVE_VENUS_CFG, - SM8750_SLAVE_VSENSE_CTRL_CFG, SM8750_SLAVE_CNOC_MNOC_CFG, - SM8750_SLAVE_PCIE_ANOC_CFG, SM8750_SLAVE_QDSS_STM, - SM8750_SLAVE_TCU }, + .link_nodes =3D { &qhs_ahb2phy0, &qhs_ahb2phy1, + &qhs_camera_cfg, &qhs_clk_ctl, + &qhs_crypto0_cfg, &qhs_display_cfg, + &qhs_eva_cfg, &qhs_gpuss_cfg, + &qhs_i2c, &qhs_i3c_ibi0_cfg, + &qhs_i3c_ibi1_cfg, &qhs_imem_cfg, + &qhs_mss_cfg, &qhs_pcie_cfg, + &qhs_prng, &qhs_qdss_cfg, + &qhs_qspi, &qhs_qup02, + &qhs_qup1, &qhs_qup2, + &qhs_sdc2, &qhs_sdc4, + &qhs_spss_cfg, &qhs_tcsr, + &qhs_tlmm, &qhs_ufs_mem_cfg, + &qhs_usb3_0, &qhs_venus_cfg, + &qhs_vsense_ctrl_cfg, &qss_mnoc_cfg, + &qss_pcie_anoc_cfg, &xs_qdss_stm, + &xs_sys_tcu_cfg }, }; =20 static struct qcom_icc_node qnm_gemnoc_cnoc =3D { .name =3D "qnm_gemnoc_cnoc", - .id =3D SM8750_MASTER_GEM_NOC_CNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 12, - .links =3D { SM8750_SLAVE_AOSS, SM8750_SLAVE_IPA_CFG, - SM8750_SLAVE_IPC_ROUTER_CFG, SM8750_SLAVE_SOCCP, - SM8750_SLAVE_TME_CFG, SM8750_SLAVE_APPSS, - SM8750_SLAVE_CNOC_CFG, SM8750_SLAVE_DDRSS_CFG, - SM8750_SLAVE_BOOT_IMEM, SM8750_SLAVE_IMEM, - SM8750_SLAVE_BOOT_IMEM_2, SM8750_SLAVE_SERVICE_CNOC }, + .link_nodes =3D { &qhs_aoss, &qhs_ipa, + &qhs_ipc_router, &qhs_soccp, + &qhs_tme_cfg, &qns_apss, + &qss_cfg, &qss_ddrss_cfg, + &qxs_boot_imem, &qxs_imem, + &qxs_modem_boot_imem, &srvc_cnoc_main }, }; =20 static struct qcom_icc_node qnm_gemnoc_pcie =3D { .name =3D "qnm_gemnoc_pcie", - .id =3D SM8750_MASTER_GEM_NOC_PCIE_SNOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8750_SLAVE_PCIE_0 }, + .link_nodes =3D { &xs_pcie }, }; =20 static struct qcom_icc_node alm_gpu_tcu =3D { .name =3D "alm_gpu_tcu", - .id =3D SM8750_MASTER_GPU_TCU, .channels =3D 1, .buswidth =3D 8, .num_links =3D 2, - .links =3D { SM8750_SLAVE_GEM_NOC_CNOC, SM8750_SLAVE_LLCC }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; =20 static struct qcom_icc_node alm_sys_tcu =3D { .name =3D "alm_sys_tcu", - .id =3D SM8750_MASTER_SYS_TCU, .channels =3D 1, .buswidth =3D 8, .num_links =3D 2, - .links =3D { SM8750_SLAVE_GEM_NOC_CNOC, SM8750_SLAVE_LLCC }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; =20 static struct qcom_icc_node chm_apps =3D { .name =3D "chm_apps", - .id =3D SM8750_MASTER_APPSS_PROC, .channels =3D 4, .buswidth =3D 32, .num_links =3D 4, - .links =3D { SM8750_SLAVE_UBWC_P, SM8750_SLAVE_GEM_NOC_CNOC, - SM8750_SLAVE_LLCC, SM8750_SLAVE_MEM_NOC_PCIE_SNOC }, + .link_nodes =3D { &chs_ubwc_p, &qns_gem_noc_cnoc, + &qns_llcc, &qns_pcie }, }; =20 static struct qcom_icc_node qnm_gpu =3D { .name =3D "qnm_gpu", - .id =3D SM8750_MASTER_GFX3D, .channels =3D 2, .buswidth =3D 32, .num_links =3D 2, - .links =3D { SM8750_SLAVE_GEM_NOC_CNOC, SM8750_SLAVE_LLCC }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; =20 static struct qcom_icc_node qnm_lpass_gemnoc =3D { .name =3D "qnm_lpass_gemnoc", - .id =3D SM8750_MASTER_LPASS_GEM_NOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 3, - .links =3D { SM8750_SLAVE_GEM_NOC_CNOC, SM8750_SLAVE_LLCC, - SM8750_SLAVE_MEM_NOC_PCIE_SNOC }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, }; =20 static struct qcom_icc_node qnm_mdsp =3D { .name =3D "qnm_mdsp", - .id =3D SM8750_MASTER_MSS_PROC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 3, - .links =3D { SM8750_SLAVE_GEM_NOC_CNOC, SM8750_SLAVE_LLCC, - SM8750_SLAVE_MEM_NOC_PCIE_SNOC }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, }; =20 static struct qcom_icc_node qnm_mnoc_hf =3D { .name =3D "qnm_mnoc_hf", - .id =3D SM8750_MASTER_MNOC_HF_MEM_NOC, .channels =3D 2, .buswidth =3D 32, .num_links =3D 2, - .links =3D { SM8750_SLAVE_GEM_NOC_CNOC, SM8750_SLAVE_LLCC }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; =20 static struct qcom_icc_node qnm_mnoc_sf =3D { .name =3D "qnm_mnoc_sf", - .id =3D SM8750_MASTER_MNOC_SF_MEM_NOC, .channels =3D 2, .buswidth =3D 32, .num_links =3D 2, - .links =3D { SM8750_SLAVE_GEM_NOC_CNOC, SM8750_SLAVE_LLCC }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; =20 static struct qcom_icc_node qnm_nsp_gemnoc =3D { .name =3D "qnm_nsp_gemnoc", - .id =3D SM8750_MASTER_COMPUTE_NOC, .channels =3D 2, .buswidth =3D 32, .num_links =3D 3, - .links =3D { SM8750_SLAVE_GEM_NOC_CNOC, SM8750_SLAVE_LLCC, - SM8750_SLAVE_MEM_NOC_PCIE_SNOC }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, }; =20 static struct qcom_icc_node qnm_pcie =3D { .name =3D "qnm_pcie", - .id =3D SM8750_MASTER_ANOC_PCIE_GEM_NOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 2, - .links =3D { SM8750_SLAVE_GEM_NOC_CNOC, SM8750_SLAVE_LLCC }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; =20 static struct qcom_icc_node qnm_snoc_sf =3D { .name =3D "qnm_snoc_sf", - .id =3D SM8750_MASTER_SNOC_SF_MEM_NOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 3, - .links =3D { SM8750_SLAVE_GEM_NOC_CNOC, SM8750_SLAVE_LLCC, - SM8750_SLAVE_MEM_NOC_PCIE_SNOC }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, }; =20 static struct qcom_icc_node qnm_ubwc_p =3D { .name =3D "qnm_ubwc_p", - .id =3D SM8750_MASTER_UBWC_P, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8750_SLAVE_LLCC }, + .link_nodes =3D { &qns_llcc }, }; =20 static struct qcom_icc_node xm_gic =3D { .name =3D "xm_gic", - .id =3D SM8750_MASTER_GIC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8750_SLAVE_LLCC }, + .link_nodes =3D { &qns_llcc }, }; =20 static struct qcom_icc_node qnm_lpiaon_noc =3D { .name =3D "qnm_lpiaon_noc", - .id =3D SM8750_MASTER_LPIAON_NOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM8750_SLAVE_LPASS_GEM_NOC }, + .link_nodes =3D { &qns_lpass_ag_noc_gemnoc }, }; =20 static struct qcom_icc_node qnm_lpass_lpinoc =3D { .name =3D "qnm_lpass_lpinoc", - .id =3D SM8750_MASTER_LPASS_LPINOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM8750_SLAVE_LPIAON_NOC_LPASS_AG_NOC }, + .link_nodes =3D { &qns_lpass_aggnoc }, }; =20 static struct qcom_icc_node qnm_lpinoc_dsp_qns4m =3D { .name =3D "qnm_lpinoc_dsp_qns4m", - .id =3D SM8750_MASTER_LPASS_PROC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM8750_SLAVE_LPICX_NOC_LPIAON_NOC }, + .link_nodes =3D { &qns_lpi_aon_noc }, }; =20 static struct qcom_icc_node llcc_mc =3D { .name =3D "llcc_mc", - .id =3D SM8750_MASTER_LLCC, .channels =3D 4, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8750_SLAVE_EBI1 }, + .link_nodes =3D { &ebi }, }; =20 static struct qcom_icc_node qnm_camnoc_hf =3D { .name =3D "qnm_camnoc_hf", - .id =3D SM8750_MASTER_CAMNOC_HF, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8750_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_hf }, }; =20 static struct qcom_icc_node qnm_camnoc_nrt_icp_sf =3D { .name =3D "qnm_camnoc_nrt_icp_sf", - .id =3D SM8750_MASTER_CAMNOC_NRT_ICP_SF, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8750_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static struct qcom_icc_node qnm_camnoc_rt_cdm_sf =3D { .name =3D "qnm_camnoc_rt_cdm_sf", - .id =3D SM8750_MASTER_CAMNOC_RT_CDM_SF, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8750_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static struct qcom_icc_node qnm_camnoc_sf =3D { .name =3D "qnm_camnoc_sf", - .id =3D SM8750_MASTER_CAMNOC_SF, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8750_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static struct qcom_icc_node qnm_mdp =3D { .name =3D "qnm_mdp", - .id =3D SM8750_MASTER_MDP, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8750_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_hf }, }; =20 static struct qcom_icc_node qnm_vapss_hcp =3D { .name =3D "qnm_vapss_hcp", - .id =3D SM8750_MASTER_CDSP_HCP, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8750_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static struct qcom_icc_node qnm_video_cv_cpu =3D { .name =3D "qnm_video_cv_cpu", - .id =3D SM8750_MASTER_VIDEO_CV_PROC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8750_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static struct qcom_icc_node qnm_video_eva =3D { .name =3D "qnm_video_eva", - .id =3D SM8750_MASTER_VIDEO_EVA, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8750_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static struct qcom_icc_node qnm_video_mvp =3D { .name =3D "qnm_video_mvp", - .id =3D SM8750_MASTER_VIDEO_MVP, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8750_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static struct qcom_icc_node qnm_video_v_cpu =3D { .name =3D "qnm_video_v_cpu", - .id =3D SM8750_MASTER_VIDEO_V_PROC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8750_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static struct qcom_icc_node qsm_mnoc_cfg =3D { .name =3D "qsm_mnoc_cfg", - .id =3D SM8750_MASTER_CNOC_MNOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8750_SLAVE_SERVICE_MNOC }, + .link_nodes =3D { &srvc_mnoc }, }; =20 static struct qcom_icc_node qnm_nsp =3D { .name =3D "qnm_nsp", - .id =3D SM8750_MASTER_CDSP_PROC, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8750_SLAVE_CDSP_MEM_NOC }, + .link_nodes =3D { &qns_nsp_gemnoc }, }; =20 static struct qcom_icc_node qsm_pcie_anoc_cfg =3D { .name =3D "qsm_pcie_anoc_cfg", - .id =3D SM8750_MASTER_PCIE_ANOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8750_SLAVE_SERVICE_PCIE_ANOC }, + .link_nodes =3D { &srvc_pcie_aggre_noc }, }; =20 static struct qcom_icc_node xm_pcie3 =3D { .name =3D "xm_pcie3", - .id =3D SM8750_MASTER_PCIE_0, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8750_SLAVE_ANOC_PCIE_GEM_NOC }, + .link_nodes =3D { &qns_pcie_mem_noc }, }; =20 static struct qcom_icc_node qnm_aggre1_noc =3D { .name =3D "qnm_aggre1_noc", - .id =3D SM8750_MASTER_A1NOC_SNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM8750_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes =3D { &qns_gemnoc_sf }, }; =20 static struct qcom_icc_node qnm_aggre2_noc =3D { .name =3D "qnm_aggre2_noc", - .id =3D SM8750_MASTER_A2NOC_SNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM8750_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes =3D { &qns_gemnoc_sf }, }; =20 static struct qcom_icc_node qns_a1noc_snoc =3D { .name =3D "qns_a1noc_snoc", - .id =3D SM8750_SLAVE_A1NOC_SNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM8750_MASTER_A1NOC_SNOC }, + .link_nodes =3D { &qnm_aggre1_noc }, }; =20 static struct qcom_icc_node qns_a2noc_snoc =3D { .name =3D "qns_a2noc_snoc", - .id =3D SM8750_SLAVE_A2NOC_SNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM8750_MASTER_A2NOC_SNOC }, + .link_nodes =3D { &qnm_aggre2_noc }, }; =20 static struct qcom_icc_node qup0_core_slave =3D { .name =3D "qup0_core_slave", - .id =3D SM8750_SLAVE_QUP_CORE_0, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qup1_core_slave =3D { .name =3D "qup1_core_slave", - .id =3D SM8750_SLAVE_QUP_CORE_1, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qup2_core_slave =3D { .name =3D "qup2_core_slave", - .id =3D SM8750_SLAVE_QUP_CORE_2, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_ahb2phy0 =3D { .name =3D "qhs_ahb2phy0", - .id =3D SM8750_SLAVE_AHB2PHY_SOUTH, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_ahb2phy1 =3D { .name =3D "qhs_ahb2phy1", - .id =3D SM8750_SLAVE_AHB2PHY_NORTH, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_camera_cfg =3D { .name =3D "qhs_camera_cfg", - .id =3D SM8750_SLAVE_CAMERA_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_clk_ctl =3D { .name =3D "qhs_clk_ctl", - .id =3D SM8750_SLAVE_CLK_CTL, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_crypto0_cfg =3D { .name =3D "qhs_crypto0_cfg", - .id =3D SM8750_SLAVE_CRYPTO_0_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_display_cfg =3D { .name =3D "qhs_display_cfg", - .id =3D SM8750_SLAVE_DISPLAY_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_eva_cfg =3D { .name =3D "qhs_eva_cfg", - .id =3D SM8750_SLAVE_EVA_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_gpuss_cfg =3D { .name =3D "qhs_gpuss_cfg", - .id =3D SM8750_SLAVE_GFX3D_CFG, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_i2c =3D { .name =3D "qhs_i2c", - .id =3D SM8750_SLAVE_I2C, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_i3c_ibi0_cfg =3D { .name =3D "qhs_i3c_ibi0_cfg", - .id =3D SM8750_SLAVE_I3C_IBI0_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_i3c_ibi1_cfg =3D { .name =3D "qhs_i3c_ibi1_cfg", - .id =3D SM8750_SLAVE_I3C_IBI1_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_imem_cfg =3D { .name =3D "qhs_imem_cfg", - .id =3D SM8750_SLAVE_IMEM_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_mss_cfg =3D { .name =3D "qhs_mss_cfg", - .id =3D SM8750_SLAVE_CNOC_MSS, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_pcie_cfg =3D { .name =3D "qhs_pcie_cfg", - .id =3D SM8750_SLAVE_PCIE_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_prng =3D { .name =3D "qhs_prng", - .id =3D SM8750_SLAVE_PRNG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_qdss_cfg =3D { .name =3D "qhs_qdss_cfg", - .id =3D SM8750_SLAVE_QDSS_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_qspi =3D { .name =3D "qhs_qspi", - .id =3D SM8750_SLAVE_QSPI_0, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_qup02 =3D { .name =3D "qhs_qup02", - .id =3D SM8750_SLAVE_QUP_3, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_qup1 =3D { .name =3D "qhs_qup1", - .id =3D SM8750_SLAVE_QUP_1, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_qup2 =3D { .name =3D "qhs_qup2", - .id =3D SM8750_SLAVE_QUP_2, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_sdc2 =3D { .name =3D "qhs_sdc2", - .id =3D SM8750_SLAVE_SDCC_2, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_sdc4 =3D { .name =3D "qhs_sdc4", - .id =3D SM8750_SLAVE_SDCC_4, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_spss_cfg =3D { .name =3D "qhs_spss_cfg", - .id =3D SM8750_SLAVE_SPSS_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_tcsr =3D { .name =3D "qhs_tcsr", - .id =3D SM8750_SLAVE_TCSR, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_tlmm =3D { .name =3D "qhs_tlmm", - .id =3D SM8750_SLAVE_TLMM, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_ufs_mem_cfg =3D { .name =3D "qhs_ufs_mem_cfg", - .id =3D SM8750_SLAVE_UFS_MEM_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_usb3_0 =3D { .name =3D "qhs_usb3_0", - .id =3D SM8750_SLAVE_USB3_0, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_venus_cfg =3D { .name =3D "qhs_venus_cfg", - .id =3D SM8750_SLAVE_VENUS_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_vsense_ctrl_cfg =3D { .name =3D "qhs_vsense_ctrl_cfg", - .id =3D SM8750_SLAVE_VSENSE_CTRL_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qss_mnoc_cfg =3D { .name =3D "qss_mnoc_cfg", - .id =3D SM8750_SLAVE_CNOC_MNOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8750_MASTER_CNOC_MNOC_CFG }, + .link_nodes =3D { &qsm_mnoc_cfg }, }; =20 static struct qcom_icc_node qss_pcie_anoc_cfg =3D { .name =3D "qss_pcie_anoc_cfg", - .id =3D SM8750_SLAVE_PCIE_ANOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8750_MASTER_PCIE_ANOC_CFG }, + .link_nodes =3D { &qsm_pcie_anoc_cfg }, }; =20 static struct qcom_icc_node xs_qdss_stm =3D { .name =3D "xs_qdss_stm", - .id =3D SM8750_SLAVE_QDSS_STM, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node xs_sys_tcu_cfg =3D { .name =3D "xs_sys_tcu_cfg", - .id =3D SM8750_SLAVE_TCU, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_aoss =3D { .name =3D "qhs_aoss", - .id =3D SM8750_SLAVE_AOSS, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_ipa =3D { .name =3D "qhs_ipa", - .id =3D SM8750_SLAVE_IPA_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_ipc_router =3D { .name =3D "qhs_ipc_router", - .id =3D SM8750_SLAVE_IPC_ROUTER_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_soccp =3D { .name =3D "qhs_soccp", - .id =3D SM8750_SLAVE_SOCCP, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_tme_cfg =3D { .name =3D "qhs_tme_cfg", - .id =3D SM8750_SLAVE_TME_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qns_apss =3D { .name =3D "qns_apss", - .id =3D SM8750_SLAVE_APPSS, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 0, }; =20 static struct qcom_icc_node qss_cfg =3D { .name =3D "qss_cfg", - .id =3D SM8750_SLAVE_CNOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8750_MASTER_CNOC_CFG }, + .link_nodes =3D { &qsm_cfg }, }; =20 static struct qcom_icc_node qss_ddrss_cfg =3D { .name =3D "qss_ddrss_cfg", - .id =3D SM8750_SLAVE_DDRSS_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qxs_boot_imem =3D { .name =3D "qxs_boot_imem", - .id =3D SM8750_SLAVE_BOOT_IMEM, .channels =3D 1, .buswidth =3D 16, - .num_links =3D 0, }; =20 static struct qcom_icc_node qxs_imem =3D { .name =3D "qxs_imem", - .id =3D SM8750_SLAVE_IMEM, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 0, }; =20 static struct qcom_icc_node qxs_modem_boot_imem =3D { .name =3D "qxs_modem_boot_imem", - .id =3D SM8750_SLAVE_BOOT_IMEM_2, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 0, }; =20 static struct qcom_icc_node srvc_cnoc_main =3D { .name =3D "srvc_cnoc_main", - .id =3D SM8750_SLAVE_SERVICE_CNOC, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node xs_pcie =3D { .name =3D "xs_pcie", - .id =3D SM8750_SLAVE_PCIE_0, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 0, }; =20 static struct qcom_icc_node chs_ubwc_p =3D { .name =3D "chs_ubwc_p", - .id =3D SM8750_SLAVE_UBWC_P, .channels =3D 1, .buswidth =3D 32, - .num_links =3D 0, }; =20 static struct qcom_icc_node qns_gem_noc_cnoc =3D { .name =3D "qns_gem_noc_cnoc", - .id =3D SM8750_SLAVE_GEM_NOC_CNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM8750_MASTER_GEM_NOC_CNOC }, + .link_nodes =3D { &qnm_gemnoc_cnoc }, }; =20 static struct qcom_icc_node qns_llcc =3D { .name =3D "qns_llcc", - .id =3D SM8750_SLAVE_LLCC, .channels =3D 4, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM8750_MASTER_LLCC }, + .link_nodes =3D { &llcc_mc }, }; =20 static struct qcom_icc_node qns_pcie =3D { .name =3D "qns_pcie", - .id =3D SM8750_SLAVE_MEM_NOC_PCIE_SNOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8750_MASTER_GEM_NOC_PCIE_SNOC }, + .link_nodes =3D { &qnm_gemnoc_pcie }, }; =20 static struct qcom_icc_node qns_lpass_ag_noc_gemnoc =3D { .name =3D "qns_lpass_ag_noc_gemnoc", - .id =3D SM8750_SLAVE_LPASS_GEM_NOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM8750_MASTER_LPASS_GEM_NOC }, + .link_nodes =3D { &qnm_lpass_gemnoc }, }; =20 static struct qcom_icc_node qns_lpass_aggnoc =3D { .name =3D "qns_lpass_aggnoc", - .id =3D SM8750_SLAVE_LPIAON_NOC_LPASS_AG_NOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM8750_MASTER_LPIAON_NOC }, + .link_nodes =3D { &qnm_lpiaon_noc }, }; =20 static struct qcom_icc_node qns_lpi_aon_noc =3D { .name =3D "qns_lpi_aon_noc", - .id =3D SM8750_SLAVE_LPICX_NOC_LPIAON_NOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM8750_MASTER_LPASS_LPINOC }, + .link_nodes =3D { &qnm_lpass_lpinoc }, }; =20 static struct qcom_icc_node ebi =3D { .name =3D "ebi", - .id =3D SM8750_SLAVE_EBI1, .channels =3D 4, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qns_mem_noc_hf =3D { .name =3D "qns_mem_noc_hf", - .id =3D SM8750_SLAVE_MNOC_HF_MEM_NOC, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8750_MASTER_MNOC_HF_MEM_NOC }, + .link_nodes =3D { &qnm_mnoc_hf }, }; =20 static struct qcom_icc_node qns_mem_noc_sf =3D { .name =3D "qns_mem_noc_sf", - .id =3D SM8750_SLAVE_MNOC_SF_MEM_NOC, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8750_MASTER_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qnm_mnoc_sf }, }; =20 static struct qcom_icc_node srvc_mnoc =3D { .name =3D "srvc_mnoc", - .id =3D SM8750_SLAVE_SERVICE_MNOC, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qns_nsp_gemnoc =3D { .name =3D "qns_nsp_gemnoc", - .id =3D SM8750_SLAVE_CDSP_MEM_NOC, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8750_MASTER_COMPUTE_NOC }, + .link_nodes =3D { &qnm_nsp_gemnoc }, }; =20 static struct qcom_icc_node qns_pcie_mem_noc =3D { .name =3D "qns_pcie_mem_noc", - .id =3D SM8750_SLAVE_ANOC_PCIE_GEM_NOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8750_MASTER_ANOC_PCIE_GEM_NOC }, + .link_nodes =3D { &qnm_pcie }, }; =20 static struct qcom_icc_node srvc_pcie_aggre_noc =3D { .name =3D "srvc_pcie_aggre_noc", - .id =3D SM8750_SLAVE_SERVICE_PCIE_ANOC, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qns_gemnoc_sf =3D { .name =3D "qns_gemnoc_sf", - .id =3D SM8750_SLAVE_SNOC_GEM_NOC_SF, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM8750_MASTER_SNOC_SF_MEM_NOC }, + .link_nodes =3D { &qnm_snoc_sf }, }; =20 static struct qcom_icc_bcm bcm_acv =3D { @@ -1364,6 +1194,7 @@ static struct qcom_icc_node * const aggre1_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sm8750_aggre1_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D aggre1_noc_nodes, .num_nodes =3D ARRAY_SIZE(aggre1_noc_nodes), }; @@ -1386,6 +1217,7 @@ static struct qcom_icc_node * const aggre2_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sm8750_aggre2_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D aggre2_noc_nodes, .num_nodes =3D ARRAY_SIZE(aggre2_noc_nodes), .bcms =3D aggre2_noc_bcms, @@ -1408,6 +1240,7 @@ static struct qcom_icc_node * const clk_virt_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sm8750_clk_virt =3D { + .alloc_dyn_id =3D true, .nodes =3D clk_virt_nodes, .num_nodes =3D ARRAY_SIZE(clk_virt_nodes), .bcms =3D clk_virt_bcms, @@ -1457,6 +1290,7 @@ static struct qcom_icc_node * const config_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sm8750_config_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D config_noc_nodes, .num_nodes =3D ARRAY_SIZE(config_noc_nodes), .bcms =3D config_noc_bcms, @@ -1486,6 +1320,7 @@ static struct qcom_icc_node * const cnoc_main_nodes[]= =3D { }; =20 static const struct qcom_icc_desc sm8750_cnoc_main =3D { + .alloc_dyn_id =3D true, .nodes =3D cnoc_main_nodes, .num_nodes =3D ARRAY_SIZE(cnoc_main_nodes), .bcms =3D cnoc_main_bcms, @@ -1519,6 +1354,7 @@ static struct qcom_icc_node * const gem_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sm8750_gem_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D gem_noc_nodes, .num_nodes =3D ARRAY_SIZE(gem_noc_nodes), .bcms =3D gem_noc_bcms, @@ -1531,6 +1367,7 @@ static struct qcom_icc_node * const lpass_ag_noc_node= s[] =3D { }; =20 static const struct qcom_icc_desc sm8750_lpass_ag_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D lpass_ag_noc_nodes, .num_nodes =3D ARRAY_SIZE(lpass_ag_noc_nodes), }; @@ -1545,6 +1382,7 @@ static struct qcom_icc_node * const lpass_lpiaon_noc_= nodes[] =3D { }; =20 static const struct qcom_icc_desc sm8750_lpass_lpiaon_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D lpass_lpiaon_noc_nodes, .num_nodes =3D ARRAY_SIZE(lpass_lpiaon_noc_nodes), .bcms =3D lpass_lpiaon_noc_bcms, @@ -1557,6 +1395,7 @@ static struct qcom_icc_node * const lpass_lpicx_noc_n= odes[] =3D { }; =20 static const struct qcom_icc_desc sm8750_lpass_lpicx_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D lpass_lpicx_noc_nodes, .num_nodes =3D ARRAY_SIZE(lpass_lpicx_noc_nodes), }; @@ -1572,6 +1411,7 @@ static struct qcom_icc_node * const mc_virt_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sm8750_mc_virt =3D { + .alloc_dyn_id =3D true, .nodes =3D mc_virt_nodes, .num_nodes =3D ARRAY_SIZE(mc_virt_nodes), .bcms =3D mc_virt_bcms, @@ -1601,6 +1441,7 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sm8750_mmss_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D mmss_noc_nodes, .num_nodes =3D ARRAY_SIZE(mmss_noc_nodes), .bcms =3D mmss_noc_bcms, @@ -1617,6 +1458,7 @@ static struct qcom_icc_node * const nsp_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sm8750_nsp_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D nsp_noc_nodes, .num_nodes =3D ARRAY_SIZE(nsp_noc_nodes), .bcms =3D nsp_noc_bcms, @@ -1635,6 +1477,7 @@ static struct qcom_icc_node * const pcie_anoc_nodes[]= =3D { }; =20 static const struct qcom_icc_desc sm8750_pcie_anoc =3D { + .alloc_dyn_id =3D true, .nodes =3D pcie_anoc_nodes, .num_nodes =3D ARRAY_SIZE(pcie_anoc_nodes), .bcms =3D pcie_anoc_bcms, @@ -1654,6 +1497,7 @@ static struct qcom_icc_node * const system_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sm8750_system_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D system_noc_nodes, .num_nodes =3D ARRAY_SIZE(system_noc_nodes), .bcms =3D system_noc_bcms, --=20 2.47.3