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This gives more flexibility and also allows us to drop the .num_links member, saving from possible errors related to it being not set or set incorrectly. Signed-off-by: Dmitry Baryshkov --- drivers/interconnect/qcom/sm8150.c | 716 ++++++++++++++++++---------------= ---- drivers/interconnect/qcom/sm8150.h | 152 -------- 2 files changed, 355 insertions(+), 513 deletions(-) diff --git a/drivers/interconnect/qcom/sm8150.c b/drivers/interconnect/qcom= /sm8150.c index edfe824cad3533cfc6263c2031838f96e1986fa5..58a6643921bb4e9c3298352e3fb= 5755b92162a6d 100644 --- a/drivers/interconnect/qcom/sm8150.c +++ b/drivers/interconnect/qcom/sm8150.c @@ -14,1268 +14,1252 @@ =20 #include "bcm-voter.h" #include "icc-rpmh.h" -#include "sm8150.h" + +static struct qcom_icc_node qhm_a1noc_cfg; +static struct qcom_icc_node qhm_qup0; +static struct qcom_icc_node xm_emac; +static struct qcom_icc_node xm_ufs_mem; +static struct qcom_icc_node xm_usb3_0; +static struct qcom_icc_node xm_usb3_1; +static struct qcom_icc_node qhm_a2noc_cfg; +static struct qcom_icc_node qhm_qdss_bam; +static struct qcom_icc_node qhm_qspi; +static struct qcom_icc_node qhm_qup1; +static struct qcom_icc_node qhm_qup2; +static struct qcom_icc_node qhm_sensorss_ahb; +static struct qcom_icc_node qhm_tsif; +static struct qcom_icc_node qnm_cnoc; +static struct qcom_icc_node qxm_crypto; +static struct qcom_icc_node qxm_ipa; +static struct qcom_icc_node xm_pcie3_0; +static struct qcom_icc_node xm_pcie3_1; +static struct qcom_icc_node xm_qdss_etr; +static struct qcom_icc_node xm_sdc2; +static struct qcom_icc_node xm_sdc4; +static struct qcom_icc_node qxm_camnoc_hf0_uncomp; +static struct qcom_icc_node qxm_camnoc_hf1_uncomp; +static struct qcom_icc_node qxm_camnoc_sf_uncomp; +static struct qcom_icc_node qnm_npu; +static struct qcom_icc_node qhm_spdm; +static struct qcom_icc_node qnm_snoc; +static struct qcom_icc_node xm_qdss_dap; +static struct qcom_icc_node qhm_cnoc_dc_noc; +static struct qcom_icc_node acm_apps; +static struct qcom_icc_node acm_gpu_tcu; +static struct qcom_icc_node acm_sys_tcu; +static struct qcom_icc_node qhm_gemnoc_cfg; +static struct qcom_icc_node qnm_cmpnoc; +static struct qcom_icc_node qnm_gpu; +static struct qcom_icc_node qnm_mnoc_hf; +static struct qcom_icc_node qnm_mnoc_sf; +static struct qcom_icc_node qnm_pcie; +static struct qcom_icc_node qnm_snoc_gc; +static struct qcom_icc_node qnm_snoc_sf; +static struct qcom_icc_node qxm_ecc; +static struct qcom_icc_node llcc_mc; +static struct qcom_icc_node qhm_mnoc_cfg; +static struct qcom_icc_node qxm_camnoc_hf0; +static struct qcom_icc_node qxm_camnoc_hf1; +static struct qcom_icc_node qxm_camnoc_sf; +static struct qcom_icc_node qxm_mdp0; +static struct qcom_icc_node qxm_mdp1; +static struct qcom_icc_node qxm_rot; +static struct qcom_icc_node qxm_venus0; +static struct qcom_icc_node qxm_venus1; +static struct qcom_icc_node qxm_venus_arm9; +static struct qcom_icc_node qhm_snoc_cfg; +static struct qcom_icc_node qnm_aggre1_noc; +static struct qcom_icc_node qnm_aggre2_noc; +static struct qcom_icc_node qnm_gemnoc; +static struct qcom_icc_node qxm_pimem; +static struct qcom_icc_node xm_gic; +static struct qcom_icc_node qns_a1noc_snoc; +static struct qcom_icc_node srvc_aggre1_noc; +static struct qcom_icc_node qns_a2noc_snoc; +static struct qcom_icc_node qns_pcie_mem_noc; +static struct qcom_icc_node srvc_aggre2_noc; +static struct qcom_icc_node qns_camnoc_uncomp; +static struct qcom_icc_node qns_cdsp_mem_noc; +static struct qcom_icc_node qhs_a1_noc_cfg; +static struct qcom_icc_node qhs_a2_noc_cfg; +static struct qcom_icc_node qhs_ahb2phy_south; +static struct qcom_icc_node qhs_aop; +static struct qcom_icc_node qhs_aoss; +static struct qcom_icc_node qhs_camera_cfg; +static struct qcom_icc_node qhs_clk_ctl; +static struct qcom_icc_node qhs_compute_dsp; +static struct qcom_icc_node qhs_cpr_cx; +static struct qcom_icc_node qhs_cpr_mmcx; +static struct qcom_icc_node qhs_cpr_mx; +static struct qcom_icc_node qhs_crypto0_cfg; +static struct qcom_icc_node qhs_ddrss_cfg; +static struct qcom_icc_node qhs_display_cfg; +static struct qcom_icc_node qhs_emac_cfg; +static struct qcom_icc_node qhs_glm; +static struct qcom_icc_node qhs_gpuss_cfg; +static struct qcom_icc_node qhs_imem_cfg; +static struct qcom_icc_node qhs_ipa; +static struct qcom_icc_node qhs_mnoc_cfg; +static struct qcom_icc_node qhs_npu_cfg; +static struct qcom_icc_node qhs_pcie0_cfg; +static struct qcom_icc_node qhs_pcie1_cfg; +static struct qcom_icc_node qhs_phy_refgen_north; +static struct qcom_icc_node qhs_pimem_cfg; +static struct qcom_icc_node qhs_prng; +static struct qcom_icc_node qhs_qdss_cfg; +static struct qcom_icc_node qhs_qspi; +static struct qcom_icc_node qhs_qupv3_east; +static struct qcom_icc_node qhs_qupv3_north; +static struct qcom_icc_node qhs_qupv3_south; +static struct qcom_icc_node qhs_sdc2; +static struct qcom_icc_node qhs_sdc4; +static struct qcom_icc_node qhs_snoc_cfg; +static struct qcom_icc_node qhs_spdm; +static struct qcom_icc_node qhs_spss_cfg; +static struct qcom_icc_node qhs_ssc_cfg; +static struct qcom_icc_node qhs_tcsr; +static struct qcom_icc_node qhs_tlmm_east; +static struct qcom_icc_node qhs_tlmm_north; +static struct qcom_icc_node qhs_tlmm_south; +static struct qcom_icc_node qhs_tlmm_west; +static struct qcom_icc_node qhs_tsif; +static struct qcom_icc_node qhs_ufs_card_cfg; +static struct qcom_icc_node qhs_ufs_mem_cfg; +static struct qcom_icc_node qhs_usb3_0; +static struct qcom_icc_node qhs_usb3_1; +static struct qcom_icc_node qhs_venus_cfg; +static struct qcom_icc_node qhs_vsense_ctrl_cfg; +static struct qcom_icc_node qns_cnoc_a2noc; +static struct qcom_icc_node srvc_cnoc; +static struct qcom_icc_node qhs_llcc; +static struct qcom_icc_node qhs_memnoc; +static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg; +static struct qcom_icc_node qns_ecc; +static struct qcom_icc_node qns_gem_noc_snoc; +static struct qcom_icc_node qns_llcc; +static struct qcom_icc_node srvc_gemnoc; +static struct qcom_icc_node ebi; +static struct qcom_icc_node qns2_mem_noc; +static struct qcom_icc_node qns_mem_noc_hf; +static struct qcom_icc_node srvc_mnoc; +static struct qcom_icc_node qhs_apss; +static struct qcom_icc_node qns_cnoc; +static struct qcom_icc_node qns_gemnoc_gc; +static struct qcom_icc_node qns_gemnoc_sf; +static struct qcom_icc_node qxs_imem; +static struct qcom_icc_node qxs_pimem; +static struct qcom_icc_node srvc_snoc; +static struct qcom_icc_node xs_pcie_0; +static struct qcom_icc_node xs_pcie_1; +static struct qcom_icc_node xs_qdss_stm; +static struct qcom_icc_node xs_sys_tcu_cfg; =20 static struct qcom_icc_node qhm_a1noc_cfg =3D { .name =3D "qhm_a1noc_cfg", - .id =3D SM8150_MASTER_A1NOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8150_SLAVE_SERVICE_A1NOC }, + .link_nodes =3D { &srvc_aggre1_noc }, }; =20 static struct qcom_icc_node qhm_qup0 =3D { .name =3D "qhm_qup0", - .id =3D SM8150_MASTER_QUP_0, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8150_A1NOC_SNOC_SLV }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node xm_emac =3D { .name =3D "xm_emac", - .id =3D SM8150_MASTER_EMAC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8150_A1NOC_SNOC_SLV }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node xm_ufs_mem =3D { .name =3D "xm_ufs_mem", - .id =3D SM8150_MASTER_UFS_MEM, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8150_A1NOC_SNOC_SLV }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node xm_usb3_0 =3D { .name =3D "xm_usb3_0", - .id =3D SM8150_MASTER_USB3, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8150_A1NOC_SNOC_SLV }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node xm_usb3_1 =3D { .name =3D "xm_usb3_1", - .id =3D SM8150_MASTER_USB3_1, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8150_A1NOC_SNOC_SLV }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node qhm_a2noc_cfg =3D { .name =3D "qhm_a2noc_cfg", - .id =3D SM8150_MASTER_A2NOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8150_SLAVE_SERVICE_A2NOC }, + .link_nodes =3D { &srvc_aggre2_noc }, }; =20 static struct qcom_icc_node qhm_qdss_bam =3D { .name =3D "qhm_qdss_bam", - .id =3D SM8150_MASTER_QDSS_BAM, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8150_A2NOC_SNOC_SLV }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qhm_qspi =3D { .name =3D "qhm_qspi", - .id =3D SM8150_MASTER_QSPI, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8150_A2NOC_SNOC_SLV }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qhm_qup1 =3D { .name =3D "qhm_qup1", - .id =3D SM8150_MASTER_QUP_1, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8150_A2NOC_SNOC_SLV }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qhm_qup2 =3D { .name =3D "qhm_qup2", - .id =3D SM8150_MASTER_QUP_2, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8150_A2NOC_SNOC_SLV }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qhm_sensorss_ahb =3D { .name =3D "qhm_sensorss_ahb", - .id =3D SM8150_MASTER_SENSORS_AHB, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8150_A2NOC_SNOC_SLV }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qhm_tsif =3D { .name =3D "qhm_tsif", - .id =3D SM8150_MASTER_TSIF, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8150_A2NOC_SNOC_SLV }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qnm_cnoc =3D { .name =3D "qnm_cnoc", - .id =3D SM8150_MASTER_CNOC_A2NOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8150_A2NOC_SNOC_SLV }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qxm_crypto =3D { .name =3D "qxm_crypto", - .id =3D SM8150_MASTER_CRYPTO_CORE_0, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8150_A2NOC_SNOC_SLV }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qxm_ipa =3D { .name =3D "qxm_ipa", - .id =3D SM8150_MASTER_IPA, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8150_A2NOC_SNOC_SLV }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node xm_pcie3_0 =3D { .name =3D "xm_pcie3_0", - .id =3D SM8150_MASTER_PCIE, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8150_SLAVE_ANOC_PCIE_GEM_NOC }, + .link_nodes =3D { &qns_pcie_mem_noc }, }; =20 static struct qcom_icc_node xm_pcie3_1 =3D { .name =3D "xm_pcie3_1", - .id =3D SM8150_MASTER_PCIE_1, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8150_SLAVE_ANOC_PCIE_GEM_NOC }, + .link_nodes =3D { &qns_pcie_mem_noc }, }; =20 static struct qcom_icc_node xm_qdss_etr =3D { .name =3D "xm_qdss_etr", - .id =3D SM8150_MASTER_QDSS_ETR, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8150_A2NOC_SNOC_SLV }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node xm_sdc2 =3D { .name =3D "xm_sdc2", - .id =3D SM8150_MASTER_SDCC_2, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8150_A2NOC_SNOC_SLV }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node xm_sdc4 =3D { .name =3D "xm_sdc4", - .id =3D SM8150_MASTER_SDCC_4, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8150_A2NOC_SNOC_SLV }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qxm_camnoc_hf0_uncomp =3D { .name =3D "qxm_camnoc_hf0_uncomp", - .id =3D SM8150_MASTER_CAMNOC_HF0_UNCOMP, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8150_SLAVE_CAMNOC_UNCOMP }, + .link_nodes =3D { &qns_camnoc_uncomp }, }; =20 static struct qcom_icc_node qxm_camnoc_hf1_uncomp =3D { .name =3D "qxm_camnoc_hf1_uncomp", - .id =3D SM8150_MASTER_CAMNOC_HF1_UNCOMP, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8150_SLAVE_CAMNOC_UNCOMP }, + .link_nodes =3D { &qns_camnoc_uncomp }, }; =20 static struct qcom_icc_node qxm_camnoc_sf_uncomp =3D { .name =3D "qxm_camnoc_sf_uncomp", - .id =3D SM8150_MASTER_CAMNOC_SF_UNCOMP, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8150_SLAVE_CAMNOC_UNCOMP }, + .link_nodes =3D { &qns_camnoc_uncomp }, }; =20 static struct qcom_icc_node qnm_npu =3D { .name =3D "qnm_npu", - .id =3D SM8150_MASTER_NPU, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8150_SLAVE_CDSP_MEM_NOC }, + .link_nodes =3D { &qns_cdsp_mem_noc }, }; =20 static struct qcom_icc_node qhm_spdm =3D { .name =3D "qhm_spdm", - .id =3D SM8150_MASTER_SPDM, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8150_SLAVE_CNOC_A2NOC }, + .link_nodes =3D { &qns_cnoc_a2noc }, }; =20 static struct qcom_icc_node qnm_snoc =3D { .name =3D "qnm_snoc", - .id =3D SM8150_SNOC_CNOC_MAS, .channels =3D 1, .buswidth =3D 8, .num_links =3D 50, - .links =3D { SM8150_SLAVE_TLMM_SOUTH, - SM8150_SLAVE_CDSP_CFG, - SM8150_SLAVE_SPSS_CFG, - SM8150_SLAVE_CAMERA_CFG, - SM8150_SLAVE_SDCC_4, - SM8150_SLAVE_SDCC_2, - SM8150_SLAVE_CNOC_MNOC_CFG, - SM8150_SLAVE_EMAC_CFG, - SM8150_SLAVE_UFS_MEM_CFG, - SM8150_SLAVE_TLMM_EAST, - SM8150_SLAVE_SSC_CFG, - SM8150_SLAVE_SNOC_CFG, - SM8150_SLAVE_NORTH_PHY_CFG, - SM8150_SLAVE_QUP_0, - SM8150_SLAVE_GLM, - SM8150_SLAVE_PCIE_1_CFG, - SM8150_SLAVE_A2NOC_CFG, - SM8150_SLAVE_QDSS_CFG, - SM8150_SLAVE_DISPLAY_CFG, - SM8150_SLAVE_TCSR, - SM8150_SLAVE_CNOC_DDRSS, - SM8150_SLAVE_RBCPR_MMCX_CFG, - SM8150_SLAVE_NPU_CFG, - SM8150_SLAVE_PCIE_0_CFG, - SM8150_SLAVE_GRAPHICS_3D_CFG, - SM8150_SLAVE_VENUS_CFG, - SM8150_SLAVE_TSIF, - SM8150_SLAVE_IPA_CFG, - SM8150_SLAVE_CLK_CTL, - SM8150_SLAVE_AOP, - SM8150_SLAVE_QUP_1, - SM8150_SLAVE_AHB2PHY_SOUTH, - SM8150_SLAVE_USB3_1, - SM8150_SLAVE_SERVICE_CNOC, - SM8150_SLAVE_UFS_CARD_CFG, - SM8150_SLAVE_QUP_2, - SM8150_SLAVE_RBCPR_CX_CFG, - SM8150_SLAVE_TLMM_WEST, - SM8150_SLAVE_A1NOC_CFG, - SM8150_SLAVE_AOSS, - SM8150_SLAVE_PRNG, - SM8150_SLAVE_VSENSE_CTRL_CFG, - SM8150_SLAVE_QSPI, - SM8150_SLAVE_USB3, - SM8150_SLAVE_SPDM_WRAPPER, - SM8150_SLAVE_CRYPTO_0_CFG, - SM8150_SLAVE_PIMEM_CFG, - SM8150_SLAVE_TLMM_NORTH, - SM8150_SLAVE_RBCPR_MX_CFG, - SM8150_SLAVE_IMEM_CFG - }, + .link_nodes =3D { &qhs_tlmm_south, + &qhs_compute_dsp, + &qhs_spss_cfg, + &qhs_camera_cfg, + &qhs_sdc4, + &qhs_sdc2, + &qhs_mnoc_cfg, + &qhs_emac_cfg, + &qhs_ufs_mem_cfg, + &qhs_tlmm_east, + &qhs_ssc_cfg, + &qhs_snoc_cfg, + &qhs_phy_refgen_north, + &qhs_qupv3_south, + &qhs_glm, + &qhs_pcie1_cfg, + &qhs_a2_noc_cfg, + &qhs_qdss_cfg, + &qhs_display_cfg, + &qhs_tcsr, + &qhs_ddrss_cfg, + &qhs_cpr_mmcx, + &qhs_npu_cfg, + &qhs_pcie0_cfg, + &qhs_gpuss_cfg, + &qhs_venus_cfg, + &qhs_tsif, + &qhs_ipa, + &qhs_clk_ctl, + &qhs_aop, + &qhs_qupv3_north, + &qhs_ahb2phy_south, + &qhs_usb3_1, + &srvc_cnoc, + &qhs_ufs_card_cfg, + &qhs_qupv3_east, + &qhs_cpr_cx, + &qhs_tlmm_west, + &qhs_a1_noc_cfg, + &qhs_aoss, + &qhs_prng, + &qhs_vsense_ctrl_cfg, + &qhs_qspi, + &qhs_usb3_0, + &qhs_spdm, + &qhs_crypto0_cfg, + &qhs_pimem_cfg, + &qhs_tlmm_north, + &qhs_cpr_mx, + &qhs_imem_cfg }, }; =20 static struct qcom_icc_node xm_qdss_dap =3D { .name =3D "xm_qdss_dap", - .id =3D SM8150_MASTER_QDSS_DAP, .channels =3D 1, .buswidth =3D 8, .num_links =3D 51, - .links =3D { SM8150_SLAVE_TLMM_SOUTH, - SM8150_SLAVE_CDSP_CFG, - SM8150_SLAVE_SPSS_CFG, - SM8150_SLAVE_CAMERA_CFG, - SM8150_SLAVE_SDCC_4, - SM8150_SLAVE_SDCC_2, - SM8150_SLAVE_CNOC_MNOC_CFG, - SM8150_SLAVE_EMAC_CFG, - SM8150_SLAVE_UFS_MEM_CFG, - SM8150_SLAVE_TLMM_EAST, - SM8150_SLAVE_SSC_CFG, - SM8150_SLAVE_SNOC_CFG, - SM8150_SLAVE_NORTH_PHY_CFG, - SM8150_SLAVE_QUP_0, - SM8150_SLAVE_GLM, - SM8150_SLAVE_PCIE_1_CFG, - SM8150_SLAVE_A2NOC_CFG, - SM8150_SLAVE_QDSS_CFG, - SM8150_SLAVE_DISPLAY_CFG, - SM8150_SLAVE_TCSR, - SM8150_SLAVE_CNOC_DDRSS, - SM8150_SLAVE_CNOC_A2NOC, - SM8150_SLAVE_RBCPR_MMCX_CFG, - SM8150_SLAVE_NPU_CFG, - SM8150_SLAVE_PCIE_0_CFG, - SM8150_SLAVE_GRAPHICS_3D_CFG, - SM8150_SLAVE_VENUS_CFG, - SM8150_SLAVE_TSIF, - SM8150_SLAVE_IPA_CFG, - SM8150_SLAVE_CLK_CTL, - SM8150_SLAVE_AOP, - SM8150_SLAVE_QUP_1, - SM8150_SLAVE_AHB2PHY_SOUTH, - SM8150_SLAVE_USB3_1, - SM8150_SLAVE_SERVICE_CNOC, - SM8150_SLAVE_UFS_CARD_CFG, - SM8150_SLAVE_QUP_2, - SM8150_SLAVE_RBCPR_CX_CFG, - SM8150_SLAVE_TLMM_WEST, - SM8150_SLAVE_A1NOC_CFG, - SM8150_SLAVE_AOSS, - SM8150_SLAVE_PRNG, - SM8150_SLAVE_VSENSE_CTRL_CFG, - SM8150_SLAVE_QSPI, - SM8150_SLAVE_USB3, - SM8150_SLAVE_SPDM_WRAPPER, - SM8150_SLAVE_CRYPTO_0_CFG, - SM8150_SLAVE_PIMEM_CFG, - SM8150_SLAVE_TLMM_NORTH, - SM8150_SLAVE_RBCPR_MX_CFG, - SM8150_SLAVE_IMEM_CFG - }, + .link_nodes =3D { &qhs_tlmm_south, + &qhs_compute_dsp, + &qhs_spss_cfg, + &qhs_camera_cfg, + &qhs_sdc4, + &qhs_sdc2, + &qhs_mnoc_cfg, + &qhs_emac_cfg, + &qhs_ufs_mem_cfg, + &qhs_tlmm_east, + &qhs_ssc_cfg, + &qhs_snoc_cfg, + &qhs_phy_refgen_north, + &qhs_qupv3_south, + &qhs_glm, + &qhs_pcie1_cfg, + &qhs_a2_noc_cfg, + &qhs_qdss_cfg, + &qhs_display_cfg, + &qhs_tcsr, + &qhs_ddrss_cfg, + &qns_cnoc_a2noc, + &qhs_cpr_mmcx, + &qhs_npu_cfg, + &qhs_pcie0_cfg, + &qhs_gpuss_cfg, + &qhs_venus_cfg, + &qhs_tsif, + &qhs_ipa, + &qhs_clk_ctl, + &qhs_aop, + &qhs_qupv3_north, + &qhs_ahb2phy_south, + &qhs_usb3_1, + &srvc_cnoc, + &qhs_ufs_card_cfg, + &qhs_qupv3_east, + &qhs_cpr_cx, + &qhs_tlmm_west, + &qhs_a1_noc_cfg, + &qhs_aoss, + &qhs_prng, + &qhs_vsense_ctrl_cfg, + &qhs_qspi, + &qhs_usb3_0, + &qhs_spdm, + &qhs_crypto0_cfg, + &qhs_pimem_cfg, + &qhs_tlmm_north, + &qhs_cpr_mx, + &qhs_imem_cfg }, }; =20 static struct qcom_icc_node qhm_cnoc_dc_noc =3D { .name =3D "qhm_cnoc_dc_noc", - .id =3D SM8150_MASTER_CNOC_DC_NOC, .channels =3D 1, .buswidth =3D 4, .num_links =3D 2, - .links =3D { SM8150_SLAVE_GEM_NOC_CFG, - SM8150_SLAVE_LLCC_CFG - }, + .link_nodes =3D { &qhs_memnoc, + &qhs_llcc }, }; =20 static struct qcom_icc_node acm_apps =3D { .name =3D "acm_apps", - .id =3D SM8150_MASTER_AMPSS_M0, .channels =3D 2, .buswidth =3D 32, .num_links =3D 3, - .links =3D { SM8150_SLAVE_ECC, - SM8150_SLAVE_LLCC, - SM8150_SLAVE_GEM_NOC_SNOC - }, + .link_nodes =3D { &qns_ecc, + &qns_llcc, + &qns_gem_noc_snoc }, }; =20 static struct qcom_icc_node acm_gpu_tcu =3D { .name =3D "acm_gpu_tcu", - .id =3D SM8150_MASTER_GPU_TCU, .channels =3D 1, .buswidth =3D 8, .num_links =3D 2, - .links =3D { SM8150_SLAVE_LLCC, - SM8150_SLAVE_GEM_NOC_SNOC - }, + .link_nodes =3D { &qns_llcc, + &qns_gem_noc_snoc }, }; =20 static struct qcom_icc_node acm_sys_tcu =3D { .name =3D "acm_sys_tcu", - .id =3D SM8150_MASTER_SYS_TCU, .channels =3D 1, .buswidth =3D 8, .num_links =3D 2, - .links =3D { SM8150_SLAVE_LLCC, - SM8150_SLAVE_GEM_NOC_SNOC - }, + .link_nodes =3D { &qns_llcc, + &qns_gem_noc_snoc }, }; =20 static struct qcom_icc_node qhm_gemnoc_cfg =3D { .name =3D "qhm_gemnoc_cfg", - .id =3D SM8150_MASTER_GEM_NOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 2, - .links =3D { SM8150_SLAVE_SERVICE_GEM_NOC, - SM8150_SLAVE_MSS_PROC_MS_MPU_CFG - }, + .link_nodes =3D { &srvc_gemnoc, + &qhs_mdsp_ms_mpu_cfg }, }; =20 static struct qcom_icc_node qnm_cmpnoc =3D { .name =3D "qnm_cmpnoc", - .id =3D SM8150_MASTER_COMPUTE_NOC, .channels =3D 2, .buswidth =3D 32, .num_links =3D 3, - .links =3D { SM8150_SLAVE_ECC, - SM8150_SLAVE_LLCC, - SM8150_SLAVE_GEM_NOC_SNOC - }, + .link_nodes =3D { &qns_ecc, + &qns_llcc, + &qns_gem_noc_snoc }, }; =20 static struct qcom_icc_node qnm_gpu =3D { .name =3D "qnm_gpu", - .id =3D SM8150_MASTER_GRAPHICS_3D, .channels =3D 2, .buswidth =3D 32, .num_links =3D 2, - .links =3D { SM8150_SLAVE_LLCC, - SM8150_SLAVE_GEM_NOC_SNOC - }, + .link_nodes =3D { &qns_llcc, + &qns_gem_noc_snoc }, }; =20 static struct qcom_icc_node qnm_mnoc_hf =3D { .name =3D "qnm_mnoc_hf", - .id =3D SM8150_MASTER_MNOC_HF_MEM_NOC, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8150_SLAVE_LLCC }, + .link_nodes =3D { &qns_llcc }, }; =20 static struct qcom_icc_node qnm_mnoc_sf =3D { .name =3D "qnm_mnoc_sf", - .id =3D SM8150_MASTER_MNOC_SF_MEM_NOC, .channels =3D 1, .buswidth =3D 32, .num_links =3D 2, - .links =3D { SM8150_SLAVE_LLCC, - SM8150_SLAVE_GEM_NOC_SNOC - }, + .link_nodes =3D { &qns_llcc, + &qns_gem_noc_snoc }, }; =20 static struct qcom_icc_node qnm_pcie =3D { .name =3D "qnm_pcie", - .id =3D SM8150_MASTER_GEM_NOC_PCIE_SNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 2, - .links =3D { SM8150_SLAVE_LLCC, - SM8150_SLAVE_GEM_NOC_SNOC - }, + .link_nodes =3D { &qns_llcc, + &qns_gem_noc_snoc }, }; =20 static struct qcom_icc_node qnm_snoc_gc =3D { .name =3D "qnm_snoc_gc", - .id =3D SM8150_MASTER_SNOC_GC_MEM_NOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8150_SLAVE_LLCC }, + .link_nodes =3D { &qns_llcc }, }; =20 static struct qcom_icc_node qnm_snoc_sf =3D { .name =3D "qnm_snoc_sf", - .id =3D SM8150_MASTER_SNOC_SF_MEM_NOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM8150_SLAVE_LLCC }, + .link_nodes =3D { &qns_llcc }, }; =20 static struct qcom_icc_node qxm_ecc =3D { .name =3D "qxm_ecc", - .id =3D SM8150_MASTER_ECC, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8150_SLAVE_LLCC }, + .link_nodes =3D { &qns_llcc }, }; =20 static struct qcom_icc_node llcc_mc =3D { .name =3D "llcc_mc", - .id =3D SM8150_MASTER_LLCC, .channels =3D 4, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8150_SLAVE_EBI_CH0 }, + .link_nodes =3D { &ebi }, }; =20 static struct qcom_icc_node qhm_mnoc_cfg =3D { .name =3D "qhm_mnoc_cfg", - .id =3D SM8150_MASTER_CNOC_MNOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8150_SLAVE_SERVICE_MNOC }, + .link_nodes =3D { &srvc_mnoc }, }; =20 static struct qcom_icc_node qxm_camnoc_hf0 =3D { .name =3D "qxm_camnoc_hf0", - .id =3D SM8150_MASTER_CAMNOC_HF0, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8150_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_hf }, }; =20 static struct qcom_icc_node qxm_camnoc_hf1 =3D { .name =3D "qxm_camnoc_hf1", - .id =3D SM8150_MASTER_CAMNOC_HF1, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8150_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_hf }, }; =20 static struct qcom_icc_node qxm_camnoc_sf =3D { .name =3D "qxm_camnoc_sf", - .id =3D SM8150_MASTER_CAMNOC_SF, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8150_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns2_mem_noc }, }; =20 static struct qcom_icc_node qxm_mdp0 =3D { .name =3D "qxm_mdp0", - .id =3D SM8150_MASTER_MDP_PORT0, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8150_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_hf }, }; =20 static struct qcom_icc_node qxm_mdp1 =3D { .name =3D "qxm_mdp1", - .id =3D SM8150_MASTER_MDP_PORT1, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8150_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_hf }, }; =20 static struct qcom_icc_node qxm_rot =3D { .name =3D "qxm_rot", - .id =3D SM8150_MASTER_ROTATOR, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8150_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns2_mem_noc }, }; =20 static struct qcom_icc_node qxm_venus0 =3D { .name =3D "qxm_venus0", - .id =3D SM8150_MASTER_VIDEO_P0, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8150_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns2_mem_noc }, }; =20 static struct qcom_icc_node qxm_venus1 =3D { .name =3D "qxm_venus1", - .id =3D SM8150_MASTER_VIDEO_P1, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8150_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns2_mem_noc }, }; =20 static struct qcom_icc_node qxm_venus_arm9 =3D { .name =3D "qxm_venus_arm9", - .id =3D SM8150_MASTER_VIDEO_PROC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8150_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns2_mem_noc }, }; =20 static struct qcom_icc_node qhm_snoc_cfg =3D { .name =3D "qhm_snoc_cfg", - .id =3D SM8150_MASTER_SNOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8150_SLAVE_SERVICE_SNOC }, + .link_nodes =3D { &srvc_snoc }, }; =20 static struct qcom_icc_node qnm_aggre1_noc =3D { .name =3D "qnm_aggre1_noc", - .id =3D SM8150_A1NOC_SNOC_MAS, .channels =3D 1, .buswidth =3D 16, .num_links =3D 6, - .links =3D { SM8150_SLAVE_SNOC_GEM_NOC_SF, - SM8150_SLAVE_PIMEM, - SM8150_SLAVE_OCIMEM, - SM8150_SLAVE_APPSS, - SM8150_SNOC_CNOC_SLV, - SM8150_SLAVE_QDSS_STM - }, + .link_nodes =3D { &qns_gemnoc_sf, + &qxs_pimem, + &qxs_imem, + &qhs_apss, + &qns_cnoc, + &xs_qdss_stm }, }; =20 static struct qcom_icc_node qnm_aggre2_noc =3D { .name =3D "qnm_aggre2_noc", - .id =3D SM8150_A2NOC_SNOC_MAS, .channels =3D 1, .buswidth =3D 16, .num_links =3D 9, - .links =3D { SM8150_SLAVE_SNOC_GEM_NOC_SF, - SM8150_SLAVE_PIMEM, - SM8150_SLAVE_OCIMEM, - SM8150_SLAVE_APPSS, - SM8150_SNOC_CNOC_SLV, - SM8150_SLAVE_PCIE_0, - SM8150_SLAVE_PCIE_1, - SM8150_SLAVE_TCU, - SM8150_SLAVE_QDSS_STM - }, + .link_nodes =3D { &qns_gemnoc_sf, + &qxs_pimem, + &qxs_imem, + &qhs_apss, + &qns_cnoc, + &xs_pcie_0, + &xs_pcie_1, + &xs_sys_tcu_cfg, + &xs_qdss_stm }, }; =20 static struct qcom_icc_node qnm_gemnoc =3D { .name =3D "qnm_gemnoc", - .id =3D SM8150_MASTER_GEM_NOC_SNOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 6, - .links =3D { SM8150_SLAVE_PIMEM, - SM8150_SLAVE_OCIMEM, - SM8150_SLAVE_APPSS, - SM8150_SNOC_CNOC_SLV, - SM8150_SLAVE_TCU, - SM8150_SLAVE_QDSS_STM - }, + .link_nodes =3D { &qxs_pimem, + &qxs_imem, + &qhs_apss, + &qns_cnoc, + &xs_sys_tcu_cfg, + &xs_qdss_stm }, }; =20 static struct qcom_icc_node qxm_pimem =3D { .name =3D "qxm_pimem", - .id =3D SM8150_MASTER_PIMEM, .channels =3D 1, .buswidth =3D 8, .num_links =3D 2, - .links =3D { SM8150_SLAVE_SNOC_GEM_NOC_GC, - SM8150_SLAVE_OCIMEM - }, + .link_nodes =3D { &qns_gemnoc_gc, + &qxs_imem }, }; =20 static struct qcom_icc_node xm_gic =3D { .name =3D "xm_gic", - .id =3D SM8150_MASTER_GIC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 2, - .links =3D { SM8150_SLAVE_SNOC_GEM_NOC_GC, - SM8150_SLAVE_OCIMEM - }, + .link_nodes =3D { &qns_gemnoc_gc, + &qxs_imem }, }; =20 static struct qcom_icc_node qns_a1noc_snoc =3D { .name =3D "qns_a1noc_snoc", - .id =3D SM8150_A1NOC_SNOC_SLV, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM8150_A1NOC_SNOC_MAS }, + .link_nodes =3D { &qnm_aggre1_noc }, }; =20 static struct qcom_icc_node srvc_aggre1_noc =3D { .name =3D "srvc_aggre1_noc", - .id =3D SM8150_SLAVE_SERVICE_A1NOC, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qns_a2noc_snoc =3D { .name =3D "qns_a2noc_snoc", - .id =3D SM8150_A2NOC_SNOC_SLV, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM8150_A2NOC_SNOC_MAS }, + .link_nodes =3D { &qnm_aggre2_noc }, }; =20 static struct qcom_icc_node qns_pcie_mem_noc =3D { .name =3D "qns_pcie_mem_noc", - .id =3D SM8150_SLAVE_ANOC_PCIE_GEM_NOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM8150_MASTER_GEM_NOC_PCIE_SNOC }, + .link_nodes =3D { &qnm_pcie }, }; =20 static struct qcom_icc_node srvc_aggre2_noc =3D { .name =3D "srvc_aggre2_noc", - .id =3D SM8150_SLAVE_SERVICE_A2NOC, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qns_camnoc_uncomp =3D { .name =3D "qns_camnoc_uncomp", - .id =3D SM8150_SLAVE_CAMNOC_UNCOMP, .channels =3D 1, .buswidth =3D 32, }; =20 static struct qcom_icc_node qns_cdsp_mem_noc =3D { .name =3D "qns_cdsp_mem_noc", - .id =3D SM8150_SLAVE_CDSP_MEM_NOC, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8150_MASTER_COMPUTE_NOC }, + .link_nodes =3D { &qnm_cmpnoc }, }; =20 static struct qcom_icc_node qhs_a1_noc_cfg =3D { .name =3D "qhs_a1_noc_cfg", - .id =3D SM8150_SLAVE_A1NOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8150_MASTER_A1NOC_CFG }, + .link_nodes =3D { &qhm_a1noc_cfg }, }; =20 static struct qcom_icc_node qhs_a2_noc_cfg =3D { .name =3D "qhs_a2_noc_cfg", - .id =3D SM8150_SLAVE_A2NOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8150_MASTER_A2NOC_CFG }, + .link_nodes =3D { &qhm_a2noc_cfg }, }; =20 static struct qcom_icc_node qhs_ahb2phy_south =3D { .name =3D "qhs_ahb2phy_south", - .id =3D SM8150_SLAVE_AHB2PHY_SOUTH, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_aop =3D { .name =3D "qhs_aop", - .id =3D SM8150_SLAVE_AOP, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_aoss =3D { .name =3D "qhs_aoss", - .id =3D SM8150_SLAVE_AOSS, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_camera_cfg =3D { .name =3D "qhs_camera_cfg", - .id =3D SM8150_SLAVE_CAMERA_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_clk_ctl =3D { .name =3D "qhs_clk_ctl", - .id =3D SM8150_SLAVE_CLK_CTL, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_compute_dsp =3D { .name =3D "qhs_compute_dsp", - .id =3D SM8150_SLAVE_CDSP_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_cpr_cx =3D { .name =3D "qhs_cpr_cx", - .id =3D SM8150_SLAVE_RBCPR_CX_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_cpr_mmcx =3D { .name =3D "qhs_cpr_mmcx", - .id =3D SM8150_SLAVE_RBCPR_MMCX_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_cpr_mx =3D { .name =3D "qhs_cpr_mx", - .id =3D SM8150_SLAVE_RBCPR_MX_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_crypto0_cfg =3D { .name =3D "qhs_crypto0_cfg", - .id =3D SM8150_SLAVE_CRYPTO_0_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_ddrss_cfg =3D { .name =3D "qhs_ddrss_cfg", - .id =3D SM8150_SLAVE_CNOC_DDRSS, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8150_MASTER_CNOC_DC_NOC }, + .link_nodes =3D { &qhm_cnoc_dc_noc }, }; =20 static struct qcom_icc_node qhs_display_cfg =3D { .name =3D "qhs_display_cfg", - .id =3D SM8150_SLAVE_DISPLAY_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_emac_cfg =3D { .name =3D "qhs_emac_cfg", - .id =3D SM8150_SLAVE_EMAC_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_glm =3D { .name =3D "qhs_glm", - .id =3D SM8150_SLAVE_GLM, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_gpuss_cfg =3D { .name =3D "qhs_gpuss_cfg", - .id =3D SM8150_SLAVE_GRAPHICS_3D_CFG, .channels =3D 1, .buswidth =3D 8, }; =20 static struct qcom_icc_node qhs_imem_cfg =3D { .name =3D "qhs_imem_cfg", - .id =3D SM8150_SLAVE_IMEM_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_ipa =3D { .name =3D "qhs_ipa", - .id =3D SM8150_SLAVE_IPA_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_mnoc_cfg =3D { .name =3D "qhs_mnoc_cfg", - .id =3D SM8150_SLAVE_CNOC_MNOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8150_MASTER_CNOC_MNOC_CFG }, + .link_nodes =3D { &qhm_mnoc_cfg }, }; =20 static struct qcom_icc_node qhs_npu_cfg =3D { .name =3D "qhs_npu_cfg", - .id =3D SM8150_SLAVE_NPU_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_pcie0_cfg =3D { .name =3D "qhs_pcie0_cfg", - .id =3D SM8150_SLAVE_PCIE_0_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_pcie1_cfg =3D { .name =3D "qhs_pcie1_cfg", - .id =3D SM8150_SLAVE_PCIE_1_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_phy_refgen_north =3D { .name =3D "qhs_phy_refgen_north", - .id =3D SM8150_SLAVE_NORTH_PHY_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_pimem_cfg =3D { .name =3D "qhs_pimem_cfg", - .id =3D SM8150_SLAVE_PIMEM_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_prng =3D { .name =3D "qhs_prng", - .id =3D SM8150_SLAVE_PRNG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_qdss_cfg =3D { .name =3D "qhs_qdss_cfg", - .id =3D SM8150_SLAVE_QDSS_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_qspi =3D { .name =3D "qhs_qspi", - .id =3D SM8150_SLAVE_QSPI, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_qupv3_east =3D { .name =3D "qhs_qupv3_east", - .id =3D SM8150_SLAVE_QUP_2, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_qupv3_north =3D { .name =3D "qhs_qupv3_north", - .id =3D SM8150_SLAVE_QUP_1, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_qupv3_south =3D { .name =3D "qhs_qupv3_south", - .id =3D SM8150_SLAVE_QUP_0, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_sdc2 =3D { .name =3D "qhs_sdc2", - .id =3D SM8150_SLAVE_SDCC_2, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_sdc4 =3D { .name =3D "qhs_sdc4", - .id =3D SM8150_SLAVE_SDCC_4, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_snoc_cfg =3D { .name =3D "qhs_snoc_cfg", - .id =3D SM8150_SLAVE_SNOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8150_MASTER_SNOC_CFG }, + .link_nodes =3D { &qhm_snoc_cfg }, }; =20 static struct qcom_icc_node qhs_spdm =3D { .name =3D "qhs_spdm", - .id =3D SM8150_SLAVE_SPDM_WRAPPER, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_spss_cfg =3D { .name =3D "qhs_spss_cfg", - .id =3D SM8150_SLAVE_SPSS_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_ssc_cfg =3D { .name =3D "qhs_ssc_cfg", - .id =3D SM8150_SLAVE_SSC_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_tcsr =3D { .name =3D "qhs_tcsr", - .id =3D SM8150_SLAVE_TCSR, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_tlmm_east =3D { .name =3D "qhs_tlmm_east", - .id =3D SM8150_SLAVE_TLMM_EAST, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_tlmm_north =3D { .name =3D "qhs_tlmm_north", - .id =3D SM8150_SLAVE_TLMM_NORTH, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_tlmm_south =3D { .name =3D "qhs_tlmm_south", - .id =3D SM8150_SLAVE_TLMM_SOUTH, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_tlmm_west =3D { .name =3D "qhs_tlmm_west", - .id =3D SM8150_SLAVE_TLMM_WEST, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_tsif =3D { .name =3D "qhs_tsif", - .id =3D SM8150_SLAVE_TSIF, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_ufs_card_cfg =3D { .name =3D "qhs_ufs_card_cfg", - .id =3D SM8150_SLAVE_UFS_CARD_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_ufs_mem_cfg =3D { .name =3D "qhs_ufs_mem_cfg", - .id =3D SM8150_SLAVE_UFS_MEM_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_usb3_0 =3D { .name =3D "qhs_usb3_0", - .id =3D SM8150_SLAVE_USB3, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_usb3_1 =3D { .name =3D "qhs_usb3_1", - .id =3D SM8150_SLAVE_USB3_1, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_venus_cfg =3D { .name =3D "qhs_venus_cfg", - .id =3D SM8150_SLAVE_VENUS_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_vsense_ctrl_cfg =3D { .name =3D "qhs_vsense_ctrl_cfg", - .id =3D SM8150_SLAVE_VSENSE_CTRL_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qns_cnoc_a2noc =3D { .name =3D "qns_cnoc_a2noc", - .id =3D SM8150_SLAVE_CNOC_A2NOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8150_MASTER_CNOC_A2NOC }, + .link_nodes =3D { &qnm_cnoc }, }; =20 static struct qcom_icc_node srvc_cnoc =3D { .name =3D "srvc_cnoc", - .id =3D SM8150_SLAVE_SERVICE_CNOC, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_llcc =3D { .name =3D "qhs_llcc", - .id =3D SM8150_SLAVE_LLCC_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_memnoc =3D { .name =3D "qhs_memnoc", - .id =3D SM8150_SLAVE_GEM_NOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8150_MASTER_GEM_NOC_CFG }, + .link_nodes =3D { &qhm_gemnoc_cfg }, }; =20 static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg =3D { .name =3D "qhs_mdsp_ms_mpu_cfg", - .id =3D SM8150_SLAVE_MSS_PROC_MS_MPU_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qns_ecc =3D { .name =3D "qns_ecc", - .id =3D SM8150_SLAVE_ECC, .channels =3D 1, .buswidth =3D 32, }; =20 static struct qcom_icc_node qns_gem_noc_snoc =3D { .name =3D "qns_gem_noc_snoc", - .id =3D SM8150_SLAVE_GEM_NOC_SNOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8150_MASTER_GEM_NOC_SNOC }, + .link_nodes =3D { &qnm_gemnoc }, }; =20 static struct qcom_icc_node qns_llcc =3D { .name =3D "qns_llcc", - .id =3D SM8150_SLAVE_LLCC, .channels =3D 4, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM8150_MASTER_LLCC }, + .link_nodes =3D { &llcc_mc }, }; =20 static struct qcom_icc_node srvc_gemnoc =3D { .name =3D "srvc_gemnoc", - .id =3D SM8150_SLAVE_SERVICE_GEM_NOC, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node ebi =3D { .name =3D "ebi", - .id =3D SM8150_SLAVE_EBI_CH0, .channels =3D 4, .buswidth =3D 4, }; =20 static struct qcom_icc_node qns2_mem_noc =3D { .name =3D "qns2_mem_noc", - .id =3D SM8150_SLAVE_MNOC_SF_MEM_NOC, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8150_MASTER_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qnm_mnoc_sf }, }; =20 static struct qcom_icc_node qns_mem_noc_hf =3D { .name =3D "qns_mem_noc_hf", - .id =3D SM8150_SLAVE_MNOC_HF_MEM_NOC, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8150_MASTER_MNOC_HF_MEM_NOC }, + .link_nodes =3D { &qnm_mnoc_hf }, }; =20 static struct qcom_icc_node srvc_mnoc =3D { .name =3D "srvc_mnoc", - .id =3D SM8150_SLAVE_SERVICE_MNOC, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_apss =3D { .name =3D "qhs_apss", - .id =3D SM8150_SLAVE_APPSS, .channels =3D 1, .buswidth =3D 8, }; =20 static struct qcom_icc_node qns_cnoc =3D { .name =3D "qns_cnoc", - .id =3D SM8150_SNOC_CNOC_SLV, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8150_SNOC_CNOC_MAS }, + .link_nodes =3D { &qnm_snoc }, }; =20 static struct qcom_icc_node qns_gemnoc_gc =3D { .name =3D "qns_gemnoc_gc", - .id =3D SM8150_SLAVE_SNOC_GEM_NOC_GC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8150_MASTER_SNOC_GC_MEM_NOC }, + .link_nodes =3D { &qnm_snoc_gc }, }; =20 static struct qcom_icc_node qns_gemnoc_sf =3D { .name =3D "qns_gemnoc_sf", - .id =3D SM8150_SLAVE_SNOC_GEM_NOC_SF, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM8150_MASTER_SNOC_SF_MEM_NOC }, + .link_nodes =3D { &qnm_snoc_sf }, }; =20 static struct qcom_icc_node qxs_imem =3D { .name =3D "qxs_imem", - .id =3D SM8150_SLAVE_OCIMEM, .channels =3D 1, .buswidth =3D 8, }; =20 static struct qcom_icc_node qxs_pimem =3D { .name =3D "qxs_pimem", - .id =3D SM8150_SLAVE_PIMEM, .channels =3D 1, .buswidth =3D 8, }; =20 static struct qcom_icc_node srvc_snoc =3D { .name =3D "srvc_snoc", - .id =3D SM8150_SLAVE_SERVICE_SNOC, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node xs_pcie_0 =3D { .name =3D "xs_pcie_0", - .id =3D SM8150_SLAVE_PCIE_0, .channels =3D 1, .buswidth =3D 8, }; =20 static struct qcom_icc_node xs_pcie_1 =3D { .name =3D "xs_pcie_1", - .id =3D SM8150_SLAVE_PCIE_1, .channels =3D 1, .buswidth =3D 8, }; =20 static struct qcom_icc_node xs_qdss_stm =3D { .name =3D "xs_qdss_stm", - .id =3D SM8150_SLAVE_QDSS_STM, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node xs_sys_tcu_cfg =3D { .name =3D "xs_sys_tcu_cfg", - .id =3D SM8150_SLAVE_TCU, .channels =3D 1, .buswidth =3D 8, }; @@ -1554,6 +1538,7 @@ static struct qcom_icc_node * const aggre1_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sm8150_aggre1_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D aggre1_noc_nodes, .num_nodes =3D ARRAY_SIZE(aggre1_noc_nodes), .bcms =3D aggre1_noc_bcms, @@ -1589,6 +1574,7 @@ static struct qcom_icc_node * const aggre2_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sm8150_aggre2_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D aggre2_noc_nodes, .num_nodes =3D ARRAY_SIZE(aggre2_noc_nodes), .bcms =3D aggre2_noc_bcms, @@ -1607,6 +1593,7 @@ static struct qcom_icc_node * const camnoc_virt_nodes= [] =3D { }; =20 static const struct qcom_icc_desc sm8150_camnoc_virt =3D { + .alloc_dyn_id =3D true, .nodes =3D camnoc_virt_nodes, .num_nodes =3D ARRAY_SIZE(camnoc_virt_nodes), .bcms =3D camnoc_virt_bcms, @@ -1624,6 +1611,7 @@ static struct qcom_icc_node * const compute_noc_nodes= [] =3D { }; =20 static const struct qcom_icc_desc sm8150_compute_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D compute_noc_nodes, .num_nodes =3D ARRAY_SIZE(compute_noc_nodes), .bcms =3D compute_noc_bcms, @@ -1692,6 +1680,7 @@ static struct qcom_icc_node * const config_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sm8150_config_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D config_noc_nodes, .num_nodes =3D ARRAY_SIZE(config_noc_nodes), .bcms =3D config_noc_bcms, @@ -1708,6 +1697,7 @@ static struct qcom_icc_node * const dc_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sm8150_dc_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D dc_noc_nodes, .num_nodes =3D ARRAY_SIZE(dc_noc_nodes), .bcms =3D dc_noc_bcms, @@ -1743,6 +1733,7 @@ static struct qcom_icc_node * const gem_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sm8150_gem_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D gem_noc_nodes, .num_nodes =3D ARRAY_SIZE(gem_noc_nodes), .bcms =3D gem_noc_bcms, @@ -1760,6 +1751,7 @@ static struct qcom_icc_node * const mc_virt_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sm8150_mc_virt =3D { + .alloc_dyn_id =3D true, .nodes =3D mc_virt_nodes, .num_nodes =3D ARRAY_SIZE(mc_virt_nodes), .bcms =3D mc_virt_bcms, @@ -1790,6 +1782,7 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sm8150_mmss_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D mmss_noc_nodes, .num_nodes =3D ARRAY_SIZE(mmss_noc_nodes), .bcms =3D mmss_noc_bcms, @@ -1831,6 +1824,7 @@ static struct qcom_icc_node * const system_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sm8150_system_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D system_noc_nodes, .num_nodes =3D ARRAY_SIZE(system_noc_nodes), .bcms =3D system_noc_bcms, diff --git a/drivers/interconnect/qcom/sm8150.h b/drivers/interconnect/qcom= /sm8150.h deleted file mode 100644 index 1d587c94eb06e1b06b0dcd582807b87aa59af075..000000000000000000000000000= 0000000000000 --- a/drivers/interconnect/qcom/sm8150.h +++ /dev/null @@ -1,152 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Qualcomm #define SM8250 interconnect IDs - * - * Copyright (c) 2020, The Linux Foundation. All rights reserved. - */ - -#ifndef __DRIVERS_INTERCONNECT_QCOM_SM8150_H -#define __DRIVERS_INTERCONNECT_QCOM_SM8150_H - -#define SM8150_A1NOC_SNOC_MAS 0 -#define SM8150_A1NOC_SNOC_SLV 1 -#define SM8150_A2NOC_SNOC_MAS 2 -#define SM8150_A2NOC_SNOC_SLV 3 -#define SM8150_MASTER_A1NOC_CFG 4 -#define SM8150_MASTER_A2NOC_CFG 5 -#define SM8150_MASTER_AMPSS_M0 6 -#define SM8150_MASTER_CAMNOC_HF0 7 -#define SM8150_MASTER_CAMNOC_HF0_UNCOMP 8 -#define SM8150_MASTER_CAMNOC_HF1 9 -#define SM8150_MASTER_CAMNOC_HF1_UNCOMP 10 -#define SM8150_MASTER_CAMNOC_SF 11 -#define SM8150_MASTER_CAMNOC_SF_UNCOMP 12 -#define SM8150_MASTER_CNOC_A2NOC 13 -#define SM8150_MASTER_CNOC_DC_NOC 14 -#define SM8150_MASTER_CNOC_MNOC_CFG 15 -#define SM8150_MASTER_COMPUTE_NOC 16 -#define SM8150_MASTER_CRYPTO_CORE_0 17 -#define SM8150_MASTER_ECC 18 -#define SM8150_MASTER_EMAC 19 -#define SM8150_MASTER_GEM_NOC_CFG 20 -#define SM8150_MASTER_GEM_NOC_PCIE_SNOC 21 -#define SM8150_MASTER_GEM_NOC_SNOC 22 -#define SM8150_MASTER_GIC 23 -#define SM8150_MASTER_GPU_TCU 24 -#define SM8150_MASTER_GRAPHICS_3D 25 -#define SM8150_MASTER_IPA 26 -/* 27 was used by SLAVE_IPA_CORE, now represented as RPMh clock */ -#define SM8150_MASTER_LLCC 28 -#define SM8150_MASTER_MDP_PORT0 29 -#define SM8150_MASTER_MDP_PORT1 30 -#define SM8150_MASTER_MNOC_HF_MEM_NOC 31 -#define SM8150_MASTER_MNOC_SF_MEM_NOC 32 -#define SM8150_MASTER_NPU 33 -#define SM8150_MASTER_PCIE 34 -#define SM8150_MASTER_PCIE_1 35 -#define SM8150_MASTER_PIMEM 36 -#define SM8150_MASTER_QDSS_BAM 37 -#define SM8150_MASTER_QDSS_DAP 38 -#define SM8150_MASTER_QDSS_ETR 39 -#define SM8150_MASTER_QSPI 40 -#define SM8150_MASTER_QUP_0 41 -#define SM8150_MASTER_QUP_1 42 -#define SM8150_MASTER_QUP_2 43 -#define SM8150_MASTER_ROTATOR 44 -#define SM8150_MASTER_SDCC_2 45 -#define SM8150_MASTER_SDCC_4 46 -#define SM8150_MASTER_SENSORS_AHB 47 -#define SM8150_MASTER_SNOC_CFG 48 -#define SM8150_MASTER_SNOC_GC_MEM_NOC 49 -#define SM8150_MASTER_SNOC_SF_MEM_NOC 50 -#define SM8150_MASTER_SPDM 51 -#define SM8150_MASTER_SYS_TCU 52 -#define SM8150_MASTER_TSIF 53 -#define SM8150_MASTER_UFS_MEM 54 -#define SM8150_MASTER_USB3 55 -#define SM8150_MASTER_USB3_1 56 -#define SM8150_MASTER_VIDEO_P0 57 -#define SM8150_MASTER_VIDEO_P1 58 -#define SM8150_MASTER_VIDEO_PROC 59 -#define SM8150_SLAVE_A1NOC_CFG 60 -#define SM8150_SLAVE_A2NOC_CFG 61 -#define SM8150_SLAVE_AHB2PHY_SOUTH 62 -#define SM8150_SLAVE_ANOC_PCIE_GEM_NOC 63 -#define SM8150_SLAVE_AOP 64 -#define SM8150_SLAVE_AOSS 65 -#define SM8150_SLAVE_APPSS 66 -#define SM8150_SLAVE_CAMERA_CFG 67 -#define SM8150_SLAVE_CAMNOC_UNCOMP 68 -#define SM8150_SLAVE_CDSP_CFG 69 -#define SM8150_SLAVE_CDSP_MEM_NOC 70 -#define SM8150_SLAVE_CLK_CTL 71 -#define SM8150_SLAVE_CNOC_A2NOC 72 -#define SM8150_SLAVE_CNOC_DDRSS 73 -#define SM8150_SLAVE_CNOC_MNOC_CFG 74 -#define SM8150_SLAVE_CRYPTO_0_CFG 75 -#define SM8150_SLAVE_DISPLAY_CFG 76 -#define SM8150_SLAVE_EBI_CH0 77 -#define SM8150_SLAVE_ECC 78 -#define SM8150_SLAVE_EMAC_CFG 79 -#define SM8150_SLAVE_GEM_NOC_CFG 80 -#define SM8150_SLAVE_GEM_NOC_SNOC 81 -#define SM8150_SLAVE_GLM 82 -#define SM8150_SLAVE_GRAPHICS_3D_CFG 83 -#define SM8150_SLAVE_IMEM_CFG 84 -#define SM8150_SLAVE_IPA_CFG 85 -/* 86 was used by SLAVE_IPA_CORE, now represented as RPMh clock */ -#define SM8150_SLAVE_LLCC 87 -#define SM8150_SLAVE_LLCC_CFG 88 -#define SM8150_SLAVE_MNOC_HF_MEM_NOC 89 -#define SM8150_SLAVE_MNOC_SF_MEM_NOC 90 -#define SM8150_SLAVE_MSS_PROC_MS_MPU_CFG 91 -#define SM8150_SLAVE_NORTH_PHY_CFG 92 -#define SM8150_SLAVE_NPU_CFG 93 -#define SM8150_SLAVE_OCIMEM 94 -#define SM8150_SLAVE_PCIE_0 95 -#define SM8150_SLAVE_PCIE_0_CFG 96 -#define SM8150_SLAVE_PCIE_1 97 -#define SM8150_SLAVE_PCIE_1_CFG 98 -#define SM8150_SLAVE_PIMEM 99 -#define SM8150_SLAVE_PIMEM_CFG 100 -#define SM8150_SLAVE_PRNG 101 -#define SM8150_SLAVE_QDSS_CFG 102 -#define SM8150_SLAVE_QDSS_STM 103 -#define SM8150_SLAVE_QSPI 104 -#define SM8150_SLAVE_QUP_0 105 -#define SM8150_SLAVE_QUP_1 106 -#define SM8150_SLAVE_QUP_2 107 -#define SM8150_SLAVE_RBCPR_CX_CFG 108 -#define SM8150_SLAVE_RBCPR_MMCX_CFG 109 -#define SM8150_SLAVE_RBCPR_MX_CFG 110 -#define SM8150_SLAVE_SDCC_2 111 -#define SM8150_SLAVE_SDCC_4 112 -#define SM8150_SLAVE_SERVICE_A1NOC 113 -#define SM8150_SLAVE_SERVICE_A2NOC 114 -#define SM8150_SLAVE_SERVICE_CNOC 115 -#define SM8150_SLAVE_SERVICE_GEM_NOC 116 -#define SM8150_SLAVE_SERVICE_MNOC 117 -#define SM8150_SLAVE_SERVICE_SNOC 118 -#define SM8150_SLAVE_SNOC_CFG 119 -#define SM8150_SLAVE_SNOC_GEM_NOC_GC 120 -#define SM8150_SLAVE_SNOC_GEM_NOC_SF 121 -#define SM8150_SLAVE_SPDM_WRAPPER 122 -#define SM8150_SLAVE_SPSS_CFG 123 -#define SM8150_SLAVE_SSC_CFG 124 -#define SM8150_SLAVE_TCSR 125 -#define SM8150_SLAVE_TCU 126 -#define SM8150_SLAVE_TLMM_EAST 127 -#define SM8150_SLAVE_TLMM_NORTH 128 -#define SM8150_SLAVE_TLMM_SOUTH 129 -#define SM8150_SLAVE_TLMM_WEST 130 -#define SM8150_SLAVE_TSIF 131 -#define SM8150_SLAVE_UFS_CARD_CFG 132 -#define SM8150_SLAVE_UFS_MEM_CFG 133 -#define SM8150_SLAVE_USB3 134 -#define SM8150_SLAVE_USB3_1 135 -#define SM8150_SLAVE_VENUS_CFG 136 -#define SM8150_SLAVE_VSENSE_CTRL_CFG 137 -#define SM8150_SNOC_CNOC_MAS 138 -#define SM8150_SNOC_CNOC_SLV 139 - -#endif --=20 2.47.3