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This gives more flexibility and also allows us to drop the .num_links member, saving from possible errors related to it being not set or set incorrectly. Signed-off-by: Dmitry Baryshkov --- drivers/interconnect/qcom/sdx75.c | 384 +++++++++++++++++-----------------= ---- drivers/interconnect/qcom/sdx75.h | 97 ---------- 2 files changed, 174 insertions(+), 307 deletions(-) diff --git a/drivers/interconnect/qcom/sdx75.c b/drivers/interconnect/qcom/= sdx75.c index 7ef1f17f3292e15959cb06e3d8d8c5f3c6ecd060..3721d8f503a022e4c5fde62b0aa= 9eed9989c1554 100644 --- a/drivers/interconnect/qcom/sdx75.c +++ b/drivers/interconnect/qcom/sdx75.c @@ -14,782 +14,740 @@ #include "bcm-voter.h" #include "icc-common.h" #include "icc-rpmh.h" -#include "sdx75.h" + +static struct qcom_icc_node qpic_core_master; +static struct qcom_icc_node qup0_core_master; +static struct qcom_icc_node qnm_cnoc; +static struct qcom_icc_node alm_sys_tcu; +static struct qcom_icc_node chm_apps; +static struct qcom_icc_node qnm_gemnoc_cfg; +static struct qcom_icc_node qnm_mdsp; +static struct qcom_icc_node qnm_pcie; +static struct qcom_icc_node qnm_snoc_sf; +static struct qcom_icc_node xm_gic; +static struct qcom_icc_node xm_ipa2pcie; +static struct qcom_icc_node llcc_mc; +static struct qcom_icc_node xm_pcie3_0; +static struct qcom_icc_node xm_pcie3_1; +static struct qcom_icc_node xm_pcie3_2; +static struct qcom_icc_node qhm_audio; +static struct qcom_icc_node qhm_gic; +static struct qcom_icc_node qhm_pcie_rscc; +static struct qcom_icc_node qhm_qdss_bam; +static struct qcom_icc_node qhm_qpic; +static struct qcom_icc_node qhm_qup0; +static struct qcom_icc_node qnm_aggre_noc; +static struct qcom_icc_node qnm_gemnoc_cnoc; +static struct qcom_icc_node qnm_gemnoc_pcie; +static struct qcom_icc_node qnm_system_noc_cfg; +static struct qcom_icc_node qnm_system_noc_pcie_cfg; +static struct qcom_icc_node qxm_crypto; +static struct qcom_icc_node qxm_ipa; +static struct qcom_icc_node qxm_mvmss; +static struct qcom_icc_node xm_emac_0; +static struct qcom_icc_node xm_emac_1; +static struct qcom_icc_node xm_qdss_etr0; +static struct qcom_icc_node xm_qdss_etr1; +static struct qcom_icc_node xm_sdc1; +static struct qcom_icc_node xm_sdc4; +static struct qcom_icc_node xm_usb3; +static struct qcom_icc_node qpic_core_slave; +static struct qcom_icc_node qup0_core_slave; +static struct qcom_icc_node qhs_lagg; +static struct qcom_icc_node qhs_mccc_master; +static struct qcom_icc_node qns_gemnoc; +static struct qcom_icc_node qss_snoop_bwmon; +static struct qcom_icc_node qns_gemnoc_cnoc; +static struct qcom_icc_node qns_llcc; +static struct qcom_icc_node qns_pcie; +static struct qcom_icc_node srvc_gemnoc; +static struct qcom_icc_node ebi; +static struct qcom_icc_node qns_pcie_gemnoc; +static struct qcom_icc_node ps_eth0_cfg; +static struct qcom_icc_node ps_eth1_cfg; +static struct qcom_icc_node qhs_audio; +static struct qcom_icc_node qhs_clk_ctl; +static struct qcom_icc_node qhs_crypto_cfg; +static struct qcom_icc_node qhs_imem_cfg; +static struct qcom_icc_node qhs_ipa; +static struct qcom_icc_node qhs_ipc_router; +static struct qcom_icc_node qhs_mss_cfg; +static struct qcom_icc_node qhs_mvmss_cfg; +static struct qcom_icc_node qhs_pcie0_cfg; +static struct qcom_icc_node qhs_pcie1_cfg; +static struct qcom_icc_node qhs_pcie2_cfg; +static struct qcom_icc_node qhs_pcie_rscc; +static struct qcom_icc_node qhs_pdm; +static struct qcom_icc_node qhs_prng; +static struct qcom_icc_node qhs_qdss_cfg; +static struct qcom_icc_node qhs_qpic; +static struct qcom_icc_node qhs_qup0; +static struct qcom_icc_node qhs_sdc1; +static struct qcom_icc_node qhs_sdc4; +static struct qcom_icc_node qhs_spmi_vgi_coex; +static struct qcom_icc_node qhs_tcsr; +static struct qcom_icc_node qhs_tlmm; +static struct qcom_icc_node qhs_usb3; +static struct qcom_icc_node qhs_usb3_phy; +static struct qcom_icc_node qns_a1noc; +static struct qcom_icc_node qns_ddrss_cfg; +static struct qcom_icc_node qns_gemnoc_sf; +static struct qcom_icc_node qns_system_noc_cfg; +static struct qcom_icc_node qns_system_noc_pcie_cfg; +static struct qcom_icc_node qxs_imem; +static struct qcom_icc_node srvc_pcie_system_noc; +static struct qcom_icc_node srvc_system_noc; +static struct qcom_icc_node xs_pcie_0; +static struct qcom_icc_node xs_pcie_1; +static struct qcom_icc_node xs_pcie_2; +static struct qcom_icc_node xs_qdss_stm; +static struct qcom_icc_node xs_sys_tcu_cfg; =20 static struct qcom_icc_node qpic_core_master =3D { .name =3D "qpic_core_master", - .id =3D SDX75_MASTER_QPIC_CORE, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SDX75_SLAVE_QPIC_CORE }, + .link_nodes =3D { &qpic_core_slave }, }; =20 static struct qcom_icc_node qup0_core_master =3D { .name =3D "qup0_core_master", - .id =3D SDX75_MASTER_QUP_CORE_0, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SDX75_SLAVE_QUP_CORE_0 }, + .link_nodes =3D { &qup0_core_slave }, }; =20 static struct qcom_icc_node qnm_cnoc =3D { .name =3D "qnm_cnoc", - .id =3D SDX75_MASTER_CNOC_DC_NOC, .channels =3D 1, .buswidth =3D 4, .num_links =3D 4, - .links =3D { SDX75_SLAVE_LAGG_CFG, SDX75_SLAVE_MCCC_MASTER, - SDX75_SLAVE_GEM_NOC_CFG, SDX75_SLAVE_SNOOP_BWMON }, + .link_nodes =3D { &qhs_lagg, &qhs_mccc_master, + &qns_gemnoc, &qss_snoop_bwmon }, }; =20 static struct qcom_icc_node alm_sys_tcu =3D { .name =3D "alm_sys_tcu", - .id =3D SDX75_MASTER_SYS_TCU, .channels =3D 1, .buswidth =3D 8, .num_links =3D 2, - .links =3D { SDX75_SLAVE_GEM_NOC_CNOC, SDX75_SLAVE_LLCC }, + .link_nodes =3D { &qns_gemnoc_cnoc, &qns_llcc }, }; =20 static struct qcom_icc_node chm_apps =3D { .name =3D "chm_apps", - .id =3D SDX75_MASTER_APPSS_PROC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 3, - .links =3D { SDX75_SLAVE_GEM_NOC_CNOC, SDX75_SLAVE_LLCC, - SDX75_SLAVE_MEM_NOC_PCIE_SNOC }, + .link_nodes =3D { &qns_gemnoc_cnoc, &qns_llcc, + &qns_pcie }, }; =20 static struct qcom_icc_node qnm_gemnoc_cfg =3D { .name =3D "qnm_gemnoc_cfg", - .id =3D SDX75_MASTER_GEM_NOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SDX75_SLAVE_SERVICE_GEM_NOC }, + .link_nodes =3D { &srvc_gemnoc }, }; =20 static struct qcom_icc_node qnm_mdsp =3D { .name =3D "qnm_mdsp", - .id =3D SDX75_MASTER_MSS_PROC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 3, - .links =3D { SDX75_SLAVE_GEM_NOC_CNOC, SDX75_SLAVE_LLCC, - SDX75_SLAVE_MEM_NOC_PCIE_SNOC }, + .link_nodes =3D { &qns_gemnoc_cnoc, &qns_llcc, + &qns_pcie }, }; =20 static struct qcom_icc_node qnm_pcie =3D { .name =3D "qnm_pcie", - .id =3D SDX75_MASTER_ANOC_PCIE_GEM_NOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 2, - .links =3D { SDX75_SLAVE_GEM_NOC_CNOC, SDX75_SLAVE_LLCC }, + .link_nodes =3D { &qns_gemnoc_cnoc, &qns_llcc }, }; =20 static struct qcom_icc_node qnm_snoc_sf =3D { .name =3D "qnm_snoc_sf", - .id =3D SDX75_MASTER_SNOC_SF_MEM_NOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 3, - .links =3D { SDX75_SLAVE_GEM_NOC_CNOC, SDX75_SLAVE_LLCC, - SDX75_SLAVE_MEM_NOC_PCIE_SNOC }, + .link_nodes =3D { &qns_gemnoc_cnoc, &qns_llcc, + &qns_pcie }, }; =20 static struct qcom_icc_node xm_gic =3D { .name =3D "xm_gic", - .id =3D SDX75_MASTER_GIC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SDX75_SLAVE_LLCC }, + .link_nodes =3D { &qns_llcc }, }; =20 static struct qcom_icc_node xm_ipa2pcie =3D { .name =3D "xm_ipa2pcie", - .id =3D SDX75_MASTER_IPA_PCIE, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SDX75_SLAVE_MEM_NOC_PCIE_SNOC }, + .link_nodes =3D { &qns_pcie }, }; =20 static struct qcom_icc_node llcc_mc =3D { .name =3D "llcc_mc", - .id =3D SDX75_MASTER_LLCC, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SDX75_SLAVE_EBI1 }, + .link_nodes =3D { &ebi }, }; =20 static struct qcom_icc_node xm_pcie3_0 =3D { .name =3D "xm_pcie3_0", - .id =3D SDX75_MASTER_PCIE_0, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SDX75_SLAVE_ANOC_PCIE_GEM_NOC }, + .link_nodes =3D { &qns_pcie_gemnoc }, }; =20 static struct qcom_icc_node xm_pcie3_1 =3D { .name =3D "xm_pcie3_1", - .id =3D SDX75_MASTER_PCIE_1, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SDX75_SLAVE_ANOC_PCIE_GEM_NOC }, + .link_nodes =3D { &qns_pcie_gemnoc }, }; =20 static struct qcom_icc_node xm_pcie3_2 =3D { .name =3D "xm_pcie3_2", - .id =3D SDX75_MASTER_PCIE_2, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SDX75_SLAVE_ANOC_PCIE_GEM_NOC }, + .link_nodes =3D { &qns_pcie_gemnoc }, }; =20 static struct qcom_icc_node qhm_audio =3D { .name =3D "qhm_audio", - .id =3D SDX75_MASTER_AUDIO, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SDX75_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes =3D { &qns_gemnoc_sf }, }; =20 static struct qcom_icc_node qhm_gic =3D { .name =3D "qhm_gic", - .id =3D SDX75_MASTER_GIC_AHB, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SDX75_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes =3D { &qns_gemnoc_sf }, }; =20 static struct qcom_icc_node qhm_pcie_rscc =3D { .name =3D "qhm_pcie_rscc", - .id =3D SDX75_MASTER_PCIE_RSCC, .channels =3D 1, .buswidth =3D 4, .num_links =3D 31, - .links =3D { SDX75_SLAVE_ETH0_CFG, SDX75_SLAVE_ETH1_CFG, - SDX75_SLAVE_AUDIO, SDX75_SLAVE_CLK_CTL, - SDX75_SLAVE_CRYPTO_0_CFG, SDX75_SLAVE_IMEM_CFG, - SDX75_SLAVE_IPA_CFG, SDX75_SLAVE_IPC_ROUTER_CFG, - SDX75_SLAVE_CNOC_MSS, SDX75_SLAVE_ICBDI_MVMSS_CFG, - SDX75_SLAVE_PCIE_0_CFG, SDX75_SLAVE_PCIE_1_CFG, - SDX75_SLAVE_PCIE_2_CFG, SDX75_SLAVE_PDM, - SDX75_SLAVE_PRNG, SDX75_SLAVE_QDSS_CFG, - SDX75_SLAVE_QPIC, SDX75_SLAVE_QUP_0, - SDX75_SLAVE_SDCC_1, SDX75_SLAVE_SDCC_4, - SDX75_SLAVE_SPMI_VGI_COEX, SDX75_SLAVE_TCSR, - SDX75_SLAVE_TLMM, SDX75_SLAVE_USB3, - SDX75_SLAVE_USB3_PHY_CFG, SDX75_SLAVE_DDRSS_CFG, - SDX75_SLAVE_SNOC_CFG, SDX75_SLAVE_PCIE_ANOC_CFG, - SDX75_SLAVE_IMEM, SDX75_SLAVE_QDSS_STM, - SDX75_SLAVE_TCU }, + .link_nodes =3D { &ps_eth0_cfg, &ps_eth1_cfg, + &qhs_audio, &qhs_clk_ctl, + &qhs_crypto_cfg, &qhs_imem_cfg, + &qhs_ipa, &qhs_ipc_router, + &qhs_mss_cfg, &qhs_mvmss_cfg, + &qhs_pcie0_cfg, &qhs_pcie1_cfg, + &qhs_pcie2_cfg, &qhs_pdm, + &qhs_prng, &qhs_qdss_cfg, + &qhs_qpic, &qhs_qup0, + &qhs_sdc1, &qhs_sdc4, + &qhs_spmi_vgi_coex, &qhs_tcsr, + &qhs_tlmm, &qhs_usb3, + &qhs_usb3_phy, &qns_ddrss_cfg, + &qns_system_noc_cfg, &qns_system_noc_pcie_cfg, + &qxs_imem, &xs_qdss_stm, + &xs_sys_tcu_cfg }, }; =20 static struct qcom_icc_node qhm_qdss_bam =3D { .name =3D "qhm_qdss_bam", - .id =3D SDX75_MASTER_QDSS_BAM, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SDX75_SLAVE_A1NOC_CFG }, + .link_nodes =3D { &qns_a1noc }, }; =20 static struct qcom_icc_node qhm_qpic =3D { .name =3D "qhm_qpic", - .id =3D SDX75_MASTER_QPIC, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SDX75_SLAVE_A1NOC_CFG }, + .link_nodes =3D { &qns_a1noc }, }; =20 static struct qcom_icc_node qhm_qup0 =3D { .name =3D "qhm_qup0", - .id =3D SDX75_MASTER_QUP_0, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SDX75_SLAVE_A1NOC_CFG }, + .link_nodes =3D { &qns_a1noc }, }; =20 static struct qcom_icc_node qnm_aggre_noc =3D { .name =3D "qnm_aggre_noc", - .id =3D SDX75_MASTER_ANOC_SNOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SDX75_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes =3D { &qns_gemnoc_sf }, }; =20 static struct qcom_icc_node qnm_gemnoc_cnoc =3D { .name =3D "qnm_gemnoc_cnoc", - .id =3D SDX75_MASTER_GEM_NOC_CNOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 32, - .links =3D { SDX75_SLAVE_ETH0_CFG, SDX75_SLAVE_ETH1_CFG, - SDX75_SLAVE_AUDIO, SDX75_SLAVE_CLK_CTL, - SDX75_SLAVE_CRYPTO_0_CFG, SDX75_SLAVE_IMEM_CFG, - SDX75_SLAVE_IPA_CFG, SDX75_SLAVE_IPC_ROUTER_CFG, - SDX75_SLAVE_CNOC_MSS, SDX75_SLAVE_ICBDI_MVMSS_CFG, - SDX75_SLAVE_PCIE_0_CFG, SDX75_SLAVE_PCIE_1_CFG, - SDX75_SLAVE_PCIE_2_CFG, SDX75_SLAVE_PCIE_RSC_CFG, - SDX75_SLAVE_PDM, SDX75_SLAVE_PRNG, - SDX75_SLAVE_QDSS_CFG, SDX75_SLAVE_QPIC, - SDX75_SLAVE_QUP_0, SDX75_SLAVE_SDCC_1, - SDX75_SLAVE_SDCC_4, SDX75_SLAVE_SPMI_VGI_COEX, - SDX75_SLAVE_TCSR, SDX75_SLAVE_TLMM, - SDX75_SLAVE_USB3, SDX75_SLAVE_USB3_PHY_CFG, - SDX75_SLAVE_DDRSS_CFG, SDX75_SLAVE_SNOC_CFG, - SDX75_SLAVE_PCIE_ANOC_CFG, SDX75_SLAVE_IMEM, - SDX75_SLAVE_QDSS_STM, SDX75_SLAVE_TCU }, + .link_nodes =3D { &ps_eth0_cfg, &ps_eth1_cfg, + &qhs_audio, &qhs_clk_ctl, + &qhs_crypto_cfg, &qhs_imem_cfg, + &qhs_ipa, &qhs_ipc_router, + &qhs_mss_cfg, &qhs_mvmss_cfg, + &qhs_pcie0_cfg, &qhs_pcie1_cfg, + &qhs_pcie2_cfg, &qhs_pcie_rscc, + &qhs_pdm, &qhs_prng, + &qhs_qdss_cfg, &qhs_qpic, + &qhs_qup0, &qhs_sdc1, + &qhs_sdc4, &qhs_spmi_vgi_coex, + &qhs_tcsr, &qhs_tlmm, + &qhs_usb3, &qhs_usb3_phy, + &qns_ddrss_cfg, &qns_system_noc_cfg, + &qns_system_noc_pcie_cfg, &qxs_imem, + &xs_qdss_stm, &xs_sys_tcu_cfg }, }; =20 static struct qcom_icc_node qnm_gemnoc_pcie =3D { .name =3D "qnm_gemnoc_pcie", - .id =3D SDX75_MASTER_GEM_NOC_PCIE_SNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 3, - .links =3D { SDX75_SLAVE_PCIE_0, SDX75_SLAVE_PCIE_1, - SDX75_SLAVE_PCIE_2 }, + .link_nodes =3D { &xs_pcie_0, &xs_pcie_1, + &xs_pcie_2 }, }; =20 static struct qcom_icc_node qnm_system_noc_cfg =3D { .name =3D "qnm_system_noc_cfg", - .id =3D SDX75_MASTER_SNOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SDX75_SLAVE_SERVICE_SNOC }, + .link_nodes =3D { &srvc_system_noc }, }; =20 static struct qcom_icc_node qnm_system_noc_pcie_cfg =3D { .name =3D "qnm_system_noc_pcie_cfg", - .id =3D SDX75_MASTER_PCIE_ANOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SDX75_SLAVE_SERVICE_PCIE_ANOC }, + .link_nodes =3D { &srvc_pcie_system_noc }, }; =20 static struct qcom_icc_node qxm_crypto =3D { .name =3D "qxm_crypto", - .id =3D SDX75_MASTER_CRYPTO, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SDX75_SLAVE_A1NOC_CFG }, + .link_nodes =3D { &qns_a1noc }, }; =20 static struct qcom_icc_node qxm_ipa =3D { .name =3D "qxm_ipa", - .id =3D SDX75_MASTER_IPA, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SDX75_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes =3D { &qns_gemnoc_sf }, }; =20 static struct qcom_icc_node qxm_mvmss =3D { .name =3D "qxm_mvmss", - .id =3D SDX75_MASTER_MVMSS, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SDX75_SLAVE_A1NOC_CFG }, + .link_nodes =3D { &qns_a1noc }, }; =20 static struct qcom_icc_node xm_emac_0 =3D { .name =3D "xm_emac_0", - .id =3D SDX75_MASTER_EMAC_0, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SDX75_SLAVE_A1NOC_CFG }, + .link_nodes =3D { &qns_a1noc }, }; =20 static struct qcom_icc_node xm_emac_1 =3D { .name =3D "xm_emac_1", - .id =3D SDX75_MASTER_EMAC_1, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SDX75_SLAVE_A1NOC_CFG }, + .link_nodes =3D { &qns_a1noc }, }; =20 static struct qcom_icc_node xm_qdss_etr0 =3D { .name =3D "xm_qdss_etr0", - .id =3D SDX75_MASTER_QDSS_ETR, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SDX75_SLAVE_A1NOC_CFG }, + .link_nodes =3D { &qns_a1noc }, }; =20 static struct qcom_icc_node xm_qdss_etr1 =3D { .name =3D "xm_qdss_etr1", - .id =3D SDX75_MASTER_QDSS_ETR_1, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SDX75_SLAVE_A1NOC_CFG }, + .link_nodes =3D { &qns_a1noc }, }; =20 static struct qcom_icc_node xm_sdc1 =3D { .name =3D "xm_sdc1", - .id =3D SDX75_MASTER_SDCC_1, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SDX75_SLAVE_A1NOC_CFG }, + .link_nodes =3D { &qns_a1noc }, }; =20 static struct qcom_icc_node xm_sdc4 =3D { .name =3D "xm_sdc4", - .id =3D SDX75_MASTER_SDCC_4, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SDX75_SLAVE_A1NOC_CFG }, + .link_nodes =3D { &qns_a1noc }, }; =20 static struct qcom_icc_node xm_usb3 =3D { .name =3D "xm_usb3", - .id =3D SDX75_MASTER_USB3_0, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SDX75_SLAVE_A1NOC_CFG }, + .link_nodes =3D { &qns_a1noc }, }; =20 static struct qcom_icc_node qpic_core_slave =3D { .name =3D "qpic_core_slave", - .id =3D SDX75_SLAVE_QPIC_CORE, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qup0_core_slave =3D { .name =3D "qup0_core_slave", - .id =3D SDX75_SLAVE_QUP_CORE_0, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_lagg =3D { .name =3D "qhs_lagg", - .id =3D SDX75_SLAVE_LAGG_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_mccc_master =3D { .name =3D "qhs_mccc_master", - .id =3D SDX75_SLAVE_MCCC_MASTER, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qns_gemnoc =3D { .name =3D "qns_gemnoc", - .id =3D SDX75_SLAVE_GEM_NOC_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qss_snoop_bwmon =3D { .name =3D "qss_snoop_bwmon", - .id =3D SDX75_SLAVE_SNOOP_BWMON, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qns_gemnoc_cnoc =3D { .name =3D "qns_gemnoc_cnoc", - .id =3D SDX75_SLAVE_GEM_NOC_CNOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SDX75_MASTER_GEM_NOC_CNOC }, + .link_nodes =3D { &qnm_gemnoc_cnoc }, }; =20 static struct qcom_icc_node qns_llcc =3D { .name =3D "qns_llcc", - .id =3D SDX75_SLAVE_LLCC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SDX75_MASTER_LLCC }, + .link_nodes =3D { &llcc_mc }, }; =20 static struct qcom_icc_node qns_pcie =3D { .name =3D "qns_pcie", - .id =3D SDX75_SLAVE_MEM_NOC_PCIE_SNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SDX75_MASTER_GEM_NOC_PCIE_SNOC }, + .link_nodes =3D { &qnm_gemnoc_pcie }, }; =20 static struct qcom_icc_node srvc_gemnoc =3D { .name =3D "srvc_gemnoc", - .id =3D SDX75_SLAVE_SERVICE_GEM_NOC, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node ebi =3D { .name =3D "ebi", - .id =3D SDX75_SLAVE_EBI1, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qns_pcie_gemnoc =3D { .name =3D "qns_pcie_gemnoc", - .id =3D SDX75_SLAVE_ANOC_PCIE_GEM_NOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SDX75_MASTER_ANOC_PCIE_GEM_NOC }, + .link_nodes =3D { &qnm_pcie }, }; =20 static struct qcom_icc_node ps_eth0_cfg =3D { .name =3D "ps_eth0_cfg", - .id =3D SDX75_SLAVE_ETH0_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node ps_eth1_cfg =3D { .name =3D "ps_eth1_cfg", - .id =3D SDX75_SLAVE_ETH1_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_audio =3D { .name =3D "qhs_audio", - .id =3D SDX75_SLAVE_AUDIO, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_clk_ctl =3D { .name =3D "qhs_clk_ctl", - .id =3D SDX75_SLAVE_CLK_CTL, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_crypto_cfg =3D { .name =3D "qhs_crypto_cfg", - .id =3D SDX75_SLAVE_CRYPTO_0_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_imem_cfg =3D { .name =3D "qhs_imem_cfg", - .id =3D SDX75_SLAVE_IMEM_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_ipa =3D { .name =3D "qhs_ipa", - .id =3D SDX75_SLAVE_IPA_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_ipc_router =3D { .name =3D "qhs_ipc_router", - .id =3D SDX75_SLAVE_IPC_ROUTER_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_mss_cfg =3D { .name =3D "qhs_mss_cfg", - .id =3D SDX75_SLAVE_CNOC_MSS, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_mvmss_cfg =3D { .name =3D "qhs_mvmss_cfg", - .id =3D SDX75_SLAVE_ICBDI_MVMSS_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_pcie0_cfg =3D { .name =3D "qhs_pcie0_cfg", - .id =3D SDX75_SLAVE_PCIE_0_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_pcie1_cfg =3D { .name =3D "qhs_pcie1_cfg", - .id =3D SDX75_SLAVE_PCIE_1_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_pcie2_cfg =3D { .name =3D "qhs_pcie2_cfg", - .id =3D SDX75_SLAVE_PCIE_2_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_pcie_rscc =3D { .name =3D "qhs_pcie_rscc", - .id =3D SDX75_SLAVE_PCIE_RSC_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_pdm =3D { .name =3D "qhs_pdm", - .id =3D SDX75_SLAVE_PDM, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_prng =3D { .name =3D "qhs_prng", - .id =3D SDX75_SLAVE_PRNG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_qdss_cfg =3D { .name =3D "qhs_qdss_cfg", - .id =3D SDX75_SLAVE_QDSS_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_qpic =3D { .name =3D "qhs_qpic", - .id =3D SDX75_SLAVE_QPIC, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_qup0 =3D { .name =3D "qhs_qup0", - .id =3D SDX75_SLAVE_QUP_0, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_sdc1 =3D { .name =3D "qhs_sdc1", - .id =3D SDX75_SLAVE_SDCC_1, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_sdc4 =3D { .name =3D "qhs_sdc4", - .id =3D SDX75_SLAVE_SDCC_4, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_spmi_vgi_coex =3D { .name =3D "qhs_spmi_vgi_coex", - .id =3D SDX75_SLAVE_SPMI_VGI_COEX, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_tcsr =3D { .name =3D "qhs_tcsr", - .id =3D SDX75_SLAVE_TCSR, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_tlmm =3D { .name =3D "qhs_tlmm", - .id =3D SDX75_SLAVE_TLMM, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_usb3 =3D { .name =3D "qhs_usb3", - .id =3D SDX75_SLAVE_USB3, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_usb3_phy =3D { .name =3D "qhs_usb3_phy", - .id =3D SDX75_SLAVE_USB3_PHY_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qns_a1noc =3D { .name =3D "qns_a1noc", - .id =3D SDX75_SLAVE_A1NOC_CFG, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SDX75_MASTER_ANOC_SNOC }, + .link_nodes =3D { &qnm_aggre_noc }, }; =20 static struct qcom_icc_node qns_ddrss_cfg =3D { .name =3D "qns_ddrss_cfg", - .id =3D SDX75_SLAVE_DDRSS_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SDX75_MASTER_CNOC_DC_NOC }, + .link_nodes =3D { &qnm_cnoc }, }; =20 static struct qcom_icc_node qns_gemnoc_sf =3D { .name =3D "qns_gemnoc_sf", - .id =3D SDX75_SLAVE_SNOC_GEM_NOC_SF, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SDX75_MASTER_SNOC_SF_MEM_NOC }, + .link_nodes =3D { &qnm_snoc_sf }, }; =20 static struct qcom_icc_node qns_system_noc_cfg =3D { .name =3D "qns_system_noc_cfg", - .id =3D SDX75_SLAVE_SNOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SDX75_MASTER_SNOC_CFG }, + .link_nodes =3D { &qnm_system_noc_cfg }, }; =20 static struct qcom_icc_node qns_system_noc_pcie_cfg =3D { .name =3D "qns_system_noc_pcie_cfg", - .id =3D SDX75_SLAVE_PCIE_ANOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SDX75_MASTER_PCIE_ANOC_CFG }, + .link_nodes =3D { &qnm_system_noc_pcie_cfg }, }; =20 static struct qcom_icc_node qxs_imem =3D { .name =3D "qxs_imem", - .id =3D SDX75_SLAVE_IMEM, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 0, }; =20 static struct qcom_icc_node srvc_pcie_system_noc =3D { .name =3D "srvc_pcie_system_noc", - .id =3D SDX75_SLAVE_SERVICE_PCIE_ANOC, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node srvc_system_noc =3D { .name =3D "srvc_system_noc", - .id =3D SDX75_SLAVE_SERVICE_SNOC, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node xs_pcie_0 =3D { .name =3D "xs_pcie_0", - .id =3D SDX75_SLAVE_PCIE_0, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 0, }; =20 static struct qcom_icc_node xs_pcie_1 =3D { .name =3D "xs_pcie_1", - .id =3D SDX75_SLAVE_PCIE_1, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 0, }; =20 static struct qcom_icc_node xs_pcie_2 =3D { .name =3D "xs_pcie_2", - .id =3D SDX75_SLAVE_PCIE_2, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 0, }; =20 static struct qcom_icc_node xs_qdss_stm =3D { .name =3D "xs_qdss_stm", - .id =3D SDX75_SLAVE_QDSS_STM, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node xs_sys_tcu_cfg =3D { .name =3D "xs_sys_tcu_cfg", - .id =3D SDX75_SLAVE_TCU, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 0, }; =20 static struct qcom_icc_bcm bcm_ce0 =3D { @@ -910,6 +868,7 @@ static struct qcom_icc_node * const clk_virt_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sdx75_clk_virt =3D { + .alloc_dyn_id =3D true, .nodes =3D clk_virt_nodes, .num_nodes =3D ARRAY_SIZE(clk_virt_nodes), .bcms =3D clk_virt_bcms, @@ -925,6 +884,7 @@ static struct qcom_icc_node * const dc_noc_nodes[] =3D { }; =20 static const struct qcom_icc_desc sdx75_dc_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D dc_noc_nodes, .num_nodes =3D ARRAY_SIZE(dc_noc_nodes), }; @@ -951,6 +911,7 @@ static struct qcom_icc_node * const gem_noc_nodes[] =3D= { }; =20 static const struct qcom_icc_desc sdx75_gem_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D gem_noc_nodes, .num_nodes =3D ARRAY_SIZE(gem_noc_nodes), .bcms =3D gem_noc_bcms, @@ -967,6 +928,7 @@ static struct qcom_icc_node * const mc_virt_nodes[] =3D= { }; =20 static const struct qcom_icc_desc sdx75_mc_virt =3D { + .alloc_dyn_id =3D true, .nodes =3D mc_virt_nodes, .num_nodes =3D ARRAY_SIZE(mc_virt_nodes), .bcms =3D mc_virt_bcms, @@ -986,6 +948,7 @@ static struct qcom_icc_node * const pcie_anoc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sdx75_pcie_anoc =3D { + .alloc_dyn_id =3D true, .nodes =3D pcie_anoc_nodes, .num_nodes =3D ARRAY_SIZE(pcie_anoc_nodes), .bcms =3D pcie_anoc_bcms, @@ -1064,6 +1027,7 @@ static struct qcom_icc_node * const system_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sdx75_system_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D system_noc_nodes, .num_nodes =3D ARRAY_SIZE(system_noc_nodes), .bcms =3D system_noc_bcms, diff --git a/drivers/interconnect/qcom/sdx75.h b/drivers/interconnect/qcom/= sdx75.h deleted file mode 100644 index 24e88715992010d934a1a630979f864af3a8426c..000000000000000000000000000= 0000000000000 --- a/drivers/interconnect/qcom/sdx75.h +++ /dev/null @@ -1,97 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserve= d. - */ - -#ifndef __DRIVERS_INTERCONNECT_QCOM_SDX75_H -#define __DRIVERS_INTERCONNECT_QCOM_SDX75_H - -#define SDX75_MASTER_ANOC_PCIE_GEM_NOC 0 -#define SDX75_MASTER_ANOC_SNOC 1 -#define SDX75_MASTER_APPSS_PROC 2 -#define SDX75_MASTER_AUDIO 3 -#define SDX75_MASTER_CNOC_DC_NOC 4 -#define SDX75_MASTER_CRYPTO 5 -#define SDX75_MASTER_EMAC_0 6 -#define SDX75_MASTER_EMAC_1 7 -#define SDX75_MASTER_GEM_NOC_CFG 8 -#define SDX75_MASTER_GEM_NOC_CNOC 9 -#define SDX75_MASTER_GEM_NOC_PCIE_SNOC 10 -#define SDX75_MASTER_GIC 11 -#define SDX75_MASTER_GIC_AHB 12 -#define SDX75_MASTER_IPA 13 -#define SDX75_MASTER_IPA_PCIE 14 -#define SDX75_MASTER_LLCC 15 -#define SDX75_MASTER_MSS_PROC 16 -#define SDX75_MASTER_MVMSS 17 -#define SDX75_MASTER_PCIE_0 18 -#define SDX75_MASTER_PCIE_1 19 -#define SDX75_MASTER_PCIE_2 20 -#define SDX75_MASTER_PCIE_ANOC_CFG 21 -#define SDX75_MASTER_PCIE_RSCC 22 -#define SDX75_MASTER_QDSS_BAM 23 -#define SDX75_MASTER_QDSS_ETR 24 -#define SDX75_MASTER_QDSS_ETR_1 25 -#define SDX75_MASTER_QPIC 26 -#define SDX75_MASTER_QPIC_CORE 27 -#define SDX75_MASTER_QUP_0 28 -#define SDX75_MASTER_QUP_CORE_0 29 -#define SDX75_MASTER_SDCC_1 30 -#define SDX75_MASTER_SDCC_4 31 -#define SDX75_MASTER_SNOC_CFG 32 -#define SDX75_MASTER_SNOC_SF_MEM_NOC 33 -#define SDX75_MASTER_SYS_TCU 34 -#define SDX75_MASTER_USB3_0 35 -#define SDX75_SLAVE_A1NOC_CFG 36 -#define SDX75_SLAVE_ANOC_PCIE_GEM_NOC 37 -#define SDX75_SLAVE_AUDIO 38 -#define SDX75_SLAVE_CLK_CTL 39 -#define SDX75_SLAVE_CRYPTO_0_CFG 40 -#define SDX75_SLAVE_CNOC_MSS 41 -#define SDX75_SLAVE_DDRSS_CFG 42 -#define SDX75_SLAVE_EBI1 43 -#define SDX75_SLAVE_ETH0_CFG 44 -#define SDX75_SLAVE_ETH1_CFG 45 -#define SDX75_SLAVE_GEM_NOC_CFG 46 -#define SDX75_SLAVE_GEM_NOC_CNOC 47 -#define SDX75_SLAVE_ICBDI_MVMSS_CFG 48 -#define SDX75_SLAVE_IMEM 49 -#define SDX75_SLAVE_IMEM_CFG 50 -#define SDX75_SLAVE_IPA_CFG 51 -#define SDX75_SLAVE_IPC_ROUTER_CFG 52 -#define SDX75_SLAVE_LAGG_CFG 53 -#define SDX75_SLAVE_LLCC 54 -#define SDX75_SLAVE_MCCC_MASTER 55 -#define SDX75_SLAVE_MEM_NOC_PCIE_SNOC 56 -#define SDX75_SLAVE_PCIE_0 57 -#define SDX75_SLAVE_PCIE_1 58 -#define SDX75_SLAVE_PCIE_2 59 -#define SDX75_SLAVE_PCIE_0_CFG 60 -#define SDX75_SLAVE_PCIE_1_CFG 61 -#define SDX75_SLAVE_PCIE_2_CFG 62 -#define SDX75_SLAVE_PCIE_ANOC_CFG 63 -#define SDX75_SLAVE_PCIE_RSC_CFG 64 -#define SDX75_SLAVE_PDM 65 -#define SDX75_SLAVE_PRNG 66 -#define SDX75_SLAVE_QDSS_CFG 67 -#define SDX75_SLAVE_QDSS_STM 68 -#define SDX75_SLAVE_QPIC 69 -#define SDX75_SLAVE_QPIC_CORE 70 -#define SDX75_SLAVE_QUP_0 71 -#define SDX75_SLAVE_QUP_CORE_0 72 -#define SDX75_SLAVE_SDCC_1 73 -#define SDX75_SLAVE_SDCC_4 74 -#define SDX75_SLAVE_SERVICE_GEM_NOC 75 -#define SDX75_SLAVE_SERVICE_PCIE_ANOC 76 -#define SDX75_SLAVE_SERVICE_SNOC 77 -#define SDX75_SLAVE_SNOC_CFG 78 -#define SDX75_SLAVE_SNOC_GEM_NOC_SF 79 -#define SDX75_SLAVE_SNOOP_BWMON 80 -#define SDX75_SLAVE_SPMI_VGI_COEX 81 -#define SDX75_SLAVE_TCSR 82 -#define SDX75_SLAVE_TCU 83 -#define SDX75_SLAVE_TLMM 84 -#define SDX75_SLAVE_USB3 85 -#define SDX75_SLAVE_USB3_PHY_CFG 86 - -#endif --=20 2.47.3