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This gives more flexibility and also allows us to drop the .num_links member, saving from possible errors related to it being not set or set incorrectly. Signed-off-by: Dmitry Baryshkov --- drivers/interconnect/qcom/sar2130p.c | 639 +++++++++++++------------------= ---- 1 file changed, 238 insertions(+), 401 deletions(-) diff --git a/drivers/interconnect/qcom/sar2130p.c b/drivers/interconnect/qc= om/sar2130p.c index 9eac0ac7681273d6f4350f4431b81ce94dbada3f..a0b04929058f7e92a60e441b2cc= 82ee8984daf41 100644 --- a/drivers/interconnect/qcom/sar2130p.c +++ b/drivers/interconnect/qcom/sar2130p.c @@ -20,125 +20,123 @@ #include "icc-common.h" #include "icc-rpmh.h" =20 -enum { - SAR2130P_MASTER_QUP_CORE_0, - SAR2130P_MASTER_QUP_CORE_1, - SAR2130P_MASTER_GEM_NOC_CNOC, - SAR2130P_MASTER_GEM_NOC_PCIE_SNOC, - SAR2130P_MASTER_QDSS_DAP, - SAR2130P_MASTER_GPU_TCU, - SAR2130P_MASTER_SYS_TCU, - SAR2130P_MASTER_APPSS_PROC, - SAR2130P_MASTER_GFX3D, - SAR2130P_MASTER_MNOC_HF_MEM_NOC, - SAR2130P_MASTER_MNOC_SF_MEM_NOC, - SAR2130P_MASTER_COMPUTE_NOC, - SAR2130P_MASTER_ANOC_PCIE_GEM_NOC, - SAR2130P_MASTER_SNOC_GC_MEM_NOC, - SAR2130P_MASTER_SNOC_SF_MEM_NOC, - SAR2130P_MASTER_WLAN_Q6, - SAR2130P_MASTER_CNOC_LPASS_AG_NOC, - SAR2130P_MASTER_LPASS_PROC, - SAR2130P_MASTER_LLCC, - SAR2130P_MASTER_CAMNOC_HF, - SAR2130P_MASTER_CAMNOC_ICP, - SAR2130P_MASTER_CAMNOC_SF, - SAR2130P_MASTER_LSR, - SAR2130P_MASTER_MDP, - SAR2130P_MASTER_CNOC_MNOC_CFG, - SAR2130P_MASTER_VIDEO, - SAR2130P_MASTER_VIDEO_CV_PROC, - SAR2130P_MASTER_VIDEO_PROC, - SAR2130P_MASTER_VIDEO_V_PROC, - SAR2130P_MASTER_CDSP_NOC_CFG, - SAR2130P_MASTER_CDSP_PROC, - SAR2130P_MASTER_PCIE_0, - SAR2130P_MASTER_PCIE_1, - SAR2130P_MASTER_GIC_AHB, - SAR2130P_MASTER_QDSS_BAM, - SAR2130P_MASTER_QSPI_0, - SAR2130P_MASTER_QUP_0, - SAR2130P_MASTER_QUP_1, - SAR2130P_MASTER_A2NOC_SNOC, - SAR2130P_MASTER_CNOC_DATAPATH, - SAR2130P_MASTER_LPASS_ANOC, - SAR2130P_MASTER_SNOC_CFG, - SAR2130P_MASTER_CRYPTO, - SAR2130P_MASTER_PIMEM, - SAR2130P_MASTER_GIC, - SAR2130P_MASTER_QDSS_ETR, - SAR2130P_MASTER_QDSS_ETR_1, - SAR2130P_MASTER_SDCC_1, - SAR2130P_MASTER_USB3_0, - SAR2130P_SLAVE_QUP_CORE_0, - SAR2130P_SLAVE_QUP_CORE_1, - SAR2130P_SLAVE_AHB2PHY_SOUTH, - SAR2130P_SLAVE_AOSS, - SAR2130P_SLAVE_CAMERA_CFG, - SAR2130P_SLAVE_CLK_CTL, - SAR2130P_SLAVE_CDSP_CFG, - SAR2130P_SLAVE_RBCPR_CX_CFG, - SAR2130P_SLAVE_RBCPR_MMCX_CFG, - SAR2130P_SLAVE_RBCPR_MXA_CFG, - SAR2130P_SLAVE_RBCPR_MXC_CFG, - SAR2130P_SLAVE_CPR_NSPCX, - SAR2130P_SLAVE_CRYPTO_0_CFG, - SAR2130P_SLAVE_CX_RDPM, - SAR2130P_SLAVE_DISPLAY_CFG, - SAR2130P_SLAVE_GFX3D_CFG, - SAR2130P_SLAVE_IMEM_CFG, - SAR2130P_SLAVE_IPC_ROUTER_CFG, - SAR2130P_SLAVE_LPASS, - SAR2130P_SLAVE_MX_RDPM, - SAR2130P_SLAVE_PCIE_0_CFG, - SAR2130P_SLAVE_PCIE_1_CFG, - SAR2130P_SLAVE_PDM, - SAR2130P_SLAVE_PIMEM_CFG, - SAR2130P_SLAVE_PRNG, - SAR2130P_SLAVE_QDSS_CFG, - SAR2130P_SLAVE_QSPI_0, - SAR2130P_SLAVE_QUP_0, - SAR2130P_SLAVE_QUP_1, - SAR2130P_SLAVE_SDCC_1, - SAR2130P_SLAVE_TCSR, - SAR2130P_SLAVE_TLMM, - SAR2130P_SLAVE_TME_CFG, - SAR2130P_SLAVE_USB3_0, - SAR2130P_SLAVE_VENUS_CFG, - SAR2130P_SLAVE_VSENSE_CTRL_CFG, - SAR2130P_SLAVE_WLAN_Q6_CFG, - SAR2130P_SLAVE_DDRSS_CFG, - SAR2130P_SLAVE_CNOC_MNOC_CFG, - SAR2130P_SLAVE_SNOC_CFG, - SAR2130P_SLAVE_IMEM, - SAR2130P_SLAVE_PIMEM, - SAR2130P_SLAVE_SERVICE_CNOC, - SAR2130P_SLAVE_PCIE_0, - SAR2130P_SLAVE_PCIE_1, - SAR2130P_SLAVE_QDSS_STM, - SAR2130P_SLAVE_TCU, - SAR2130P_SLAVE_GEM_NOC_CNOC, - SAR2130P_SLAVE_LLCC, - SAR2130P_SLAVE_MEM_NOC_PCIE_SNOC, - SAR2130P_SLAVE_LPASS_CORE_CFG, - SAR2130P_SLAVE_LPASS_LPI_CFG, - SAR2130P_SLAVE_LPASS_MPU_CFG, - SAR2130P_SLAVE_LPASS_TOP_CFG, - SAR2130P_SLAVE_LPASS_SNOC, - SAR2130P_SLAVE_SERVICES_LPASS_AML_NOC, - SAR2130P_SLAVE_SERVICE_LPASS_AG_NOC, - SAR2130P_SLAVE_EBI1, - SAR2130P_SLAVE_MNOC_HF_MEM_NOC, - SAR2130P_SLAVE_MNOC_SF_MEM_NOC, - SAR2130P_SLAVE_SERVICE_MNOC, - SAR2130P_SLAVE_CDSP_MEM_NOC, - SAR2130P_SLAVE_SERVICE_NSP_NOC, - SAR2130P_SLAVE_ANOC_PCIE_GEM_NOC, - SAR2130P_SLAVE_A2NOC_SNOC, - SAR2130P_SLAVE_SNOC_GEM_NOC_GC, - SAR2130P_SLAVE_SNOC_GEM_NOC_SF, - SAR2130P_SLAVE_SERVICE_SNOC, -}; +static struct qcom_icc_node qup0_core_master; +static struct qcom_icc_node qup1_core_master; +static struct qcom_icc_node qnm_gemnoc_cnoc; +static struct qcom_icc_node qnm_gemnoc_pcie; +static struct qcom_icc_node xm_qdss_dap; +static struct qcom_icc_node alm_gpu_tcu; +static struct qcom_icc_node alm_sys_tcu; +static struct qcom_icc_node chm_apps; +static struct qcom_icc_node qnm_gpu; +static struct qcom_icc_node qnm_mnoc_hf; +static struct qcom_icc_node qnm_mnoc_sf; +static struct qcom_icc_node qnm_nsp_gemnoc; +static struct qcom_icc_node qnm_pcie; +static struct qcom_icc_node qnm_snoc_gc; +static struct qcom_icc_node qnm_snoc_sf; +static struct qcom_icc_node qxm_wlan_q6; +static struct qcom_icc_node qhm_config_noc; +static struct qcom_icc_node qxm_lpass_dsp; +static struct qcom_icc_node llcc_mc; +static struct qcom_icc_node qnm_camnoc_hf; +static struct qcom_icc_node qnm_camnoc_icp; +static struct qcom_icc_node qnm_camnoc_sf; +static struct qcom_icc_node qnm_lsr; +static struct qcom_icc_node qnm_mdp; +static struct qcom_icc_node qnm_mnoc_cfg; +static struct qcom_icc_node qnm_video; +static struct qcom_icc_node qnm_video_cv_cpu; +static struct qcom_icc_node qnm_video_cvp; +static struct qcom_icc_node qnm_video_v_cpu; +static struct qcom_icc_node qhm_nsp_noc_config; +static struct qcom_icc_node qxm_nsp; +static struct qcom_icc_node xm_pcie3_0; +static struct qcom_icc_node xm_pcie3_1; +static struct qcom_icc_node qhm_gic; +static struct qcom_icc_node qhm_qdss_bam; +static struct qcom_icc_node qhm_qspi; +static struct qcom_icc_node qhm_qup0; +static struct qcom_icc_node qhm_qup1; +static struct qcom_icc_node qnm_aggre2_noc; +static struct qcom_icc_node qnm_cnoc_datapath; +static struct qcom_icc_node qnm_lpass_noc; +static struct qcom_icc_node qnm_snoc_cfg; +static struct qcom_icc_node qxm_crypto; +static struct qcom_icc_node qxm_pimem; +static struct qcom_icc_node xm_gic; +static struct qcom_icc_node xm_qdss_etr_0; +static struct qcom_icc_node xm_qdss_etr_1; +static struct qcom_icc_node xm_sdc1; +static struct qcom_icc_node xm_usb3_0; +static struct qcom_icc_node qup0_core_slave; +static struct qcom_icc_node qup1_core_slave; +static struct qcom_icc_node qhs_ahb2phy0; +static struct qcom_icc_node qhs_aoss; +static struct qcom_icc_node qhs_camera_cfg; +static struct qcom_icc_node qhs_clk_ctl; +static struct qcom_icc_node qhs_compute_cfg; +static struct qcom_icc_node qhs_cpr_cx; +static struct qcom_icc_node qhs_cpr_mmcx; +static struct qcom_icc_node qhs_cpr_mxa; +static struct qcom_icc_node qhs_cpr_mxc; +static struct qcom_icc_node qhs_cpr_nspcx; +static struct qcom_icc_node qhs_crypto0_cfg; +static struct qcom_icc_node qhs_cx_rdpm; +static struct qcom_icc_node qhs_display_cfg; +static struct qcom_icc_node qhs_gpuss_cfg; +static struct qcom_icc_node qhs_imem_cfg; +static struct qcom_icc_node qhs_ipc_router; +static struct qcom_icc_node qhs_lpass_cfg; +static struct qcom_icc_node qhs_mx_rdpm; +static struct qcom_icc_node qhs_pcie0_cfg; +static struct qcom_icc_node qhs_pcie1_cfg; +static struct qcom_icc_node qhs_pdm; +static struct qcom_icc_node qhs_pimem_cfg; +static struct qcom_icc_node qhs_prng; +static struct qcom_icc_node qhs_qdss_cfg; +static struct qcom_icc_node qhs_qspi; +static struct qcom_icc_node qhs_qup0; +static struct qcom_icc_node qhs_qup1; +static struct qcom_icc_node qhs_sdc1; +static struct qcom_icc_node qhs_tcsr; +static struct qcom_icc_node qhs_tlmm; +static struct qcom_icc_node qhs_tme_cfg; +static struct qcom_icc_node qhs_usb3_0; +static struct qcom_icc_node qhs_venus_cfg; +static struct qcom_icc_node qhs_vsense_ctrl_cfg; +static struct qcom_icc_node qhs_wlan_q6; +static struct qcom_icc_node qns_ddrss_cfg; +static struct qcom_icc_node qns_mnoc_cfg; +static struct qcom_icc_node qns_snoc_cfg; +static struct qcom_icc_node qxs_imem; +static struct qcom_icc_node qxs_pimem; +static struct qcom_icc_node srvc_cnoc; +static struct qcom_icc_node xs_pcie_0; +static struct qcom_icc_node xs_pcie_1; +static struct qcom_icc_node xs_qdss_stm; +static struct qcom_icc_node xs_sys_tcu_cfg; +static struct qcom_icc_node qns_gem_noc_cnoc; +static struct qcom_icc_node qns_llcc; +static struct qcom_icc_node qns_pcie; +static struct qcom_icc_node qhs_lpass_core; +static struct qcom_icc_node qhs_lpass_lpi; +static struct qcom_icc_node qhs_lpass_mpu; +static struct qcom_icc_node qhs_lpass_top; +static struct qcom_icc_node qns_sysnoc; +static struct qcom_icc_node srvc_niu_aml_noc; +static struct qcom_icc_node srvc_niu_lpass_agnoc; +static struct qcom_icc_node ebi; +static struct qcom_icc_node qns_mem_noc_hf; +static struct qcom_icc_node qns_mem_noc_sf; +static struct qcom_icc_node srvc_mnoc; +static struct qcom_icc_node qns_nsp_gemnoc; +static struct qcom_icc_node service_nsp_noc; +static struct qcom_icc_node qns_pcie_mem_noc; +static struct qcom_icc_node qns_a2noc_snoc; +static struct qcom_icc_node qns_gemnoc_gc; +static struct qcom_icc_node qns_gemnoc_sf; +static struct qcom_icc_node srvc_snoc; =20 static const struct regmap_config icc_regmap_config =3D { .reg_bits =3D 32, @@ -149,89 +147,84 @@ static const struct regmap_config icc_regmap_config = =3D { =20 static struct qcom_icc_node qup0_core_master =3D { .name =3D "qup0_core_master", - .id =3D SAR2130P_MASTER_QUP_CORE_0, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SAR2130P_SLAVE_QUP_CORE_0 }, + .link_nodes =3D { &qup0_core_slave }, }; =20 static struct qcom_icc_node qup1_core_master =3D { .name =3D "qup1_core_master", - .id =3D SAR2130P_MASTER_QUP_CORE_1, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SAR2130P_SLAVE_QUP_CORE_1 }, + .link_nodes =3D { &qup1_core_slave }, }; =20 static struct qcom_icc_node qnm_gemnoc_cnoc =3D { .name =3D "qnm_gemnoc_cnoc", - .id =3D SAR2130P_MASTER_GEM_NOC_CNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 43, - .links =3D { SAR2130P_SLAVE_AHB2PHY_SOUTH, SAR2130P_SLAVE_AOSS, - SAR2130P_SLAVE_CAMERA_CFG, SAR2130P_SLAVE_CLK_CTL, - SAR2130P_SLAVE_CDSP_CFG, SAR2130P_SLAVE_RBCPR_CX_CFG, - SAR2130P_SLAVE_RBCPR_MMCX_CFG, SAR2130P_SLAVE_RBCPR_MXA_CFG, - SAR2130P_SLAVE_RBCPR_MXC_CFG, SAR2130P_SLAVE_CPR_NSPCX, - SAR2130P_SLAVE_CRYPTO_0_CFG, SAR2130P_SLAVE_CX_RDPM, - SAR2130P_SLAVE_DISPLAY_CFG, SAR2130P_SLAVE_GFX3D_CFG, - SAR2130P_SLAVE_IMEM_CFG, SAR2130P_SLAVE_IPC_ROUTER_CFG, - SAR2130P_SLAVE_LPASS, SAR2130P_SLAVE_MX_RDPM, - SAR2130P_SLAVE_PCIE_0_CFG, SAR2130P_SLAVE_PCIE_1_CFG, - SAR2130P_SLAVE_PDM, SAR2130P_SLAVE_PIMEM_CFG, - SAR2130P_SLAVE_PRNG, SAR2130P_SLAVE_QDSS_CFG, - SAR2130P_SLAVE_QSPI_0, SAR2130P_SLAVE_QUP_0, - SAR2130P_SLAVE_QUP_1, SAR2130P_SLAVE_SDCC_1, - SAR2130P_SLAVE_TCSR, SAR2130P_SLAVE_TLMM, - SAR2130P_SLAVE_TME_CFG, SAR2130P_SLAVE_USB3_0, - SAR2130P_SLAVE_VENUS_CFG, SAR2130P_SLAVE_VSENSE_CTRL_CFG, - SAR2130P_SLAVE_WLAN_Q6_CFG, SAR2130P_SLAVE_DDRSS_CFG, - SAR2130P_SLAVE_CNOC_MNOC_CFG, SAR2130P_SLAVE_SNOC_CFG, - SAR2130P_SLAVE_IMEM, SAR2130P_SLAVE_PIMEM, - SAR2130P_SLAVE_SERVICE_CNOC, SAR2130P_SLAVE_QDSS_STM, - SAR2130P_SLAVE_TCU }, + .link_nodes =3D { &qhs_ahb2phy0, &qhs_aoss, + &qhs_camera_cfg, &qhs_clk_ctl, + &qhs_compute_cfg, &qhs_cpr_cx, + &qhs_cpr_mmcx, &qhs_cpr_mxa, + &qhs_cpr_mxc, &qhs_cpr_nspcx, + &qhs_crypto0_cfg, &qhs_cx_rdpm, + &qhs_display_cfg, &qhs_gpuss_cfg, + &qhs_imem_cfg, &qhs_ipc_router, + &qhs_lpass_cfg, &qhs_mx_rdpm, + &qhs_pcie0_cfg, &qhs_pcie1_cfg, + &qhs_pdm, &qhs_pimem_cfg, + &qhs_prng, &qhs_qdss_cfg, + &qhs_qspi, &qhs_qup0, + &qhs_qup1, &qhs_sdc1, + &qhs_tcsr, &qhs_tlmm, + &qhs_tme_cfg, &qhs_usb3_0, + &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, + &qhs_wlan_q6, &qns_ddrss_cfg, + &qns_mnoc_cfg, &qns_snoc_cfg, + &qxs_imem, &qxs_pimem, + &srvc_cnoc, &xs_qdss_stm, + &xs_sys_tcu_cfg }, }; =20 static struct qcom_icc_node qnm_gemnoc_pcie =3D { .name =3D "qnm_gemnoc_pcie", - .id =3D SAR2130P_MASTER_GEM_NOC_PCIE_SNOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 2, - .links =3D { SAR2130P_SLAVE_PCIE_0, SAR2130P_SLAVE_PCIE_1 }, + .link_nodes =3D { &xs_pcie_0, &xs_pcie_1 }, }; =20 static struct qcom_icc_node xm_qdss_dap =3D { .name =3D "xm_qdss_dap", - .id =3D SAR2130P_MASTER_QDSS_DAP, .channels =3D 1, .buswidth =3D 8, .num_links =3D 43, - .links =3D { SAR2130P_SLAVE_AHB2PHY_SOUTH, SAR2130P_SLAVE_AOSS, - SAR2130P_SLAVE_CAMERA_CFG, SAR2130P_SLAVE_CLK_CTL, - SAR2130P_SLAVE_CDSP_CFG, SAR2130P_SLAVE_RBCPR_CX_CFG, - SAR2130P_SLAVE_RBCPR_MMCX_CFG, SAR2130P_SLAVE_RBCPR_MXA_CFG, - SAR2130P_SLAVE_RBCPR_MXC_CFG, SAR2130P_SLAVE_CPR_NSPCX, - SAR2130P_SLAVE_CRYPTO_0_CFG, SAR2130P_SLAVE_CX_RDPM, - SAR2130P_SLAVE_DISPLAY_CFG, SAR2130P_SLAVE_GFX3D_CFG, - SAR2130P_SLAVE_IMEM_CFG, SAR2130P_SLAVE_IPC_ROUTER_CFG, - SAR2130P_SLAVE_LPASS, SAR2130P_SLAVE_MX_RDPM, - SAR2130P_SLAVE_PCIE_0_CFG, SAR2130P_SLAVE_PCIE_1_CFG, - SAR2130P_SLAVE_PDM, SAR2130P_SLAVE_PIMEM_CFG, - SAR2130P_SLAVE_PRNG, SAR2130P_SLAVE_QDSS_CFG, - SAR2130P_SLAVE_QSPI_0, SAR2130P_SLAVE_QUP_0, - SAR2130P_SLAVE_QUP_1, SAR2130P_SLAVE_SDCC_1, - SAR2130P_SLAVE_TCSR, SAR2130P_SLAVE_TLMM, - SAR2130P_SLAVE_TME_CFG, SAR2130P_SLAVE_USB3_0, - SAR2130P_SLAVE_VENUS_CFG, SAR2130P_SLAVE_VSENSE_CTRL_CFG, - SAR2130P_SLAVE_WLAN_Q6_CFG, SAR2130P_SLAVE_DDRSS_CFG, - SAR2130P_SLAVE_CNOC_MNOC_CFG, SAR2130P_SLAVE_SNOC_CFG, - SAR2130P_SLAVE_IMEM, SAR2130P_SLAVE_PIMEM, - SAR2130P_SLAVE_SERVICE_CNOC, SAR2130P_SLAVE_QDSS_STM, - SAR2130P_SLAVE_TCU }, + .link_nodes =3D { &qhs_ahb2phy0, &qhs_aoss, + &qhs_camera_cfg, &qhs_clk_ctl, + &qhs_compute_cfg, &qhs_cpr_cx, + &qhs_cpr_mmcx, &qhs_cpr_mxa, + &qhs_cpr_mxc, &qhs_cpr_nspcx, + &qhs_crypto0_cfg, &qhs_cx_rdpm, + &qhs_display_cfg, &qhs_gpuss_cfg, + &qhs_imem_cfg, &qhs_ipc_router, + &qhs_lpass_cfg, &qhs_mx_rdpm, + &qhs_pcie0_cfg, &qhs_pcie1_cfg, + &qhs_pdm, &qhs_pimem_cfg, + &qhs_prng, &qhs_qdss_cfg, + &qhs_qspi, &qhs_qup0, + &qhs_qup1, &qhs_sdc1, + &qhs_tcsr, &qhs_tlmm, + &qhs_tme_cfg, &qhs_usb3_0, + &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, + &qhs_wlan_q6, &qns_ddrss_cfg, + &qns_mnoc_cfg, &qns_snoc_cfg, + &qxs_imem, &qxs_pimem, + &srvc_cnoc, &xs_qdss_stm, + &xs_sys_tcu_cfg }, }; =20 static const struct qcom_icc_qosbox alm_gpu_tcu_qos =3D { @@ -244,12 +237,11 @@ static const struct qcom_icc_qosbox alm_gpu_tcu_qos = =3D { =20 static struct qcom_icc_node alm_gpu_tcu =3D { .name =3D "alm_gpu_tcu", - .id =3D SAR2130P_MASTER_GPU_TCU, .channels =3D 1, .buswidth =3D 8, .qosbox =3D &alm_gpu_tcu_qos, .num_links =3D 2, - .links =3D { SAR2130P_SLAVE_GEM_NOC_CNOC, SAR2130P_SLAVE_LLCC }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; =20 static const struct qcom_icc_qosbox alm_sys_tcu_qos =3D { @@ -262,22 +254,20 @@ static const struct qcom_icc_qosbox alm_sys_tcu_qos = =3D { =20 static struct qcom_icc_node alm_sys_tcu =3D { .name =3D "alm_sys_tcu", - .id =3D SAR2130P_MASTER_SYS_TCU, .channels =3D 1, .buswidth =3D 8, .qosbox =3D &alm_sys_tcu_qos, .num_links =3D 2, - .links =3D { SAR2130P_SLAVE_GEM_NOC_CNOC, SAR2130P_SLAVE_LLCC }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; =20 static struct qcom_icc_node chm_apps =3D { .name =3D "chm_apps", - .id =3D SAR2130P_MASTER_APPSS_PROC, .channels =3D 1, .buswidth =3D 32, .num_links =3D 3, - .links =3D { SAR2130P_SLAVE_GEM_NOC_CNOC, SAR2130P_SLAVE_LLCC, - SAR2130P_SLAVE_MEM_NOC_PCIE_SNOC }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, }; =20 static const struct qcom_icc_qosbox qnm_gpu_qos =3D { @@ -290,12 +280,11 @@ static const struct qcom_icc_qosbox qnm_gpu_qos =3D { =20 static struct qcom_icc_node qnm_gpu =3D { .name =3D "qnm_gpu", - .id =3D SAR2130P_MASTER_GFX3D, .channels =3D 2, .buswidth =3D 32, .qosbox =3D &qnm_gpu_qos, .num_links =3D 2, - .links =3D { SAR2130P_SLAVE_GEM_NOC_CNOC, SAR2130P_SLAVE_LLCC }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; =20 static const struct qcom_icc_qosbox qnm_mnoc_hf_qos =3D { @@ -307,12 +296,11 @@ static const struct qcom_icc_qosbox qnm_mnoc_hf_qos = =3D { =20 static struct qcom_icc_node qnm_mnoc_hf =3D { .name =3D "qnm_mnoc_hf", - .id =3D SAR2130P_MASTER_MNOC_HF_MEM_NOC, .channels =3D 2, .buswidth =3D 32, .qosbox =3D &qnm_mnoc_hf_qos, .num_links =3D 2, - .links =3D { SAR2130P_SLAVE_GEM_NOC_CNOC, SAR2130P_SLAVE_LLCC }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; =20 static const struct qcom_icc_qosbox qnm_mnoc_sf_qos =3D { @@ -324,12 +312,11 @@ static const struct qcom_icc_qosbox qnm_mnoc_sf_qos = =3D { =20 static struct qcom_icc_node qnm_mnoc_sf =3D { .name =3D "qnm_mnoc_sf", - .id =3D SAR2130P_MASTER_MNOC_SF_MEM_NOC, .channels =3D 1, .buswidth =3D 32, .qosbox =3D &qnm_mnoc_sf_qos, .num_links =3D 2, - .links =3D { SAR2130P_SLAVE_GEM_NOC_CNOC, SAR2130P_SLAVE_LLCC }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; =20 static const struct qcom_icc_qosbox qnm_nsp_gemnoc_qos =3D { @@ -342,12 +329,11 @@ static const struct qcom_icc_qosbox qnm_nsp_gemnoc_qo= s =3D { =20 static struct qcom_icc_node qnm_nsp_gemnoc =3D { .name =3D "qnm_nsp_gemnoc", - .id =3D SAR2130P_MASTER_COMPUTE_NOC, .channels =3D 2, .buswidth =3D 32, .qosbox =3D &qnm_nsp_gemnoc_qos, .num_links =3D 2, - .links =3D { SAR2130P_SLAVE_GEM_NOC_CNOC, SAR2130P_SLAVE_LLCC }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; =20 static const struct qcom_icc_qosbox qnm_pcie_qos =3D { @@ -359,12 +345,11 @@ static const struct qcom_icc_qosbox qnm_pcie_qos =3D { =20 static struct qcom_icc_node qnm_pcie =3D { .name =3D "qnm_pcie", - .id =3D SAR2130P_MASTER_ANOC_PCIE_GEM_NOC, .channels =3D 1, .buswidth =3D 16, .qosbox =3D &qnm_pcie_qos, .num_links =3D 2, - .links =3D { SAR2130P_SLAVE_GEM_NOC_CNOC, SAR2130P_SLAVE_LLCC }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; =20 static const struct qcom_icc_qosbox qnm_snoc_gc_qos =3D { @@ -376,12 +361,11 @@ static const struct qcom_icc_qosbox qnm_snoc_gc_qos = =3D { =20 static struct qcom_icc_node qnm_snoc_gc =3D { .name =3D "qnm_snoc_gc", - .id =3D SAR2130P_MASTER_SNOC_GC_MEM_NOC, .channels =3D 1, .buswidth =3D 8, .qosbox =3D &qnm_snoc_gc_qos, .num_links =3D 1, - .links =3D { SAR2130P_SLAVE_LLCC }, + .link_nodes =3D { &qns_llcc }, }; =20 static const struct qcom_icc_qosbox qnm_snoc_sf_qos =3D { @@ -393,53 +377,48 @@ static const struct qcom_icc_qosbox qnm_snoc_sf_qos = =3D { =20 static struct qcom_icc_node qnm_snoc_sf =3D { .name =3D "qnm_snoc_sf", - .id =3D SAR2130P_MASTER_SNOC_SF_MEM_NOC, .channels =3D 1, .buswidth =3D 16, .qosbox =3D &qnm_snoc_sf_qos, .num_links =3D 3, - .links =3D { SAR2130P_SLAVE_GEM_NOC_CNOC, SAR2130P_SLAVE_LLCC, - SAR2130P_SLAVE_MEM_NOC_PCIE_SNOC }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, }; =20 static struct qcom_icc_node qxm_wlan_q6 =3D { .name =3D "qxm_wlan_q6", - .id =3D SAR2130P_MASTER_WLAN_Q6, .channels =3D 1, .buswidth =3D 8, .num_links =3D 3, - .links =3D { SAR2130P_SLAVE_GEM_NOC_CNOC, SAR2130P_SLAVE_LLCC, - SAR2130P_SLAVE_MEM_NOC_PCIE_SNOC }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, }; =20 static struct qcom_icc_node qhm_config_noc =3D { .name =3D "qhm_config_noc", - .id =3D SAR2130P_MASTER_CNOC_LPASS_AG_NOC, .channels =3D 1, .buswidth =3D 4, .num_links =3D 6, - .links =3D { SAR2130P_SLAVE_LPASS_CORE_CFG, SAR2130P_SLAVE_LPASS_LPI_CFG, - SAR2130P_SLAVE_LPASS_MPU_CFG, SAR2130P_SLAVE_LPASS_TOP_CFG, - SAR2130P_SLAVE_SERVICES_LPASS_AML_NOC, SAR2130P_SLAVE_SERVICE_LPASS_A= G_NOC }, + .link_nodes =3D { &qhs_lpass_core, &qhs_lpass_lpi, + &qhs_lpass_mpu, &qhs_lpass_top, + &srvc_niu_aml_noc, &srvc_niu_lpass_agnoc }, }; =20 static struct qcom_icc_node qxm_lpass_dsp =3D { .name =3D "qxm_lpass_dsp", - .id =3D SAR2130P_MASTER_LPASS_PROC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 4, - .links =3D { SAR2130P_SLAVE_LPASS_TOP_CFG, SAR2130P_SLAVE_LPASS_SNOC, - SAR2130P_SLAVE_SERVICES_LPASS_AML_NOC, SAR2130P_SLAVE_SERVICE_LPASS_A= G_NOC }, + .link_nodes =3D { &qhs_lpass_top, &qns_sysnoc, + &srvc_niu_aml_noc, &srvc_niu_lpass_agnoc }, }; =20 static struct qcom_icc_node llcc_mc =3D { .name =3D "llcc_mc", - .id =3D SAR2130P_MASTER_LLCC, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SAR2130P_SLAVE_EBI1 }, + .link_nodes =3D { &ebi }, }; =20 static const struct qcom_icc_qosbox qnm_camnoc_hf_qos =3D { @@ -451,12 +430,11 @@ static const struct qcom_icc_qosbox qnm_camnoc_hf_qos= =3D { =20 static struct qcom_icc_node qnm_camnoc_hf =3D { .name =3D "qnm_camnoc_hf", - .id =3D SAR2130P_MASTER_CAMNOC_HF, .channels =3D 1, .buswidth =3D 32, .qosbox =3D &qnm_camnoc_hf_qos, .num_links =3D 1, - .links =3D { SAR2130P_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_hf }, }; =20 static const struct qcom_icc_qosbox qnm_camnoc_icp_qos =3D { @@ -468,12 +446,11 @@ static const struct qcom_icc_qosbox qnm_camnoc_icp_qo= s =3D { =20 static struct qcom_icc_node qnm_camnoc_icp =3D { .name =3D "qnm_camnoc_icp", - .id =3D SAR2130P_MASTER_CAMNOC_ICP, .channels =3D 1, .buswidth =3D 8, .qosbox =3D &qnm_camnoc_icp_qos, .num_links =3D 1, - .links =3D { SAR2130P_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static const struct qcom_icc_qosbox qnm_camnoc_sf_qos =3D { @@ -485,12 +462,11 @@ static const struct qcom_icc_qosbox qnm_camnoc_sf_qos= =3D { =20 static struct qcom_icc_node qnm_camnoc_sf =3D { .name =3D "qnm_camnoc_sf", - .id =3D SAR2130P_MASTER_CAMNOC_SF, .channels =3D 1, .buswidth =3D 32, .qosbox =3D &qnm_camnoc_sf_qos, .num_links =3D 1, - .links =3D { SAR2130P_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static const struct qcom_icc_qosbox qnm_lsr_qos =3D { @@ -502,12 +478,11 @@ static const struct qcom_icc_qosbox qnm_lsr_qos =3D { =20 static struct qcom_icc_node qnm_lsr =3D { .name =3D "qnm_lsr", - .id =3D SAR2130P_MASTER_LSR, .channels =3D 2, .buswidth =3D 32, .qosbox =3D &qnm_lsr_qos, .num_links =3D 1, - .links =3D { SAR2130P_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_hf }, }; =20 static const struct qcom_icc_qosbox qnm_mdp_qos =3D { @@ -519,21 +494,19 @@ static const struct qcom_icc_qosbox qnm_mdp_qos =3D { =20 static struct qcom_icc_node qnm_mdp =3D { .name =3D "qnm_mdp", - .id =3D SAR2130P_MASTER_MDP, .channels =3D 2, .buswidth =3D 32, .qosbox =3D &qnm_mdp_qos, .num_links =3D 1, - .links =3D { SAR2130P_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_hf }, }; =20 static struct qcom_icc_node qnm_mnoc_cfg =3D { .name =3D "qnm_mnoc_cfg", - .id =3D SAR2130P_MASTER_CNOC_MNOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SAR2130P_SLAVE_SERVICE_MNOC }, + .link_nodes =3D { &srvc_mnoc }, }; =20 static const struct qcom_icc_qosbox qnm_video_qos =3D { @@ -545,12 +518,11 @@ static const struct qcom_icc_qosbox qnm_video_qos =3D= { =20 static struct qcom_icc_node qnm_video =3D { .name =3D "qnm_video", - .id =3D SAR2130P_MASTER_VIDEO, .channels =3D 2, .buswidth =3D 32, .qosbox =3D &qnm_video_qos, .num_links =3D 1, - .links =3D { SAR2130P_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static const struct qcom_icc_qosbox qnm_video_cv_cpu_qos =3D { @@ -562,12 +534,11 @@ static const struct qcom_icc_qosbox qnm_video_cv_cpu_= qos =3D { =20 static struct qcom_icc_node qnm_video_cv_cpu =3D { .name =3D "qnm_video_cv_cpu", - .id =3D SAR2130P_MASTER_VIDEO_CV_PROC, .channels =3D 1, .buswidth =3D 8, .qosbox =3D &qnm_video_cv_cpu_qos, .num_links =3D 1, - .links =3D { SAR2130P_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static const struct qcom_icc_qosbox qnm_video_cvp_qos =3D { @@ -579,12 +550,11 @@ static const struct qcom_icc_qosbox qnm_video_cvp_qos= =3D { =20 static struct qcom_icc_node qnm_video_cvp =3D { .name =3D "qnm_video_cvp", - .id =3D SAR2130P_MASTER_VIDEO_PROC, .channels =3D 1, .buswidth =3D 32, .qosbox =3D &qnm_video_cvp_qos, .num_links =3D 1, - .links =3D { SAR2130P_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static const struct qcom_icc_qosbox qnm_video_v_cpu_qos =3D { @@ -596,30 +566,27 @@ static const struct qcom_icc_qosbox qnm_video_v_cpu_q= os =3D { =20 static struct qcom_icc_node qnm_video_v_cpu =3D { .name =3D "qnm_video_v_cpu", - .id =3D SAR2130P_MASTER_VIDEO_V_PROC, .channels =3D 1, .buswidth =3D 8, .qosbox =3D &qnm_video_v_cpu_qos, .num_links =3D 1, - .links =3D { SAR2130P_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static struct qcom_icc_node qhm_nsp_noc_config =3D { .name =3D "qhm_nsp_noc_config", - .id =3D SAR2130P_MASTER_CDSP_NOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SAR2130P_SLAVE_SERVICE_NSP_NOC }, + .link_nodes =3D { &service_nsp_noc }, }; =20 static struct qcom_icc_node qxm_nsp =3D { .name =3D "qxm_nsp", - .id =3D SAR2130P_MASTER_CDSP_PROC, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SAR2130P_SLAVE_CDSP_MEM_NOC }, + .link_nodes =3D { &qns_nsp_gemnoc }, }; =20 static const struct qcom_icc_qosbox xm_pcie3_0_qos =3D { @@ -632,12 +599,11 @@ static const struct qcom_icc_qosbox xm_pcie3_0_qos = =3D { =20 static struct qcom_icc_node xm_pcie3_0 =3D { .name =3D "xm_pcie3_0", - .id =3D SAR2130P_MASTER_PCIE_0, .channels =3D 1, .buswidth =3D 8, .qosbox =3D &xm_pcie3_0_qos, .num_links =3D 1, - .links =3D { SAR2130P_SLAVE_ANOC_PCIE_GEM_NOC }, + .link_nodes =3D { &qns_pcie_mem_noc }, }; =20 static const struct qcom_icc_qosbox xm_pcie3_1_qos =3D { @@ -650,12 +616,11 @@ static const struct qcom_icc_qosbox xm_pcie3_1_qos = =3D { =20 static struct qcom_icc_node xm_pcie3_1 =3D { .name =3D "xm_pcie3_1", - .id =3D SAR2130P_MASTER_PCIE_1, .channels =3D 1, .buswidth =3D 8, .qosbox =3D &xm_pcie3_1_qos, .num_links =3D 1, - .links =3D { SAR2130P_SLAVE_ANOC_PCIE_GEM_NOC }, + .link_nodes =3D { &qns_pcie_mem_noc }, }; =20 static const struct qcom_icc_qosbox qhm_gic_qos =3D { @@ -668,12 +633,11 @@ static const struct qcom_icc_qosbox qhm_gic_qos =3D { =20 static struct qcom_icc_node qhm_gic =3D { .name =3D "qhm_gic", - .id =3D SAR2130P_MASTER_GIC_AHB, .channels =3D 1, .buswidth =3D 4, .qosbox =3D &qhm_gic_qos, .num_links =3D 1, - .links =3D { SAR2130P_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes =3D { &qns_gemnoc_sf }, }; =20 static const struct qcom_icc_qosbox qhm_qdss_bam_qos =3D { @@ -686,12 +650,11 @@ static const struct qcom_icc_qosbox qhm_qdss_bam_qos = =3D { =20 static struct qcom_icc_node qhm_qdss_bam =3D { .name =3D "qhm_qdss_bam", - .id =3D SAR2130P_MASTER_QDSS_BAM, .channels =3D 1, .buswidth =3D 4, .qosbox =3D &qhm_qdss_bam_qos, .num_links =3D 1, - .links =3D { SAR2130P_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static const struct qcom_icc_qosbox qhm_qspi_qos =3D { @@ -704,12 +667,11 @@ static const struct qcom_icc_qosbox qhm_qspi_qos =3D { =20 static struct qcom_icc_node qhm_qspi =3D { .name =3D "qhm_qspi", - .id =3D SAR2130P_MASTER_QSPI_0, .channels =3D 1, .buswidth =3D 4, .qosbox =3D &qhm_qspi_qos, .num_links =3D 1, - .links =3D { SAR2130P_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static const struct qcom_icc_qosbox qhm_qup0_qos =3D { @@ -722,12 +684,11 @@ static const struct qcom_icc_qosbox qhm_qup0_qos =3D { =20 static struct qcom_icc_node qhm_qup0 =3D { .name =3D "qhm_qup0", - .id =3D SAR2130P_MASTER_QUP_0, .channels =3D 1, .buswidth =3D 4, .qosbox =3D &qhm_qup0_qos, .num_links =3D 1, - .links =3D { SAR2130P_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static const struct qcom_icc_qosbox qhm_qup1_qos =3D { @@ -740,21 +701,19 @@ static const struct qcom_icc_qosbox qhm_qup1_qos =3D { =20 static struct qcom_icc_node qhm_qup1 =3D { .name =3D "qhm_qup1", - .id =3D SAR2130P_MASTER_QUP_1, .channels =3D 1, .buswidth =3D 4, .qosbox =3D &qhm_qup1_qos, .num_links =3D 1, - .links =3D { SAR2130P_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qnm_aggre2_noc =3D { .name =3D "qnm_aggre2_noc", - .id =3D SAR2130P_MASTER_A2NOC_SNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SAR2130P_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes =3D { &qns_gemnoc_sf }, }; =20 static const struct qcom_icc_qosbox qnm_cnoc_datapath_qos =3D { @@ -767,12 +726,11 @@ static const struct qcom_icc_qosbox qnm_cnoc_datapath= _qos =3D { =20 static struct qcom_icc_node qnm_cnoc_datapath =3D { .name =3D "qnm_cnoc_datapath", - .id =3D SAR2130P_MASTER_CNOC_DATAPATH, .channels =3D 1, .buswidth =3D 8, .qosbox =3D &qnm_cnoc_datapath_qos, .num_links =3D 1, - .links =3D { SAR2130P_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static const struct qcom_icc_qosbox qnm_lpass_noc_qos =3D { @@ -785,21 +743,19 @@ static const struct qcom_icc_qosbox qnm_lpass_noc_qos= =3D { =20 static struct qcom_icc_node qnm_lpass_noc =3D { .name =3D "qnm_lpass_noc", - .id =3D SAR2130P_MASTER_LPASS_ANOC, .channels =3D 1, .buswidth =3D 16, .qosbox =3D &qnm_lpass_noc_qos, .num_links =3D 1, - .links =3D { SAR2130P_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes =3D { &qns_gemnoc_sf }, }; =20 static struct qcom_icc_node qnm_snoc_cfg =3D { .name =3D "qnm_snoc_cfg", - .id =3D SAR2130P_MASTER_SNOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SAR2130P_SLAVE_SERVICE_SNOC }, + .link_nodes =3D { &srvc_snoc }, }; =20 static const struct qcom_icc_qosbox qxm_crypto_qos =3D { @@ -812,12 +768,11 @@ static const struct qcom_icc_qosbox qxm_crypto_qos = =3D { =20 static struct qcom_icc_node qxm_crypto =3D { .name =3D "qxm_crypto", - .id =3D SAR2130P_MASTER_CRYPTO, .channels =3D 1, .buswidth =3D 8, .qosbox =3D &qxm_crypto_qos, .num_links =3D 1, - .links =3D { SAR2130P_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static const struct qcom_icc_qosbox qxm_pimem_qos =3D { @@ -830,12 +785,11 @@ static const struct qcom_icc_qosbox qxm_pimem_qos =3D= { =20 static struct qcom_icc_node qxm_pimem =3D { .name =3D "qxm_pimem", - .id =3D SAR2130P_MASTER_PIMEM, .channels =3D 1, .buswidth =3D 8, .qosbox =3D &qxm_pimem_qos, .num_links =3D 1, - .links =3D { SAR2130P_SLAVE_SNOC_GEM_NOC_GC }, + .link_nodes =3D { &qns_gemnoc_gc }, }; =20 static const struct qcom_icc_qosbox xm_gic_qos =3D { @@ -848,12 +802,11 @@ static const struct qcom_icc_qosbox xm_gic_qos =3D { =20 static struct qcom_icc_node xm_gic =3D { .name =3D "xm_gic", - .id =3D SAR2130P_MASTER_GIC, .channels =3D 1, .buswidth =3D 8, .qosbox =3D &xm_gic_qos, .num_links =3D 1, - .links =3D { SAR2130P_SLAVE_SNOC_GEM_NOC_GC }, + .link_nodes =3D { &qns_gemnoc_gc }, }; =20 static const struct qcom_icc_qosbox xm_qdss_etr_0_qos =3D { @@ -866,12 +819,11 @@ static const struct qcom_icc_qosbox xm_qdss_etr_0_qos= =3D { =20 static struct qcom_icc_node xm_qdss_etr_0 =3D { .name =3D "xm_qdss_etr_0", - .id =3D SAR2130P_MASTER_QDSS_ETR, .channels =3D 1, .buswidth =3D 8, .qosbox =3D &xm_qdss_etr_0_qos, .num_links =3D 1, - .links =3D { SAR2130P_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static const struct qcom_icc_qosbox xm_qdss_etr_1_qos =3D { @@ -884,12 +836,11 @@ static const struct qcom_icc_qosbox xm_qdss_etr_1_qos= =3D { =20 static struct qcom_icc_node xm_qdss_etr_1 =3D { .name =3D "xm_qdss_etr_1", - .id =3D SAR2130P_MASTER_QDSS_ETR_1, .channels =3D 1, .buswidth =3D 8, .qosbox =3D &xm_qdss_etr_1_qos, .num_links =3D 1, - .links =3D { SAR2130P_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static const struct qcom_icc_qosbox xm_sdc1_qos =3D { @@ -902,12 +853,11 @@ static const struct qcom_icc_qosbox xm_sdc1_qos =3D { =20 static struct qcom_icc_node xm_sdc1 =3D { .name =3D "xm_sdc1", - .id =3D SAR2130P_MASTER_SDCC_1, .channels =3D 1, .buswidth =3D 8, .qosbox =3D &xm_sdc1_qos, .num_links =3D 1, - .links =3D { SAR2130P_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static const struct qcom_icc_qosbox xm_usb3_0_qos =3D { @@ -920,571 +870,449 @@ static const struct qcom_icc_qosbox xm_usb3_0_qos = =3D { =20 static struct qcom_icc_node xm_usb3_0 =3D { .name =3D "xm_usb3_0", - .id =3D SAR2130P_MASTER_USB3_0, .channels =3D 1, .buswidth =3D 8, .qosbox =3D &xm_usb3_0_qos, .num_links =3D 1, - .links =3D { SAR2130P_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qup0_core_slave =3D { .name =3D "qup0_core_slave", - .id =3D SAR2130P_SLAVE_QUP_CORE_0, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qup1_core_slave =3D { .name =3D "qup1_core_slave", - .id =3D SAR2130P_SLAVE_QUP_CORE_1, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_ahb2phy0 =3D { .name =3D "qhs_ahb2phy0", - .id =3D SAR2130P_SLAVE_AHB2PHY_SOUTH, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_aoss =3D { .name =3D "qhs_aoss", - .id =3D SAR2130P_SLAVE_AOSS, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_camera_cfg =3D { .name =3D "qhs_camera_cfg", - .id =3D SAR2130P_SLAVE_CAMERA_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_clk_ctl =3D { .name =3D "qhs_clk_ctl", - .id =3D SAR2130P_SLAVE_CLK_CTL, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_compute_cfg =3D { .name =3D "qhs_compute_cfg", - .id =3D SAR2130P_SLAVE_CDSP_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SAR2130P_MASTER_CDSP_NOC_CFG }, + .link_nodes =3D { &qhm_nsp_noc_config }, }; =20 static struct qcom_icc_node qhs_cpr_cx =3D { .name =3D "qhs_cpr_cx", - .id =3D SAR2130P_SLAVE_RBCPR_CX_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_cpr_mmcx =3D { .name =3D "qhs_cpr_mmcx", - .id =3D SAR2130P_SLAVE_RBCPR_MMCX_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_cpr_mxa =3D { .name =3D "qhs_cpr_mxa", - .id =3D SAR2130P_SLAVE_RBCPR_MXA_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_cpr_mxc =3D { .name =3D "qhs_cpr_mxc", - .id =3D SAR2130P_SLAVE_RBCPR_MXC_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_cpr_nspcx =3D { .name =3D "qhs_cpr_nspcx", - .id =3D SAR2130P_SLAVE_CPR_NSPCX, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_crypto0_cfg =3D { .name =3D "qhs_crypto0_cfg", - .id =3D SAR2130P_SLAVE_CRYPTO_0_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_cx_rdpm =3D { .name =3D "qhs_cx_rdpm", - .id =3D SAR2130P_SLAVE_CX_RDPM, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_display_cfg =3D { .name =3D "qhs_display_cfg", - .id =3D SAR2130P_SLAVE_DISPLAY_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_gpuss_cfg =3D { .name =3D "qhs_gpuss_cfg", - .id =3D SAR2130P_SLAVE_GFX3D_CFG, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_imem_cfg =3D { .name =3D "qhs_imem_cfg", - .id =3D SAR2130P_SLAVE_IMEM_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_ipc_router =3D { .name =3D "qhs_ipc_router", - .id =3D SAR2130P_SLAVE_IPC_ROUTER_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_lpass_cfg =3D { .name =3D "qhs_lpass_cfg", - .id =3D SAR2130P_SLAVE_LPASS, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SAR2130P_MASTER_CNOC_LPASS_AG_NOC }, + .link_nodes =3D { &qhm_config_noc }, }; =20 static struct qcom_icc_node qhs_mx_rdpm =3D { .name =3D "qhs_mx_rdpm", - .id =3D SAR2130P_SLAVE_MX_RDPM, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_pcie0_cfg =3D { .name =3D "qhs_pcie0_cfg", - .id =3D SAR2130P_SLAVE_PCIE_0_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_pcie1_cfg =3D { .name =3D "qhs_pcie1_cfg", - .id =3D SAR2130P_SLAVE_PCIE_1_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_pdm =3D { .name =3D "qhs_pdm", - .id =3D SAR2130P_SLAVE_PDM, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_pimem_cfg =3D { .name =3D "qhs_pimem_cfg", - .id =3D SAR2130P_SLAVE_PIMEM_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_prng =3D { .name =3D "qhs_prng", - .id =3D SAR2130P_SLAVE_PRNG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_qdss_cfg =3D { .name =3D "qhs_qdss_cfg", - .id =3D SAR2130P_SLAVE_QDSS_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_qspi =3D { .name =3D "qhs_qspi", - .id =3D SAR2130P_SLAVE_QSPI_0, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_qup0 =3D { .name =3D "qhs_qup0", - .id =3D SAR2130P_SLAVE_QUP_0, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_qup1 =3D { .name =3D "qhs_qup1", - .id =3D SAR2130P_SLAVE_QUP_1, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_sdc1 =3D { .name =3D "qhs_sdc1", - .id =3D SAR2130P_SLAVE_SDCC_1, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_tcsr =3D { .name =3D "qhs_tcsr", - .id =3D SAR2130P_SLAVE_TCSR, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_tlmm =3D { .name =3D "qhs_tlmm", - .id =3D SAR2130P_SLAVE_TLMM, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_tme_cfg =3D { .name =3D "qhs_tme_cfg", - .id =3D SAR2130P_SLAVE_TME_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_usb3_0 =3D { .name =3D "qhs_usb3_0", - .id =3D SAR2130P_SLAVE_USB3_0, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_venus_cfg =3D { .name =3D "qhs_venus_cfg", - .id =3D SAR2130P_SLAVE_VENUS_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_vsense_ctrl_cfg =3D { .name =3D "qhs_vsense_ctrl_cfg", - .id =3D SAR2130P_SLAVE_VSENSE_CTRL_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_wlan_q6 =3D { .name =3D "qhs_wlan_q6", - .id =3D SAR2130P_SLAVE_WLAN_Q6_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qns_ddrss_cfg =3D { .name =3D "qns_ddrss_cfg", - .id =3D SAR2130P_SLAVE_DDRSS_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qns_mnoc_cfg =3D { .name =3D "qns_mnoc_cfg", - .id =3D SAR2130P_SLAVE_CNOC_MNOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SAR2130P_MASTER_CNOC_MNOC_CFG }, + .link_nodes =3D { &qnm_mnoc_cfg }, }; =20 static struct qcom_icc_node qns_snoc_cfg =3D { .name =3D "qns_snoc_cfg", - .id =3D SAR2130P_SLAVE_SNOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SAR2130P_MASTER_SNOC_CFG }, + .link_nodes =3D { &qnm_snoc_cfg }, }; =20 static struct qcom_icc_node qxs_imem =3D { .name =3D "qxs_imem", - .id =3D SAR2130P_SLAVE_IMEM, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 0, }; =20 static struct qcom_icc_node qxs_pimem =3D { .name =3D "qxs_pimem", - .id =3D SAR2130P_SLAVE_PIMEM, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 0, }; =20 static struct qcom_icc_node srvc_cnoc =3D { .name =3D "srvc_cnoc", - .id =3D SAR2130P_SLAVE_SERVICE_CNOC, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node xs_pcie_0 =3D { .name =3D "xs_pcie_0", - .id =3D SAR2130P_SLAVE_PCIE_0, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 0, }; =20 static struct qcom_icc_node xs_pcie_1 =3D { .name =3D "xs_pcie_1", - .id =3D SAR2130P_SLAVE_PCIE_1, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 0, }; =20 static struct qcom_icc_node xs_qdss_stm =3D { .name =3D "xs_qdss_stm", - .id =3D SAR2130P_SLAVE_QDSS_STM, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node xs_sys_tcu_cfg =3D { .name =3D "xs_sys_tcu_cfg", - .id =3D SAR2130P_SLAVE_TCU, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 0, }; =20 static struct qcom_icc_node qns_gem_noc_cnoc =3D { .name =3D "qns_gem_noc_cnoc", - .id =3D SAR2130P_SLAVE_GEM_NOC_CNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SAR2130P_MASTER_GEM_NOC_CNOC }, + .link_nodes =3D { &qnm_gemnoc_cnoc }, }; =20 static struct qcom_icc_node qns_llcc =3D { .name =3D "qns_llcc", - .id =3D SAR2130P_SLAVE_LLCC, .channels =3D 2, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SAR2130P_MASTER_LLCC }, + .link_nodes =3D { &llcc_mc }, }; =20 static struct qcom_icc_node qns_pcie =3D { .name =3D "qns_pcie", - .id =3D SAR2130P_SLAVE_MEM_NOC_PCIE_SNOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SAR2130P_MASTER_GEM_NOC_PCIE_SNOC }, + .link_nodes =3D { &qnm_gemnoc_pcie }, }; =20 static struct qcom_icc_node qhs_lpass_core =3D { .name =3D "qhs_lpass_core", - .id =3D SAR2130P_SLAVE_LPASS_CORE_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_lpass_lpi =3D { .name =3D "qhs_lpass_lpi", - .id =3D SAR2130P_SLAVE_LPASS_LPI_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_lpass_mpu =3D { .name =3D "qhs_lpass_mpu", - .id =3D SAR2130P_SLAVE_LPASS_MPU_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_lpass_top =3D { .name =3D "qhs_lpass_top", - .id =3D SAR2130P_SLAVE_LPASS_TOP_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qns_sysnoc =3D { .name =3D "qns_sysnoc", - .id =3D SAR2130P_SLAVE_LPASS_SNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SAR2130P_MASTER_LPASS_ANOC }, + .link_nodes =3D { &qnm_lpass_noc }, }; =20 static struct qcom_icc_node srvc_niu_aml_noc =3D { .name =3D "srvc_niu_aml_noc", - .id =3D SAR2130P_SLAVE_SERVICES_LPASS_AML_NOC, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node srvc_niu_lpass_agnoc =3D { .name =3D "srvc_niu_lpass_agnoc", - .id =3D SAR2130P_SLAVE_SERVICE_LPASS_AG_NOC, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node ebi =3D { .name =3D "ebi", - .id =3D SAR2130P_SLAVE_EBI1, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qns_mem_noc_hf =3D { .name =3D "qns_mem_noc_hf", - .id =3D SAR2130P_SLAVE_MNOC_HF_MEM_NOC, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SAR2130P_MASTER_MNOC_HF_MEM_NOC }, + .link_nodes =3D { &qnm_mnoc_hf }, }; =20 static struct qcom_icc_node qns_mem_noc_sf =3D { .name =3D "qns_mem_noc_sf", - .id =3D SAR2130P_SLAVE_MNOC_SF_MEM_NOC, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SAR2130P_MASTER_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qnm_mnoc_sf }, }; =20 static struct qcom_icc_node srvc_mnoc =3D { .name =3D "srvc_mnoc", - .id =3D SAR2130P_SLAVE_SERVICE_MNOC, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qns_nsp_gemnoc =3D { .name =3D "qns_nsp_gemnoc", - .id =3D SAR2130P_SLAVE_CDSP_MEM_NOC, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SAR2130P_MASTER_COMPUTE_NOC }, + .link_nodes =3D { &qnm_nsp_gemnoc }, }; =20 static struct qcom_icc_node service_nsp_noc =3D { .name =3D "service_nsp_noc", - .id =3D SAR2130P_SLAVE_SERVICE_NSP_NOC, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qns_pcie_mem_noc =3D { .name =3D "qns_pcie_mem_noc", - .id =3D SAR2130P_SLAVE_ANOC_PCIE_GEM_NOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SAR2130P_MASTER_ANOC_PCIE_GEM_NOC }, + .link_nodes =3D { &qnm_pcie }, }; =20 static struct qcom_icc_node qns_a2noc_snoc =3D { .name =3D "qns_a2noc_snoc", - .id =3D SAR2130P_SLAVE_A2NOC_SNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SAR2130P_MASTER_A2NOC_SNOC }, + .link_nodes =3D { &qnm_aggre2_noc }, }; =20 static struct qcom_icc_node qns_gemnoc_gc =3D { .name =3D "qns_gemnoc_gc", - .id =3D SAR2130P_SLAVE_SNOC_GEM_NOC_GC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SAR2130P_MASTER_SNOC_GC_MEM_NOC }, + .link_nodes =3D { &qnm_snoc_gc }, }; =20 static struct qcom_icc_node qns_gemnoc_sf =3D { .name =3D "qns_gemnoc_sf", - .id =3D SAR2130P_SLAVE_SNOC_GEM_NOC_SF, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SAR2130P_MASTER_SNOC_SF_MEM_NOC }, + .link_nodes =3D { &qnm_snoc_sf }, }; =20 static struct qcom_icc_node srvc_snoc =3D { .name =3D "srvc_snoc", - .id =3D SAR2130P_SLAVE_SERVICE_SNOC, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_bcm bcm_acv =3D { @@ -1646,6 +1474,7 @@ static struct qcom_icc_node * const clk_virt_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sar2130p_clk_virt =3D { + .alloc_dyn_id =3D true, .nodes =3D clk_virt_nodes, .num_nodes =3D ARRAY_SIZE(clk_virt_nodes), .bcms =3D clk_virt_bcms, @@ -1708,6 +1537,7 @@ static struct qcom_icc_node * const config_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sar2130p_config_noc =3D { + .alloc_dyn_id =3D true, .config =3D &icc_regmap_config, .nodes =3D config_noc_nodes, .num_nodes =3D ARRAY_SIZE(config_noc_nodes), @@ -1738,6 +1568,7 @@ static struct qcom_icc_node * const gem_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sar2130p_gem_noc =3D { + .alloc_dyn_id =3D true, .config =3D &icc_regmap_config, .nodes =3D gem_noc_nodes, .num_nodes =3D ARRAY_SIZE(gem_noc_nodes), @@ -1761,6 +1592,7 @@ static struct qcom_icc_node * const lpass_ag_noc_node= s[] =3D { }; =20 static const struct qcom_icc_desc sar2130p_lpass_ag_noc =3D { + .alloc_dyn_id =3D true, .config =3D &icc_regmap_config, .nodes =3D lpass_ag_noc_nodes, .num_nodes =3D ARRAY_SIZE(lpass_ag_noc_nodes), @@ -1779,6 +1611,7 @@ static struct qcom_icc_node * const mc_virt_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sar2130p_mc_virt =3D { + .alloc_dyn_id =3D true, .nodes =3D mc_virt_nodes, .num_nodes =3D ARRAY_SIZE(mc_virt_nodes), .bcms =3D mc_virt_bcms, @@ -1807,6 +1640,7 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sar2130p_mmss_noc =3D { + .alloc_dyn_id =3D true, .config =3D &icc_regmap_config, .nodes =3D mmss_noc_nodes, .num_nodes =3D ARRAY_SIZE(mmss_noc_nodes), @@ -1826,6 +1660,7 @@ static struct qcom_icc_node * const nsp_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sar2130p_nsp_noc =3D { + .alloc_dyn_id =3D true, .config =3D &icc_regmap_config, .nodes =3D nsp_noc_nodes, .num_nodes =3D ARRAY_SIZE(nsp_noc_nodes), @@ -1844,6 +1679,7 @@ static struct qcom_icc_node * const pcie_anoc_nodes[]= =3D { }; =20 static const struct qcom_icc_desc sar2130p_pcie_anoc =3D { + .alloc_dyn_id =3D true, .config =3D &icc_regmap_config, .nodes =3D pcie_anoc_nodes, .num_nodes =3D ARRAY_SIZE(pcie_anoc_nodes), @@ -1883,6 +1719,7 @@ static struct qcom_icc_node * const system_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sar2130p_system_noc =3D { + .alloc_dyn_id =3D true, .config =3D &icc_regmap_config, .nodes =3D system_noc_nodes, .num_nodes =3D ARRAY_SIZE(system_noc_nodes), --=20 2.47.3