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Change the type of link_nodes field to the array to remove the need for the extra typecast. Signed-off-by: Dmitry Baryshkov --- drivers/interconnect/qcom/glymur.c | 204 +++++++++++++++++--------------= ---- drivers/interconnect/qcom/icc-rpmh.h | 2 +- drivers/interconnect/qcom/milos.c | 130 +++++++++++----------- drivers/interconnect/qcom/sa8775p.c | 186 ++++++++++++++++---------------- 4 files changed, 261 insertions(+), 261 deletions(-) diff --git a/drivers/interconnect/qcom/glymur.c b/drivers/interconnect/qcom= /glymur.c index cf20b5752dbbf4a5e7a79926910993445d7cbb4f..104ac6c1bd3665de92e15d577cb= 51111289c794a 100644 --- a/drivers/interconnect/qcom/glymur.c +++ b/drivers/interconnect/qcom/glymur.c @@ -457,7 +457,7 @@ static struct qcom_icc_node qup0_core_master =3D { .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qup0_core_slave }, + .link_nodes =3D { &qup0_core_slave }, }; =20 static struct qcom_icc_node qup1_core_master =3D { @@ -465,7 +465,7 @@ static struct qcom_icc_node qup1_core_master =3D { .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qup1_core_slave }, + .link_nodes =3D { &qup1_core_slave }, }; =20 static struct qcom_icc_node qup2_core_master =3D { @@ -473,7 +473,7 @@ static struct qcom_icc_node qup2_core_master =3D { .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qup2_core_slave }, + .link_nodes =3D { &qup2_core_slave }, }; =20 static struct qcom_icc_node llcc_mc =3D { @@ -481,7 +481,7 @@ static struct qcom_icc_node llcc_mc =3D { .channels =3D 12, .buswidth =3D 4, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &ebi }, + .link_nodes =3D { &ebi }, }; =20 static struct qcom_icc_node qsm_mnoc_cfg =3D { @@ -489,7 +489,7 @@ static struct qcom_icc_node qsm_mnoc_cfg =3D { .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &srvc_mnoc }, + .link_nodes =3D { &srvc_mnoc }, }; =20 static struct qcom_icc_node qsm_pcie_east_anoc_cfg =3D { @@ -497,7 +497,7 @@ static struct qcom_icc_node qsm_pcie_east_anoc_cfg =3D { .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &srvc_pcie_east_aggre_noc }, + .link_nodes =3D { &srvc_pcie_east_aggre_noc }, }; =20 static struct qcom_icc_node qnm_hscnoc_pcie_east =3D { @@ -505,7 +505,7 @@ static struct qcom_icc_node qnm_hscnoc_pcie_east =3D { .channels =3D 1, .buswidth =3D 32, .num_links =3D 3, - .link_nodes =3D (struct qcom_icc_node *[]) { &xs_pcie_0, &xs_pcie_1, + .link_nodes =3D { &xs_pcie_0, &xs_pcie_1, &xs_pcie_5 }, }; =20 @@ -514,7 +514,7 @@ static struct qcom_icc_node qsm_cnoc_pcie_east_slave_cf= g =3D { .channels =3D 1, .buswidth =3D 4, .num_links =3D 2, - .link_nodes =3D (struct qcom_icc_node *[]) { &qhs_hscnoc_pcie_east_ms_mpu= _cfg, + .link_nodes =3D { &qhs_hscnoc_pcie_east_ms_mpu_cfg, &srvc_pcie_east }, }; =20 @@ -523,7 +523,7 @@ static struct qcom_icc_node qsm_pcie_west_anoc_cfg =3D { .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &srvc_pcie_west_aggre_noc }, + .link_nodes =3D { &srvc_pcie_west_aggre_noc }, }; =20 static struct qcom_icc_node qnm_hscnoc_pcie_west =3D { @@ -531,7 +531,7 @@ static struct qcom_icc_node qnm_hscnoc_pcie_west =3D { .channels =3D 1, .buswidth =3D 32, .num_links =3D 5, - .link_nodes =3D (struct qcom_icc_node *[]) { &xs_pcie_2, &xs_pcie_3a, + .link_nodes =3D { &xs_pcie_2, &xs_pcie_3a, &xs_pcie_3b, &xs_pcie_4, &xs_pcie_6 }, }; @@ -541,7 +541,7 @@ static struct qcom_icc_node qsm_cnoc_pcie_west_slave_cf= g =3D { .channels =3D 1, .buswidth =3D 4, .num_links =3D 2, - .link_nodes =3D (struct qcom_icc_node *[]) { &qhs_hscnoc_pcie_west_ms_mpu= _cfg, + .link_nodes =3D { &qhs_hscnoc_pcie_west_ms_mpu_cfg, &srvc_pcie_west }, }; =20 @@ -550,7 +550,7 @@ static struct qcom_icc_node qss_cnoc_pcie_slave_east_cf= g =3D { .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qsm_cnoc_pcie_east_slave_cf= g }, + .link_nodes =3D { &qsm_cnoc_pcie_east_slave_cfg }, }; =20 static struct qcom_icc_node qss_cnoc_pcie_slave_west_cfg =3D { @@ -558,7 +558,7 @@ static struct qcom_icc_node qss_cnoc_pcie_slave_west_cf= g =3D { .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qsm_cnoc_pcie_west_slave_cf= g }, + .link_nodes =3D { &qsm_cnoc_pcie_west_slave_cfg }, }; =20 static struct qcom_icc_node qss_mnoc_cfg =3D { @@ -566,7 +566,7 @@ static struct qcom_icc_node qss_mnoc_cfg =3D { .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qsm_mnoc_cfg }, + .link_nodes =3D { &qsm_mnoc_cfg }, }; =20 static struct qcom_icc_node qss_pcie_east_anoc_cfg =3D { @@ -574,7 +574,7 @@ static struct qcom_icc_node qss_pcie_east_anoc_cfg =3D { .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qsm_pcie_east_anoc_cfg }, + .link_nodes =3D { &qsm_pcie_east_anoc_cfg }, }; =20 static struct qcom_icc_node qss_pcie_west_anoc_cfg =3D { @@ -582,7 +582,7 @@ static struct qcom_icc_node qss_pcie_west_anoc_cfg =3D { .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qsm_pcie_west_anoc_cfg }, + .link_nodes =3D { &qsm_pcie_west_anoc_cfg }, }; =20 static struct qcom_icc_node qns_llcc =3D { @@ -590,7 +590,7 @@ static struct qcom_icc_node qns_llcc =3D { .channels =3D 12, .buswidth =3D 16, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &llcc_mc }, + .link_nodes =3D { &llcc_mc }, }; =20 static struct qcom_icc_node qns_pcie_east =3D { @@ -598,7 +598,7 @@ static struct qcom_icc_node qns_pcie_east =3D { .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qnm_hscnoc_pcie_east }, + .link_nodes =3D { &qnm_hscnoc_pcie_east }, }; =20 static struct qcom_icc_node qns_pcie_west =3D { @@ -606,7 +606,7 @@ static struct qcom_icc_node qns_pcie_west =3D { .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qnm_hscnoc_pcie_west }, + .link_nodes =3D { &qnm_hscnoc_pcie_west }, }; =20 static struct qcom_icc_node qsm_cfg =3D { @@ -614,7 +614,7 @@ static struct qcom_icc_node qsm_cfg =3D { .channels =3D 1, .buswidth =3D 4, .num_links =3D 51, - .link_nodes =3D (struct qcom_icc_node *[]) { &qhs_ahb2phy0, &qhs_ahb2phy1, + .link_nodes =3D { &qhs_ahb2phy0, &qhs_ahb2phy1, &qhs_ahb2phy2, &qhs_ahb2phy3, &qhs_av1_enc_cfg, &qhs_camera_cfg, &qhs_clk_ctl, &qhs_crypto0_cfg, @@ -654,7 +654,7 @@ static struct qcom_icc_node xm_gic =3D { .prio_fwd_disable =3D 0, }, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_llcc }, + .link_nodes =3D { &qns_llcc }, }; =20 static struct qcom_icc_node qss_cfg =3D { @@ -662,7 +662,7 @@ static struct qcom_icc_node qss_cfg =3D { .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qsm_cfg }, + .link_nodes =3D { &qsm_cfg }, }; =20 static struct qcom_icc_node qnm_hscnoc_cnoc =3D { @@ -670,7 +670,7 @@ static struct qcom_icc_node qnm_hscnoc_cnoc =3D { .channels =3D 1, .buswidth =3D 16, .num_links =3D 8, - .link_nodes =3D (struct qcom_icc_node *[]) { &qhs_aoss, &qhs_ipc_router, + .link_nodes =3D { &qhs_aoss, &qhs_ipc_router, &qhs_soccp, &qhs_tme_cfg, &qns_apss, &qss_cfg, &qxs_boot_imem, &qxs_imem }, @@ -681,7 +681,7 @@ static struct qcom_icc_node qns_hscnoc_cnoc =3D { .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qnm_hscnoc_cnoc }, + .link_nodes =3D { &qnm_hscnoc_cnoc }, }; =20 static struct qcom_icc_node alm_gpu_tcu =3D { @@ -696,7 +696,7 @@ static struct qcom_icc_node alm_gpu_tcu =3D { .prio_fwd_disable =3D 1, }, .num_links =3D 2, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_hscnoc_cnoc, &qns_llcc = }, + .link_nodes =3D { &qns_hscnoc_cnoc, &qns_llcc }, }; =20 static struct qcom_icc_node alm_pcie_qtc =3D { @@ -711,7 +711,7 @@ static struct qcom_icc_node alm_pcie_qtc =3D { .prio_fwd_disable =3D 1, }, .num_links =3D 2, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_hscnoc_cnoc, &qns_llcc = }, + .link_nodes =3D { &qns_hscnoc_cnoc, &qns_llcc }, }; =20 static struct qcom_icc_node alm_sys_tcu =3D { @@ -726,7 +726,7 @@ static struct qcom_icc_node alm_sys_tcu =3D { .prio_fwd_disable =3D 1, }, .num_links =3D 2, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_hscnoc_cnoc, &qns_llcc = }, + .link_nodes =3D { &qns_hscnoc_cnoc, &qns_llcc }, }; =20 static struct qcom_icc_node chm_apps =3D { @@ -734,7 +734,7 @@ static struct qcom_icc_node chm_apps =3D { .channels =3D 6, .buswidth =3D 32, .num_links =3D 4, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_hscnoc_cnoc, &qns_llcc, + .link_nodes =3D { &qns_hscnoc_cnoc, &qns_llcc, &qns_pcie_east, &qns_pcie_west }, }; =20 @@ -750,7 +750,7 @@ static struct qcom_icc_node qnm_aggre_noc_east =3D { .prio_fwd_disable =3D 1, }, .num_links =3D 4, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_hscnoc_cnoc, &qns_llcc, + .link_nodes =3D { &qns_hscnoc_cnoc, &qns_llcc, &qns_pcie_east, &qns_pcie_west }, }; =20 @@ -766,7 +766,7 @@ static struct qcom_icc_node qnm_gpu =3D { .prio_fwd_disable =3D 1, }, .num_links =3D 4, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_hscnoc_cnoc, &qns_llcc, + .link_nodes =3D { &qns_hscnoc_cnoc, &qns_llcc, &qns_pcie_east, &qns_pcie_west }, }; =20 @@ -782,7 +782,7 @@ static struct qcom_icc_node qnm_lpass =3D { .prio_fwd_disable =3D 0, }, .num_links =3D 4, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_hscnoc_cnoc, &qns_llcc, + .link_nodes =3D { &qns_hscnoc_cnoc, &qns_llcc, &qns_pcie_east, &qns_pcie_west }, }; =20 @@ -798,7 +798,7 @@ static struct qcom_icc_node qnm_mnoc_hf =3D { .prio_fwd_disable =3D 0, }, .num_links =3D 4, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_hscnoc_cnoc, &qns_llcc, + .link_nodes =3D { &qns_hscnoc_cnoc, &qns_llcc, &qns_pcie_east, &qns_pcie_west }, }; =20 @@ -814,7 +814,7 @@ static struct qcom_icc_node qnm_mnoc_sf =3D { .prio_fwd_disable =3D 0, }, .num_links =3D 4, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_hscnoc_cnoc, &qns_llcc, + .link_nodes =3D { &qns_hscnoc_cnoc, &qns_llcc, &qns_pcie_east, &qns_pcie_west }, }; =20 @@ -830,7 +830,7 @@ static struct qcom_icc_node qnm_nsp_noc =3D { .prio_fwd_disable =3D 1, }, .num_links =3D 4, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_hscnoc_cnoc, &qns_llcc, + .link_nodes =3D { &qns_hscnoc_cnoc, &qns_llcc, &qns_pcie_east, &qns_pcie_west }, }; =20 @@ -846,7 +846,7 @@ static struct qcom_icc_node qnm_pcie_east =3D { .prio_fwd_disable =3D 1, }, .num_links =3D 2, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_hscnoc_cnoc, &qns_llcc = }, + .link_nodes =3D { &qns_hscnoc_cnoc, &qns_llcc }, }; =20 static struct qcom_icc_node qnm_pcie_west =3D { @@ -861,7 +861,7 @@ static struct qcom_icc_node qnm_pcie_west =3D { .prio_fwd_disable =3D 1, }, .num_links =3D 2, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_hscnoc_cnoc, &qns_llcc = }, + .link_nodes =3D { &qns_hscnoc_cnoc, &qns_llcc }, }; =20 static struct qcom_icc_node qnm_snoc_sf =3D { @@ -876,7 +876,7 @@ static struct qcom_icc_node qnm_snoc_sf =3D { .prio_fwd_disable =3D 1, }, .num_links =3D 4, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_hscnoc_cnoc, &qns_llcc, + .link_nodes =3D { &qns_hscnoc_cnoc, &qns_llcc, &qns_pcie_east, &qns_pcie_west }, }; =20 @@ -885,7 +885,7 @@ static struct qcom_icc_node qxm_wlan_q6 =3D { .channels =3D 1, .buswidth =3D 8, .num_links =3D 4, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_hscnoc_cnoc, &qns_llcc, + .link_nodes =3D { &qns_hscnoc_cnoc, &qns_llcc, &qns_pcie_east, &qns_pcie_west }, }; =20 @@ -894,7 +894,7 @@ static struct qcom_icc_node qns_a4noc_hscnoc =3D { .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qnm_aggre_noc_east }, + .link_nodes =3D { &qnm_aggre_noc_east }, }; =20 static struct qcom_icc_node qns_lpass_ag_noc_gemnoc =3D { @@ -902,7 +902,7 @@ static struct qcom_icc_node qns_lpass_ag_noc_gemnoc =3D= { .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qnm_lpass }, + .link_nodes =3D { &qnm_lpass }, }; =20 static struct qcom_icc_node qns_mem_noc_hf =3D { @@ -910,7 +910,7 @@ static struct qcom_icc_node qns_mem_noc_hf =3D { .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qnm_mnoc_hf }, + .link_nodes =3D { &qnm_mnoc_hf }, }; =20 static struct qcom_icc_node qns_mem_noc_sf =3D { @@ -918,7 +918,7 @@ static struct qcom_icc_node qns_mem_noc_sf =3D { .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qnm_mnoc_sf }, + .link_nodes =3D { &qnm_mnoc_sf }, }; =20 static struct qcom_icc_node qns_nsp_hscnoc =3D { @@ -926,7 +926,7 @@ static struct qcom_icc_node qns_nsp_hscnoc =3D { .channels =3D 4, .buswidth =3D 32, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qnm_nsp_noc }, + .link_nodes =3D { &qnm_nsp_noc }, }; =20 static struct qcom_icc_node qns_pcie_east_mem_noc =3D { @@ -934,7 +934,7 @@ static struct qcom_icc_node qns_pcie_east_mem_noc =3D { .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qnm_pcie_east }, + .link_nodes =3D { &qnm_pcie_east }, }; =20 static struct qcom_icc_node qns_pcie_west_mem_noc =3D { @@ -942,7 +942,7 @@ static struct qcom_icc_node qns_pcie_west_mem_noc =3D { .channels =3D 1, .buswidth =3D 64, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qnm_pcie_west }, + .link_nodes =3D { &qnm_pcie_west }, }; =20 static struct qcom_icc_node qns_gemnoc_sf =3D { @@ -950,7 +950,7 @@ static struct qcom_icc_node qns_gemnoc_sf =3D { .channels =3D 1, .buswidth =3D 64, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qnm_snoc_sf }, + .link_nodes =3D { &qnm_snoc_sf }, }; =20 static struct qcom_icc_node xm_usb3_0 =3D { @@ -965,7 +965,7 @@ static struct qcom_icc_node xm_usb3_0 =3D { .prio_fwd_disable =3D 1, }, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a4noc_hscnoc }, + .link_nodes =3D { &qns_a4noc_hscnoc }, }; =20 static struct qcom_icc_node xm_usb3_1 =3D { @@ -980,7 +980,7 @@ static struct qcom_icc_node xm_usb3_1 =3D { .prio_fwd_disable =3D 1, }, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a4noc_hscnoc }, + .link_nodes =3D { &qns_a4noc_hscnoc }, }; =20 static struct qcom_icc_node xm_usb4_0 =3D { @@ -995,7 +995,7 @@ static struct qcom_icc_node xm_usb4_0 =3D { .prio_fwd_disable =3D 1, }, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a4noc_hscnoc }, + .link_nodes =3D { &qns_a4noc_hscnoc }, }; =20 static struct qcom_icc_node xm_usb4_1 =3D { @@ -1010,7 +1010,7 @@ static struct qcom_icc_node xm_usb4_1 =3D { .prio_fwd_disable =3D 1, }, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a4noc_hscnoc }, + .link_nodes =3D { &qns_a4noc_hscnoc }, }; =20 static struct qcom_icc_node qnm_lpiaon_noc =3D { @@ -1018,7 +1018,7 @@ static struct qcom_icc_node qnm_lpiaon_noc =3D { .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_lpass_ag_noc_gemnoc }, + .link_nodes =3D { &qns_lpass_ag_noc_gemnoc }, }; =20 static struct qcom_icc_node qnm_av1_enc =3D { @@ -1033,7 +1033,7 @@ static struct qcom_icc_node qnm_av1_enc =3D { .prio_fwd_disable =3D 1, }, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_mem_noc_sf }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static struct qcom_icc_node qnm_camnoc_hf =3D { @@ -1048,7 +1048,7 @@ static struct qcom_icc_node qnm_camnoc_hf =3D { .prio_fwd_disable =3D 0, }, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_mem_noc_hf }, + .link_nodes =3D { &qns_mem_noc_hf }, }; =20 static struct qcom_icc_node qnm_camnoc_icp =3D { @@ -1063,7 +1063,7 @@ static struct qcom_icc_node qnm_camnoc_icp =3D { .prio_fwd_disable =3D 1, }, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_mem_noc_sf }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static struct qcom_icc_node qnm_camnoc_sf =3D { @@ -1078,7 +1078,7 @@ static struct qcom_icc_node qnm_camnoc_sf =3D { .prio_fwd_disable =3D 0, }, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_mem_noc_sf }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static struct qcom_icc_node qnm_eva =3D { @@ -1093,7 +1093,7 @@ static struct qcom_icc_node qnm_eva =3D { .prio_fwd_disable =3D 0, }, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_mem_noc_sf }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static struct qcom_icc_node qnm_mdp =3D { @@ -1108,7 +1108,7 @@ static struct qcom_icc_node qnm_mdp =3D { .prio_fwd_disable =3D 0, }, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_mem_noc_hf }, + .link_nodes =3D { &qns_mem_noc_hf }, }; =20 static struct qcom_icc_node qnm_vapss_hcp =3D { @@ -1116,7 +1116,7 @@ static struct qcom_icc_node qnm_vapss_hcp =3D { .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_mem_noc_sf }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static struct qcom_icc_node qnm_video =3D { @@ -1131,7 +1131,7 @@ static struct qcom_icc_node qnm_video =3D { .prio_fwd_disable =3D 0, }, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_mem_noc_sf }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static struct qcom_icc_node qnm_video_cv_cpu =3D { @@ -1146,7 +1146,7 @@ static struct qcom_icc_node qnm_video_cv_cpu =3D { .prio_fwd_disable =3D 1, }, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_mem_noc_sf }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static struct qcom_icc_node qnm_video_v_cpu =3D { @@ -1161,7 +1161,7 @@ static struct qcom_icc_node qnm_video_v_cpu =3D { .prio_fwd_disable =3D 1, }, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_mem_noc_sf }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static struct qcom_icc_node qnm_nsp =3D { @@ -1169,7 +1169,7 @@ static struct qcom_icc_node qnm_nsp =3D { .channels =3D 4, .buswidth =3D 32, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_nsp_hscnoc }, + .link_nodes =3D { &qns_nsp_hscnoc }, }; =20 static struct qcom_icc_node xm_pcie_0 =3D { @@ -1184,7 +1184,7 @@ static struct qcom_icc_node xm_pcie_0 =3D { .prio_fwd_disable =3D 0, }, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_pcie_east_mem_noc }, + .link_nodes =3D { &qns_pcie_east_mem_noc }, }; =20 static struct qcom_icc_node xm_pcie_1 =3D { @@ -1199,7 +1199,7 @@ static struct qcom_icc_node xm_pcie_1 =3D { .prio_fwd_disable =3D 0, }, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_pcie_east_mem_noc }, + .link_nodes =3D { &qns_pcie_east_mem_noc }, }; =20 static struct qcom_icc_node xm_pcie_5 =3D { @@ -1214,7 +1214,7 @@ static struct qcom_icc_node xm_pcie_5 =3D { .prio_fwd_disable =3D 0, }, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_pcie_east_mem_noc }, + .link_nodes =3D { &qns_pcie_east_mem_noc }, }; =20 static struct qcom_icc_node xm_pcie_2 =3D { @@ -1229,7 +1229,7 @@ static struct qcom_icc_node xm_pcie_2 =3D { .prio_fwd_disable =3D 0, }, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_pcie_west_mem_noc }, + .link_nodes =3D { &qns_pcie_west_mem_noc }, }; =20 static struct qcom_icc_node xm_pcie_3a =3D { @@ -1244,7 +1244,7 @@ static struct qcom_icc_node xm_pcie_3a =3D { .prio_fwd_disable =3D 0, }, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_pcie_west_mem_noc }, + .link_nodes =3D { &qns_pcie_west_mem_noc }, }; =20 static struct qcom_icc_node xm_pcie_3b =3D { @@ -1259,7 +1259,7 @@ static struct qcom_icc_node xm_pcie_3b =3D { .prio_fwd_disable =3D 0, }, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_pcie_west_mem_noc }, + .link_nodes =3D { &qns_pcie_west_mem_noc }, }; =20 static struct qcom_icc_node xm_pcie_4 =3D { @@ -1274,7 +1274,7 @@ static struct qcom_icc_node xm_pcie_4 =3D { .prio_fwd_disable =3D 0, }, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_pcie_west_mem_noc }, + .link_nodes =3D { &qns_pcie_west_mem_noc }, }; =20 static struct qcom_icc_node xm_pcie_6 =3D { @@ -1289,7 +1289,7 @@ static struct qcom_icc_node xm_pcie_6 =3D { .prio_fwd_disable =3D 0, }, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_pcie_west_mem_noc }, + .link_nodes =3D { &qns_pcie_west_mem_noc }, }; =20 static struct qcom_icc_node qnm_aggre1_noc =3D { @@ -1297,7 +1297,7 @@ static struct qcom_icc_node qnm_aggre1_noc =3D { .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_gemnoc_sf }, + .link_nodes =3D { &qns_gemnoc_sf }, }; =20 static struct qcom_icc_node qnm_aggre2_noc =3D { @@ -1305,7 +1305,7 @@ static struct qcom_icc_node qnm_aggre2_noc =3D { .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_gemnoc_sf }, + .link_nodes =3D { &qns_gemnoc_sf }, }; =20 static struct qcom_icc_node qnm_aggre3_noc =3D { @@ -1313,7 +1313,7 @@ static struct qcom_icc_node qnm_aggre3_noc =3D { .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_gemnoc_sf }, + .link_nodes =3D { &qns_gemnoc_sf }, }; =20 static struct qcom_icc_node qnm_nsi_noc =3D { @@ -1328,7 +1328,7 @@ static struct qcom_icc_node qnm_nsi_noc =3D { .prio_fwd_disable =3D 1, }, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_gemnoc_sf }, + .link_nodes =3D { &qns_gemnoc_sf }, }; =20 static struct qcom_icc_node qnm_oobmss =3D { @@ -1343,7 +1343,7 @@ static struct qcom_icc_node qnm_oobmss =3D { .prio_fwd_disable =3D 1, }, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_gemnoc_sf }, + .link_nodes =3D { &qns_gemnoc_sf }, }; =20 static struct qcom_icc_node qns_a1noc_snoc =3D { @@ -1351,7 +1351,7 @@ static struct qcom_icc_node qns_a1noc_snoc =3D { .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qnm_aggre1_noc }, + .link_nodes =3D { &qnm_aggre1_noc }, }; =20 static struct qcom_icc_node qns_a2noc_snoc =3D { @@ -1359,7 +1359,7 @@ static struct qcom_icc_node qns_a2noc_snoc =3D { .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qnm_aggre2_noc }, + .link_nodes =3D { &qnm_aggre2_noc }, }; =20 static struct qcom_icc_node qns_a3noc_snoc =3D { @@ -1367,7 +1367,7 @@ static struct qcom_icc_node qns_a3noc_snoc =3D { .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qnm_aggre3_noc }, + .link_nodes =3D { &qnm_aggre3_noc }, }; =20 static struct qcom_icc_node qns_lpass_aggnoc =3D { @@ -1375,7 +1375,7 @@ static struct qcom_icc_node qns_lpass_aggnoc =3D { .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qnm_lpiaon_noc }, + .link_nodes =3D { &qnm_lpiaon_noc }, }; =20 static struct qcom_icc_node qns_system_noc =3D { @@ -1383,7 +1383,7 @@ static struct qcom_icc_node qns_system_noc =3D { .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qnm_nsi_noc }, + .link_nodes =3D { &qnm_nsi_noc }, }; =20 static struct qcom_icc_node qns_oobmss_snoc =3D { @@ -1391,7 +1391,7 @@ static struct qcom_icc_node qns_oobmss_snoc =3D { .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qnm_oobmss }, + .link_nodes =3D { &qnm_oobmss }, }; =20 static struct qcom_icc_node qxm_crypto =3D { @@ -1406,7 +1406,7 @@ static struct qcom_icc_node qxm_crypto =3D { .prio_fwd_disable =3D 1, }, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a1noc_snoc }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node qxm_soccp =3D { @@ -1421,7 +1421,7 @@ static struct qcom_icc_node qxm_soccp =3D { .prio_fwd_disable =3D 1, }, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a1noc_snoc }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node xm_qdss_etr_0 =3D { @@ -1436,7 +1436,7 @@ static struct qcom_icc_node xm_qdss_etr_0 =3D { .prio_fwd_disable =3D 1, }, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a1noc_snoc }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node xm_qdss_etr_1 =3D { @@ -1451,7 +1451,7 @@ static struct qcom_icc_node xm_qdss_etr_1 =3D { .prio_fwd_disable =3D 1, }, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a1noc_snoc }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node xm_ufs_mem =3D { @@ -1466,7 +1466,7 @@ static struct qcom_icc_node xm_ufs_mem =3D { .prio_fwd_disable =3D 1, }, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node xm_usb3_2 =3D { @@ -1481,7 +1481,7 @@ static struct qcom_icc_node xm_usb3_2 =3D { .prio_fwd_disable =3D 1, }, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node xm_usb4_2 =3D { @@ -1496,7 +1496,7 @@ static struct qcom_icc_node xm_usb4_2 =3D { .prio_fwd_disable =3D 1, }, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qhm_qspi =3D { @@ -1511,7 +1511,7 @@ static struct qcom_icc_node qhm_qspi =3D { .prio_fwd_disable =3D 1, }, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a3noc_snoc }, + .link_nodes =3D { &qns_a3noc_snoc }, }; =20 static struct qcom_icc_node qhm_qup0 =3D { @@ -1526,7 +1526,7 @@ static struct qcom_icc_node qhm_qup0 =3D { .prio_fwd_disable =3D 1, }, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a3noc_snoc }, + .link_nodes =3D { &qns_a3noc_snoc }, }; =20 static struct qcom_icc_node qhm_qup1 =3D { @@ -1541,7 +1541,7 @@ static struct qcom_icc_node qhm_qup1 =3D { .prio_fwd_disable =3D 1, }, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a3noc_snoc }, + .link_nodes =3D { &qns_a3noc_snoc }, }; =20 static struct qcom_icc_node qhm_qup2 =3D { @@ -1556,7 +1556,7 @@ static struct qcom_icc_node qhm_qup2 =3D { .prio_fwd_disable =3D 1, }, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a3noc_snoc }, + .link_nodes =3D { &qns_a3noc_snoc }, }; =20 static struct qcom_icc_node qxm_sp =3D { @@ -1564,7 +1564,7 @@ static struct qcom_icc_node qxm_sp =3D { .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a3noc_snoc }, + .link_nodes =3D { &qns_a3noc_snoc }, }; =20 static struct qcom_icc_node xm_sdc2 =3D { @@ -1579,7 +1579,7 @@ static struct qcom_icc_node xm_sdc2 =3D { .prio_fwd_disable =3D 1, }, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a3noc_snoc }, + .link_nodes =3D { &qns_a3noc_snoc }, }; =20 static struct qcom_icc_node xm_sdc4 =3D { @@ -1594,7 +1594,7 @@ static struct qcom_icc_node xm_sdc4 =3D { .prio_fwd_disable =3D 1, }, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a3noc_snoc }, + .link_nodes =3D { &qns_a3noc_snoc }, }; =20 static struct qcom_icc_node xm_usb2_0 =3D { @@ -1609,7 +1609,7 @@ static struct qcom_icc_node xm_usb2_0 =3D { .prio_fwd_disable =3D 1, }, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a3noc_snoc }, + .link_nodes =3D { &qns_a3noc_snoc }, }; =20 static struct qcom_icc_node xm_usb3_mp =3D { @@ -1624,7 +1624,7 @@ static struct qcom_icc_node xm_usb3_mp =3D { .prio_fwd_disable =3D 1, }, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a3noc_snoc }, + .link_nodes =3D { &qns_a3noc_snoc }, }; =20 static struct qcom_icc_node qnm_lpass_lpinoc =3D { @@ -1632,7 +1632,7 @@ static struct qcom_icc_node qnm_lpass_lpinoc =3D { .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_lpass_aggnoc }, + .link_nodes =3D { &qns_lpass_aggnoc }, }; =20 static struct qcom_icc_node xm_cpucp =3D { @@ -1640,7 +1640,7 @@ static struct qcom_icc_node xm_cpucp =3D { .channels =3D 1, .buswidth =3D 8, .num_links =3D 2, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_system_noc, &srvc_nsino= c }, + .link_nodes =3D { &qns_system_noc, &srvc_nsinoc }, }; =20 static struct qcom_icc_node xm_mem_sp =3D { @@ -1648,7 +1648,7 @@ static struct qcom_icc_node xm_mem_sp =3D { .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_oobmss_snoc }, + .link_nodes =3D { &qns_oobmss_snoc }, }; =20 static struct qcom_icc_node qns_lpi_aon_noc =3D { @@ -1656,7 +1656,7 @@ static struct qcom_icc_node qns_lpi_aon_noc =3D { .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qnm_lpass_lpinoc }, + .link_nodes =3D { &qnm_lpass_lpinoc }, }; =20 static struct qcom_icc_node qnm_lpinoc_dsp_qns4m =3D { @@ -1664,7 +1664,7 @@ static struct qcom_icc_node qnm_lpinoc_dsp_qns4m =3D { .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_lpi_aon_noc }, + .link_nodes =3D { &qns_lpi_aon_noc }, }; =20 static struct qcom_icc_bcm bcm_acv =3D { diff --git a/drivers/interconnect/qcom/icc-rpmh.h b/drivers/interconnect/qc= om/icc-rpmh.h index 307f48412563690049e944907bd80500f263f738..b72939cceba38e92154f6af5a93= 149337fa13479 100644 --- a/drivers/interconnect/qcom/icc-rpmh.h +++ b/drivers/interconnect/qcom/icc-rpmh.h @@ -98,7 +98,6 @@ struct qcom_icc_node { const char *name; u16 links[MAX_LINKS]; u16 id; - struct qcom_icc_node **link_nodes; struct icc_node *node; u16 num_links; u16 channels; @@ -108,6 +107,7 @@ struct qcom_icc_node { struct qcom_icc_bcm *bcms[MAX_BCM_PER_NODE]; size_t num_bcms; const struct qcom_icc_qosbox *qosbox; + struct qcom_icc_node *link_nodes[]; }; =20 /** diff --git a/drivers/interconnect/qcom/milos.c b/drivers/interconnect/qcom/= milos.c index 167d479f77641a3c1a69f8a0beb20473a251a9d9..814ec0517f6b8f42ae9d7ce3cd5= cebcbaae35ae8 100644 --- a/drivers/interconnect/qcom/milos.c +++ b/drivers/interconnect/qcom/milos.c @@ -151,7 +151,7 @@ static struct qcom_icc_node qhm_qup1 =3D { .buswidth =3D 4, .qosbox =3D &qhm_qup1_qos, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a1noc_snoc }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_qosbox xm_ufs_mem_qos =3D { @@ -168,7 +168,7 @@ static struct qcom_icc_node xm_ufs_mem =3D { .buswidth =3D 8, .qosbox =3D &xm_ufs_mem_qos, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a1noc_snoc }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_qosbox xm_usb3_0_qos =3D { @@ -185,7 +185,7 @@ static struct qcom_icc_node xm_usb3_0 =3D { .buswidth =3D 8, .qosbox =3D &xm_usb3_0_qos, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a1noc_snoc }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_qosbox qhm_qdss_bam_qos =3D { @@ -202,7 +202,7 @@ static struct qcom_icc_node qhm_qdss_bam =3D { .buswidth =3D 4, .qosbox =3D &qhm_qdss_bam_qos, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_qosbox qhm_qspi_qos =3D { @@ -219,7 +219,7 @@ static struct qcom_icc_node qhm_qspi =3D { .buswidth =3D 4, .qosbox =3D &qhm_qspi_qos, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_qosbox qhm_qup0_qos =3D { @@ -236,7 +236,7 @@ static struct qcom_icc_node qhm_qup0 =3D { .buswidth =3D 4, .qosbox =3D &qhm_qup0_qos, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_qosbox qxm_crypto_qos =3D { @@ -253,7 +253,7 @@ static struct qcom_icc_node qxm_crypto =3D { .buswidth =3D 8, .qosbox =3D &qxm_crypto_qos, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_qosbox qxm_ipa_qos =3D { @@ -270,7 +270,7 @@ static struct qcom_icc_node qxm_ipa =3D { .buswidth =3D 8, .qosbox =3D &qxm_ipa_qos, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_qosbox xm_qdss_etr_0_qos =3D { @@ -287,7 +287,7 @@ static struct qcom_icc_node xm_qdss_etr_0 =3D { .buswidth =3D 8, .qosbox =3D &xm_qdss_etr_0_qos, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_qosbox xm_qdss_etr_1_qos =3D { @@ -304,7 +304,7 @@ static struct qcom_icc_node xm_qdss_etr_1 =3D { .buswidth =3D 8, .qosbox =3D &xm_qdss_etr_1_qos, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_qosbox xm_sdc1_qos =3D { @@ -321,7 +321,7 @@ static struct qcom_icc_node xm_sdc1 =3D { .buswidth =3D 8, .qosbox =3D &xm_sdc1_qos, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_qosbox xm_sdc2_qos =3D { @@ -338,7 +338,7 @@ static struct qcom_icc_node xm_sdc2 =3D { .buswidth =3D 8, .qosbox =3D &xm_sdc2_qos, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qup0_core_master =3D { @@ -346,7 +346,7 @@ static struct qcom_icc_node qup0_core_master =3D { .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qup0_core_slave }, + .link_nodes =3D { &qup0_core_slave }, }; =20 static struct qcom_icc_node qup1_core_master =3D { @@ -354,7 +354,7 @@ static struct qcom_icc_node qup1_core_master =3D { .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qup1_core_slave }, + .link_nodes =3D { &qup1_core_slave }, }; =20 static struct qcom_icc_node qsm_cfg =3D { @@ -362,7 +362,7 @@ static struct qcom_icc_node qsm_cfg =3D { .channels =3D 1, .buswidth =3D 4, .num_links =3D 35, - .link_nodes =3D (struct qcom_icc_node *[]) { &qhs_ahb2phy0, &qhs_ahb2phy1, + .link_nodes =3D { &qhs_ahb2phy0, &qhs_ahb2phy1, &qhs_camera_cfg, &qhs_clk_ctl, &qhs_cpr_cx, &qhs_cpr_mxa, &qhs_crypto0_cfg, &qhs_cx_rdpm, @@ -387,7 +387,7 @@ static struct qcom_icc_node qnm_gemnoc_cnoc =3D { .channels =3D 1, .buswidth =3D 16, .num_links =3D 14, - .link_nodes =3D (struct qcom_icc_node *[]) { &qhs_aoss, &qhs_display_cfg, + .link_nodes =3D { &qhs_aoss, &qhs_display_cfg, &qhs_ipa, &qhs_ipc_router, &qhs_pcie0_cfg, &qhs_pcie1_cfg, &qhs_prng, &qhs_tme_cfg, @@ -401,7 +401,7 @@ static struct qcom_icc_node qnm_gemnoc_pcie =3D { .channels =3D 1, .buswidth =3D 8, .num_links =3D 2, - .link_nodes =3D (struct qcom_icc_node *[]) { &xs_pcie_0, &xs_pcie_1 }, + .link_nodes =3D { &xs_pcie_0, &xs_pcie_1 }, }; =20 static struct qcom_icc_qosbox alm_gpu_tcu_qos =3D { @@ -418,7 +418,7 @@ static struct qcom_icc_node alm_gpu_tcu =3D { .buswidth =3D 8, .qosbox =3D &alm_gpu_tcu_qos, .num_links =3D 2, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc= }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; =20 static struct qcom_icc_qosbox alm_sys_tcu_qos =3D { @@ -435,7 +435,7 @@ static struct qcom_icc_node alm_sys_tcu =3D { .buswidth =3D 8, .qosbox =3D &alm_sys_tcu_qos, .num_links =3D 2, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc= }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; =20 static struct qcom_icc_node chm_apps =3D { @@ -443,7 +443,7 @@ static struct qcom_icc_node chm_apps =3D { .channels =3D 3, .buswidth =3D 32, .num_links =3D 3, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc, &qns_pcie }, }; =20 @@ -461,7 +461,7 @@ static struct qcom_icc_node qnm_gpu =3D { .buswidth =3D 32, .qosbox =3D &qnm_gpu_qos, .num_links =3D 2, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc= }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; =20 static struct qcom_icc_qosbox qnm_lpass_gemnoc_qos =3D { @@ -478,7 +478,7 @@ static struct qcom_icc_node qnm_lpass_gemnoc =3D { .buswidth =3D 16, .qosbox =3D &qnm_lpass_gemnoc_qos, .num_links =3D 3, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc, &qns_pcie }, }; =20 @@ -487,7 +487,7 @@ static struct qcom_icc_node qnm_mdsp =3D { .channels =3D 1, .buswidth =3D 16, .num_links =3D 3, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc, &qns_pcie }, }; =20 @@ -505,7 +505,7 @@ static struct qcom_icc_node qnm_mnoc_hf =3D { .buswidth =3D 32, .qosbox =3D &qnm_mnoc_hf_qos, .num_links =3D 2, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc= }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; =20 static struct qcom_icc_qosbox qnm_mnoc_sf_qos =3D { @@ -522,7 +522,7 @@ static struct qcom_icc_node qnm_mnoc_sf =3D { .buswidth =3D 32, .qosbox =3D &qnm_mnoc_sf_qos, .num_links =3D 2, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc= }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; =20 static struct qcom_icc_qosbox qnm_nsp_gemnoc_qos =3D { @@ -539,7 +539,7 @@ static struct qcom_icc_node qnm_nsp_gemnoc =3D { .buswidth =3D 32, .qosbox =3D &qnm_nsp_gemnoc_qos, .num_links =3D 3, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc, &qns_pcie }, }; =20 @@ -557,7 +557,7 @@ static struct qcom_icc_node qnm_pcie =3D { .buswidth =3D 8, .qosbox =3D &qnm_pcie_qos, .num_links =3D 2, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc= }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; =20 static struct qcom_icc_qosbox qnm_snoc_gc_qos =3D { @@ -574,7 +574,7 @@ static struct qcom_icc_node qnm_snoc_gc =3D { .buswidth =3D 8, .qosbox =3D &qnm_snoc_gc_qos, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_llcc }, + .link_nodes =3D { &qns_llcc }, }; =20 static struct qcom_icc_qosbox qnm_snoc_sf_qos =3D { @@ -591,7 +591,7 @@ static struct qcom_icc_node qnm_snoc_sf =3D { .buswidth =3D 16, .qosbox =3D &qnm_snoc_sf_qos, .num_links =3D 3, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc, &qns_pcie }, }; =20 @@ -600,7 +600,7 @@ static struct qcom_icc_node qxm_wlan_q6 =3D { .channels =3D 1, .buswidth =3D 8, .num_links =3D 3, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc, &qns_pcie }, }; =20 @@ -609,7 +609,7 @@ static struct qcom_icc_node qxm_lpass_dsp =3D { .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_lpass_ag_noc_gemnoc }, + .link_nodes =3D { &qns_lpass_ag_noc_gemnoc }, }; =20 static struct qcom_icc_node llcc_mc =3D { @@ -617,7 +617,7 @@ static struct qcom_icc_node llcc_mc =3D { .channels =3D 2, .buswidth =3D 4, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &ebi }, + .link_nodes =3D { &ebi }, }; =20 static struct qcom_icc_qosbox qnm_camnoc_hf_qos =3D { @@ -634,7 +634,7 @@ static struct qcom_icc_node qnm_camnoc_hf =3D { .buswidth =3D 32, .qosbox =3D &qnm_camnoc_hf_qos, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_mem_noc_hf }, + .link_nodes =3D { &qns_mem_noc_hf }, }; =20 static struct qcom_icc_qosbox qnm_camnoc_icp_qos =3D { @@ -651,7 +651,7 @@ static struct qcom_icc_node qnm_camnoc_icp =3D { .buswidth =3D 8, .qosbox =3D &qnm_camnoc_icp_qos, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_mem_noc_sf }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static struct qcom_icc_qosbox qnm_camnoc_sf_qos =3D { @@ -668,7 +668,7 @@ static struct qcom_icc_node qnm_camnoc_sf =3D { .buswidth =3D 32, .qosbox =3D &qnm_camnoc_sf_qos, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_mem_noc_sf }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static struct qcom_icc_qosbox qnm_mdp_qos =3D { @@ -685,7 +685,7 @@ static struct qcom_icc_node qnm_mdp =3D { .buswidth =3D 32, .qosbox =3D &qnm_mdp_qos, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_mem_noc_hf }, + .link_nodes =3D { &qns_mem_noc_hf }, }; =20 static struct qcom_icc_qosbox qnm_video_qos =3D { @@ -702,7 +702,7 @@ static struct qcom_icc_node qnm_video =3D { .buswidth =3D 32, .qosbox =3D &qnm_video_qos, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_mem_noc_sf }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static struct qcom_icc_node qsm_hf_mnoc_cfg =3D { @@ -710,7 +710,7 @@ static struct qcom_icc_node qsm_hf_mnoc_cfg =3D { .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &srvc_mnoc_hf }, + .link_nodes =3D { &srvc_mnoc_hf }, }; =20 static struct qcom_icc_node qsm_sf_mnoc_cfg =3D { @@ -718,7 +718,7 @@ static struct qcom_icc_node qsm_sf_mnoc_cfg =3D { .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &srvc_mnoc_sf }, + .link_nodes =3D { &srvc_mnoc_sf }, }; =20 static struct qcom_icc_node qxm_nsp =3D { @@ -726,7 +726,7 @@ static struct qcom_icc_node qxm_nsp =3D { .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_nsp_gemnoc }, + .link_nodes =3D { &qns_nsp_gemnoc }, }; =20 static struct qcom_icc_node qsm_pcie_anoc_cfg =3D { @@ -734,7 +734,7 @@ static struct qcom_icc_node qsm_pcie_anoc_cfg =3D { .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &srvc_pcie_aggre_noc }, + .link_nodes =3D { &srvc_pcie_aggre_noc }, }; =20 static struct qcom_icc_qosbox xm_pcie3_0_qos =3D { @@ -751,7 +751,7 @@ static struct qcom_icc_node xm_pcie3_0 =3D { .buswidth =3D 8, .qosbox =3D &xm_pcie3_0_qos, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_pcie_mem_noc }, + .link_nodes =3D { &qns_pcie_mem_noc }, }; =20 static struct qcom_icc_qosbox xm_pcie3_1_qos =3D { @@ -768,7 +768,7 @@ static struct qcom_icc_node xm_pcie3_1 =3D { .buswidth =3D 8, .qosbox =3D &xm_pcie3_1_qos, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_pcie_mem_noc }, + .link_nodes =3D { &qns_pcie_mem_noc }, }; =20 static struct qcom_icc_node qnm_aggre1_noc =3D { @@ -776,7 +776,7 @@ static struct qcom_icc_node qnm_aggre1_noc =3D { .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_gemnoc_sf }, + .link_nodes =3D { &qns_gemnoc_sf }, }; =20 static struct qcom_icc_node qnm_aggre2_noc =3D { @@ -784,7 +784,7 @@ static struct qcom_icc_node qnm_aggre2_noc =3D { .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_gemnoc_sf }, + .link_nodes =3D { &qns_gemnoc_sf }, }; =20 static struct qcom_icc_qosbox qnm_apss_noc_qos =3D { @@ -801,7 +801,7 @@ static struct qcom_icc_node qnm_apss_noc =3D { .buswidth =3D 4, .qosbox =3D &qnm_apss_noc_qos, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_gemnoc_sf }, + .link_nodes =3D { &qns_gemnoc_sf }, }; =20 static struct qcom_icc_qosbox qnm_cnoc_data_qos =3D { @@ -818,7 +818,7 @@ static struct qcom_icc_node qnm_cnoc_data =3D { .buswidth =3D 8, .qosbox =3D &qnm_cnoc_data_qos, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_gemnoc_sf }, + .link_nodes =3D { &qns_gemnoc_sf }, }; =20 static struct qcom_icc_qosbox qxm_pimem_qos =3D { @@ -835,7 +835,7 @@ static struct qcom_icc_node qxm_pimem =3D { .buswidth =3D 8, .qosbox =3D &qxm_pimem_qos, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_gemnoc_gc }, + .link_nodes =3D { &qns_gemnoc_gc }, }; =20 static struct qcom_icc_qosbox xm_gic_qos =3D { @@ -852,7 +852,7 @@ static struct qcom_icc_node xm_gic =3D { .buswidth =3D 8, .qosbox =3D &xm_gic_qos, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_gemnoc_gc }, + .link_nodes =3D { &qns_gemnoc_gc }, }; =20 static struct qcom_icc_node qns_a1noc_snoc =3D { @@ -860,7 +860,7 @@ static struct qcom_icc_node qns_a1noc_snoc =3D { .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qnm_aggre1_noc }, + .link_nodes =3D { &qnm_aggre1_noc }, }; =20 static struct qcom_icc_node qns_a2noc_snoc =3D { @@ -868,7 +868,7 @@ static struct qcom_icc_node qns_a2noc_snoc =3D { .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qnm_aggre2_noc }, + .link_nodes =3D { &qnm_aggre2_noc }, }; =20 static struct qcom_icc_node qup0_core_slave =3D { @@ -1079,7 +1079,7 @@ static struct qcom_icc_node qss_mnoc_hf_cfg =3D { .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qsm_hf_mnoc_cfg }, + .link_nodes =3D { &qsm_hf_mnoc_cfg }, }; =20 static struct qcom_icc_node qss_mnoc_sf_cfg =3D { @@ -1087,7 +1087,7 @@ static struct qcom_icc_node qss_mnoc_sf_cfg =3D { .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qsm_sf_mnoc_cfg }, + .link_nodes =3D { &qsm_sf_mnoc_cfg }, }; =20 static struct qcom_icc_node qss_nsp_qtb_cfg =3D { @@ -1102,7 +1102,7 @@ static struct qcom_icc_node qss_pcie_anoc_cfg =3D { .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qsm_pcie_anoc_cfg }, + .link_nodes =3D { &qsm_pcie_anoc_cfg }, }; =20 static struct qcom_icc_node qss_wlan_q6_throttle_cfg =3D { @@ -1201,7 +1201,7 @@ static struct qcom_icc_node qss_cfg =3D { .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qsm_cfg }, + .link_nodes =3D { &qsm_cfg }, }; =20 static struct qcom_icc_node qss_ddrss_cfg =3D { @@ -1251,7 +1251,7 @@ static struct qcom_icc_node qns_gem_noc_cnoc =3D { .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qnm_gemnoc_cnoc }, + .link_nodes =3D { &qnm_gemnoc_cnoc }, }; =20 static struct qcom_icc_node qns_llcc =3D { @@ -1259,7 +1259,7 @@ static struct qcom_icc_node qns_llcc =3D { .channels =3D 2, .buswidth =3D 16, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &llcc_mc }, + .link_nodes =3D { &llcc_mc }, }; =20 static struct qcom_icc_node qns_pcie =3D { @@ -1267,7 +1267,7 @@ static struct qcom_icc_node qns_pcie =3D { .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qnm_gemnoc_pcie }, + .link_nodes =3D { &qnm_gemnoc_pcie }, }; =20 static struct qcom_icc_node qns_lpass_ag_noc_gemnoc =3D { @@ -1275,7 +1275,7 @@ static struct qcom_icc_node qns_lpass_ag_noc_gemnoc = =3D { .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qnm_lpass_gemnoc }, + .link_nodes =3D { &qnm_lpass_gemnoc }, }; =20 static struct qcom_icc_node ebi =3D { @@ -1290,7 +1290,7 @@ static struct qcom_icc_node qns_mem_noc_hf =3D { .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qnm_mnoc_hf }, + .link_nodes =3D { &qnm_mnoc_hf }, }; =20 static struct qcom_icc_node qns_mem_noc_sf =3D { @@ -1298,7 +1298,7 @@ static struct qcom_icc_node qns_mem_noc_sf =3D { .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qnm_mnoc_sf }, + .link_nodes =3D { &qnm_mnoc_sf }, }; =20 static struct qcom_icc_node srvc_mnoc_hf =3D { @@ -1320,7 +1320,7 @@ static struct qcom_icc_node qns_nsp_gemnoc =3D { .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qnm_nsp_gemnoc }, + .link_nodes =3D { &qnm_nsp_gemnoc }, }; =20 static struct qcom_icc_node qns_pcie_mem_noc =3D { @@ -1328,7 +1328,7 @@ static struct qcom_icc_node qns_pcie_mem_noc =3D { .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qnm_pcie }, + .link_nodes =3D { &qnm_pcie }, }; =20 static struct qcom_icc_node srvc_pcie_aggre_noc =3D { @@ -1343,7 +1343,7 @@ static struct qcom_icc_node qns_gemnoc_gc =3D { .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qnm_snoc_gc }, + .link_nodes =3D { &qnm_snoc_gc }, }; =20 static struct qcom_icc_node qns_gemnoc_sf =3D { @@ -1351,7 +1351,7 @@ static struct qcom_icc_node qns_gemnoc_sf =3D { .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qnm_snoc_sf }, + .link_nodes =3D { &qnm_snoc_sf }, }; =20 static struct qcom_icc_bcm bcm_acv =3D { diff --git a/drivers/interconnect/qcom/sa8775p.c b/drivers/interconnect/qco= m/sa8775p.c index 04b4abbf44875c767ac67c552b36a8c64a06b2c3..d144e8cb5d1e3a69410975bd6b7= abd9578c01407 100644 --- a/drivers/interconnect/qcom/sa8775p.c +++ b/drivers/interconnect/qcom/sa8775p.c @@ -214,7 +214,7 @@ static struct qcom_icc_node qxm_qup3 =3D { .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a1noc_snoc }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node xm_emac_0 =3D { @@ -222,7 +222,7 @@ static struct qcom_icc_node xm_emac_0 =3D { .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a1noc_snoc }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node xm_emac_1 =3D { @@ -230,7 +230,7 @@ static struct qcom_icc_node xm_emac_1 =3D { .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a1noc_snoc }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node xm_sdc1 =3D { @@ -238,7 +238,7 @@ static struct qcom_icc_node xm_sdc1 =3D { .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a1noc_snoc }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node xm_ufs_mem =3D { @@ -246,7 +246,7 @@ static struct qcom_icc_node xm_ufs_mem =3D { .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a1noc_snoc }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node xm_usb2_2 =3D { @@ -254,7 +254,7 @@ static struct qcom_icc_node xm_usb2_2 =3D { .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a1noc_snoc }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node xm_usb3_0 =3D { @@ -262,7 +262,7 @@ static struct qcom_icc_node xm_usb3_0 =3D { .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a1noc_snoc }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node xm_usb3_1 =3D { @@ -270,7 +270,7 @@ static struct qcom_icc_node xm_usb3_1 =3D { .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a1noc_snoc }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node qhm_qdss_bam =3D { @@ -278,7 +278,7 @@ static struct qcom_icc_node qhm_qdss_bam =3D { .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qhm_qup0 =3D { @@ -286,7 +286,7 @@ static struct qcom_icc_node qhm_qup0 =3D { .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qhm_qup1 =3D { @@ -294,7 +294,7 @@ static struct qcom_icc_node qhm_qup1 =3D { .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qhm_qup2 =3D { @@ -302,7 +302,7 @@ static struct qcom_icc_node qhm_qup2 =3D { .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qnm_cnoc_datapath =3D { @@ -310,7 +310,7 @@ static struct qcom_icc_node qnm_cnoc_datapath =3D { .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qxm_crypto_0 =3D { @@ -318,7 +318,7 @@ static struct qcom_icc_node qxm_crypto_0 =3D { .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qxm_crypto_1 =3D { @@ -326,7 +326,7 @@ static struct qcom_icc_node qxm_crypto_1 =3D { .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qxm_ipa =3D { @@ -334,7 +334,7 @@ static struct qcom_icc_node qxm_ipa =3D { .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node xm_qdss_etr_0 =3D { @@ -342,7 +342,7 @@ static struct qcom_icc_node xm_qdss_etr_0 =3D { .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node xm_qdss_etr_1 =3D { @@ -350,7 +350,7 @@ static struct qcom_icc_node xm_qdss_etr_1 =3D { .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node xm_ufs_card =3D { @@ -358,7 +358,7 @@ static struct qcom_icc_node xm_ufs_card =3D { .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qup0_core_master =3D { @@ -366,7 +366,7 @@ static struct qcom_icc_node qup0_core_master =3D { .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qup0_core_slave }, + .link_nodes =3D { &qup0_core_slave }, }; =20 static struct qcom_icc_node qup1_core_master =3D { @@ -374,7 +374,7 @@ static struct qcom_icc_node qup1_core_master =3D { .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qup1_core_slave }, + .link_nodes =3D { &qup1_core_slave }, }; =20 static struct qcom_icc_node qup2_core_master =3D { @@ -382,7 +382,7 @@ static struct qcom_icc_node qup2_core_master =3D { .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qup2_core_slave }, + .link_nodes =3D { &qup2_core_slave }, }; =20 static struct qcom_icc_node qup3_core_master =3D { @@ -390,7 +390,7 @@ static struct qcom_icc_node qup3_core_master =3D { .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qup3_core_slave }, + .link_nodes =3D { &qup3_core_slave }, }; =20 static struct qcom_icc_node qnm_gemnoc_cnoc =3D { @@ -398,7 +398,7 @@ static struct qcom_icc_node qnm_gemnoc_cnoc =3D { .channels =3D 1, .buswidth =3D 16, .num_links =3D 82, - .link_nodes =3D (struct qcom_icc_node *[]) { &qhs_ahb2phy0, &qhs_ahb2phy1, + .link_nodes =3D { &qhs_ahb2phy0, &qhs_ahb2phy1, &qhs_ahb2phy2, &qhs_ahb2phy3, &qhs_anoc_throttle_cfg, &qhs_aoss, &qhs_apss, &qhs_boot_rom, @@ -446,7 +446,7 @@ static struct qcom_icc_node qnm_gemnoc_pcie =3D { .channels =3D 1, .buswidth =3D 16, .num_links =3D 2, - .link_nodes =3D (struct qcom_icc_node *[]) { &xs_pcie_0, &xs_pcie_1 }, + .link_nodes =3D { &xs_pcie_0, &xs_pcie_1 }, }; =20 static struct qcom_icc_node qnm_cnoc_dc_noc =3D { @@ -454,7 +454,7 @@ static struct qcom_icc_node qnm_cnoc_dc_noc =3D { .channels =3D 1, .buswidth =3D 4, .num_links =3D 2, - .link_nodes =3D (struct qcom_icc_node *[]) { &qhs_llcc, &qns_gemnoc }, + .link_nodes =3D { &qhs_llcc, &qns_gemnoc }, }; =20 static struct qcom_icc_node alm_gpu_tcu =3D { @@ -462,7 +462,7 @@ static struct qcom_icc_node alm_gpu_tcu =3D { .channels =3D 1, .buswidth =3D 8, .num_links =3D 2, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc= }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; =20 static struct qcom_icc_node alm_pcie_tcu =3D { @@ -470,7 +470,7 @@ static struct qcom_icc_node alm_pcie_tcu =3D { .channels =3D 1, .buswidth =3D 8, .num_links =3D 2, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc= }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; =20 static struct qcom_icc_node alm_sys_tcu =3D { @@ -478,7 +478,7 @@ static struct qcom_icc_node alm_sys_tcu =3D { .channels =3D 1, .buswidth =3D 8, .num_links =3D 2, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc= }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; =20 static struct qcom_icc_node chm_apps =3D { @@ -486,7 +486,7 @@ static struct qcom_icc_node chm_apps =3D { .channels =3D 4, .buswidth =3D 32, .num_links =3D 3, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc, &qns_pcie }, }; =20 @@ -495,7 +495,7 @@ static struct qcom_icc_node qnm_cmpnoc0 =3D { .channels =3D 2, .buswidth =3D 32, .num_links =3D 2, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc= }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; =20 static struct qcom_icc_node qnm_cmpnoc1 =3D { @@ -503,7 +503,7 @@ static struct qcom_icc_node qnm_cmpnoc1 =3D { .channels =3D 2, .buswidth =3D 32, .num_links =3D 2, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc= }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; =20 static struct qcom_icc_node qnm_gemnoc_cfg =3D { @@ -511,7 +511,7 @@ static struct qcom_icc_node qnm_gemnoc_cfg =3D { .channels =3D 1, .buswidth =3D 4, .num_links =3D 4, - .link_nodes =3D (struct qcom_icc_node *[]) { &srvc_even_gemnoc, &srvc_odd= _gemnoc, + .link_nodes =3D { &srvc_even_gemnoc, &srvc_odd_gemnoc, &srvc_sys_gemnoc, &srvc_sys_gemnoc_2 }, }; =20 @@ -520,7 +520,7 @@ static struct qcom_icc_node qnm_gpdsp_sail =3D { .channels =3D 1, .buswidth =3D 16, .num_links =3D 2, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc= }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; =20 static struct qcom_icc_node qnm_gpu =3D { @@ -528,7 +528,7 @@ static struct qcom_icc_node qnm_gpu =3D { .channels =3D 2, .buswidth =3D 32, .num_links =3D 2, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc= }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; =20 static struct qcom_icc_node qnm_mnoc_hf =3D { @@ -536,7 +536,7 @@ static struct qcom_icc_node qnm_mnoc_hf =3D { .channels =3D 2, .buswidth =3D 32, .num_links =3D 2, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_llcc, &qns_pcie }, + .link_nodes =3D { &qns_llcc, &qns_pcie }, }; =20 static struct qcom_icc_node qnm_mnoc_sf =3D { @@ -544,7 +544,7 @@ static struct qcom_icc_node qnm_mnoc_sf =3D { .channels =3D 2, .buswidth =3D 32, .num_links =3D 3, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc, &qns_pcie }, }; =20 @@ -553,7 +553,7 @@ static struct qcom_icc_node qnm_pcie =3D { .channels =3D 1, .buswidth =3D 32, .num_links =3D 2, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc= }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; =20 static struct qcom_icc_node qnm_snoc_gc =3D { @@ -561,7 +561,7 @@ static struct qcom_icc_node qnm_snoc_gc =3D { .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_llcc }, + .link_nodes =3D { &qns_llcc }, }; =20 static struct qcom_icc_node qnm_snoc_sf =3D { @@ -569,7 +569,7 @@ static struct qcom_icc_node qnm_snoc_sf =3D { .channels =3D 1, .buswidth =3D 16, .num_links =3D 3, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc, &qns_pcie }, }; =20 @@ -578,7 +578,7 @@ static struct qcom_icc_node qxm_dsp0 =3D { .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_gp_dsp_sail_noc }, + .link_nodes =3D { &qns_gp_dsp_sail_noc }, }; =20 static struct qcom_icc_node qxm_dsp1 =3D { @@ -586,7 +586,7 @@ static struct qcom_icc_node qxm_dsp1 =3D { .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_gp_dsp_sail_noc }, + .link_nodes =3D { &qns_gp_dsp_sail_noc }, }; =20 static struct qcom_icc_node qhm_config_noc =3D { @@ -594,7 +594,7 @@ static struct qcom_icc_node qhm_config_noc =3D { .channels =3D 1, .buswidth =3D 4, .num_links =3D 6, - .link_nodes =3D (struct qcom_icc_node *[]) { &qhs_lpass_core, &qhs_lpass_= lpi, + .link_nodes =3D { &qhs_lpass_core, &qhs_lpass_lpi, &qhs_lpass_mpu, &qhs_lpass_top, &srvc_niu_aml_noc, &srvc_niu_lpass_agnoc }, }; @@ -604,7 +604,7 @@ static struct qcom_icc_node qxm_lpass_dsp =3D { .channels =3D 1, .buswidth =3D 8, .num_links =3D 4, - .link_nodes =3D (struct qcom_icc_node *[]) { &qhs_lpass_top, &qns_sysnoc, + .link_nodes =3D { &qhs_lpass_top, &qns_sysnoc, &srvc_niu_aml_noc, &srvc_niu_lpass_agnoc }, }; =20 @@ -613,7 +613,7 @@ static struct qcom_icc_node llcc_mc =3D { .channels =3D 8, .buswidth =3D 4, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &ebi }, + .link_nodes =3D { &ebi }, }; =20 static struct qcom_icc_node qnm_camnoc_hf =3D { @@ -621,7 +621,7 @@ static struct qcom_icc_node qnm_camnoc_hf =3D { .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_mem_noc_hf }, + .link_nodes =3D { &qns_mem_noc_hf }, }; =20 static struct qcom_icc_node qnm_camnoc_icp =3D { @@ -629,7 +629,7 @@ static struct qcom_icc_node qnm_camnoc_icp =3D { .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_mem_noc_sf }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static struct qcom_icc_node qnm_camnoc_sf =3D { @@ -637,7 +637,7 @@ static struct qcom_icc_node qnm_camnoc_sf =3D { .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_mem_noc_sf }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static struct qcom_icc_node qnm_mdp0_0 =3D { @@ -645,7 +645,7 @@ static struct qcom_icc_node qnm_mdp0_0 =3D { .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_mem_noc_hf }, + .link_nodes =3D { &qns_mem_noc_hf }, }; =20 static struct qcom_icc_node qnm_mdp0_1 =3D { @@ -653,7 +653,7 @@ static struct qcom_icc_node qnm_mdp0_1 =3D { .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_mem_noc_hf }, + .link_nodes =3D { &qns_mem_noc_hf }, }; =20 static struct qcom_icc_node qnm_mdp1_0 =3D { @@ -661,7 +661,7 @@ static struct qcom_icc_node qnm_mdp1_0 =3D { .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_mem_noc_hf }, + .link_nodes =3D { &qns_mem_noc_hf }, }; =20 static struct qcom_icc_node qnm_mdp1_1 =3D { @@ -669,7 +669,7 @@ static struct qcom_icc_node qnm_mdp1_1 =3D { .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_mem_noc_hf }, + .link_nodes =3D { &qns_mem_noc_hf }, }; =20 static struct qcom_icc_node qnm_mnoc_hf_cfg =3D { @@ -677,7 +677,7 @@ static struct qcom_icc_node qnm_mnoc_hf_cfg =3D { .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &srvc_mnoc_hf }, + .link_nodes =3D { &srvc_mnoc_hf }, }; =20 static struct qcom_icc_node qnm_mnoc_sf_cfg =3D { @@ -685,7 +685,7 @@ static struct qcom_icc_node qnm_mnoc_sf_cfg =3D { .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &srvc_mnoc_sf }, + .link_nodes =3D { &srvc_mnoc_sf }, }; =20 static struct qcom_icc_node qnm_video0 =3D { @@ -693,7 +693,7 @@ static struct qcom_icc_node qnm_video0 =3D { .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_mem_noc_sf }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static struct qcom_icc_node qnm_video1 =3D { @@ -701,7 +701,7 @@ static struct qcom_icc_node qnm_video1 =3D { .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_mem_noc_sf }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static struct qcom_icc_node qnm_video_cvp =3D { @@ -709,7 +709,7 @@ static struct qcom_icc_node qnm_video_cvp =3D { .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_mem_noc_sf }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static struct qcom_icc_node qnm_video_v_cpu =3D { @@ -717,7 +717,7 @@ static struct qcom_icc_node qnm_video_v_cpu =3D { .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_mem_noc_sf }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static struct qcom_icc_node qhm_nsp_noc_config =3D { @@ -725,7 +725,7 @@ static struct qcom_icc_node qhm_nsp_noc_config =3D { .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &service_nsp_noc }, + .link_nodes =3D { &service_nsp_noc }, }; =20 static struct qcom_icc_node qxm_nsp =3D { @@ -733,7 +733,7 @@ static struct qcom_icc_node qxm_nsp =3D { .channels =3D 2, .buswidth =3D 32, .num_links =3D 2, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_hcp, &qns_nsp_gemnoc }, + .link_nodes =3D { &qns_hcp, &qns_nsp_gemnoc }, }; =20 static struct qcom_icc_node qhm_nspb_noc_config =3D { @@ -741,7 +741,7 @@ static struct qcom_icc_node qhm_nspb_noc_config =3D { .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &service_nspb_noc }, + .link_nodes =3D { &service_nspb_noc }, }; =20 static struct qcom_icc_node qxm_nspb =3D { @@ -749,7 +749,7 @@ static struct qcom_icc_node qxm_nspb =3D { .channels =3D 2, .buswidth =3D 32, .num_links =3D 2, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_nspb_hcp, &qns_nspb_gem= noc }, + .link_nodes =3D { &qns_nspb_hcp, &qns_nspb_gemnoc }, }; =20 static struct qcom_icc_node xm_pcie3_0 =3D { @@ -757,7 +757,7 @@ static struct qcom_icc_node xm_pcie3_0 =3D { .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_pcie_mem_noc }, + .link_nodes =3D { &qns_pcie_mem_noc }, }; =20 static struct qcom_icc_node xm_pcie3_1 =3D { @@ -765,7 +765,7 @@ static struct qcom_icc_node xm_pcie3_1 =3D { .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_pcie_mem_noc }, + .link_nodes =3D { &qns_pcie_mem_noc }, }; =20 static struct qcom_icc_node qhm_gic =3D { @@ -773,7 +773,7 @@ static struct qcom_icc_node qhm_gic =3D { .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_gemnoc_sf }, + .link_nodes =3D { &qns_gemnoc_sf }, }; =20 static struct qcom_icc_node qnm_aggre1_noc =3D { @@ -781,7 +781,7 @@ static struct qcom_icc_node qnm_aggre1_noc =3D { .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_gemnoc_sf }, + .link_nodes =3D { &qns_gemnoc_sf }, }; =20 static struct qcom_icc_node qnm_aggre2_noc =3D { @@ -789,7 +789,7 @@ static struct qcom_icc_node qnm_aggre2_noc =3D { .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_gemnoc_sf }, + .link_nodes =3D { &qns_gemnoc_sf }, }; =20 static struct qcom_icc_node qnm_lpass_noc =3D { @@ -797,7 +797,7 @@ static struct qcom_icc_node qnm_lpass_noc =3D { .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_gemnoc_sf }, + .link_nodes =3D { &qns_gemnoc_sf }, }; =20 static struct qcom_icc_node qnm_snoc_cfg =3D { @@ -805,7 +805,7 @@ static struct qcom_icc_node qnm_snoc_cfg =3D { .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &srvc_snoc }, + .link_nodes =3D { &srvc_snoc }, }; =20 static struct qcom_icc_node qxm_pimem =3D { @@ -813,7 +813,7 @@ static struct qcom_icc_node qxm_pimem =3D { .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_gemnoc_gc }, + .link_nodes =3D { &qns_gemnoc_gc }, }; =20 static struct qcom_icc_node xm_gic =3D { @@ -821,7 +821,7 @@ static struct qcom_icc_node xm_gic =3D { .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_gemnoc_gc }, + .link_nodes =3D { &qns_gemnoc_gc }, }; =20 static struct qcom_icc_node qns_a1noc_snoc =3D { @@ -829,7 +829,7 @@ static struct qcom_icc_node qns_a1noc_snoc =3D { .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qnm_aggre1_noc }, + .link_nodes =3D { &qnm_aggre1_noc }, }; =20 static struct qcom_icc_node qns_a2noc_snoc =3D { @@ -837,7 +837,7 @@ static struct qcom_icc_node qns_a2noc_snoc =3D { .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qnm_aggre2_noc }, + .link_nodes =3D { &qnm_aggre2_noc }, }; =20 static struct qcom_icc_node qup0_core_slave =3D { @@ -941,7 +941,7 @@ static struct qcom_icc_node qhs_compute0_cfg =3D { .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qhm_nsp_noc_config }, + .link_nodes =3D { &qhm_nsp_noc_config }, }; =20 static struct qcom_icc_node qhs_compute1_cfg =3D { @@ -949,7 +949,7 @@ static struct qcom_icc_node qhs_compute1_cfg =3D { .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qhm_nspb_noc_config }, + .link_nodes =3D { &qhm_nspb_noc_config }, }; =20 static struct qcom_icc_node qhs_cpr_cx =3D { @@ -1089,7 +1089,7 @@ static struct qcom_icc_node qhs_lpass_cfg =3D { .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qhm_config_noc }, + .link_nodes =3D { &qhm_config_noc }, }; =20 static struct qcom_icc_node qhs_lpass_throttle_cfg =3D { @@ -1301,7 +1301,7 @@ static struct qcom_icc_node qns_ddrss_cfg =3D { .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qnm_cnoc_dc_noc }, + .link_nodes =3D { &qnm_cnoc_dc_noc }, }; =20 static struct qcom_icc_node qns_gpdsp_noc_cfg =3D { @@ -1315,7 +1315,7 @@ static struct qcom_icc_node qns_mnoc_hf_cfg =3D { .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qnm_mnoc_hf_cfg }, + .link_nodes =3D { &qnm_mnoc_hf_cfg }, }; =20 static struct qcom_icc_node qns_mnoc_sf_cfg =3D { @@ -1323,7 +1323,7 @@ static struct qcom_icc_node qns_mnoc_sf_cfg =3D { .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qnm_mnoc_sf_cfg }, + .link_nodes =3D { &qnm_mnoc_sf_cfg }, }; =20 static struct qcom_icc_node qns_pcie_anoc_cfg =3D { @@ -1337,7 +1337,7 @@ static struct qcom_icc_node qns_snoc_cfg =3D { .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qnm_snoc_cfg }, + .link_nodes =3D { &qnm_snoc_cfg }, }; =20 static struct qcom_icc_node qxs_boot_imem =3D { @@ -1393,7 +1393,7 @@ static struct qcom_icc_node qns_gemnoc =3D { .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qnm_gemnoc_cfg }, + .link_nodes =3D { &qnm_gemnoc_cfg }, }; =20 static struct qcom_icc_node qns_gem_noc_cnoc =3D { @@ -1401,7 +1401,7 @@ static struct qcom_icc_node qns_gem_noc_cnoc =3D { .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qnm_gemnoc_cnoc }, + .link_nodes =3D { &qnm_gemnoc_cnoc }, }; =20 static struct qcom_icc_node qns_llcc =3D { @@ -1409,7 +1409,7 @@ static struct qcom_icc_node qns_llcc =3D { .channels =3D 6, .buswidth =3D 16, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &llcc_mc }, + .link_nodes =3D { &llcc_mc }, }; =20 static struct qcom_icc_node qns_pcie =3D { @@ -1417,7 +1417,7 @@ static struct qcom_icc_node qns_pcie =3D { .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qnm_gemnoc_pcie }, + .link_nodes =3D { &qnm_gemnoc_pcie }, }; =20 static struct qcom_icc_node srvc_even_gemnoc =3D { @@ -1449,7 +1449,7 @@ static struct qcom_icc_node qns_gp_dsp_sail_noc =3D { .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qnm_gpdsp_sail }, + .link_nodes =3D { &qnm_gpdsp_sail }, }; =20 static struct qcom_icc_node qhs_lpass_core =3D { @@ -1481,7 +1481,7 @@ static struct qcom_icc_node qns_sysnoc =3D { .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qnm_lpass_noc }, + .link_nodes =3D { &qnm_lpass_noc }, }; =20 static struct qcom_icc_node srvc_niu_aml_noc =3D { @@ -1507,7 +1507,7 @@ static struct qcom_icc_node qns_mem_noc_hf =3D { .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qnm_mnoc_hf }, + .link_nodes =3D { &qnm_mnoc_hf }, }; =20 static struct qcom_icc_node qns_mem_noc_sf =3D { @@ -1515,7 +1515,7 @@ static struct qcom_icc_node qns_mem_noc_sf =3D { .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qnm_mnoc_sf }, + .link_nodes =3D { &qnm_mnoc_sf }, }; =20 static struct qcom_icc_node srvc_mnoc_hf =3D { @@ -1541,7 +1541,7 @@ static struct qcom_icc_node qns_nsp_gemnoc =3D { .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qnm_cmpnoc0 }, + .link_nodes =3D { &qnm_cmpnoc0 }, }; =20 static struct qcom_icc_node service_nsp_noc =3D { @@ -1555,7 +1555,7 @@ static struct qcom_icc_node qns_nspb_gemnoc =3D { .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qnm_cmpnoc1 }, + .link_nodes =3D { &qnm_cmpnoc1 }, }; =20 static struct qcom_icc_node qns_nspb_hcp =3D { @@ -1575,7 +1575,7 @@ static struct qcom_icc_node qns_pcie_mem_noc =3D { .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qnm_pcie }, + .link_nodes =3D { &qnm_pcie }, }; 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This gives more flexibility and also allows us to drop the .num_links member, saving from possible errors related to it being not set or set incorrectly. Signed-off-by: Dmitry Baryshkov --- drivers/interconnect/qcom/sc7280.c | 629 +++++++++++++++++----------------= ---- drivers/interconnect/qcom/sc7280.h | 154 --------- 2 files changed, 287 insertions(+), 496 deletions(-) diff --git a/drivers/interconnect/qcom/sc7280.c b/drivers/interconnect/qcom= /sc7280.c index 905403a3a930a2e1cd01f62e375e60c6b2d524f7..3dc8b81f917d5de69f67112bd31= 3326b4658f77c 100644 --- a/drivers/interconnect/qcom/sc7280.c +++ b/drivers/interconnect/qcom/sc7280.c @@ -15,11 +15,152 @@ =20 #include "bcm-voter.h" #include "icc-rpmh.h" -#include "sc7280.h" + +static struct qcom_icc_node qhm_qspi; +static struct qcom_icc_node qhm_qup0; +static struct qcom_icc_node qhm_qup1; +static struct qcom_icc_node qnm_a1noc_cfg; +static struct qcom_icc_node xm_sdc1; +static struct qcom_icc_node xm_sdc2; +static struct qcom_icc_node xm_sdc4; +static struct qcom_icc_node xm_ufs_mem; +static struct qcom_icc_node xm_usb2; +static struct qcom_icc_node xm_usb3_0; +static struct qcom_icc_node qhm_qdss_bam; +static struct qcom_icc_node qnm_a2noc_cfg; +static struct qcom_icc_node qnm_cnoc_datapath; +static struct qcom_icc_node qxm_crypto; +static struct qcom_icc_node qxm_ipa; +static struct qcom_icc_node xm_pcie3_0; +static struct qcom_icc_node xm_pcie3_1; +static struct qcom_icc_node xm_qdss_etr; +static struct qcom_icc_node qup0_core_master; +static struct qcom_icc_node qup1_core_master; +static struct qcom_icc_node qnm_cnoc3_cnoc2; +static struct qcom_icc_node xm_qdss_dap; +static struct qcom_icc_node qnm_cnoc2_cnoc3; +static struct qcom_icc_node qnm_gemnoc_cnoc; +static struct qcom_icc_node qnm_gemnoc_pcie; +static struct qcom_icc_node qnm_cnoc_dc_noc; +static struct qcom_icc_node alm_gpu_tcu; +static struct qcom_icc_node alm_sys_tcu; +static struct qcom_icc_node chm_apps; +static struct qcom_icc_node qnm_cmpnoc; +static struct qcom_icc_node qnm_gemnoc_cfg; +static struct qcom_icc_node qnm_gpu; +static struct qcom_icc_node qnm_mnoc_hf; +static struct qcom_icc_node qnm_mnoc_sf; +static struct qcom_icc_node qnm_pcie; +static struct qcom_icc_node qnm_snoc_gc; +static struct qcom_icc_node qnm_snoc_sf; +static struct qcom_icc_node qhm_config_noc; +static struct qcom_icc_node llcc_mc; +static struct qcom_icc_node qnm_mnoc_cfg; +static struct qcom_icc_node qnm_video0; +static struct qcom_icc_node qnm_video_cpu; +static struct qcom_icc_node qxm_camnoc_hf; +static struct qcom_icc_node qxm_camnoc_icp; +static struct qcom_icc_node qxm_camnoc_sf; +static struct qcom_icc_node qxm_mdp0; +static struct qcom_icc_node qhm_nsp_noc_config; +static struct qcom_icc_node qxm_nsp; +static struct qcom_icc_node qnm_aggre1_noc; +static struct qcom_icc_node qnm_aggre2_noc; +static struct qcom_icc_node qnm_snoc_cfg; +static struct qcom_icc_node qxm_pimem; +static struct qcom_icc_node xm_gic; +static struct qcom_icc_node qns_a1noc_snoc; +static struct qcom_icc_node srvc_aggre1_noc; +static struct qcom_icc_node qns_a2noc_snoc; +static struct qcom_icc_node qns_pcie_mem_noc; +static struct qcom_icc_node srvc_aggre2_noc; +static struct qcom_icc_node qup0_core_slave; +static struct qcom_icc_node qup1_core_slave; +static struct qcom_icc_node qhs_ahb2phy0; +static struct qcom_icc_node qhs_ahb2phy1; +static struct qcom_icc_node qhs_camera_cfg; +static struct qcom_icc_node qhs_clk_ctl; +static struct qcom_icc_node qhs_compute_cfg; +static struct qcom_icc_node qhs_cpr_cx; +static struct qcom_icc_node qhs_cpr_mx; +static struct qcom_icc_node qhs_crypto0_cfg; +static struct qcom_icc_node qhs_cx_rdpm; +static struct qcom_icc_node qhs_dcc_cfg; +static struct qcom_icc_node qhs_display_cfg; +static struct qcom_icc_node qhs_gpuss_cfg; +static struct qcom_icc_node qhs_hwkm; +static struct qcom_icc_node qhs_imem_cfg; +static struct qcom_icc_node qhs_ipa; +static struct qcom_icc_node qhs_ipc_router; +static struct qcom_icc_node qhs_lpass_cfg; +static struct qcom_icc_node qhs_mss_cfg; +static struct qcom_icc_node qhs_mx_rdpm; +static struct qcom_icc_node qhs_pcie0_cfg; +static struct qcom_icc_node qhs_pcie1_cfg; +static struct qcom_icc_node qhs_pdm; +static struct qcom_icc_node qhs_pimem_cfg; +static struct qcom_icc_node qhs_pka_wrapper_cfg; +static struct qcom_icc_node qhs_pmu_wrapper_cfg; +static struct qcom_icc_node qhs_qdss_cfg; +static struct qcom_icc_node qhs_qspi; +static struct qcom_icc_node qhs_qup0; +static struct qcom_icc_node qhs_qup1; +static struct qcom_icc_node qhs_sdc1; +static struct qcom_icc_node qhs_sdc2; +static struct qcom_icc_node qhs_sdc4; +static struct qcom_icc_node qhs_security; +static struct qcom_icc_node qhs_tcsr; +static struct qcom_icc_node qhs_tlmm; +static struct qcom_icc_node qhs_ufs_mem_cfg; +static struct qcom_icc_node qhs_usb2; +static struct qcom_icc_node qhs_usb3_0; +static struct qcom_icc_node qhs_venus_cfg; +static struct qcom_icc_node qhs_vsense_ctrl_cfg; +static struct qcom_icc_node qns_a1_noc_cfg; +static struct qcom_icc_node qns_a2_noc_cfg; +static struct qcom_icc_node qns_cnoc2_cnoc3; +static struct qcom_icc_node qns_mnoc_cfg; +static struct qcom_icc_node qns_snoc_cfg; +static struct qcom_icc_node qhs_aoss; +static struct qcom_icc_node qhs_apss; +static struct qcom_icc_node qns_cnoc3_cnoc2; +static struct qcom_icc_node qns_cnoc_a2noc; +static struct qcom_icc_node qns_ddrss_cfg; +static struct qcom_icc_node qxs_boot_imem; +static struct qcom_icc_node qxs_imem; +static struct qcom_icc_node qxs_pimem; +static struct qcom_icc_node xs_pcie_0; +static struct qcom_icc_node xs_pcie_1; +static struct qcom_icc_node xs_qdss_stm; +static struct qcom_icc_node xs_sys_tcu_cfg; +static struct qcom_icc_node qhs_llcc; +static struct qcom_icc_node qns_gemnoc; +static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg; +static struct qcom_icc_node qhs_modem_ms_mpu_cfg; +static struct qcom_icc_node qns_gem_noc_cnoc; +static struct qcom_icc_node qns_llcc; +static struct qcom_icc_node qns_pcie; +static struct qcom_icc_node srvc_even_gemnoc; +static struct qcom_icc_node srvc_odd_gemnoc; +static struct qcom_icc_node srvc_sys_gemnoc; +static struct qcom_icc_node qhs_lpass_core; +static struct qcom_icc_node qhs_lpass_lpi; +static struct qcom_icc_node qhs_lpass_mpu; +static struct qcom_icc_node qhs_lpass_top; +static struct qcom_icc_node srvc_niu_aml_noc; +static struct qcom_icc_node srvc_niu_lpass_agnoc; +static struct qcom_icc_node ebi; +static struct qcom_icc_node qns_mem_noc_hf; +static struct qcom_icc_node qns_mem_noc_sf; +static struct qcom_icc_node srvc_mnoc; +static struct qcom_icc_node qns_nsp_gemnoc; +static struct qcom_icc_node service_nsp_noc; +static struct qcom_icc_node qns_gemnoc_gc; +static struct qcom_icc_node qns_gemnoc_sf; +static struct qcom_icc_node srvc_snoc; =20 static struct qcom_icc_node qhm_qspi =3D { .name =3D "qhm_qspi", - .id =3D SC7280_MASTER_QSPI_0, .channels =3D 1, .buswidth =3D 4, .qosbox =3D &(const struct qcom_icc_qosbox) { @@ -29,12 +170,11 @@ static struct qcom_icc_node qhm_qspi =3D { .urg_fwd =3D 0, }, .num_links =3D 1, - .links =3D { SC7280_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node qhm_qup0 =3D { .name =3D "qhm_qup0", - .id =3D SC7280_MASTER_QUP_0, .channels =3D 1, .buswidth =3D 4, .qosbox =3D &(const struct qcom_icc_qosbox) { @@ -44,12 +184,11 @@ static struct qcom_icc_node qhm_qup0 =3D { .urg_fwd =3D 0, }, .num_links =3D 1, - .links =3D { SC7280_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node qhm_qup1 =3D { .name =3D "qhm_qup1", - .id =3D SC7280_MASTER_QUP_1, .channels =3D 1, .buswidth =3D 4, .qosbox =3D &(const struct qcom_icc_qosbox) { @@ -59,21 +198,19 @@ static struct qcom_icc_node qhm_qup1 =3D { .urg_fwd =3D 0, }, .num_links =3D 1, - .links =3D { SC7280_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node qnm_a1noc_cfg =3D { .name =3D "qnm_a1noc_cfg", - .id =3D SC7280_MASTER_A1NOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SC7280_SLAVE_SERVICE_A1NOC }, + .link_nodes =3D { &srvc_aggre1_noc }, }; =20 static struct qcom_icc_node xm_sdc1 =3D { .name =3D "xm_sdc1", - .id =3D SC7280_MASTER_SDCC_1, .channels =3D 1, .buswidth =3D 8, .qosbox =3D &(const struct qcom_icc_qosbox) { @@ -83,12 +220,11 @@ static struct qcom_icc_node xm_sdc1 =3D { .urg_fwd =3D 0, }, .num_links =3D 1, - .links =3D { SC7280_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node xm_sdc2 =3D { .name =3D "xm_sdc2", - .id =3D SC7280_MASTER_SDCC_2, .channels =3D 1, .buswidth =3D 8, .qosbox =3D &(const struct qcom_icc_qosbox) { @@ -98,12 +234,11 @@ static struct qcom_icc_node xm_sdc2 =3D { .urg_fwd =3D 0, }, .num_links =3D 1, - .links =3D { SC7280_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node xm_sdc4 =3D { .name =3D "xm_sdc4", - .id =3D SC7280_MASTER_SDCC_4, .channels =3D 1, .buswidth =3D 8, .qosbox =3D &(const struct qcom_icc_qosbox) { @@ -113,12 +248,11 @@ static struct qcom_icc_node xm_sdc4 =3D { .urg_fwd =3D 0, }, .num_links =3D 1, - .links =3D { SC7280_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node xm_ufs_mem =3D { .name =3D "xm_ufs_mem", - .id =3D SC7280_MASTER_UFS_MEM, .channels =3D 1, .buswidth =3D 8, .qosbox =3D &(const struct qcom_icc_qosbox) { @@ -128,21 +262,19 @@ static struct qcom_icc_node xm_ufs_mem =3D { .urg_fwd =3D 0, }, .num_links =3D 1, - .links =3D { SC7280_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node xm_usb2 =3D { .name =3D "xm_usb2", - .id =3D SC7280_MASTER_USB2, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SC7280_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node xm_usb3_0 =3D { .name =3D "xm_usb3_0", - .id =3D SC7280_MASTER_USB3_0, .channels =3D 1, .buswidth =3D 8, .qosbox =3D &(const struct qcom_icc_qosbox) { @@ -152,12 +284,11 @@ static struct qcom_icc_node xm_usb3_0 =3D { .urg_fwd =3D 0, }, .num_links =3D 1, - .links =3D { SC7280_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node qhm_qdss_bam =3D { .name =3D "qhm_qdss_bam", - .id =3D SC7280_MASTER_QDSS_BAM, .channels =3D 1, .buswidth =3D 4, .qosbox =3D &(const struct qcom_icc_qosbox) { @@ -167,21 +298,19 @@ static struct qcom_icc_node qhm_qdss_bam =3D { .urg_fwd =3D 0, }, .num_links =3D 1, - .links =3D { SC7280_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qnm_a2noc_cfg =3D { .name =3D "qnm_a2noc_cfg", - .id =3D SC7280_MASTER_A2NOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SC7280_SLAVE_SERVICE_A2NOC }, + .link_nodes =3D { &srvc_aggre2_noc }, }; =20 static struct qcom_icc_node qnm_cnoc_datapath =3D { .name =3D "qnm_cnoc_datapath", - .id =3D SC7280_MASTER_CNOC_A2NOC, .channels =3D 1, .buswidth =3D 8, .qosbox =3D &(const struct qcom_icc_qosbox) { @@ -191,12 +320,11 @@ static struct qcom_icc_node qnm_cnoc_datapath =3D { .urg_fwd =3D 0, }, .num_links =3D 1, - .links =3D { SC7280_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qxm_crypto =3D { .name =3D "qxm_crypto", - .id =3D SC7280_MASTER_CRYPTO, .channels =3D 1, .buswidth =3D 8, .qosbox =3D &(const struct qcom_icc_qosbox) { @@ -206,12 +334,11 @@ static struct qcom_icc_node qxm_crypto =3D { .urg_fwd =3D 0, }, .num_links =3D 1, - .links =3D { SC7280_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qxm_ipa =3D { .name =3D "qxm_ipa", - .id =3D SC7280_MASTER_IPA, .channels =3D 1, .buswidth =3D 8, .qosbox =3D &(const struct qcom_icc_qosbox) { @@ -221,30 +348,27 @@ static struct qcom_icc_node qxm_ipa =3D { .urg_fwd =3D 0, }, .num_links =3D 1, - .links =3D { SC7280_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node xm_pcie3_0 =3D { .name =3D "xm_pcie3_0", - .id =3D SC7280_MASTER_PCIE_0, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SC7280_SLAVE_ANOC_PCIE_GEM_NOC }, + .link_nodes =3D { &qns_pcie_mem_noc }, }; =20 static struct qcom_icc_node xm_pcie3_1 =3D { .name =3D "xm_pcie3_1", - .id =3D SC7280_MASTER_PCIE_1, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SC7280_SLAVE_ANOC_PCIE_GEM_NOC }, + .link_nodes =3D { &qns_pcie_mem_noc }, }; =20 static struct qcom_icc_node xm_qdss_etr =3D { .name =3D "xm_qdss_etr", - .id =3D SC7280_MASTER_QDSS_ETR, .channels =3D 1, .buswidth =3D 8, .qosbox =3D &(const struct qcom_icc_qosbox) { @@ -254,135 +378,126 @@ static struct qcom_icc_node xm_qdss_etr =3D { .urg_fwd =3D 0, }, .num_links =3D 1, - .links =3D { SC7280_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qup0_core_master =3D { .name =3D "qup0_core_master", - .id =3D SC7280_MASTER_QUP_CORE_0, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SC7280_SLAVE_QUP_CORE_0 }, + .link_nodes =3D { &qup0_core_slave }, }; =20 static struct qcom_icc_node qup1_core_master =3D { .name =3D "qup1_core_master", - .id =3D SC7280_MASTER_QUP_CORE_1, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SC7280_SLAVE_QUP_CORE_1 }, + .link_nodes =3D { &qup1_core_slave }, }; =20 static struct qcom_icc_node qnm_cnoc3_cnoc2 =3D { .name =3D "qnm_cnoc3_cnoc2", - .id =3D SC7280_MASTER_CNOC3_CNOC2, .channels =3D 1, .buswidth =3D 8, .num_links =3D 44, - .links =3D { SC7280_SLAVE_AHB2PHY_SOUTH, SC7280_SLAVE_AHB2PHY_NORTH, - SC7280_SLAVE_CAMERA_CFG, SC7280_SLAVE_CLK_CTL, - SC7280_SLAVE_CDSP_CFG, SC7280_SLAVE_RBCPR_CX_CFG, - SC7280_SLAVE_RBCPR_MX_CFG, SC7280_SLAVE_CRYPTO_0_CFG, - SC7280_SLAVE_CX_RDPM, SC7280_SLAVE_DCC_CFG, - SC7280_SLAVE_DISPLAY_CFG, SC7280_SLAVE_GFX3D_CFG, - SC7280_SLAVE_HWKM, SC7280_SLAVE_IMEM_CFG, - SC7280_SLAVE_IPA_CFG, SC7280_SLAVE_IPC_ROUTER_CFG, - SC7280_SLAVE_LPASS, SC7280_SLAVE_CNOC_MSS, - SC7280_SLAVE_MX_RDPM, SC7280_SLAVE_PCIE_0_CFG, - SC7280_SLAVE_PCIE_1_CFG, SC7280_SLAVE_PDM, - SC7280_SLAVE_PIMEM_CFG, SC7280_SLAVE_PKA_WRAPPER_CFG, - SC7280_SLAVE_PMU_WRAPPER_CFG, SC7280_SLAVE_QDSS_CFG, - SC7280_SLAVE_QSPI_0, SC7280_SLAVE_QUP_0, - SC7280_SLAVE_QUP_1, SC7280_SLAVE_SDCC_1, - SC7280_SLAVE_SDCC_2, SC7280_SLAVE_SDCC_4, - SC7280_SLAVE_SECURITY, SC7280_SLAVE_TCSR, - SC7280_SLAVE_TLMM, SC7280_SLAVE_UFS_MEM_CFG, - SC7280_SLAVE_USB2, SC7280_SLAVE_USB3_0, - SC7280_SLAVE_VENUS_CFG, SC7280_SLAVE_VSENSE_CTRL_CFG, - SC7280_SLAVE_A1NOC_CFG, SC7280_SLAVE_A2NOC_CFG, - SC7280_SLAVE_CNOC_MNOC_CFG, SC7280_SLAVE_SNOC_CFG }, + .link_nodes =3D { &qhs_ahb2phy0, &qhs_ahb2phy1, + &qhs_camera_cfg, &qhs_clk_ctl, + &qhs_compute_cfg, &qhs_cpr_cx, + &qhs_cpr_mx, &qhs_crypto0_cfg, + &qhs_cx_rdpm, &qhs_dcc_cfg, + &qhs_display_cfg, &qhs_gpuss_cfg, + &qhs_hwkm, &qhs_imem_cfg, + &qhs_ipa, &qhs_ipc_router, + &qhs_lpass_cfg, &qhs_mss_cfg, + &qhs_mx_rdpm, &qhs_pcie0_cfg, + &qhs_pcie1_cfg, &qhs_pdm, + &qhs_pimem_cfg, &qhs_pka_wrapper_cfg, + &qhs_pmu_wrapper_cfg, &qhs_qdss_cfg, + &qhs_qspi, &qhs_qup0, + &qhs_qup1, &qhs_sdc1, + &qhs_sdc2, &qhs_sdc4, + &qhs_security, &qhs_tcsr, + &qhs_tlmm, &qhs_ufs_mem_cfg, + &qhs_usb2, &qhs_usb3_0, + &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, + &qns_a1_noc_cfg, &qns_a2_noc_cfg, + &qns_mnoc_cfg, &qns_snoc_cfg }, }; =20 static struct qcom_icc_node xm_qdss_dap =3D { .name =3D "xm_qdss_dap", - .id =3D SC7280_MASTER_QDSS_DAP, .channels =3D 1, .buswidth =3D 8, .num_links =3D 45, - .links =3D { SC7280_SLAVE_AHB2PHY_SOUTH, SC7280_SLAVE_AHB2PHY_NORTH, - SC7280_SLAVE_CAMERA_CFG, SC7280_SLAVE_CLK_CTL, - SC7280_SLAVE_CDSP_CFG, SC7280_SLAVE_RBCPR_CX_CFG, - SC7280_SLAVE_RBCPR_MX_CFG, SC7280_SLAVE_CRYPTO_0_CFG, - SC7280_SLAVE_CX_RDPM, SC7280_SLAVE_DCC_CFG, - SC7280_SLAVE_DISPLAY_CFG, SC7280_SLAVE_GFX3D_CFG, - SC7280_SLAVE_HWKM, SC7280_SLAVE_IMEM_CFG, - SC7280_SLAVE_IPA_CFG, SC7280_SLAVE_IPC_ROUTER_CFG, - SC7280_SLAVE_LPASS, SC7280_SLAVE_CNOC_MSS, - SC7280_SLAVE_MX_RDPM, SC7280_SLAVE_PCIE_0_CFG, - SC7280_SLAVE_PCIE_1_CFG, SC7280_SLAVE_PDM, - SC7280_SLAVE_PIMEM_CFG, SC7280_SLAVE_PKA_WRAPPER_CFG, - SC7280_SLAVE_PMU_WRAPPER_CFG, SC7280_SLAVE_QDSS_CFG, - SC7280_SLAVE_QSPI_0, SC7280_SLAVE_QUP_0, - SC7280_SLAVE_QUP_1, SC7280_SLAVE_SDCC_1, - SC7280_SLAVE_SDCC_2, SC7280_SLAVE_SDCC_4, - SC7280_SLAVE_SECURITY, SC7280_SLAVE_TCSR, - SC7280_SLAVE_TLMM, SC7280_SLAVE_UFS_MEM_CFG, - SC7280_SLAVE_USB2, SC7280_SLAVE_USB3_0, - SC7280_SLAVE_VENUS_CFG, SC7280_SLAVE_VSENSE_CTRL_CFG, - SC7280_SLAVE_A1NOC_CFG, SC7280_SLAVE_A2NOC_CFG, - SC7280_SLAVE_CNOC2_CNOC3, SC7280_SLAVE_CNOC_MNOC_CFG, - SC7280_SLAVE_SNOC_CFG }, + .link_nodes =3D { &qhs_ahb2phy0, &qhs_ahb2phy1, + &qhs_camera_cfg, &qhs_clk_ctl, + &qhs_compute_cfg, &qhs_cpr_cx, + &qhs_cpr_mx, &qhs_crypto0_cfg, + &qhs_cx_rdpm, &qhs_dcc_cfg, + &qhs_display_cfg, &qhs_gpuss_cfg, + &qhs_hwkm, &qhs_imem_cfg, + &qhs_ipa, &qhs_ipc_router, + &qhs_lpass_cfg, &qhs_mss_cfg, + &qhs_mx_rdpm, &qhs_pcie0_cfg, + &qhs_pcie1_cfg, &qhs_pdm, + &qhs_pimem_cfg, &qhs_pka_wrapper_cfg, + &qhs_pmu_wrapper_cfg, &qhs_qdss_cfg, + &qhs_qspi, &qhs_qup0, + &qhs_qup1, &qhs_sdc1, + &qhs_sdc2, &qhs_sdc4, + &qhs_security, &qhs_tcsr, + &qhs_tlmm, &qhs_ufs_mem_cfg, + &qhs_usb2, &qhs_usb3_0, + &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, + &qns_a1_noc_cfg, &qns_a2_noc_cfg, + &qns_cnoc2_cnoc3, &qns_mnoc_cfg, + &qns_snoc_cfg }, }; =20 static struct qcom_icc_node qnm_cnoc2_cnoc3 =3D { .name =3D "qnm_cnoc2_cnoc3", - .id =3D SC7280_MASTER_CNOC2_CNOC3, .channels =3D 1, .buswidth =3D 8, .num_links =3D 9, - .links =3D { SC7280_SLAVE_AOSS, SC7280_SLAVE_APPSS, - SC7280_SLAVE_CNOC_A2NOC, SC7280_SLAVE_DDRSS_CFG, - SC7280_SLAVE_BOOT_IMEM, SC7280_SLAVE_IMEM, - SC7280_SLAVE_PIMEM, SC7280_SLAVE_QDSS_STM, - SC7280_SLAVE_TCU }, + .link_nodes =3D { &qhs_aoss, &qhs_apss, + &qns_cnoc_a2noc, &qns_ddrss_cfg, + &qxs_boot_imem, &qxs_imem, + &qxs_pimem, &xs_qdss_stm, + &xs_sys_tcu_cfg }, }; =20 static struct qcom_icc_node qnm_gemnoc_cnoc =3D { .name =3D "qnm_gemnoc_cnoc", - .id =3D SC7280_MASTER_GEM_NOC_CNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 9, - .links =3D { SC7280_SLAVE_AOSS, SC7280_SLAVE_APPSS, - SC7280_SLAVE_CNOC3_CNOC2, SC7280_SLAVE_DDRSS_CFG, - SC7280_SLAVE_BOOT_IMEM, SC7280_SLAVE_IMEM, - SC7280_SLAVE_PIMEM, SC7280_SLAVE_QDSS_STM, - SC7280_SLAVE_TCU }, + .link_nodes =3D { &qhs_aoss, &qhs_apss, + &qns_cnoc3_cnoc2, &qns_ddrss_cfg, + &qxs_boot_imem, &qxs_imem, + &qxs_pimem, &xs_qdss_stm, + &xs_sys_tcu_cfg }, }; =20 static struct qcom_icc_node qnm_gemnoc_pcie =3D { .name =3D "qnm_gemnoc_pcie", - .id =3D SC7280_MASTER_GEM_NOC_PCIE_SNOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 2, - .links =3D { SC7280_SLAVE_PCIE_0, SC7280_SLAVE_PCIE_1 }, + .link_nodes =3D { &xs_pcie_0, &xs_pcie_1 }, }; =20 static struct qcom_icc_node qnm_cnoc_dc_noc =3D { .name =3D "qnm_cnoc_dc_noc", - .id =3D SC7280_MASTER_CNOC_DC_NOC, .channels =3D 1, .buswidth =3D 4, .num_links =3D 2, - .links =3D { SC7280_SLAVE_LLCC_CFG, SC7280_SLAVE_GEM_NOC_CFG }, + .link_nodes =3D { &qhs_llcc, &qns_gemnoc }, }; =20 static struct qcom_icc_node alm_gpu_tcu =3D { .name =3D "alm_gpu_tcu", - .id =3D SC7280_MASTER_GPU_TCU, .channels =3D 1, .buswidth =3D 8, .qosbox =3D &(const struct qcom_icc_qosbox) { @@ -392,12 +507,11 @@ static struct qcom_icc_node alm_gpu_tcu =3D { .urg_fwd =3D 0, }, .num_links =3D 2, - .links =3D { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; =20 static struct qcom_icc_node alm_sys_tcu =3D { .name =3D "alm_sys_tcu", - .id =3D SC7280_MASTER_SYS_TCU, .channels =3D 1, .buswidth =3D 8, .qosbox =3D &(const struct qcom_icc_qosbox) { @@ -407,22 +521,20 @@ static struct qcom_icc_node alm_sys_tcu =3D { .urg_fwd =3D 0, }, .num_links =3D 2, - .links =3D { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; =20 static struct qcom_icc_node chm_apps =3D { .name =3D "chm_apps", - .id =3D SC7280_MASTER_APPSS_PROC, .channels =3D 1, .buswidth =3D 32, .num_links =3D 3, - .links =3D { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC, - SC7280_SLAVE_MEM_NOC_PCIE_SNOC }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, }; =20 static struct qcom_icc_node qnm_cmpnoc =3D { .name =3D "qnm_cmpnoc", - .id =3D SC7280_MASTER_COMPUTE_NOC, .channels =3D 2, .buswidth =3D 32, .qosbox =3D &(const struct qcom_icc_qosbox) { @@ -432,23 +544,21 @@ static struct qcom_icc_node qnm_cmpnoc =3D { .urg_fwd =3D 1, }, .num_links =3D 2, - .links =3D { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; =20 static struct qcom_icc_node qnm_gemnoc_cfg =3D { .name =3D "qnm_gemnoc_cfg", - .id =3D SC7280_MASTER_GEM_NOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 5, - .links =3D { SC7280_SLAVE_MSS_PROC_MS_MPU_CFG, SC7280_SLAVE_MCDMA_MS_MPU_= CFG, - SC7280_SLAVE_SERVICE_GEM_NOC_1, SC7280_SLAVE_SERVICE_GEM_NOC_2, - SC7280_SLAVE_SERVICE_GEM_NOC }, + .link_nodes =3D { &qhs_mdsp_ms_mpu_cfg, &qhs_modem_ms_mpu_cfg, + &srvc_even_gemnoc, &srvc_odd_gemnoc, + &srvc_sys_gemnoc }, }; =20 static struct qcom_icc_node qnm_gpu =3D { .name =3D "qnm_gpu", - .id =3D SC7280_MASTER_GFX3D, .channels =3D 2, .buswidth =3D 32, .qosbox =3D &(const struct qcom_icc_qosbox) { @@ -458,12 +568,11 @@ static struct qcom_icc_node qnm_gpu =3D { .urg_fwd =3D 0, }, .num_links =3D 2, - .links =3D { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; =20 static struct qcom_icc_node qnm_mnoc_hf =3D { .name =3D "qnm_mnoc_hf", - .id =3D SC7280_MASTER_MNOC_HF_MEM_NOC, .channels =3D 2, .buswidth =3D 32, .qosbox =3D &(const struct qcom_icc_qosbox) { @@ -473,12 +582,11 @@ static struct qcom_icc_node qnm_mnoc_hf =3D { .urg_fwd =3D 1, }, .num_links =3D 1, - .links =3D { SC7280_SLAVE_LLCC }, + .link_nodes =3D { &qns_llcc }, }; =20 static struct qcom_icc_node qnm_mnoc_sf =3D { .name =3D "qnm_mnoc_sf", - .id =3D SC7280_MASTER_MNOC_SF_MEM_NOC, .channels =3D 1, .buswidth =3D 32, .qosbox =3D &(const struct qcom_icc_qosbox) { @@ -488,21 +596,19 @@ static struct qcom_icc_node qnm_mnoc_sf =3D { .urg_fwd =3D 1, }, .num_links =3D 2, - .links =3D { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; =20 static struct qcom_icc_node qnm_pcie =3D { .name =3D "qnm_pcie", - .id =3D SC7280_MASTER_ANOC_PCIE_GEM_NOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 2, - .links =3D { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; =20 static struct qcom_icc_node qnm_snoc_gc =3D { .name =3D "qnm_snoc_gc", - .id =3D SC7280_MASTER_SNOC_GC_MEM_NOC, .channels =3D 1, .buswidth =3D 8, .qosbox =3D &(const struct qcom_icc_qosbox) { @@ -512,12 +618,11 @@ static struct qcom_icc_node qnm_snoc_gc =3D { .urg_fwd =3D 1, }, .num_links =3D 1, - .links =3D { SC7280_SLAVE_LLCC }, + .link_nodes =3D { &qns_llcc }, }; =20 static struct qcom_icc_node qnm_snoc_sf =3D { .name =3D "qnm_snoc_sf", - .id =3D SC7280_MASTER_SNOC_SF_MEM_NOC, .channels =3D 1, .buswidth =3D 16, .qosbox =3D &(const struct qcom_icc_qosbox) { @@ -527,42 +632,38 @@ static struct qcom_icc_node qnm_snoc_sf =3D { .urg_fwd =3D 1, }, .num_links =3D 3, - .links =3D { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC, - SC7280_SLAVE_MEM_NOC_PCIE_SNOC }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, }; =20 static struct qcom_icc_node qhm_config_noc =3D { .name =3D "qhm_config_noc", - .id =3D SC7280_MASTER_CNOC_LPASS_AG_NOC, .channels =3D 1, .buswidth =3D 4, .num_links =3D 6, - .links =3D { SC7280_SLAVE_LPASS_CORE_CFG, SC7280_SLAVE_LPASS_LPI_CFG, - SC7280_SLAVE_LPASS_MPU_CFG, SC7280_SLAVE_LPASS_TOP_CFG, - SC7280_SLAVE_SERVICES_LPASS_AML_NOC, SC7280_SLAVE_SERVICE_LPASS_AG_NO= C }, + .link_nodes =3D { &qhs_lpass_core, &qhs_lpass_lpi, + &qhs_lpass_mpu, &qhs_lpass_top, + &srvc_niu_aml_noc, &srvc_niu_lpass_agnoc }, }; =20 static struct qcom_icc_node llcc_mc =3D { .name =3D "llcc_mc", - .id =3D SC7280_MASTER_LLCC, .channels =3D 2, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SC7280_SLAVE_EBI1 }, + .link_nodes =3D { &ebi }, }; =20 static struct qcom_icc_node qnm_mnoc_cfg =3D { .name =3D "qnm_mnoc_cfg", - .id =3D SC7280_MASTER_CNOC_MNOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SC7280_SLAVE_SERVICE_MNOC }, + .link_nodes =3D { &srvc_mnoc }, }; =20 static struct qcom_icc_node qnm_video0 =3D { .name =3D "qnm_video0", - .id =3D SC7280_MASTER_VIDEO_P0, .channels =3D 1, .buswidth =3D 32, .qosbox =3D &(const struct qcom_icc_qosbox) { @@ -572,12 +673,11 @@ static struct qcom_icc_node qnm_video0 =3D { .urg_fwd =3D 1, }, .num_links =3D 1, - .links =3D { SC7280_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static struct qcom_icc_node qnm_video_cpu =3D { .name =3D "qnm_video_cpu", - .id =3D SC7280_MASTER_VIDEO_PROC, .channels =3D 1, .buswidth =3D 8, .qosbox =3D &(const struct qcom_icc_qosbox) { @@ -587,12 +687,11 @@ static struct qcom_icc_node qnm_video_cpu =3D { .urg_fwd =3D 1, }, .num_links =3D 1, - .links =3D { SC7280_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static struct qcom_icc_node qxm_camnoc_hf =3D { .name =3D "qxm_camnoc_hf", - .id =3D SC7280_MASTER_CAMNOC_HF, .channels =3D 2, .buswidth =3D 32, .qosbox =3D &(const struct qcom_icc_qosbox) { @@ -602,12 +701,11 @@ static struct qcom_icc_node qxm_camnoc_hf =3D { .urg_fwd =3D 1, }, .num_links =3D 1, - .links =3D { SC7280_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_hf }, }; =20 static struct qcom_icc_node qxm_camnoc_icp =3D { .name =3D "qxm_camnoc_icp", - .id =3D SC7280_MASTER_CAMNOC_ICP, .channels =3D 1, .buswidth =3D 8, .qosbox =3D &(const struct qcom_icc_qosbox) { @@ -617,12 +715,11 @@ static struct qcom_icc_node qxm_camnoc_icp =3D { .urg_fwd =3D 1, }, .num_links =3D 1, - .links =3D { SC7280_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static struct qcom_icc_node qxm_camnoc_sf =3D { .name =3D "qxm_camnoc_sf", - .id =3D SC7280_MASTER_CAMNOC_SF, .channels =3D 1, .buswidth =3D 32, .qosbox =3D &(const struct qcom_icc_qosbox) { @@ -632,12 +729,11 @@ static struct qcom_icc_node qxm_camnoc_sf =3D { .urg_fwd =3D 1, }, .num_links =3D 1, - .links =3D { SC7280_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static struct qcom_icc_node qxm_mdp0 =3D { .name =3D "qxm_mdp0", - .id =3D SC7280_MASTER_MDP0, .channels =3D 1, .buswidth =3D 32, .qosbox =3D &(const struct qcom_icc_qosbox) { @@ -647,57 +743,51 @@ static struct qcom_icc_node qxm_mdp0 =3D { .urg_fwd =3D 1, }, .num_links =3D 1, - .links =3D { SC7280_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_hf }, }; =20 static struct qcom_icc_node qhm_nsp_noc_config =3D { .name =3D "qhm_nsp_noc_config", - .id =3D SC7280_MASTER_CDSP_NOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SC7280_SLAVE_SERVICE_NSP_NOC }, + .link_nodes =3D { &service_nsp_noc }, }; =20 static struct qcom_icc_node qxm_nsp =3D { .name =3D "qxm_nsp", - .id =3D SC7280_MASTER_CDSP_PROC, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SC7280_SLAVE_CDSP_MEM_NOC }, + .link_nodes =3D { &qns_nsp_gemnoc }, }; =20 static struct qcom_icc_node qnm_aggre1_noc =3D { .name =3D "qnm_aggre1_noc", - .id =3D SC7280_MASTER_A1NOC_SNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SC7280_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes =3D { &qns_gemnoc_sf }, }; =20 static struct qcom_icc_node qnm_aggre2_noc =3D { .name =3D "qnm_aggre2_noc", - .id =3D SC7280_MASTER_A2NOC_SNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SC7280_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes =3D { &qns_gemnoc_sf }, }; =20 static struct qcom_icc_node qnm_snoc_cfg =3D { .name =3D "qnm_snoc_cfg", - .id =3D SC7280_MASTER_SNOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SC7280_SLAVE_SERVICE_SNOC }, + .link_nodes =3D { &srvc_snoc }, }; =20 static struct qcom_icc_node qxm_pimem =3D { .name =3D "qxm_pimem", - .id =3D SC7280_MASTER_PIMEM, .channels =3D 1, .buswidth =3D 8, .qosbox =3D &(const struct qcom_icc_qosbox) { @@ -707,12 +797,11 @@ static struct qcom_icc_node qxm_pimem =3D { .urg_fwd =3D 0, }, .num_links =3D 1, - .links =3D { SC7280_SLAVE_SNOC_GEM_NOC_GC }, + .link_nodes =3D { &qns_gemnoc_gc }, }; =20 static struct qcom_icc_node xm_gic =3D { .name =3D "xm_gic", - .id =3D SC7280_MASTER_GIC, .channels =3D 1, .buswidth =3D 8, .qosbox =3D &(const struct qcom_icc_qosbox) { @@ -722,741 +811,585 @@ static struct qcom_icc_node xm_gic =3D { .urg_fwd =3D 0, }, .num_links =3D 1, - .links =3D { SC7280_SLAVE_SNOC_GEM_NOC_GC }, + .link_nodes =3D { &qns_gemnoc_gc }, }; =20 static struct qcom_icc_node qns_a1noc_snoc =3D { .name =3D "qns_a1noc_snoc", - .id =3D SC7280_SLAVE_A1NOC_SNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SC7280_MASTER_A1NOC_SNOC }, + .link_nodes =3D { &qnm_aggre1_noc }, }; =20 static struct qcom_icc_node srvc_aggre1_noc =3D { .name =3D "srvc_aggre1_noc", - .id =3D SC7280_SLAVE_SERVICE_A1NOC, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qns_a2noc_snoc =3D { .name =3D "qns_a2noc_snoc", - .id =3D SC7280_SLAVE_A2NOC_SNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SC7280_MASTER_A2NOC_SNOC }, + .link_nodes =3D { &qnm_aggre2_noc }, }; =20 static struct qcom_icc_node qns_pcie_mem_noc =3D { .name =3D "qns_pcie_mem_noc", - .id =3D SC7280_SLAVE_ANOC_PCIE_GEM_NOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SC7280_MASTER_ANOC_PCIE_GEM_NOC }, + .link_nodes =3D { &qnm_pcie }, }; =20 static struct qcom_icc_node srvc_aggre2_noc =3D { .name =3D "srvc_aggre2_noc", - .id =3D SC7280_SLAVE_SERVICE_A2NOC, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qup0_core_slave =3D { .name =3D "qup0_core_slave", - .id =3D SC7280_SLAVE_QUP_CORE_0, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qup1_core_slave =3D { .name =3D "qup1_core_slave", - .id =3D SC7280_SLAVE_QUP_CORE_1, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_ahb2phy0 =3D { .name =3D "qhs_ahb2phy0", - .id =3D SC7280_SLAVE_AHB2PHY_SOUTH, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_ahb2phy1 =3D { .name =3D "qhs_ahb2phy1", - .id =3D SC7280_SLAVE_AHB2PHY_NORTH, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_camera_cfg =3D { .name =3D "qhs_camera_cfg", - .id =3D SC7280_SLAVE_CAMERA_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_clk_ctl =3D { .name =3D "qhs_clk_ctl", - .id =3D SC7280_SLAVE_CLK_CTL, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_compute_cfg =3D { .name =3D "qhs_compute_cfg", - .id =3D SC7280_SLAVE_CDSP_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SC7280_MASTER_CDSP_NOC_CFG }, + .link_nodes =3D { &qhm_nsp_noc_config }, }; =20 static struct qcom_icc_node qhs_cpr_cx =3D { .name =3D "qhs_cpr_cx", - .id =3D SC7280_SLAVE_RBCPR_CX_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_cpr_mx =3D { .name =3D "qhs_cpr_mx", - .id =3D SC7280_SLAVE_RBCPR_MX_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_crypto0_cfg =3D { .name =3D "qhs_crypto0_cfg", - .id =3D SC7280_SLAVE_CRYPTO_0_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_cx_rdpm =3D { .name =3D "qhs_cx_rdpm", - .id =3D SC7280_SLAVE_CX_RDPM, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_dcc_cfg =3D { .name =3D "qhs_dcc_cfg", - .id =3D SC7280_SLAVE_DCC_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_display_cfg =3D { .name =3D "qhs_display_cfg", - .id =3D SC7280_SLAVE_DISPLAY_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_gpuss_cfg =3D { .name =3D "qhs_gpuss_cfg", - .id =3D SC7280_SLAVE_GFX3D_CFG, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_hwkm =3D { .name =3D "qhs_hwkm", - .id =3D SC7280_SLAVE_HWKM, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_imem_cfg =3D { .name =3D "qhs_imem_cfg", - .id =3D SC7280_SLAVE_IMEM_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_ipa =3D { .name =3D "qhs_ipa", - .id =3D SC7280_SLAVE_IPA_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_ipc_router =3D { .name =3D "qhs_ipc_router", - .id =3D SC7280_SLAVE_IPC_ROUTER_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_lpass_cfg =3D { .name =3D "qhs_lpass_cfg", - .id =3D SC7280_SLAVE_LPASS, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SC7280_MASTER_CNOC_LPASS_AG_NOC }, + .link_nodes =3D { &qhm_config_noc }, }; =20 static struct qcom_icc_node qhs_mss_cfg =3D { .name =3D "qhs_mss_cfg", - .id =3D SC7280_SLAVE_CNOC_MSS, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_mx_rdpm =3D { .name =3D "qhs_mx_rdpm", - .id =3D SC7280_SLAVE_MX_RDPM, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_pcie0_cfg =3D { .name =3D "qhs_pcie0_cfg", - .id =3D SC7280_SLAVE_PCIE_0_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_pcie1_cfg =3D { .name =3D "qhs_pcie1_cfg", - .id =3D SC7280_SLAVE_PCIE_1_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_pdm =3D { .name =3D "qhs_pdm", - .id =3D SC7280_SLAVE_PDM, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_pimem_cfg =3D { .name =3D "qhs_pimem_cfg", - .id =3D SC7280_SLAVE_PIMEM_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_pka_wrapper_cfg =3D { .name =3D "qhs_pka_wrapper_cfg", - .id =3D SC7280_SLAVE_PKA_WRAPPER_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_pmu_wrapper_cfg =3D { .name =3D "qhs_pmu_wrapper_cfg", - .id =3D SC7280_SLAVE_PMU_WRAPPER_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_qdss_cfg =3D { .name =3D "qhs_qdss_cfg", - .id =3D SC7280_SLAVE_QDSS_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_qspi =3D { .name =3D "qhs_qspi", - .id =3D SC7280_SLAVE_QSPI_0, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_qup0 =3D { .name =3D "qhs_qup0", - .id =3D SC7280_SLAVE_QUP_0, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_qup1 =3D { .name =3D "qhs_qup1", - .id =3D SC7280_SLAVE_QUP_1, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_sdc1 =3D { .name =3D "qhs_sdc1", - .id =3D SC7280_SLAVE_SDCC_1, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_sdc2 =3D { .name =3D "qhs_sdc2", - .id =3D SC7280_SLAVE_SDCC_2, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_sdc4 =3D { .name =3D "qhs_sdc4", - .id =3D SC7280_SLAVE_SDCC_4, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_security =3D { .name =3D "qhs_security", - .id =3D SC7280_SLAVE_SECURITY, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_tcsr =3D { .name =3D "qhs_tcsr", - .id =3D SC7280_SLAVE_TCSR, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_tlmm =3D { .name =3D "qhs_tlmm", - .id =3D SC7280_SLAVE_TLMM, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_ufs_mem_cfg =3D { .name =3D "qhs_ufs_mem_cfg", - .id =3D SC7280_SLAVE_UFS_MEM_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_usb2 =3D { .name =3D "qhs_usb2", - .id =3D SC7280_SLAVE_USB2, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_usb3_0 =3D { .name =3D "qhs_usb3_0", - .id =3D SC7280_SLAVE_USB3_0, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_venus_cfg =3D { .name =3D "qhs_venus_cfg", - .id =3D SC7280_SLAVE_VENUS_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_vsense_ctrl_cfg =3D { .name =3D "qhs_vsense_ctrl_cfg", - .id =3D SC7280_SLAVE_VSENSE_CTRL_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qns_a1_noc_cfg =3D { .name =3D "qns_a1_noc_cfg", - .id =3D SC7280_SLAVE_A1NOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SC7280_MASTER_A1NOC_CFG }, + .link_nodes =3D { &qnm_a1noc_cfg }, }; =20 static struct qcom_icc_node qns_a2_noc_cfg =3D { .name =3D "qns_a2_noc_cfg", - .id =3D SC7280_SLAVE_A2NOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SC7280_MASTER_A2NOC_CFG }, + .link_nodes =3D { &qnm_a2noc_cfg }, }; =20 static struct qcom_icc_node qns_cnoc2_cnoc3 =3D { .name =3D "qns_cnoc2_cnoc3", - .id =3D SC7280_SLAVE_CNOC2_CNOC3, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SC7280_MASTER_CNOC2_CNOC3 }, + .link_nodes =3D { &qnm_cnoc2_cnoc3 }, }; =20 static struct qcom_icc_node qns_mnoc_cfg =3D { .name =3D "qns_mnoc_cfg", - .id =3D SC7280_SLAVE_CNOC_MNOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SC7280_MASTER_CNOC_MNOC_CFG }, + .link_nodes =3D { &qnm_mnoc_cfg }, }; =20 static struct qcom_icc_node qns_snoc_cfg =3D { .name =3D "qns_snoc_cfg", - .id =3D SC7280_SLAVE_SNOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SC7280_MASTER_SNOC_CFG }, + .link_nodes =3D { &qnm_snoc_cfg }, }; =20 static struct qcom_icc_node qhs_aoss =3D { .name =3D "qhs_aoss", - .id =3D SC7280_SLAVE_AOSS, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_apss =3D { .name =3D "qhs_apss", - .id =3D SC7280_SLAVE_APPSS, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 0, }; =20 static struct qcom_icc_node qns_cnoc3_cnoc2 =3D { .name =3D "qns_cnoc3_cnoc2", - .id =3D SC7280_SLAVE_CNOC3_CNOC2, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SC7280_MASTER_CNOC3_CNOC2 }, + .link_nodes =3D { &qnm_cnoc3_cnoc2 }, }; =20 static struct qcom_icc_node qns_cnoc_a2noc =3D { .name =3D "qns_cnoc_a2noc", - .id =3D SC7280_SLAVE_CNOC_A2NOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SC7280_MASTER_CNOC_A2NOC }, + .link_nodes =3D { &qnm_cnoc_datapath }, }; =20 static struct qcom_icc_node qns_ddrss_cfg =3D { .name =3D "qns_ddrss_cfg", - .id =3D SC7280_SLAVE_DDRSS_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SC7280_MASTER_CNOC_DC_NOC }, + .link_nodes =3D { &qnm_cnoc_dc_noc }, }; =20 static struct qcom_icc_node qxs_boot_imem =3D { .name =3D "qxs_boot_imem", - .id =3D SC7280_SLAVE_BOOT_IMEM, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 0, }; =20 static struct qcom_icc_node qxs_imem =3D { .name =3D "qxs_imem", - .id =3D SC7280_SLAVE_IMEM, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 0, }; =20 static struct qcom_icc_node qxs_pimem =3D { .name =3D "qxs_pimem", - .id =3D SC7280_SLAVE_PIMEM, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 0, }; =20 static struct qcom_icc_node xs_pcie_0 =3D { .name =3D "xs_pcie_0", - .id =3D SC7280_SLAVE_PCIE_0, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 0, }; =20 static struct qcom_icc_node xs_pcie_1 =3D { .name =3D "xs_pcie_1", - .id =3D SC7280_SLAVE_PCIE_1, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 0, }; =20 static struct qcom_icc_node xs_qdss_stm =3D { .name =3D "xs_qdss_stm", - .id =3D SC7280_SLAVE_QDSS_STM, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node xs_sys_tcu_cfg =3D { .name =3D "xs_sys_tcu_cfg", - .id =3D SC7280_SLAVE_TCU, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_llcc =3D { .name =3D "qhs_llcc", - .id =3D SC7280_SLAVE_LLCC_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qns_gemnoc =3D { .name =3D "qns_gemnoc", - .id =3D SC7280_SLAVE_GEM_NOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SC7280_MASTER_GEM_NOC_CFG }, + .link_nodes =3D { &qnm_gemnoc_cfg }, }; =20 static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg =3D { .name =3D "qhs_mdsp_ms_mpu_cfg", - .id =3D SC7280_SLAVE_MSS_PROC_MS_MPU_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_modem_ms_mpu_cfg =3D { .name =3D "qhs_modem_ms_mpu_cfg", - .id =3D SC7280_SLAVE_MCDMA_MS_MPU_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qns_gem_noc_cnoc =3D { .name =3D "qns_gem_noc_cnoc", - .id =3D SC7280_SLAVE_GEM_NOC_CNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SC7280_MASTER_GEM_NOC_CNOC }, + .link_nodes =3D { &qnm_gemnoc_cnoc }, }; =20 static struct qcom_icc_node qns_llcc =3D { .name =3D "qns_llcc", - .id =3D SC7280_SLAVE_LLCC, .channels =3D 2, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SC7280_MASTER_LLCC }, + .link_nodes =3D { &llcc_mc }, }; =20 static struct qcom_icc_node qns_pcie =3D { .name =3D "qns_pcie", - .id =3D SC7280_SLAVE_MEM_NOC_PCIE_SNOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SC7280_MASTER_GEM_NOC_PCIE_SNOC }, + .link_nodes =3D { &qnm_gemnoc_pcie }, }; =20 static struct qcom_icc_node srvc_even_gemnoc =3D { .name =3D "srvc_even_gemnoc", - .id =3D SC7280_SLAVE_SERVICE_GEM_NOC_1, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node srvc_odd_gemnoc =3D { .name =3D "srvc_odd_gemnoc", - .id =3D SC7280_SLAVE_SERVICE_GEM_NOC_2, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node srvc_sys_gemnoc =3D { .name =3D "srvc_sys_gemnoc", - .id =3D SC7280_SLAVE_SERVICE_GEM_NOC, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_lpass_core =3D { .name =3D "qhs_lpass_core", - .id =3D SC7280_SLAVE_LPASS_CORE_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_lpass_lpi =3D { .name =3D "qhs_lpass_lpi", - .id =3D SC7280_SLAVE_LPASS_LPI_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_lpass_mpu =3D { .name =3D "qhs_lpass_mpu", - .id =3D SC7280_SLAVE_LPASS_MPU_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_lpass_top =3D { .name =3D "qhs_lpass_top", - .id =3D SC7280_SLAVE_LPASS_TOP_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node srvc_niu_aml_noc =3D { .name =3D "srvc_niu_aml_noc", - .id =3D SC7280_SLAVE_SERVICES_LPASS_AML_NOC, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node srvc_niu_lpass_agnoc =3D { .name =3D "srvc_niu_lpass_agnoc", - .id =3D SC7280_SLAVE_SERVICE_LPASS_AG_NOC, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node ebi =3D { .name =3D "ebi", - .id =3D SC7280_SLAVE_EBI1, .channels =3D 2, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qns_mem_noc_hf =3D { .name =3D "qns_mem_noc_hf", - .id =3D SC7280_SLAVE_MNOC_HF_MEM_NOC, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SC7280_MASTER_MNOC_HF_MEM_NOC }, + .link_nodes =3D { &qnm_mnoc_hf }, }; =20 static struct qcom_icc_node qns_mem_noc_sf =3D { .name =3D "qns_mem_noc_sf", - .id =3D SC7280_SLAVE_MNOC_SF_MEM_NOC, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SC7280_MASTER_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qnm_mnoc_sf }, }; =20 static struct qcom_icc_node srvc_mnoc =3D { .name =3D "srvc_mnoc", - .id =3D SC7280_SLAVE_SERVICE_MNOC, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qns_nsp_gemnoc =3D { .name =3D "qns_nsp_gemnoc", - .id =3D SC7280_SLAVE_CDSP_MEM_NOC, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SC7280_MASTER_COMPUTE_NOC }, + .link_nodes =3D { &qnm_cmpnoc }, }; =20 static struct qcom_icc_node service_nsp_noc =3D { .name =3D "service_nsp_noc", - .id =3D SC7280_SLAVE_SERVICE_NSP_NOC, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qns_gemnoc_gc =3D { .name =3D "qns_gemnoc_gc", - .id =3D SC7280_SLAVE_SNOC_GEM_NOC_GC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SC7280_MASTER_SNOC_GC_MEM_NOC }, + .link_nodes =3D { &qnm_snoc_gc }, }; =20 static struct qcom_icc_node qns_gemnoc_sf =3D { .name =3D "qns_gemnoc_sf", - .id =3D SC7280_SLAVE_SNOC_GEM_NOC_SF, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SC7280_MASTER_SNOC_SF_MEM_NOC }, + .link_nodes =3D { &qnm_snoc_sf }, }; =20 static struct qcom_icc_node srvc_snoc =3D { .name =3D "srvc_snoc", - .id =3D SC7280_SLAVE_SERVICE_SNOC, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_bcm bcm_acv =3D { @@ -1687,6 +1620,7 @@ static const struct regmap_config sc7280_aggre1_noc_r= egmap_config =3D { }; =20 static const struct qcom_icc_desc sc7280_aggre1_noc =3D { + .alloc_dyn_id =3D true, .config =3D &sc7280_aggre1_noc_regmap_config, .nodes =3D aggre1_noc_nodes, .num_nodes =3D ARRAY_SIZE(aggre1_noc_nodes), @@ -1719,6 +1653,7 @@ static struct qcom_icc_node * const aggre2_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sc7280_aggre2_noc =3D { + .alloc_dyn_id =3D true, .config =3D &sc7280_aggre2_noc_regmap_config, .nodes =3D aggre2_noc_nodes, .num_nodes =3D ARRAY_SIZE(aggre2_noc_nodes), @@ -1740,6 +1675,7 @@ static struct qcom_icc_node * const clk_virt_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sc7280_clk_virt =3D { + .alloc_dyn_id =3D true, .nodes =3D clk_virt_nodes, .num_nodes =3D ARRAY_SIZE(clk_virt_nodes), .bcms =3D clk_virt_bcms, @@ -1810,6 +1746,7 @@ static const struct regmap_config sc7280_cnoc2_regmap= _config =3D { }; =20 static const struct qcom_icc_desc sc7280_cnoc2 =3D { + .alloc_dyn_id =3D true, .config =3D &sc7280_cnoc2_regmap_config, .nodes =3D cnoc2_nodes, .num_nodes =3D ARRAY_SIZE(cnoc2_nodes), @@ -1851,6 +1788,7 @@ static const struct regmap_config sc7280_cnoc3_regmap= _config =3D { }; =20 static const struct qcom_icc_desc sc7280_cnoc3 =3D { + .alloc_dyn_id =3D true, .config =3D &sc7280_cnoc3_regmap_config, .nodes =3D cnoc3_nodes, .num_nodes =3D ARRAY_SIZE(cnoc3_nodes), @@ -1876,6 +1814,7 @@ static const struct regmap_config sc7280_dc_noc_regma= p_config =3D { }; =20 static const struct qcom_icc_desc sc7280_dc_noc =3D { + .alloc_dyn_id =3D true, .config =3D &sc7280_dc_noc_regmap_config, .nodes =3D dc_noc_nodes, .num_nodes =3D ARRAY_SIZE(dc_noc_nodes), @@ -1921,6 +1860,7 @@ static const struct regmap_config sc7280_gem_noc_regm= ap_config =3D { }; =20 static const struct qcom_icc_desc sc7280_gem_noc =3D { + .alloc_dyn_id =3D true, .config =3D &sc7280_gem_noc_regmap_config, .nodes =3D gem_noc_nodes, .num_nodes =3D ARRAY_SIZE(gem_noc_nodes), @@ -1950,6 +1890,7 @@ static const struct regmap_config sc7280_lpass_ag_noc= _regmap_config =3D { }; =20 static const struct qcom_icc_desc sc7280_lpass_ag_noc =3D { + .alloc_dyn_id =3D true, .config =3D &sc7280_lpass_ag_noc_regmap_config, .nodes =3D lpass_ag_noc_nodes, .num_nodes =3D ARRAY_SIZE(lpass_ag_noc_nodes), @@ -1976,6 +1917,7 @@ static const struct regmap_config sc7280_mc_virt_regm= ap_config =3D { }; =20 static const struct qcom_icc_desc sc7280_mc_virt =3D { + .alloc_dyn_id =3D true, .config =3D &sc7280_mc_virt_regmap_config, .nodes =3D mc_virt_nodes, .num_nodes =3D ARRAY_SIZE(mc_virt_nodes), @@ -2012,6 +1954,7 @@ static const struct regmap_config sc7280_mmss_noc_reg= map_config =3D { }; =20 static const struct qcom_icc_desc sc7280_mmss_noc =3D { + .alloc_dyn_id =3D true, .config =3D &sc7280_mmss_noc_regmap_config, .nodes =3D mmss_noc_nodes, .num_nodes =3D ARRAY_SIZE(mmss_noc_nodes), @@ -2040,6 +1983,7 @@ static const struct regmap_config sc7280_nsp_noc_regm= ap_config =3D { }; =20 static const struct qcom_icc_desc sc7280_nsp_noc =3D { + .alloc_dyn_id =3D true, .config =3D &sc7280_nsp_noc_regmap_config, .nodes =3D nsp_noc_nodes, .num_nodes =3D ARRAY_SIZE(nsp_noc_nodes), @@ -2074,6 +2018,7 @@ static const struct regmap_config sc7280_system_noc_r= egmap_config =3D { }; =20 static const struct qcom_icc_desc sc7280_system_noc =3D { + .alloc_dyn_id =3D true, .config =3D &sc7280_system_noc_regmap_config, .nodes =3D system_noc_nodes, .num_nodes =3D ARRAY_SIZE(system_noc_nodes), diff --git a/drivers/interconnect/qcom/sc7280.h b/drivers/interconnect/qcom= /sc7280.h deleted file mode 100644 index 175e400305c513a5f0d08468da7f4c72eb1a04e6..000000000000000000000000000= 0000000000000 --- a/drivers/interconnect/qcom/sc7280.h +++ /dev/null @@ -1,154 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Qualcomm #define SC7280 interconnect IDs - * - * Copyright (c) 2021, The Linux Foundation. All rights reserved. - */ - -#ifndef __DRIVERS_INTERCONNECT_QCOM_SC7280_H -#define __DRIVERS_INTERCONNECT_QCOM_SC7280_H - -#define SC7280_MASTER_GPU_TCU 0 -#define SC7280_MASTER_SYS_TCU 1 -#define SC7280_MASTER_APPSS_PROC 2 -#define SC7280_MASTER_LLCC 3 -#define SC7280_MASTER_CNOC_LPASS_AG_NOC 4 -#define SC7280_MASTER_CDSP_NOC_CFG 5 -#define SC7280_MASTER_QDSS_BAM 6 -#define SC7280_MASTER_QSPI_0 7 -#define SC7280_MASTER_QUP_0 8 -#define SC7280_MASTER_QUP_1 9 -#define SC7280_MASTER_A1NOC_CFG 10 -#define SC7280_MASTER_A2NOC_CFG 11 -#define SC7280_MASTER_A1NOC_SNOC 12 -#define SC7280_MASTER_A2NOC_SNOC 13 -#define SC7280_MASTER_COMPUTE_NOC 14 -#define SC7280_MASTER_CNOC2_CNOC3 15 -#define SC7280_MASTER_CNOC3_CNOC2 16 -#define SC7280_MASTER_CNOC_A2NOC 17 -#define SC7280_MASTER_CNOC_DC_NOC 18 -#define SC7280_MASTER_GEM_NOC_CFG 19 -#define SC7280_MASTER_GEM_NOC_CNOC 20 -#define SC7280_MASTER_GEM_NOC_PCIE_SNOC 21 -#define SC7280_MASTER_GFX3D 22 -#define SC7280_MASTER_CNOC_MNOC_CFG 23 -#define SC7280_MASTER_MNOC_HF_MEM_NOC 24 -#define SC7280_MASTER_MNOC_SF_MEM_NOC 25 -#define SC7280_MASTER_ANOC_PCIE_GEM_NOC 26 -#define SC7280_MASTER_SNOC_CFG 27 -#define SC7280_MASTER_SNOC_GC_MEM_NOC 28 -#define SC7280_MASTER_SNOC_SF_MEM_NOC 29 -#define SC7280_MASTER_VIDEO_P0 30 -#define SC7280_MASTER_VIDEO_PROC 31 -#define SC7280_MASTER_QUP_CORE_0 32 -#define SC7280_MASTER_QUP_CORE_1 33 -#define SC7280_MASTER_CAMNOC_HF 34 -#define SC7280_MASTER_CAMNOC_ICP 35 -#define SC7280_MASTER_CAMNOC_SF 36 -#define SC7280_MASTER_CRYPTO 37 -#define SC7280_MASTER_IPA 38 -#define SC7280_MASTER_MDP0 39 -#define SC7280_MASTER_CDSP_PROC 40 -#define SC7280_MASTER_PIMEM 41 -#define SC7280_MASTER_GIC 42 -#define SC7280_MASTER_PCIE_0 43 -#define SC7280_MASTER_PCIE_1 44 -#define SC7280_MASTER_QDSS_DAP 45 -#define SC7280_MASTER_QDSS_ETR 46 -#define SC7280_MASTER_SDCC_1 47 -#define SC7280_MASTER_SDCC_2 48 -#define SC7280_MASTER_SDCC_4 49 -#define SC7280_MASTER_UFS_MEM 50 -#define SC7280_MASTER_USB2 51 -#define SC7280_MASTER_USB3_0 52 -#define SC7280_SLAVE_EBI1 53 -#define SC7280_SLAVE_AHB2PHY_SOUTH 54 -#define SC7280_SLAVE_AHB2PHY_NORTH 55 -#define SC7280_SLAVE_AOSS 56 -#define SC7280_SLAVE_APPSS 57 -#define SC7280_SLAVE_CAMERA_CFG 58 -#define SC7280_SLAVE_CLK_CTL 59 -#define SC7280_SLAVE_CDSP_CFG 60 -#define SC7280_SLAVE_RBCPR_CX_CFG 61 -#define SC7280_SLAVE_RBCPR_MX_CFG 62 -#define SC7280_SLAVE_CRYPTO_0_CFG 63 -#define SC7280_SLAVE_CX_RDPM 64 -#define SC7280_SLAVE_DCC_CFG 65 -#define SC7280_SLAVE_DISPLAY_CFG 66 -#define SC7280_SLAVE_GFX3D_CFG 67 -#define SC7280_SLAVE_HWKM 68 -#define SC7280_SLAVE_IMEM_CFG 69 -#define SC7280_SLAVE_IPA_CFG 70 -#define SC7280_SLAVE_IPC_ROUTER_CFG 71 -#define SC7280_SLAVE_LLCC_CFG 72 -#define SC7280_SLAVE_LPASS 73 -#define SC7280_SLAVE_LPASS_CORE_CFG 74 -#define SC7280_SLAVE_LPASS_LPI_CFG 75 -#define SC7280_SLAVE_LPASS_MPU_CFG 76 -#define SC7280_SLAVE_LPASS_TOP_CFG 77 -#define SC7280_SLAVE_MSS_PROC_MS_MPU_CFG 78 -#define SC7280_SLAVE_MCDMA_MS_MPU_CFG 79 -#define SC7280_SLAVE_CNOC_MSS 80 -#define SC7280_SLAVE_MX_RDPM 81 -#define SC7280_SLAVE_PCIE_0_CFG 82 -#define SC7280_SLAVE_PCIE_1_CFG 83 -#define SC7280_SLAVE_PDM 84 -#define SC7280_SLAVE_PIMEM_CFG 85 -#define SC7280_SLAVE_PKA_WRAPPER_CFG 86 -#define SC7280_SLAVE_PMU_WRAPPER_CFG 87 -#define SC7280_SLAVE_QDSS_CFG 88 -#define SC7280_SLAVE_QSPI_0 89 -#define SC7280_SLAVE_QUP_0 90 -#define SC7280_SLAVE_QUP_1 91 -#define SC7280_SLAVE_SDCC_1 92 -#define SC7280_SLAVE_SDCC_2 93 -#define SC7280_SLAVE_SDCC_4 94 -#define SC7280_SLAVE_SECURITY 95 -#define SC7280_SLAVE_TCSR 96 -#define SC7280_SLAVE_TLMM 97 -#define SC7280_SLAVE_UFS_MEM_CFG 98 -#define SC7280_SLAVE_USB2 99 -#define SC7280_SLAVE_USB3_0 100 -#define SC7280_SLAVE_VENUS_CFG 101 -#define SC7280_SLAVE_VSENSE_CTRL_CFG 102 -#define SC7280_SLAVE_A1NOC_CFG 103 -#define SC7280_SLAVE_A1NOC_SNOC 104 -#define SC7280_SLAVE_A2NOC_CFG 105 -#define SC7280_SLAVE_A2NOC_SNOC 106 -#define SC7280_SLAVE_CNOC2_CNOC3 107 -#define SC7280_SLAVE_CNOC3_CNOC2 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This gives more flexibility and also allows us to drop the .num_links member, saving from possible errors related to it being not set or set incorrectly. Signed-off-by: Dmitry Baryshkov --- drivers/interconnect/qcom/sc8180x.c | 659 ++++++++++++++++++--------------= ---- drivers/interconnect/qcom/sc8180x.h | 179 ---------- 2 files changed, 335 insertions(+), 503 deletions(-) diff --git a/drivers/interconnect/qcom/sc8180x.c b/drivers/interconnect/qco= m/sc8180x.c index 4dd1d2f2e8216271c15b91b726d4f0c46994ae78..b80a255ba8c322f72f436a351ee= 3ea4a354be1fa 100644 --- a/drivers/interconnect/qcom/sc8180x.c +++ b/drivers/interconnect/qcom/sc8180x.c @@ -14,1331 +14,1331 @@ =20 #include "bcm-voter.h" #include "icc-rpmh.h" -#include "sc8180x.h" + +static struct qcom_icc_node mas_qhm_a1noc_cfg; +static struct qcom_icc_node mas_xm_ufs_card; +static struct qcom_icc_node mas_xm_ufs_g4; +static struct qcom_icc_node mas_xm_ufs_mem; +static struct qcom_icc_node mas_xm_usb3_0; +static struct qcom_icc_node mas_xm_usb3_1; +static struct qcom_icc_node mas_xm_usb3_2; +static struct qcom_icc_node mas_qhm_a2noc_cfg; +static struct qcom_icc_node mas_qhm_qdss_bam; +static struct qcom_icc_node mas_qhm_qspi; +static struct qcom_icc_node mas_qhm_qspi1; +static struct qcom_icc_node mas_qhm_qup0; +static struct qcom_icc_node mas_qhm_qup1; +static struct qcom_icc_node mas_qhm_qup2; +static struct qcom_icc_node mas_qhm_sensorss_ahb; +static struct qcom_icc_node mas_qxm_crypto; +static struct qcom_icc_node mas_qxm_ipa; +static struct qcom_icc_node mas_xm_emac; +static struct qcom_icc_node mas_xm_pcie3_0; +static struct qcom_icc_node mas_xm_pcie3_1; +static struct qcom_icc_node mas_xm_pcie3_2; +static struct qcom_icc_node mas_xm_pcie3_3; +static struct qcom_icc_node mas_xm_qdss_etr; +static struct qcom_icc_node mas_xm_sdc2; +static struct qcom_icc_node mas_xm_sdc4; +static struct qcom_icc_node mas_qxm_camnoc_hf0_uncomp; +static struct qcom_icc_node mas_qxm_camnoc_hf1_uncomp; +static struct qcom_icc_node mas_qxm_camnoc_sf_uncomp; +static struct qcom_icc_node mas_qnm_npu; +static struct qcom_icc_node mas_qnm_snoc; +static struct qcom_icc_node mas_qhm_cnoc_dc_noc; +static struct qcom_icc_node mas_acm_apps; +static struct qcom_icc_node mas_acm_gpu_tcu; +static struct qcom_icc_node mas_acm_sys_tcu; +static struct qcom_icc_node mas_qhm_gemnoc_cfg; +static struct qcom_icc_node mas_qnm_cmpnoc; +static struct qcom_icc_node mas_qnm_gpu; +static struct qcom_icc_node mas_qnm_mnoc_hf; +static struct qcom_icc_node mas_qnm_mnoc_sf; +static struct qcom_icc_node mas_qnm_pcie; +static struct qcom_icc_node mas_qnm_snoc_gc; +static struct qcom_icc_node mas_qnm_snoc_sf; +static struct qcom_icc_node mas_qxm_ecc; +static struct qcom_icc_node mas_llcc_mc; +static struct qcom_icc_node mas_qhm_mnoc_cfg; +static struct qcom_icc_node mas_qxm_camnoc_hf0; +static struct qcom_icc_node mas_qxm_camnoc_hf1; +static struct qcom_icc_node mas_qxm_camnoc_sf; +static struct qcom_icc_node mas_qxm_mdp0; +static struct qcom_icc_node mas_qxm_mdp1; +static struct qcom_icc_node mas_qxm_rot; +static struct qcom_icc_node mas_qxm_venus0; +static struct qcom_icc_node mas_qxm_venus1; +static struct qcom_icc_node mas_qxm_venus_arm9; +static struct qcom_icc_node mas_qhm_snoc_cfg; +static struct qcom_icc_node mas_qnm_aggre1_noc; +static struct qcom_icc_node mas_qnm_aggre2_noc; +static struct qcom_icc_node mas_qnm_gemnoc; +static struct qcom_icc_node mas_qxm_pimem; +static struct qcom_icc_node mas_xm_gic; +static struct qcom_icc_node mas_qup_core_0; +static struct qcom_icc_node mas_qup_core_1; +static struct qcom_icc_node mas_qup_core_2; +static struct qcom_icc_node slv_qns_a1noc_snoc; +static struct qcom_icc_node slv_srvc_aggre1_noc; +static struct qcom_icc_node slv_qns_a2noc_snoc; +static struct qcom_icc_node slv_qns_pcie_mem_noc; +static struct qcom_icc_node slv_srvc_aggre2_noc; +static struct qcom_icc_node slv_qns_camnoc_uncomp; +static struct qcom_icc_node slv_qns_cdsp_mem_noc; +static struct qcom_icc_node slv_qhs_a1_noc_cfg; +static struct qcom_icc_node slv_qhs_a2_noc_cfg; +static struct qcom_icc_node slv_qhs_ahb2phy_refgen_center; +static struct qcom_icc_node slv_qhs_ahb2phy_refgen_east; +static struct qcom_icc_node slv_qhs_ahb2phy_refgen_west; +static struct qcom_icc_node slv_qhs_ahb2phy_south; +static struct qcom_icc_node slv_qhs_aop; +static struct qcom_icc_node slv_qhs_aoss; +static struct qcom_icc_node slv_qhs_camera_cfg; +static struct qcom_icc_node slv_qhs_clk_ctl; +static struct qcom_icc_node slv_qhs_compute_dsp; +static struct qcom_icc_node slv_qhs_cpr_cx; +static struct qcom_icc_node slv_qhs_cpr_mmcx; +static struct qcom_icc_node slv_qhs_cpr_mx; +static struct qcom_icc_node slv_qhs_crypto0_cfg; +static struct qcom_icc_node slv_qhs_ddrss_cfg; +static struct qcom_icc_node slv_qhs_display_cfg; +static struct qcom_icc_node slv_qhs_emac_cfg; +static struct qcom_icc_node slv_qhs_glm; +static struct qcom_icc_node slv_qhs_gpuss_cfg; +static struct qcom_icc_node slv_qhs_imem_cfg; +static struct qcom_icc_node slv_qhs_ipa; +static struct qcom_icc_node slv_qhs_mnoc_cfg; +static struct qcom_icc_node slv_qhs_npu_cfg; +static struct qcom_icc_node slv_qhs_pcie0_cfg; +static struct qcom_icc_node slv_qhs_pcie1_cfg; +static struct qcom_icc_node slv_qhs_pcie2_cfg; +static struct qcom_icc_node slv_qhs_pcie3_cfg; +static struct qcom_icc_node slv_qhs_pdm; +static struct qcom_icc_node slv_qhs_pimem_cfg; +static struct qcom_icc_node slv_qhs_prng; +static struct qcom_icc_node slv_qhs_qdss_cfg; +static struct qcom_icc_node slv_qhs_qspi_0; +static struct qcom_icc_node slv_qhs_qspi_1; +static struct qcom_icc_node slv_qhs_qupv3_east0; +static struct qcom_icc_node slv_qhs_qupv3_east1; +static struct qcom_icc_node slv_qhs_qupv3_west; +static struct qcom_icc_node slv_qhs_sdc2; +static struct qcom_icc_node slv_qhs_sdc4; +static struct qcom_icc_node slv_qhs_security; +static struct qcom_icc_node slv_qhs_snoc_cfg; +static struct qcom_icc_node slv_qhs_spss_cfg; +static struct qcom_icc_node slv_qhs_tcsr; +static struct qcom_icc_node slv_qhs_tlmm_east; +static struct qcom_icc_node slv_qhs_tlmm_south; +static struct qcom_icc_node slv_qhs_tlmm_west; +static struct qcom_icc_node slv_qhs_tsif; +static struct qcom_icc_node slv_qhs_ufs_card_cfg; +static struct qcom_icc_node slv_qhs_ufs_mem0_cfg; +static struct qcom_icc_node slv_qhs_ufs_mem1_cfg; +static struct qcom_icc_node slv_qhs_usb3_0; +static struct qcom_icc_node slv_qhs_usb3_1; +static struct qcom_icc_node slv_qhs_usb3_2; +static struct qcom_icc_node slv_qhs_venus_cfg; +static struct qcom_icc_node slv_qhs_vsense_ctrl_cfg; +static struct qcom_icc_node slv_srvc_cnoc; +static struct qcom_icc_node slv_qhs_gemnoc; +static struct qcom_icc_node slv_qhs_llcc; +static struct qcom_icc_node slv_qhs_mdsp_ms_mpu_cfg; +static struct qcom_icc_node slv_qns_ecc; +static struct qcom_icc_node slv_qns_gem_noc_snoc; +static struct qcom_icc_node slv_qns_llcc; +static struct qcom_icc_node slv_srvc_gemnoc; +static struct qcom_icc_node slv_srvc_gemnoc1; +static struct qcom_icc_node slv_ebi; +static struct qcom_icc_node slv_qns2_mem_noc; +static struct qcom_icc_node slv_qns_mem_noc_hf; +static struct qcom_icc_node slv_srvc_mnoc; +static struct qcom_icc_node slv_qhs_apss; +static struct qcom_icc_node slv_qns_cnoc; +static struct qcom_icc_node slv_qns_gemnoc_gc; +static struct qcom_icc_node slv_qns_gemnoc_sf; +static struct qcom_icc_node slv_qxs_imem; +static struct qcom_icc_node slv_qxs_pimem; +static struct qcom_icc_node slv_srvc_snoc; +static struct qcom_icc_node slv_xs_pcie_0; +static struct qcom_icc_node slv_xs_pcie_1; +static struct qcom_icc_node slv_xs_pcie_2; +static struct qcom_icc_node slv_xs_pcie_3; +static struct qcom_icc_node slv_xs_qdss_stm; +static struct qcom_icc_node slv_xs_sys_tcu_cfg; +static struct qcom_icc_node slv_qup_core_0; +static struct qcom_icc_node slv_qup_core_1; +static struct qcom_icc_node slv_qup_core_2; =20 static struct qcom_icc_node mas_qhm_a1noc_cfg =3D { .name =3D "mas_qhm_a1noc_cfg", - .id =3D SC8180X_MASTER_A1NOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SC8180X_SLAVE_SERVICE_A1NOC } + .link_nodes =3D { &slv_srvc_aggre1_noc }, }; =20 static struct qcom_icc_node mas_xm_ufs_card =3D { .name =3D "mas_xm_ufs_card", - .id =3D SC8180X_MASTER_UFS_CARD, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SC8180X_A1NOC_SNOC_SLV } + .link_nodes =3D { &slv_qns_a1noc_snoc }, }; =20 static struct qcom_icc_node mas_xm_ufs_g4 =3D { .name =3D "mas_xm_ufs_g4", - .id =3D SC8180X_MASTER_UFS_GEN4, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SC8180X_A1NOC_SNOC_SLV } + .link_nodes =3D { &slv_qns_a1noc_snoc }, }; =20 static struct qcom_icc_node mas_xm_ufs_mem =3D { .name =3D "mas_xm_ufs_mem", - .id =3D SC8180X_MASTER_UFS_MEM, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SC8180X_A1NOC_SNOC_SLV } + .link_nodes =3D { &slv_qns_a1noc_snoc }, }; =20 static struct qcom_icc_node mas_xm_usb3_0 =3D { .name =3D "mas_xm_usb3_0", - .id =3D SC8180X_MASTER_USB3, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SC8180X_A1NOC_SNOC_SLV } + .link_nodes =3D { &slv_qns_a1noc_snoc }, }; =20 static struct qcom_icc_node mas_xm_usb3_1 =3D { .name =3D "mas_xm_usb3_1", - .id =3D SC8180X_MASTER_USB3_1, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SC8180X_A1NOC_SNOC_SLV } + .link_nodes =3D { &slv_qns_a1noc_snoc }, }; =20 static struct qcom_icc_node mas_xm_usb3_2 =3D { .name =3D "mas_xm_usb3_2", - .id =3D SC8180X_MASTER_USB3_2, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SC8180X_A1NOC_SNOC_SLV } + .link_nodes =3D { &slv_qns_a1noc_snoc }, }; =20 static struct qcom_icc_node mas_qhm_a2noc_cfg =3D { .name =3D "mas_qhm_a2noc_cfg", - .id =3D SC8180X_MASTER_A2NOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SC8180X_SLAVE_SERVICE_A2NOC } + .link_nodes =3D { &slv_srvc_aggre2_noc }, }; =20 static struct qcom_icc_node mas_qhm_qdss_bam =3D { .name =3D "mas_qhm_qdss_bam", - .id =3D SC8180X_MASTER_QDSS_BAM, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SC8180X_A2NOC_SNOC_SLV } + .link_nodes =3D { &slv_qns_a2noc_snoc }, }; =20 static struct qcom_icc_node mas_qhm_qspi =3D { .name =3D "mas_qhm_qspi", - .id =3D SC8180X_MASTER_QSPI_0, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SC8180X_A2NOC_SNOC_SLV } + .link_nodes =3D { &slv_qns_a2noc_snoc }, }; =20 static struct qcom_icc_node mas_qhm_qspi1 =3D { .name =3D "mas_qhm_qspi1", - .id =3D SC8180X_MASTER_QSPI_1, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SC8180X_A2NOC_SNOC_SLV } + .link_nodes =3D { &slv_qns_a2noc_snoc }, }; =20 static struct qcom_icc_node mas_qhm_qup0 =3D { .name =3D "mas_qhm_qup0", - .id =3D SC8180X_MASTER_QUP_0, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SC8180X_A2NOC_SNOC_SLV } + .link_nodes =3D { &slv_qns_a2noc_snoc }, }; =20 static struct qcom_icc_node mas_qhm_qup1 =3D { .name =3D "mas_qhm_qup1", - .id =3D SC8180X_MASTER_QUP_1, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SC8180X_A2NOC_SNOC_SLV } + .link_nodes =3D { &slv_qns_a2noc_snoc }, }; =20 static struct qcom_icc_node mas_qhm_qup2 =3D { .name =3D "mas_qhm_qup2", - .id =3D SC8180X_MASTER_QUP_2, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SC8180X_A2NOC_SNOC_SLV } + .link_nodes =3D { &slv_qns_a2noc_snoc }, }; =20 static struct qcom_icc_node mas_qhm_sensorss_ahb =3D { .name =3D "mas_qhm_sensorss_ahb", - .id =3D SC8180X_MASTER_SENSORS_AHB, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SC8180X_A2NOC_SNOC_SLV } + .link_nodes =3D { &slv_qns_a2noc_snoc }, }; =20 static struct qcom_icc_node mas_qxm_crypto =3D { .name =3D "mas_qxm_crypto", - .id =3D SC8180X_MASTER_CRYPTO_CORE_0, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SC8180X_A2NOC_SNOC_SLV } + .link_nodes =3D { &slv_qns_a2noc_snoc }, }; =20 static struct qcom_icc_node mas_qxm_ipa =3D { .name =3D "mas_qxm_ipa", - .id =3D SC8180X_MASTER_IPA, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SC8180X_A2NOC_SNOC_SLV } + .link_nodes =3D { &slv_qns_a2noc_snoc }, }; =20 static struct qcom_icc_node mas_xm_emac =3D { .name =3D "mas_xm_emac", - .id =3D SC8180X_MASTER_EMAC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SC8180X_A2NOC_SNOC_SLV } + .link_nodes =3D { &slv_qns_a2noc_snoc }, }; =20 static struct qcom_icc_node mas_xm_pcie3_0 =3D { .name =3D "mas_xm_pcie3_0", - .id =3D SC8180X_MASTER_PCIE, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SC8180X_SLAVE_ANOC_PCIE_GEM_NOC } + .link_nodes =3D { &slv_qns_pcie_mem_noc }, }; =20 static struct qcom_icc_node mas_xm_pcie3_1 =3D { .name =3D "mas_xm_pcie3_1", - .id =3D SC8180X_MASTER_PCIE_1, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SC8180X_SLAVE_ANOC_PCIE_GEM_NOC } + .link_nodes =3D { &slv_qns_pcie_mem_noc }, }; =20 static struct qcom_icc_node mas_xm_pcie3_2 =3D { .name =3D "mas_xm_pcie3_2", - .id =3D SC8180X_MASTER_PCIE_2, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SC8180X_SLAVE_ANOC_PCIE_GEM_NOC } + .link_nodes =3D { &slv_qns_pcie_mem_noc }, }; =20 static struct qcom_icc_node mas_xm_pcie3_3 =3D { .name =3D "mas_xm_pcie3_3", - .id =3D SC8180X_MASTER_PCIE_3, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SC8180X_SLAVE_ANOC_PCIE_GEM_NOC } + .link_nodes =3D { &slv_qns_pcie_mem_noc }, }; =20 static struct qcom_icc_node mas_xm_qdss_etr =3D { .name =3D "mas_xm_qdss_etr", - .id =3D SC8180X_MASTER_QDSS_ETR, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SC8180X_A2NOC_SNOC_SLV } + .link_nodes =3D { &slv_qns_a2noc_snoc }, }; =20 static struct qcom_icc_node mas_xm_sdc2 =3D { .name =3D "mas_xm_sdc2", - .id =3D SC8180X_MASTER_SDCC_2, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SC8180X_A2NOC_SNOC_SLV } + .link_nodes =3D { &slv_qns_a2noc_snoc }, }; =20 static struct qcom_icc_node mas_xm_sdc4 =3D { .name =3D "mas_xm_sdc4", - .id =3D SC8180X_MASTER_SDCC_4, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SC8180X_A2NOC_SNOC_SLV } + .link_nodes =3D { &slv_qns_a2noc_snoc }, }; =20 static struct qcom_icc_node mas_qxm_camnoc_hf0_uncomp =3D { .name =3D "mas_qxm_camnoc_hf0_uncomp", - .id =3D SC8180X_MASTER_CAMNOC_HF0_UNCOMP, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SC8180X_SLAVE_CAMNOC_UNCOMP } + .link_nodes =3D { &slv_qns_camnoc_uncomp }, }; =20 static struct qcom_icc_node mas_qxm_camnoc_hf1_uncomp =3D { .name =3D "mas_qxm_camnoc_hf1_uncomp", - .id =3D SC8180X_MASTER_CAMNOC_HF1_UNCOMP, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SC8180X_SLAVE_CAMNOC_UNCOMP } + .link_nodes =3D { &slv_qns_camnoc_uncomp }, }; =20 static struct qcom_icc_node mas_qxm_camnoc_sf_uncomp =3D { .name =3D "mas_qxm_camnoc_sf_uncomp", - .id =3D SC8180X_MASTER_CAMNOC_SF_UNCOMP, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SC8180X_SLAVE_CAMNOC_UNCOMP } + .link_nodes =3D { &slv_qns_camnoc_uncomp }, }; =20 static struct qcom_icc_node mas_qnm_npu =3D { .name =3D "mas_qnm_npu", - .id =3D SC8180X_MASTER_NPU, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SC8180X_SLAVE_CDSP_MEM_NOC } + .link_nodes =3D { &slv_qns_cdsp_mem_noc }, }; =20 static struct qcom_icc_node mas_qnm_snoc =3D { .name =3D "mas_qnm_snoc", - .id =3D SC8180X_SNOC_CNOC_MAS, .channels =3D 1, .buswidth =3D 8, .num_links =3D 56, - .links =3D { SC8180X_SLAVE_TLMM_SOUTH, - SC8180X_SLAVE_CDSP_CFG, - SC8180X_SLAVE_SPSS_CFG, - SC8180X_SLAVE_CAMERA_CFG, - SC8180X_SLAVE_SDCC_4, - SC8180X_SLAVE_AHB2PHY_CENTER, - SC8180X_SLAVE_SDCC_2, - SC8180X_SLAVE_PCIE_2_CFG, - SC8180X_SLAVE_CNOC_MNOC_CFG, - SC8180X_SLAVE_EMAC_CFG, - SC8180X_SLAVE_QSPI_0, - SC8180X_SLAVE_QSPI_1, - SC8180X_SLAVE_TLMM_EAST, - SC8180X_SLAVE_SNOC_CFG, - SC8180X_SLAVE_AHB2PHY_EAST, - SC8180X_SLAVE_GLM, - SC8180X_SLAVE_PDM, - SC8180X_SLAVE_PCIE_1_CFG, - SC8180X_SLAVE_A2NOC_CFG, - SC8180X_SLAVE_QDSS_CFG, - SC8180X_SLAVE_DISPLAY_CFG, - SC8180X_SLAVE_TCSR, - SC8180X_SLAVE_UFS_MEM_0_CFG, - SC8180X_SLAVE_CNOC_DDRSS, - SC8180X_SLAVE_PCIE_0_CFG, - SC8180X_SLAVE_QUP_1, - SC8180X_SLAVE_QUP_2, - SC8180X_SLAVE_NPU_CFG, - SC8180X_SLAVE_CRYPTO_0_CFG, - SC8180X_SLAVE_GRAPHICS_3D_CFG, - SC8180X_SLAVE_VENUS_CFG, - SC8180X_SLAVE_TSIF, - SC8180X_SLAVE_IPA_CFG, - SC8180X_SLAVE_CLK_CTL, - SC8180X_SLAVE_SECURITY, - SC8180X_SLAVE_AOP, - SC8180X_SLAVE_AHB2PHY_WEST, - SC8180X_SLAVE_AHB2PHY_SOUTH, - SC8180X_SLAVE_SERVICE_CNOC, - SC8180X_SLAVE_UFS_CARD_CFG, - SC8180X_SLAVE_USB3_1, - SC8180X_SLAVE_USB3_2, - SC8180X_SLAVE_PCIE_3_CFG, - SC8180X_SLAVE_RBCPR_CX_CFG, - SC8180X_SLAVE_TLMM_WEST, - SC8180X_SLAVE_A1NOC_CFG, - SC8180X_SLAVE_AOSS, - SC8180X_SLAVE_PRNG, - SC8180X_SLAVE_VSENSE_CTRL_CFG, - SC8180X_SLAVE_QUP_0, - SC8180X_SLAVE_USB3, - SC8180X_SLAVE_RBCPR_MMCX_CFG, - SC8180X_SLAVE_PIMEM_CFG, - SC8180X_SLAVE_UFS_MEM_1_CFG, - SC8180X_SLAVE_RBCPR_MX_CFG, - SC8180X_SLAVE_IMEM_CFG } + .link_nodes =3D { &slv_qhs_tlmm_south, + &slv_qhs_compute_dsp, + &slv_qhs_spss_cfg, + &slv_qhs_camera_cfg, + &slv_qhs_sdc4, + &slv_qhs_ahb2phy_refgen_center, + &slv_qhs_sdc2, + &slv_qhs_pcie2_cfg, + &slv_qhs_mnoc_cfg, + &slv_qhs_emac_cfg, + &slv_qhs_qspi_0, + &slv_qhs_qspi_1, + &slv_qhs_tlmm_east, + &slv_qhs_snoc_cfg, + &slv_qhs_ahb2phy_refgen_east, + &slv_qhs_glm, + &slv_qhs_pdm, + &slv_qhs_pcie1_cfg, + &slv_qhs_a2_noc_cfg, + &slv_qhs_qdss_cfg, + &slv_qhs_display_cfg, + &slv_qhs_tcsr, + &slv_qhs_ufs_mem0_cfg, + &slv_qhs_ddrss_cfg, + &slv_qhs_pcie0_cfg, + &slv_qhs_qupv3_east0, + &slv_qhs_qupv3_east1, + &slv_qhs_npu_cfg, + &slv_qhs_crypto0_cfg, + &slv_qhs_gpuss_cfg, + &slv_qhs_venus_cfg, + &slv_qhs_tsif, + &slv_qhs_ipa, + &slv_qhs_clk_ctl, + &slv_qhs_security, + &slv_qhs_aop, + &slv_qhs_ahb2phy_refgen_west, + &slv_qhs_ahb2phy_south, + &slv_srvc_cnoc, + &slv_qhs_ufs_card_cfg, + &slv_qhs_usb3_1, + &slv_qhs_usb3_2, + &slv_qhs_pcie3_cfg, + &slv_qhs_cpr_cx, + &slv_qhs_tlmm_west, + &slv_qhs_a1_noc_cfg, + &slv_qhs_aoss, + &slv_qhs_prng, + &slv_qhs_vsense_ctrl_cfg, + &slv_qhs_qupv3_west, + &slv_qhs_usb3_0, + &slv_qhs_cpr_mmcx, + &slv_qhs_pimem_cfg, + &slv_qhs_ufs_mem1_cfg, + &slv_qhs_cpr_mx, + &slv_qhs_imem_cfg }, }; =20 static struct qcom_icc_node mas_qhm_cnoc_dc_noc =3D { .name =3D "mas_qhm_cnoc_dc_noc", - .id =3D SC8180X_MASTER_CNOC_DC_NOC, .channels =3D 1, .buswidth =3D 4, .num_links =3D 2, - .links =3D { SC8180X_SLAVE_LLCC_CFG, - SC8180X_SLAVE_GEM_NOC_CFG } + .link_nodes =3D { &slv_qhs_llcc, + &slv_qhs_gemnoc }, }; =20 static struct qcom_icc_node mas_acm_apps =3D { .name =3D "mas_acm_apps", - .id =3D SC8180X_MASTER_AMPSS_M0, .channels =3D 4, .buswidth =3D 64, .num_links =3D 3, - .links =3D { SC8180X_SLAVE_ECC, - SC8180X_SLAVE_LLCC, - SC8180X_SLAVE_GEM_NOC_SNOC } + .link_nodes =3D { &slv_qns_ecc, + &slv_qns_llcc, + &slv_qns_gem_noc_snoc }, }; =20 static struct qcom_icc_node mas_acm_gpu_tcu =3D { .name =3D "mas_acm_gpu_tcu", - .id =3D SC8180X_MASTER_GPU_TCU, .channels =3D 1, .buswidth =3D 8, .num_links =3D 2, - .links =3D { SC8180X_SLAVE_LLCC, - SC8180X_SLAVE_GEM_NOC_SNOC } + .link_nodes =3D { &slv_qns_llcc, + &slv_qns_gem_noc_snoc }, }; =20 static struct qcom_icc_node mas_acm_sys_tcu =3D { .name =3D "mas_acm_sys_tcu", - .id =3D SC8180X_MASTER_SYS_TCU, .channels =3D 1, .buswidth =3D 8, .num_links =3D 2, - .links =3D { SC8180X_SLAVE_LLCC, - SC8180X_SLAVE_GEM_NOC_SNOC } + .link_nodes =3D { &slv_qns_llcc, + &slv_qns_gem_noc_snoc }, }; =20 static struct qcom_icc_node mas_qhm_gemnoc_cfg =3D { .name =3D "mas_qhm_gemnoc_cfg", - .id =3D SC8180X_MASTER_GEM_NOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 3, - .links =3D { SC8180X_SLAVE_SERVICE_GEM_NOC_1, - SC8180X_SLAVE_SERVICE_GEM_NOC, - SC8180X_SLAVE_MSS_PROC_MS_MPU_CFG } + .link_nodes =3D { &slv_srvc_gemnoc1, + &slv_srvc_gemnoc, + &slv_qhs_mdsp_ms_mpu_cfg }, }; =20 static struct qcom_icc_node mas_qnm_cmpnoc =3D { .name =3D "mas_qnm_cmpnoc", - .id =3D SC8180X_MASTER_COMPUTE_NOC, .channels =3D 2, .buswidth =3D 32, .num_links =3D 3, - .links =3D { SC8180X_SLAVE_ECC, - SC8180X_SLAVE_LLCC, - SC8180X_SLAVE_GEM_NOC_SNOC } + .link_nodes =3D { &slv_qns_ecc, + &slv_qns_llcc, + &slv_qns_gem_noc_snoc }, }; =20 static struct qcom_icc_node mas_qnm_gpu =3D { .name =3D "mas_qnm_gpu", - .id =3D SC8180X_MASTER_GRAPHICS_3D, .channels =3D 4, .buswidth =3D 32, .num_links =3D 2, - .links =3D { SC8180X_SLAVE_LLCC, - SC8180X_SLAVE_GEM_NOC_SNOC } + .link_nodes =3D { &slv_qns_llcc, + &slv_qns_gem_noc_snoc }, }; =20 static struct qcom_icc_node mas_qnm_mnoc_hf =3D { .name =3D "mas_qnm_mnoc_hf", - .id =3D SC8180X_MASTER_MNOC_HF_MEM_NOC, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SC8180X_SLAVE_LLCC } + .link_nodes =3D { &slv_qns_llcc }, }; =20 static struct qcom_icc_node mas_qnm_mnoc_sf =3D { .name =3D "mas_qnm_mnoc_sf", - .id =3D SC8180X_MASTER_MNOC_SF_MEM_NOC, .channels =3D 1, .buswidth =3D 32, .num_links =3D 2, - .links =3D { SC8180X_SLAVE_LLCC, - SC8180X_SLAVE_GEM_NOC_SNOC } + .link_nodes =3D { &slv_qns_llcc, + &slv_qns_gem_noc_snoc }, }; =20 static struct qcom_icc_node mas_qnm_pcie =3D { .name =3D "mas_qnm_pcie", - .id =3D SC8180X_MASTER_GEM_NOC_PCIE_SNOC, .channels =3D 1, .buswidth =3D 32, .num_links =3D 2, - .links =3D { SC8180X_SLAVE_LLCC, - SC8180X_SLAVE_GEM_NOC_SNOC } + .link_nodes =3D { &slv_qns_llcc, + &slv_qns_gem_noc_snoc }, }; =20 static struct qcom_icc_node mas_qnm_snoc_gc =3D { .name =3D "mas_qnm_snoc_gc", - .id =3D SC8180X_MASTER_SNOC_GC_MEM_NOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SC8180X_SLAVE_LLCC } + .link_nodes =3D { &slv_qns_llcc }, }; =20 static struct qcom_icc_node mas_qnm_snoc_sf =3D { .name =3D "mas_qnm_snoc_sf", - .id =3D SC8180X_MASTER_SNOC_SF_MEM_NOC, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SC8180X_SLAVE_LLCC } + .link_nodes =3D { &slv_qns_llcc }, }; =20 static struct qcom_icc_node mas_qxm_ecc =3D { .name =3D "mas_qxm_ecc", - .id =3D SC8180X_MASTER_ECC, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SC8180X_SLAVE_LLCC } + .link_nodes =3D { &slv_qns_llcc }, }; =20 static struct qcom_icc_node mas_llcc_mc =3D { .name =3D "mas_llcc_mc", - .id =3D SC8180X_MASTER_LLCC, .channels =3D 8, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SC8180X_SLAVE_EBI_CH0 } + .link_nodes =3D { &slv_ebi }, }; =20 static struct qcom_icc_node mas_qhm_mnoc_cfg =3D { .name =3D "mas_qhm_mnoc_cfg", - .id =3D SC8180X_MASTER_CNOC_MNOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SC8180X_SLAVE_SERVICE_MNOC } + .link_nodes =3D { &slv_srvc_mnoc }, }; =20 static struct qcom_icc_node mas_qxm_camnoc_hf0 =3D { .name =3D "mas_qxm_camnoc_hf0", - .id =3D SC8180X_MASTER_CAMNOC_HF0, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SC8180X_SLAVE_MNOC_HF_MEM_NOC } + .link_nodes =3D { &slv_qns_mem_noc_hf }, }; =20 static struct qcom_icc_node mas_qxm_camnoc_hf1 =3D { .name =3D "mas_qxm_camnoc_hf1", - .id =3D SC8180X_MASTER_CAMNOC_HF1, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SC8180X_SLAVE_MNOC_HF_MEM_NOC } + .link_nodes =3D { &slv_qns_mem_noc_hf }, }; =20 static struct qcom_icc_node mas_qxm_camnoc_sf =3D { .name =3D "mas_qxm_camnoc_sf", - .id =3D SC8180X_MASTER_CAMNOC_SF, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SC8180X_SLAVE_MNOC_SF_MEM_NOC } + .link_nodes =3D { &slv_qns2_mem_noc }, }; =20 static struct qcom_icc_node mas_qxm_mdp0 =3D { .name =3D "mas_qxm_mdp0", - .id =3D SC8180X_MASTER_MDP_PORT0, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SC8180X_SLAVE_MNOC_HF_MEM_NOC } + .link_nodes =3D { &slv_qns_mem_noc_hf }, }; =20 static struct qcom_icc_node mas_qxm_mdp1 =3D { .name =3D "mas_qxm_mdp1", - .id =3D SC8180X_MASTER_MDP_PORT1, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SC8180X_SLAVE_MNOC_HF_MEM_NOC } + .link_nodes =3D { &slv_qns_mem_noc_hf }, }; =20 static struct qcom_icc_node mas_qxm_rot =3D { .name =3D "mas_qxm_rot", - .id =3D SC8180X_MASTER_ROTATOR, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SC8180X_SLAVE_MNOC_SF_MEM_NOC } + .link_nodes =3D { &slv_qns2_mem_noc }, }; =20 static struct qcom_icc_node mas_qxm_venus0 =3D { .name =3D "mas_qxm_venus0", - .id =3D SC8180X_MASTER_VIDEO_P0, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SC8180X_SLAVE_MNOC_SF_MEM_NOC } + .link_nodes =3D { &slv_qns2_mem_noc }, }; =20 static struct qcom_icc_node mas_qxm_venus1 =3D { .name =3D "mas_qxm_venus1", - .id =3D SC8180X_MASTER_VIDEO_P1, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SC8180X_SLAVE_MNOC_SF_MEM_NOC } + .link_nodes =3D { &slv_qns2_mem_noc }, }; =20 static struct qcom_icc_node mas_qxm_venus_arm9 =3D { .name =3D "mas_qxm_venus_arm9", - .id =3D SC8180X_MASTER_VIDEO_PROC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SC8180X_SLAVE_MNOC_SF_MEM_NOC } + .link_nodes =3D { &slv_qns2_mem_noc }, }; =20 static struct qcom_icc_node mas_qhm_snoc_cfg =3D { .name =3D "mas_qhm_snoc_cfg", - .id =3D SC8180X_MASTER_SNOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SC8180X_SLAVE_SERVICE_SNOC } + .link_nodes =3D { &slv_srvc_snoc }, }; =20 static struct qcom_icc_node mas_qnm_aggre1_noc =3D { .name =3D "mas_qnm_aggre1_noc", - .id =3D SC8180X_A1NOC_SNOC_MAS, .channels =3D 1, .buswidth =3D 32, .num_links =3D 6, - .links =3D { SC8180X_SLAVE_SNOC_GEM_NOC_SF, - SC8180X_SLAVE_PIMEM, - SC8180X_SLAVE_OCIMEM, - SC8180X_SLAVE_APPSS, - SC8180X_SNOC_CNOC_SLV, - SC8180X_SLAVE_QDSS_STM } + .link_nodes =3D { &slv_qns_gemnoc_sf, + &slv_qxs_pimem, + &slv_qxs_imem, + &slv_qhs_apss, + &slv_qns_cnoc, + &slv_xs_qdss_stm }, }; =20 static struct qcom_icc_node mas_qnm_aggre2_noc =3D { .name =3D "mas_qnm_aggre2_noc", - .id =3D SC8180X_A2NOC_SNOC_MAS, .channels =3D 1, .buswidth =3D 16, .num_links =3D 11, - .links =3D { SC8180X_SLAVE_SNOC_GEM_NOC_SF, - SC8180X_SLAVE_PIMEM, - SC8180X_SLAVE_PCIE_3, - SC8180X_SLAVE_OCIMEM, - SC8180X_SLAVE_APPSS, - SC8180X_SLAVE_PCIE_2, - SC8180X_SNOC_CNOC_SLV, - SC8180X_SLAVE_PCIE_0, - SC8180X_SLAVE_PCIE_1, - SC8180X_SLAVE_TCU, - SC8180X_SLAVE_QDSS_STM } + .link_nodes =3D { &slv_qns_gemnoc_sf, + &slv_qxs_pimem, + &slv_xs_pcie_3, + &slv_qxs_imem, + &slv_qhs_apss, + &slv_xs_pcie_2, + &slv_qns_cnoc, + &slv_xs_pcie_0, + &slv_xs_pcie_1, + &slv_xs_sys_tcu_cfg, + &slv_xs_qdss_stm }, }; =20 static struct qcom_icc_node mas_qnm_gemnoc =3D { .name =3D "mas_qnm_gemnoc", - .id =3D SC8180X_MASTER_GEM_NOC_SNOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 6, - .links =3D { SC8180X_SLAVE_PIMEM, - SC8180X_SLAVE_OCIMEM, - SC8180X_SLAVE_APPSS, - SC8180X_SNOC_CNOC_SLV, - SC8180X_SLAVE_TCU, - SC8180X_SLAVE_QDSS_STM } + .link_nodes =3D { &slv_qxs_pimem, + &slv_qxs_imem, + &slv_qhs_apss, + &slv_qns_cnoc, + &slv_xs_sys_tcu_cfg, + &slv_xs_qdss_stm }, }; =20 static struct qcom_icc_node mas_qxm_pimem =3D { .name =3D "mas_qxm_pimem", - .id =3D SC8180X_MASTER_PIMEM, .channels =3D 1, .buswidth =3D 8, .num_links =3D 2, - .links =3D { SC8180X_SLAVE_SNOC_GEM_NOC_GC, - SC8180X_SLAVE_OCIMEM } + .link_nodes =3D { &slv_qns_gemnoc_gc, + &slv_qxs_imem }, }; =20 static struct qcom_icc_node mas_xm_gic =3D { .name =3D "mas_xm_gic", - .id =3D SC8180X_MASTER_GIC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 2, - .links =3D { SC8180X_SLAVE_SNOC_GEM_NOC_GC, - SC8180X_SLAVE_OCIMEM } + .link_nodes =3D { &slv_qns_gemnoc_gc, + &slv_qxs_imem }, }; =20 static struct qcom_icc_node mas_qup_core_0 =3D { .name =3D "mas_qup_core_0", - .id =3D SC8180X_MASTER_QUP_CORE_0, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SC8180X_SLAVE_QUP_CORE_0 } + .link_nodes =3D { &slv_qup_core_0 }, }; =20 static struct qcom_icc_node mas_qup_core_1 =3D { .name =3D "mas_qup_core_1", - .id =3D SC8180X_MASTER_QUP_CORE_1, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SC8180X_SLAVE_QUP_CORE_1 } + .link_nodes =3D { &slv_qup_core_1 }, }; =20 static struct qcom_icc_node mas_qup_core_2 =3D { .name =3D "mas_qup_core_2", - .id =3D SC8180X_MASTER_QUP_CORE_2, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SC8180X_SLAVE_QUP_CORE_2 } + .link_nodes =3D { &slv_qup_core_2 }, }; =20 static struct qcom_icc_node slv_qns_a1noc_snoc =3D { .name =3D "slv_qns_a1noc_snoc", - .id =3D SC8180X_A1NOC_SNOC_SLV, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SC8180X_A1NOC_SNOC_MAS } + .link_nodes =3D { &mas_qnm_aggre1_noc }, }; =20 static struct qcom_icc_node slv_srvc_aggre1_noc =3D { .name =3D "slv_srvc_aggre1_noc", - .id =3D SC8180X_SLAVE_SERVICE_A1NOC, .channels =3D 1, .buswidth =3D 4 }; =20 static struct qcom_icc_node slv_qns_a2noc_snoc =3D { .name =3D "slv_qns_a2noc_snoc", - .id =3D SC8180X_A2NOC_SNOC_SLV, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SC8180X_A2NOC_SNOC_MAS } + .link_nodes =3D { &mas_qnm_aggre2_noc }, }; =20 static struct qcom_icc_node slv_qns_pcie_mem_noc =3D { .name =3D "slv_qns_pcie_mem_noc", - .id =3D SC8180X_SLAVE_ANOC_PCIE_GEM_NOC, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SC8180X_MASTER_GEM_NOC_PCIE_SNOC } + .link_nodes =3D { &mas_qnm_pcie }, }; =20 static struct qcom_icc_node slv_srvc_aggre2_noc =3D { .name =3D "slv_srvc_aggre2_noc", - .id =3D SC8180X_SLAVE_SERVICE_A2NOC, .channels =3D 1, .buswidth =3D 4 }; =20 static struct qcom_icc_node slv_qns_camnoc_uncomp =3D { .name =3D "slv_qns_camnoc_uncomp", - .id =3D SC8180X_SLAVE_CAMNOC_UNCOMP, .channels =3D 1, .buswidth =3D 32 }; =20 static struct qcom_icc_node slv_qns_cdsp_mem_noc =3D { .name =3D "slv_qns_cdsp_mem_noc", - .id =3D SC8180X_SLAVE_CDSP_MEM_NOC, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SC8180X_MASTER_COMPUTE_NOC } + .link_nodes =3D { &mas_qnm_cmpnoc }, }; =20 static struct qcom_icc_node slv_qhs_a1_noc_cfg =3D { .name =3D "slv_qhs_a1_noc_cfg", - .id =3D SC8180X_SLAVE_A1NOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SC8180X_MASTER_A1NOC_CFG } + .link_nodes =3D { &mas_qhm_a1noc_cfg }, }; =20 static struct qcom_icc_node slv_qhs_a2_noc_cfg =3D { .name =3D "slv_qhs_a2_noc_cfg", - .id =3D SC8180X_SLAVE_A2NOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SC8180X_MASTER_A2NOC_CFG } + .link_nodes =3D { &mas_qhm_a2noc_cfg }, }; =20 static struct qcom_icc_node slv_qhs_ahb2phy_refgen_center =3D { .name =3D "slv_qhs_ahb2phy_refgen_center", - .id =3D SC8180X_SLAVE_AHB2PHY_CENTER, .channels =3D 1, .buswidth =3D 4 }; =20 static struct qcom_icc_node slv_qhs_ahb2phy_refgen_east =3D { .name =3D "slv_qhs_ahb2phy_refgen_east", - .id =3D SC8180X_SLAVE_AHB2PHY_EAST, .channels =3D 1, .buswidth =3D 4 }; =20 static struct qcom_icc_node slv_qhs_ahb2phy_refgen_west =3D { .name =3D "slv_qhs_ahb2phy_refgen_west", - .id =3D SC8180X_SLAVE_AHB2PHY_WEST, .channels =3D 1, .buswidth =3D 4 }; =20 static struct qcom_icc_node slv_qhs_ahb2phy_south =3D { .name =3D "slv_qhs_ahb2phy_south", - .id =3D SC8180X_SLAVE_AHB2PHY_SOUTH, .channels =3D 1, .buswidth =3D 4 }; =20 static struct qcom_icc_node slv_qhs_aop =3D { .name =3D "slv_qhs_aop", - .id =3D SC8180X_SLAVE_AOP, .channels =3D 1, .buswidth =3D 4 }; =20 static struct qcom_icc_node slv_qhs_aoss =3D { .name =3D "slv_qhs_aoss", - .id =3D SC8180X_SLAVE_AOSS, .channels =3D 1, .buswidth =3D 4 }; =20 static struct qcom_icc_node slv_qhs_camera_cfg =3D { .name =3D "slv_qhs_camera_cfg", - .id =3D SC8180X_SLAVE_CAMERA_CFG, .channels =3D 1, .buswidth =3D 4 }; =20 static struct qcom_icc_node slv_qhs_clk_ctl =3D { .name =3D "slv_qhs_clk_ctl", - .id =3D SC8180X_SLAVE_CLK_CTL, .channels =3D 1, .buswidth =3D 4 }; =20 static struct qcom_icc_node slv_qhs_compute_dsp =3D { .name =3D "slv_qhs_compute_dsp", - .id =3D SC8180X_SLAVE_CDSP_CFG, .channels =3D 1, .buswidth =3D 4 }; =20 static struct qcom_icc_node slv_qhs_cpr_cx =3D { .name =3D "slv_qhs_cpr_cx", - .id =3D SC8180X_SLAVE_RBCPR_CX_CFG, .channels =3D 1, .buswidth =3D 4 }; =20 static struct qcom_icc_node slv_qhs_cpr_mmcx =3D { .name =3D "slv_qhs_cpr_mmcx", - .id =3D SC8180X_SLAVE_RBCPR_MMCX_CFG, .channels =3D 1, .buswidth =3D 4 }; =20 static struct qcom_icc_node slv_qhs_cpr_mx =3D { .name =3D "slv_qhs_cpr_mx", - .id =3D SC8180X_SLAVE_RBCPR_MX_CFG, .channels =3D 1, .buswidth =3D 4 }; =20 static struct qcom_icc_node slv_qhs_crypto0_cfg =3D { .name =3D "slv_qhs_crypto0_cfg", - .id =3D SC8180X_SLAVE_CRYPTO_0_CFG, .channels =3D 1, .buswidth =3D 4 }; =20 static struct qcom_icc_node slv_qhs_ddrss_cfg =3D { .name =3D "slv_qhs_ddrss_cfg", - .id =3D SC8180X_SLAVE_CNOC_DDRSS, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SC8180X_MASTER_CNOC_DC_NOC } + .link_nodes =3D { &mas_qhm_cnoc_dc_noc }, }; =20 static struct qcom_icc_node slv_qhs_display_cfg =3D { .name =3D "slv_qhs_display_cfg", - .id =3D SC8180X_SLAVE_DISPLAY_CFG, .channels =3D 1, .buswidth =3D 4 }; =20 static struct qcom_icc_node slv_qhs_emac_cfg =3D { .name =3D "slv_qhs_emac_cfg", - .id =3D SC8180X_SLAVE_EMAC_CFG, .channels =3D 1, .buswidth =3D 4 }; =20 static struct qcom_icc_node slv_qhs_glm =3D { .name =3D "slv_qhs_glm", - .id =3D SC8180X_SLAVE_GLM, .channels =3D 1, .buswidth =3D 4 }; =20 static struct qcom_icc_node slv_qhs_gpuss_cfg =3D { .name =3D "slv_qhs_gpuss_cfg", - .id =3D SC8180X_SLAVE_GRAPHICS_3D_CFG, .channels =3D 1, .buswidth =3D 8 }; =20 static struct qcom_icc_node slv_qhs_imem_cfg =3D { .name =3D "slv_qhs_imem_cfg", - .id =3D SC8180X_SLAVE_IMEM_CFG, .channels =3D 1, .buswidth =3D 4 }; =20 static struct qcom_icc_node slv_qhs_ipa =3D { .name =3D "slv_qhs_ipa", - .id =3D SC8180X_SLAVE_IPA_CFG, .channels =3D 1, .buswidth =3D 4 }; =20 static struct qcom_icc_node slv_qhs_mnoc_cfg =3D { .name =3D "slv_qhs_mnoc_cfg", - .id =3D SC8180X_SLAVE_CNOC_MNOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SC8180X_MASTER_CNOC_MNOC_CFG } + .link_nodes =3D { &mas_qhm_mnoc_cfg }, }; =20 static struct qcom_icc_node slv_qhs_npu_cfg =3D { .name =3D "slv_qhs_npu_cfg", - .id =3D SC8180X_SLAVE_NPU_CFG, .channels =3D 1, .buswidth =3D 4 }; =20 static struct qcom_icc_node slv_qhs_pcie0_cfg =3D { .name =3D "slv_qhs_pcie0_cfg", - .id =3D SC8180X_SLAVE_PCIE_0_CFG, .channels =3D 1, .buswidth =3D 4 }; =20 static struct qcom_icc_node slv_qhs_pcie1_cfg =3D { .name =3D "slv_qhs_pcie1_cfg", - .id =3D SC8180X_SLAVE_PCIE_1_CFG, .channels =3D 1, .buswidth =3D 4 }; =20 static struct qcom_icc_node slv_qhs_pcie2_cfg =3D { .name =3D "slv_qhs_pcie2_cfg", - .id =3D SC8180X_SLAVE_PCIE_2_CFG, .channels =3D 1, .buswidth =3D 4 }; =20 static struct qcom_icc_node slv_qhs_pcie3_cfg =3D { .name =3D "slv_qhs_pcie3_cfg", - .id =3D SC8180X_SLAVE_PCIE_3_CFG, .channels =3D 1, .buswidth =3D 4 }; =20 static struct qcom_icc_node slv_qhs_pdm =3D { .name =3D "slv_qhs_pdm", - .id =3D SC8180X_SLAVE_PDM, .channels =3D 1, .buswidth =3D 4 }; =20 static struct qcom_icc_node slv_qhs_pimem_cfg =3D { .name =3D "slv_qhs_pimem_cfg", - .id =3D SC8180X_SLAVE_PIMEM_CFG, .channels =3D 1, .buswidth =3D 4 }; =20 static struct qcom_icc_node slv_qhs_prng =3D { .name =3D "slv_qhs_prng", - .id =3D SC8180X_SLAVE_PRNG, .channels =3D 1, .buswidth =3D 4 }; =20 static struct qcom_icc_node slv_qhs_qdss_cfg =3D { .name =3D "slv_qhs_qdss_cfg", - .id =3D SC8180X_SLAVE_QDSS_CFG, .channels =3D 1, .buswidth =3D 4 }; =20 static struct qcom_icc_node slv_qhs_qspi_0 =3D { .name =3D "slv_qhs_qspi_0", - .id =3D SC8180X_SLAVE_QSPI_0, .channels =3D 1, .buswidth =3D 4 }; =20 static struct qcom_icc_node slv_qhs_qspi_1 =3D { .name =3D "slv_qhs_qspi_1", - .id =3D SC8180X_SLAVE_QSPI_1, .channels =3D 1, .buswidth =3D 4 }; =20 static struct qcom_icc_node slv_qhs_qupv3_east0 =3D { .name =3D "slv_qhs_qupv3_east0", - .id =3D SC8180X_SLAVE_QUP_1, .channels =3D 1, .buswidth =3D 4 }; =20 static struct qcom_icc_node slv_qhs_qupv3_east1 =3D { .name =3D "slv_qhs_qupv3_east1", - .id =3D SC8180X_SLAVE_QUP_2, .channels =3D 1, .buswidth =3D 4 }; =20 static struct qcom_icc_node slv_qhs_qupv3_west =3D { .name =3D "slv_qhs_qupv3_west", - .id =3D SC8180X_SLAVE_QUP_0, .channels =3D 1, .buswidth =3D 4 }; =20 static struct qcom_icc_node slv_qhs_sdc2 =3D { .name =3D "slv_qhs_sdc2", - .id =3D SC8180X_SLAVE_SDCC_2, .channels =3D 1, .buswidth =3D 4 }; =20 static struct qcom_icc_node slv_qhs_sdc4 =3D { .name =3D "slv_qhs_sdc4", - .id =3D SC8180X_SLAVE_SDCC_4, .channels =3D 1, .buswidth =3D 4 }; =20 static struct qcom_icc_node slv_qhs_security =3D { .name =3D "slv_qhs_security", - .id =3D SC8180X_SLAVE_SECURITY, .channels =3D 1, .buswidth =3D 4 }; =20 static struct qcom_icc_node slv_qhs_snoc_cfg =3D { .name =3D "slv_qhs_snoc_cfg", - .id =3D SC8180X_SLAVE_SNOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SC8180X_MASTER_SNOC_CFG } + .link_nodes =3D { &mas_qhm_snoc_cfg }, }; =20 static struct qcom_icc_node slv_qhs_spss_cfg =3D { .name =3D "slv_qhs_spss_cfg", - .id =3D SC8180X_SLAVE_SPSS_CFG, .channels =3D 1, .buswidth =3D 4 }; =20 static struct qcom_icc_node slv_qhs_tcsr =3D { .name =3D "slv_qhs_tcsr", - .id =3D SC8180X_SLAVE_TCSR, .channels =3D 1, .buswidth =3D 4 }; =20 static struct qcom_icc_node slv_qhs_tlmm_east =3D { .name =3D "slv_qhs_tlmm_east", - .id =3D SC8180X_SLAVE_TLMM_EAST, .channels =3D 1, .buswidth =3D 4 }; =20 static struct qcom_icc_node slv_qhs_tlmm_south =3D { .name =3D "slv_qhs_tlmm_south", - .id =3D SC8180X_SLAVE_TLMM_SOUTH, .channels =3D 1, .buswidth =3D 4 }; =20 static struct qcom_icc_node slv_qhs_tlmm_west =3D { .name =3D "slv_qhs_tlmm_west", - .id =3D SC8180X_SLAVE_TLMM_WEST, .channels =3D 1, .buswidth =3D 4 }; =20 static struct qcom_icc_node slv_qhs_tsif =3D { .name =3D "slv_qhs_tsif", - .id =3D SC8180X_SLAVE_TSIF, .channels =3D 1, .buswidth =3D 4 }; =20 static struct qcom_icc_node slv_qhs_ufs_card_cfg =3D { .name =3D "slv_qhs_ufs_card_cfg", - .id =3D SC8180X_SLAVE_UFS_CARD_CFG, .channels =3D 1, .buswidth =3D 4 }; =20 static struct qcom_icc_node slv_qhs_ufs_mem0_cfg =3D { .name =3D "slv_qhs_ufs_mem0_cfg", - .id =3D SC8180X_SLAVE_UFS_MEM_0_CFG, .channels =3D 1, .buswidth =3D 4 }; =20 static struct qcom_icc_node slv_qhs_ufs_mem1_cfg =3D { .name =3D "slv_qhs_ufs_mem1_cfg", - .id =3D SC8180X_SLAVE_UFS_MEM_1_CFG, .channels =3D 1, .buswidth =3D 4 }; =20 static struct qcom_icc_node slv_qhs_usb3_0 =3D { .name =3D "slv_qhs_usb3_0", - .id =3D SC8180X_SLAVE_USB3, .channels =3D 1, .buswidth =3D 4 }; =20 static struct qcom_icc_node slv_qhs_usb3_1 =3D { .name =3D "slv_qhs_usb3_1", - .id =3D SC8180X_SLAVE_USB3_1, .channels =3D 1, .buswidth =3D 4 }; =20 static struct qcom_icc_node slv_qhs_usb3_2 =3D { .name =3D "slv_qhs_usb3_2", - .id =3D SC8180X_SLAVE_USB3_2, .channels =3D 1, .buswidth =3D 4 }; =20 static struct qcom_icc_node slv_qhs_venus_cfg =3D { .name =3D "slv_qhs_venus_cfg", - .id =3D SC8180X_SLAVE_VENUS_CFG, .channels =3D 1, .buswidth =3D 4 }; =20 static struct qcom_icc_node slv_qhs_vsense_ctrl_cfg =3D { .name =3D "slv_qhs_vsense_ctrl_cfg", - .id =3D SC8180X_SLAVE_VSENSE_CTRL_CFG, .channels =3D 1, .buswidth =3D 4 }; =20 static struct qcom_icc_node slv_srvc_cnoc =3D { .name =3D "slv_srvc_cnoc", - .id =3D SC8180X_SLAVE_SERVICE_CNOC, .channels =3D 1, .buswidth =3D 4 }; =20 static struct qcom_icc_node slv_qhs_gemnoc =3D { .name =3D "slv_qhs_gemnoc", - .id =3D SC8180X_SLAVE_GEM_NOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SC8180X_MASTER_GEM_NOC_CFG } + .link_nodes =3D { &mas_qhm_gemnoc_cfg }, }; =20 static struct qcom_icc_node slv_qhs_llcc =3D { .name =3D "slv_qhs_llcc", - .id =3D SC8180X_SLAVE_LLCC_CFG, .channels =3D 1, .buswidth =3D 4 }; =20 static struct qcom_icc_node slv_qhs_mdsp_ms_mpu_cfg =3D { .name =3D "slv_qhs_mdsp_ms_mpu_cfg", - .id =3D SC8180X_SLAVE_MSS_PROC_MS_MPU_CFG, .channels =3D 1, .buswidth =3D 4 }; =20 static struct qcom_icc_node slv_qns_ecc =3D { .name =3D "slv_qns_ecc", - .id =3D SC8180X_SLAVE_ECC, .channels =3D 1, .buswidth =3D 32 }; =20 static struct qcom_icc_node slv_qns_gem_noc_snoc =3D { .name =3D "slv_qns_gem_noc_snoc", - .id =3D SC8180X_SLAVE_GEM_NOC_SNOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SC8180X_MASTER_GEM_NOC_SNOC } + .link_nodes =3D { &mas_qnm_gemnoc }, }; =20 static struct qcom_icc_node slv_qns_llcc =3D { .name =3D "slv_qns_llcc", - .id =3D SC8180X_SLAVE_LLCC, .channels =3D 8, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SC8180X_MASTER_LLCC } + .link_nodes =3D { &mas_llcc_mc }, }; =20 static struct qcom_icc_node slv_srvc_gemnoc =3D { .name =3D "slv_srvc_gemnoc", - .id =3D SC8180X_SLAVE_SERVICE_GEM_NOC, .channels =3D 1, .buswidth =3D 4 }; =20 static struct qcom_icc_node slv_srvc_gemnoc1 =3D { .name =3D "slv_srvc_gemnoc1", - .id =3D SC8180X_SLAVE_SERVICE_GEM_NOC_1, .channels =3D 1, .buswidth =3D 4 }; =20 static struct qcom_icc_node slv_ebi =3D { .name =3D "slv_ebi", - .id =3D SC8180X_SLAVE_EBI_CH0, .channels =3D 8, .buswidth =3D 4 }; =20 static struct qcom_icc_node slv_qns2_mem_noc =3D { .name =3D "slv_qns2_mem_noc", - .id =3D SC8180X_SLAVE_MNOC_SF_MEM_NOC, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SC8180X_MASTER_MNOC_SF_MEM_NOC } + .link_nodes =3D { &mas_qnm_mnoc_sf }, }; =20 static struct qcom_icc_node slv_qns_mem_noc_hf =3D { .name =3D "slv_qns_mem_noc_hf", - .id =3D SC8180X_SLAVE_MNOC_HF_MEM_NOC, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SC8180X_MASTER_MNOC_HF_MEM_NOC } + .link_nodes =3D { &mas_qnm_mnoc_hf }, }; =20 static struct qcom_icc_node slv_srvc_mnoc =3D { .name =3D "slv_srvc_mnoc", - .id =3D SC8180X_SLAVE_SERVICE_MNOC, .channels =3D 1, .buswidth =3D 4 }; =20 static struct qcom_icc_node slv_qhs_apss =3D { .name =3D "slv_qhs_apss", - .id =3D SC8180X_SLAVE_APPSS, .channels =3D 1, .buswidth =3D 8 }; =20 static struct qcom_icc_node slv_qns_cnoc =3D { .name =3D "slv_qns_cnoc", - .id =3D SC8180X_SNOC_CNOC_SLV, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SC8180X_SNOC_CNOC_MAS } + .link_nodes =3D { &mas_qnm_snoc }, }; =20 static struct qcom_icc_node slv_qns_gemnoc_gc =3D { .name =3D "slv_qns_gemnoc_gc", - .id =3D SC8180X_SLAVE_SNOC_GEM_NOC_GC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SC8180X_MASTER_SNOC_GC_MEM_NOC } + .link_nodes =3D { &mas_qnm_snoc_gc }, }; =20 static struct qcom_icc_node slv_qns_gemnoc_sf =3D { .name =3D "slv_qns_gemnoc_sf", - .id =3D SC8180X_SLAVE_SNOC_GEM_NOC_SF, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SC8180X_MASTER_SNOC_SF_MEM_NOC } + .link_nodes =3D { &mas_qnm_snoc_sf }, }; =20 static struct qcom_icc_node slv_qxs_imem =3D { .name =3D "slv_qxs_imem", - .id =3D SC8180X_SLAVE_OCIMEM, .channels =3D 1, .buswidth =3D 8 }; =20 static struct qcom_icc_node slv_qxs_pimem =3D { .name =3D "slv_qxs_pimem", - .id =3D SC8180X_SLAVE_PIMEM, .channels =3D 1, .buswidth =3D 8 }; =20 static struct qcom_icc_node slv_srvc_snoc =3D { .name =3D "slv_srvc_snoc", - .id =3D SC8180X_SLAVE_SERVICE_SNOC, .channels =3D 1, .buswidth =3D 4 }; =20 static struct qcom_icc_node slv_xs_pcie_0 =3D { .name =3D "slv_xs_pcie_0", - .id =3D SC8180X_SLAVE_PCIE_0, .channels =3D 1, .buswidth =3D 8 }; =20 static struct qcom_icc_node slv_xs_pcie_1 =3D { .name =3D "slv_xs_pcie_1", - .id =3D SC8180X_SLAVE_PCIE_1, .channels =3D 1, .buswidth =3D 8 }; =20 static struct qcom_icc_node slv_xs_pcie_2 =3D { .name =3D "slv_xs_pcie_2", - .id =3D SC8180X_SLAVE_PCIE_2, .channels =3D 1, .buswidth =3D 8 }; =20 static struct qcom_icc_node slv_xs_pcie_3 =3D { .name =3D "slv_xs_pcie_3", - .id =3D SC8180X_SLAVE_PCIE_3, .channels =3D 1, .buswidth =3D 8 }; =20 static struct qcom_icc_node slv_xs_qdss_stm =3D { .name =3D "slv_xs_qdss_stm", - .id =3D SC8180X_SLAVE_QDSS_STM, .channels =3D 1, .buswidth =3D 4 }; =20 static struct qcom_icc_node slv_xs_sys_tcu_cfg =3D { .name =3D "slv_xs_sys_tcu_cfg", - .id =3D SC8180X_SLAVE_TCU, .channels =3D 1, .buswidth =3D 8 }; =20 static struct qcom_icc_node slv_qup_core_0 =3D { .name =3D "slv_qup_core_0", - .id =3D SC8180X_SLAVE_QUP_CORE_0, .channels =3D 1, .buswidth =3D 4 }; =20 static struct qcom_icc_node slv_qup_core_1 =3D { .name =3D "slv_qup_core_1", - .id =3D SC8180X_SLAVE_QUP_CORE_1, .channels =3D 1, .buswidth =3D 4 }; =20 static struct qcom_icc_node slv_qup_core_2 =3D { .name =3D "slv_qup_core_2", - .id =3D SC8180X_SLAVE_QUP_CORE_2, .channels =3D 1, .buswidth =3D 4 }; @@ -1790,6 +1790,7 @@ static struct qcom_icc_node * const system_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sc8180x_aggre1_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D aggre1_noc_nodes, .num_nodes =3D ARRAY_SIZE(aggre1_noc_nodes), .bcms =3D aggre1_noc_bcms, @@ -1797,6 +1798,7 @@ static const struct qcom_icc_desc sc8180x_aggre1_noc = =3D { }; =20 static const struct qcom_icc_desc sc8180x_aggre2_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D aggre2_noc_nodes, .num_nodes =3D ARRAY_SIZE(aggre2_noc_nodes), .bcms =3D aggre2_noc_bcms, @@ -1804,6 +1806,7 @@ static const struct qcom_icc_desc sc8180x_aggre2_noc = =3D { }; =20 static const struct qcom_icc_desc sc8180x_camnoc_virt =3D { + .alloc_dyn_id =3D true, .nodes =3D camnoc_virt_nodes, .num_nodes =3D ARRAY_SIZE(camnoc_virt_nodes), .bcms =3D camnoc_virt_bcms, @@ -1811,6 +1814,7 @@ static const struct qcom_icc_desc sc8180x_camnoc_virt= =3D { }; =20 static const struct qcom_icc_desc sc8180x_compute_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D compute_noc_nodes, .num_nodes =3D ARRAY_SIZE(compute_noc_nodes), .bcms =3D compute_noc_bcms, @@ -1818,6 +1822,7 @@ static const struct qcom_icc_desc sc8180x_compute_noc= =3D { }; =20 static const struct qcom_icc_desc sc8180x_config_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D config_noc_nodes, .num_nodes =3D ARRAY_SIZE(config_noc_nodes), .bcms =3D config_noc_bcms, @@ -1825,11 +1830,13 @@ static const struct qcom_icc_desc sc8180x_config_no= c =3D { }; =20 static const struct qcom_icc_desc sc8180x_dc_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D dc_noc_nodes, .num_nodes =3D ARRAY_SIZE(dc_noc_nodes), }; =20 static const struct qcom_icc_desc sc8180x_gem_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D gem_noc_nodes, .num_nodes =3D ARRAY_SIZE(gem_noc_nodes), .bcms =3D gem_noc_bcms, @@ -1837,6 +1844,7 @@ static const struct qcom_icc_desc sc8180x_gem_noc = =3D { }; =20 static const struct qcom_icc_desc sc8180x_mc_virt =3D { + .alloc_dyn_id =3D true, .nodes =3D mc_virt_nodes, .num_nodes =3D ARRAY_SIZE(mc_virt_nodes), .bcms =3D mc_virt_bcms, @@ -1844,6 +1852,7 @@ static const struct qcom_icc_desc sc8180x_mc_virt = =3D { }; =20 static const struct qcom_icc_desc sc8180x_mmss_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D mmss_noc_nodes, .num_nodes =3D ARRAY_SIZE(mmss_noc_nodes), .bcms =3D mmss_noc_bcms, @@ -1851,6 +1860,7 @@ static const struct qcom_icc_desc sc8180x_mmss_noc = =3D { }; =20 static const struct qcom_icc_desc sc8180x_system_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D system_noc_nodes, .num_nodes =3D ARRAY_SIZE(system_noc_nodes), .bcms =3D system_noc_bcms, @@ -1871,6 +1881,7 @@ static struct qcom_icc_node * const qup_virt_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sc8180x_qup_virt =3D { + .alloc_dyn_id =3D true, .nodes =3D qup_virt_nodes, .num_nodes =3D ARRAY_SIZE(qup_virt_nodes), .bcms =3D qup_virt_bcms, diff --git a/drivers/interconnect/qcom/sc8180x.h b/drivers/interconnect/qco= m/sc8180x.h deleted file mode 100644 index f8d90598335a1d334a6b783bfe8569ab3c46b4f2..000000000000000000000000000= 0000000000000 --- a/drivers/interconnect/qcom/sc8180x.h +++ /dev/null @@ -1,179 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Qualcomm #define SC8180X interconnect IDs - * - * Copyright (c) 2020, The Linux Foundation. All rights reserved. - */ - -#ifndef __DRIVERS_INTERCONNECT_QCOM_SC8180X_H -#define __DRIVERS_INTERCONNECT_QCOM_SC8180X_H - -#define SC8180X_MASTER_A1NOC_CFG 1 -#define SC8180X_MASTER_UFS_CARD 2 -#define SC8180X_MASTER_UFS_GEN4 3 -#define SC8180X_MASTER_UFS_MEM 4 -#define SC8180X_MASTER_USB3 5 -#define SC8180X_MASTER_USB3_1 6 -#define SC8180X_MASTER_USB3_2 7 -#define SC8180X_MASTER_A2NOC_CFG 8 -#define SC8180X_MASTER_QDSS_BAM 9 -#define SC8180X_MASTER_QSPI_0 10 -#define SC8180X_MASTER_QSPI_1 11 -#define SC8180X_MASTER_QUP_0 12 -#define SC8180X_MASTER_QUP_1 13 -#define SC8180X_MASTER_QUP_2 14 -#define SC8180X_MASTER_SENSORS_AHB 15 -#define SC8180X_MASTER_CRYPTO_CORE_0 16 -#define SC8180X_MASTER_IPA 17 -#define SC8180X_MASTER_EMAC 18 -#define SC8180X_MASTER_PCIE 19 -#define SC8180X_MASTER_PCIE_1 20 -#define SC8180X_MASTER_PCIE_2 21 -#define SC8180X_MASTER_PCIE_3 22 -#define SC8180X_MASTER_QDSS_ETR 23 -#define SC8180X_MASTER_SDCC_2 24 -#define SC8180X_MASTER_SDCC_4 25 -#define SC8180X_MASTER_CAMNOC_HF0_UNCOMP 26 -#define SC8180X_MASTER_CAMNOC_HF1_UNCOMP 27 -#define SC8180X_MASTER_CAMNOC_SF_UNCOMP 28 -#define SC8180X_MASTER_NPU 29 -#define SC8180X_SNOC_CNOC_MAS 30 -#define SC8180X_MASTER_CNOC_DC_NOC 31 -#define SC8180X_MASTER_AMPSS_M0 32 -#define SC8180X_MASTER_GPU_TCU 33 -#define SC8180X_MASTER_SYS_TCU 34 -#define SC8180X_MASTER_GEM_NOC_CFG 35 -#define SC8180X_MASTER_COMPUTE_NOC 36 -#define SC8180X_MASTER_GRAPHICS_3D 37 -#define SC8180X_MASTER_MNOC_HF_MEM_NOC 38 -#define SC8180X_MASTER_MNOC_SF_MEM_NOC 39 -#define SC8180X_MASTER_GEM_NOC_PCIE_SNOC 40 -#define SC8180X_MASTER_SNOC_GC_MEM_NOC 41 -#define SC8180X_MASTER_SNOC_SF_MEM_NOC 42 -#define SC8180X_MASTER_ECC 43 -/* 44 was used by MASTER_IPA_CORE, now represented as RPMh clock */ -#define SC8180X_MASTER_LLCC 45 -#define SC8180X_MASTER_CNOC_MNOC_CFG 46 -#define SC8180X_MASTER_CAMNOC_HF0 47 -#define SC8180X_MASTER_CAMNOC_HF1 48 -#define SC8180X_MASTER_CAMNOC_SF 49 -#define SC8180X_MASTER_MDP_PORT0 50 -#define SC8180X_MASTER_MDP_PORT1 51 -#define SC8180X_MASTER_ROTATOR 52 -#define SC8180X_MASTER_VIDEO_P0 53 -#define SC8180X_MASTER_VIDEO_P1 54 -#define SC8180X_MASTER_VIDEO_PROC 55 -#define SC8180X_MASTER_SNOC_CFG 56 -#define SC8180X_A1NOC_SNOC_MAS 57 -#define SC8180X_A2NOC_SNOC_MAS 58 -#define SC8180X_MASTER_GEM_NOC_SNOC 59 -#define SC8180X_MASTER_PIMEM 60 -#define SC8180X_MASTER_GIC 61 -#define SC8180X_MASTER_MNOC_HF_MEM_NOC_DISPLAY 62 -#define SC8180X_MASTER_MNOC_SF_MEM_NOC_DISPLAY 63 -#define SC8180X_MASTER_LLCC_DISPLAY 64 -#define SC8180X_MASTER_MDP_PORT0_DISPLAY 65 -#define SC8180X_MASTER_MDP_PORT1_DISPLAY 66 -#define SC8180X_MASTER_ROTATOR_DISPLAY 67 -#define SC8180X_A1NOC_SNOC_SLV 68 -#define SC8180X_SLAVE_SERVICE_A1NOC 69 -#define SC8180X_A2NOC_SNOC_SLV 70 -#define SC8180X_SLAVE_ANOC_PCIE_GEM_NOC 71 -#define SC8180X_SLAVE_SERVICE_A2NOC 72 -#define SC8180X_SLAVE_CAMNOC_UNCOMP 73 -#define SC8180X_SLAVE_CDSP_MEM_NOC 74 -#define SC8180X_SLAVE_A1NOC_CFG 75 -#define SC8180X_SLAVE_A2NOC_CFG 76 -#define SC8180X_SLAVE_AHB2PHY_CENTER 77 -#define SC8180X_SLAVE_AHB2PHY_EAST 78 -#define SC8180X_SLAVE_AHB2PHY_WEST 79 -#define SC8180X_SLAVE_AHB2PHY_SOUTH 80 -#define SC8180X_SLAVE_AOP 81 -#define SC8180X_SLAVE_AOSS 82 -#define SC8180X_SLAVE_CAMERA_CFG 83 -#define SC8180X_SLAVE_CLK_CTL 84 -#define SC8180X_SLAVE_CDSP_CFG 85 -#define SC8180X_SLAVE_RBCPR_CX_CFG 86 -#define SC8180X_SLAVE_RBCPR_MMCX_CFG 87 -#define SC8180X_SLAVE_RBCPR_MX_CFG 88 -#define SC8180X_SLAVE_CRYPTO_0_CFG 89 -#define SC8180X_SLAVE_CNOC_DDRSS 90 -#define SC8180X_SLAVE_DISPLAY_CFG 91 -#define SC8180X_SLAVE_EMAC_CFG 92 -#define SC8180X_SLAVE_GLM 93 -#define SC8180X_SLAVE_GRAPHICS_3D_CFG 94 -#define SC8180X_SLAVE_IMEM_CFG 95 -#define SC8180X_SLAVE_IPA_CFG 96 -#define SC8180X_SLAVE_CNOC_MNOC_CFG 97 -#define SC8180X_SLAVE_NPU_CFG 98 -#define SC8180X_SLAVE_PCIE_0_CFG 99 -#define SC8180X_SLAVE_PCIE_1_CFG 100 -#define SC8180X_SLAVE_PCIE_2_CFG 101 -#define SC8180X_SLAVE_PCIE_3_CFG 102 -#define SC8180X_SLAVE_PDM 103 -#define SC8180X_SLAVE_PIMEM_CFG 104 -#define SC8180X_SLAVE_PRNG 105 -#define SC8180X_SLAVE_QDSS_CFG 106 -#define SC8180X_SLAVE_QSPI_0 107 -#define SC8180X_SLAVE_QSPI_1 108 -#define SC8180X_SLAVE_QUP_1 109 -#define SC8180X_SLAVE_QUP_2 110 -#define SC8180X_SLAVE_QUP_0 111 -#define SC8180X_SLAVE_SDCC_2 112 -#define SC8180X_SLAVE_SDCC_4 113 -#define SC8180X_SLAVE_SECURITY 114 -#define SC8180X_SLAVE_SNOC_CFG 115 -#define SC8180X_SLAVE_SPSS_CFG 116 -#define SC8180X_SLAVE_TCSR 117 -#define SC8180X_SLAVE_TLMM_EAST 118 -#define SC8180X_SLAVE_TLMM_SOUTH 119 -#define SC8180X_SLAVE_TLMM_WEST 120 -#define SC8180X_SLAVE_TSIF 121 -#define SC8180X_SLAVE_UFS_CARD_CFG 122 -#define SC8180X_SLAVE_UFS_MEM_0_CFG 123 -#define SC8180X_SLAVE_UFS_MEM_1_CFG 124 -#define SC8180X_SLAVE_USB3 125 -#define SC8180X_SLAVE_USB3_1 126 -#define SC8180X_SLAVE_USB3_2 127 -#define SC8180X_SLAVE_VENUS_CFG 128 -#define SC8180X_SLAVE_VSENSE_CTRL_CFG 129 -#define SC8180X_SLAVE_SERVICE_CNOC 130 -#define SC8180X_SLAVE_GEM_NOC_CFG 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This gives more flexibility and also allows us to drop the .num_links member, saving from possible errors related to it being not set or set incorrectly. Signed-off-by: Dmitry Baryshkov --- drivers/interconnect/qcom/sc8280xp.c | 837 +++++++++++++++++--------------= ---- drivers/interconnect/qcom/sc8280xp.h | 209 --------- 2 files changed, 416 insertions(+), 630 deletions(-) diff --git a/drivers/interconnect/qcom/sc8280xp.c b/drivers/interconnect/qc= om/sc8280xp.c index c646cdf8a19bf6f5a581cd9491b104259259fff3..c46846191e63f41a16dd3af5f0a= 77919b4b14568 100644 --- a/drivers/interconnect/qcom/sc8280xp.c +++ b/drivers/interconnect/qcom/sc8280xp.c @@ -14,1699 +14,1682 @@ =20 #include "bcm-voter.h" #include "icc-rpmh.h" -#include "sc8280xp.h" + +static struct qcom_icc_node qhm_qspi; +static struct qcom_icc_node qhm_qup1; +static struct qcom_icc_node qhm_qup2; +static struct qcom_icc_node qnm_a1noc_cfg; +static struct qcom_icc_node qxm_ipa; +static struct qcom_icc_node xm_emac_1; +static struct qcom_icc_node xm_sdc4; +static struct qcom_icc_node xm_ufs_mem; +static struct qcom_icc_node xm_usb3_0; +static struct qcom_icc_node xm_usb3_1; +static struct qcom_icc_node xm_usb3_mp; +static struct qcom_icc_node xm_usb4_host0; +static struct qcom_icc_node xm_usb4_host1; +static struct qcom_icc_node qhm_qdss_bam; +static struct qcom_icc_node qhm_qup0; +static struct qcom_icc_node qnm_a2noc_cfg; +static struct qcom_icc_node qxm_crypto; +static struct qcom_icc_node qxm_sensorss_q6; +static struct qcom_icc_node qxm_sp; +static struct qcom_icc_node xm_emac_0; +static struct qcom_icc_node xm_pcie3_0; +static struct qcom_icc_node xm_pcie3_1; +static struct qcom_icc_node xm_pcie3_2a; +static struct qcom_icc_node xm_pcie3_2b; +static struct qcom_icc_node xm_pcie3_3a; +static struct qcom_icc_node xm_pcie3_3b; +static struct qcom_icc_node xm_pcie3_4; +static struct qcom_icc_node xm_qdss_etr; +static struct qcom_icc_node xm_sdc2; +static struct qcom_icc_node xm_ufs_card; +static struct qcom_icc_node qup0_core_master; +static struct qcom_icc_node qup1_core_master; +static struct qcom_icc_node qup2_core_master; +static struct qcom_icc_node qnm_gemnoc_cnoc; +static struct qcom_icc_node qnm_gemnoc_pcie; +static struct qcom_icc_node qnm_cnoc_dc_noc; +static struct qcom_icc_node alm_gpu_tcu; +static struct qcom_icc_node alm_pcie_tcu; +static struct qcom_icc_node alm_sys_tcu; +static struct qcom_icc_node chm_apps; +static struct qcom_icc_node qnm_cmpnoc0; +static struct qcom_icc_node qnm_cmpnoc1; +static struct qcom_icc_node qnm_gemnoc_cfg; +static struct qcom_icc_node qnm_gpu; +static struct qcom_icc_node qnm_mnoc_hf; +static struct qcom_icc_node qnm_mnoc_sf; +static struct qcom_icc_node qnm_pcie; +static struct qcom_icc_node qnm_snoc_gc; +static struct qcom_icc_node qnm_snoc_sf; +static struct qcom_icc_node qhm_config_noc; +static struct qcom_icc_node qxm_lpass_dsp; +static struct qcom_icc_node llcc_mc; +static struct qcom_icc_node qnm_camnoc_hf; +static struct qcom_icc_node qnm_mdp0_0; +static struct qcom_icc_node qnm_mdp0_1; +static struct qcom_icc_node qnm_mdp1_0; +static struct qcom_icc_node qnm_mdp1_1; +static struct qcom_icc_node qnm_mnoc_cfg; +static struct qcom_icc_node qnm_rot_0; +static struct qcom_icc_node qnm_rot_1; +static struct qcom_icc_node qnm_video0; +static struct qcom_icc_node qnm_video1; +static struct qcom_icc_node qnm_video_cvp; +static struct qcom_icc_node qxm_camnoc_icp; +static struct qcom_icc_node qxm_camnoc_sf; +static struct qcom_icc_node qhm_nsp_noc_config; +static struct qcom_icc_node qxm_nsp; +static struct qcom_icc_node qhm_nspb_noc_config; +static struct qcom_icc_node qxm_nspb; +static struct qcom_icc_node qnm_aggre1_noc; +static struct qcom_icc_node qnm_aggre2_noc; +static struct qcom_icc_node qnm_aggre_usb_noc; +static struct qcom_icc_node qnm_lpass_noc; +static struct qcom_icc_node qnm_snoc_cfg; +static struct qcom_icc_node qxm_pimem; +static struct qcom_icc_node xm_gic; +static struct qcom_icc_node qns_a1noc_snoc; +static struct qcom_icc_node qns_aggre_usb_snoc; +static struct qcom_icc_node srvc_aggre1_noc; +static struct qcom_icc_node qns_a2noc_snoc; +static struct qcom_icc_node qns_pcie_gem_noc; +static struct qcom_icc_node srvc_aggre2_noc; +static struct qcom_icc_node qup0_core_slave; +static struct qcom_icc_node qup1_core_slave; +static struct qcom_icc_node qup2_core_slave; +static struct qcom_icc_node qhs_ahb2phy0; +static struct qcom_icc_node qhs_ahb2phy1; +static struct qcom_icc_node qhs_ahb2phy2; +static struct qcom_icc_node qhs_aoss; +static struct qcom_icc_node qhs_apss; +static struct qcom_icc_node qhs_camera_cfg; +static struct qcom_icc_node qhs_clk_ctl; +static struct qcom_icc_node qhs_compute0_cfg; +static struct qcom_icc_node qhs_compute1_cfg; +static struct qcom_icc_node qhs_cpr_cx; +static struct qcom_icc_node qhs_cpr_mmcx; +static struct qcom_icc_node qhs_cpr_mx; +static struct qcom_icc_node qhs_cpr_nspcx; +static struct qcom_icc_node qhs_crypto0_cfg; +static struct qcom_icc_node qhs_cx_rdpm; +static struct qcom_icc_node qhs_dcc_cfg; +static struct qcom_icc_node qhs_display0_cfg; +static struct qcom_icc_node qhs_display1_cfg; +static struct qcom_icc_node qhs_emac0_cfg; +static struct qcom_icc_node qhs_emac1_cfg; +static struct qcom_icc_node qhs_gpuss_cfg; +static struct qcom_icc_node qhs_hwkm; +static struct qcom_icc_node qhs_imem_cfg; +static struct qcom_icc_node qhs_ipa; +static struct qcom_icc_node qhs_ipc_router; +static struct qcom_icc_node qhs_lpass_cfg; +static struct qcom_icc_node qhs_mx_rdpm; +static struct qcom_icc_node qhs_mxc_rdpm; +static struct qcom_icc_node qhs_pcie0_cfg; +static struct qcom_icc_node qhs_pcie1_cfg; +static struct qcom_icc_node qhs_pcie2a_cfg; +static struct qcom_icc_node qhs_pcie2b_cfg; +static struct qcom_icc_node qhs_pcie3a_cfg; +static struct qcom_icc_node qhs_pcie3b_cfg; +static struct qcom_icc_node qhs_pcie4_cfg; +static struct qcom_icc_node qhs_pcie_rsc_cfg; +static struct qcom_icc_node qhs_pdm; +static struct qcom_icc_node qhs_pimem_cfg; +static struct qcom_icc_node qhs_pka_wrapper_cfg; +static struct qcom_icc_node qhs_pmu_wrapper_cfg; +static struct qcom_icc_node qhs_qdss_cfg; +static struct qcom_icc_node qhs_qspi; +static struct qcom_icc_node qhs_qup0; +static struct qcom_icc_node qhs_qup1; +static struct qcom_icc_node qhs_qup2; +static struct qcom_icc_node qhs_sdc2; +static struct qcom_icc_node qhs_sdc4; +static struct qcom_icc_node qhs_security; +static struct qcom_icc_node qhs_smmuv3_cfg; +static struct qcom_icc_node qhs_smss_cfg; +static struct qcom_icc_node qhs_spss_cfg; +static struct qcom_icc_node qhs_tcsr; +static struct qcom_icc_node qhs_tlmm; +static struct qcom_icc_node qhs_ufs_card_cfg; +static struct qcom_icc_node qhs_ufs_mem_cfg; +static struct qcom_icc_node qhs_usb3_0; +static struct qcom_icc_node qhs_usb3_1; +static struct qcom_icc_node qhs_usb3_mp; +static struct qcom_icc_node qhs_usb4_host_0; +static struct qcom_icc_node qhs_usb4_host_1; +static struct qcom_icc_node qhs_venus_cfg; +static struct qcom_icc_node qhs_vsense_ctrl_cfg; +static struct qcom_icc_node qhs_vsense_ctrl_r_cfg; +static struct qcom_icc_node qns_a1_noc_cfg; +static struct qcom_icc_node qns_a2_noc_cfg; +static struct qcom_icc_node qns_anoc_pcie_bridge_cfg; +static struct qcom_icc_node qns_ddrss_cfg; +static struct qcom_icc_node qns_mnoc_cfg; +static struct qcom_icc_node qns_snoc_cfg; +static struct qcom_icc_node qns_snoc_sf_bridge_cfg; +static struct qcom_icc_node qxs_imem; +static struct qcom_icc_node qxs_pimem; +static struct qcom_icc_node srvc_cnoc; +static struct qcom_icc_node xs_pcie_0; +static struct qcom_icc_node xs_pcie_1; +static struct qcom_icc_node xs_pcie_2a; +static struct qcom_icc_node xs_pcie_2b; +static struct qcom_icc_node xs_pcie_3a; +static struct qcom_icc_node xs_pcie_3b; +static struct qcom_icc_node xs_pcie_4; +static struct qcom_icc_node xs_qdss_stm; +static struct qcom_icc_node xs_smss; +static struct qcom_icc_node xs_sys_tcu_cfg; +static struct qcom_icc_node qhs_llcc; +static struct qcom_icc_node qns_gemnoc; +static struct qcom_icc_node qns_gem_noc_cnoc; +static struct qcom_icc_node qns_llcc; +static struct qcom_icc_node qns_pcie; +static struct qcom_icc_node srvc_even_gemnoc; +static struct qcom_icc_node srvc_odd_gemnoc; +static struct qcom_icc_node srvc_sys_gemnoc; +static struct qcom_icc_node qhs_lpass_core; +static struct qcom_icc_node qhs_lpass_lpi; +static struct qcom_icc_node qhs_lpass_mpu; +static struct qcom_icc_node qhs_lpass_top; +static struct qcom_icc_node qns_sysnoc; +static struct qcom_icc_node srvc_niu_aml_noc; +static struct qcom_icc_node srvc_niu_lpass_agnoc; +static struct qcom_icc_node ebi; +static struct qcom_icc_node qns_mem_noc_hf; +static struct qcom_icc_node qns_mem_noc_sf; +static struct qcom_icc_node srvc_mnoc; +static struct qcom_icc_node qns_nsp_gemnoc; +static struct qcom_icc_node qxs_nsp_xfr; +static struct qcom_icc_node service_nsp_noc; +static struct qcom_icc_node qns_nspb_gemnoc; +static struct qcom_icc_node qxs_nspb_xfr; +static struct qcom_icc_node service_nspb_noc; +static struct qcom_icc_node qns_gemnoc_gc; +static struct qcom_icc_node qns_gemnoc_sf; +static struct qcom_icc_node srvc_snoc; =20 static struct qcom_icc_node qhm_qspi =3D { .name =3D "qhm_qspi", - .id =3D SC8280XP_MASTER_QSPI_0, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SC8280XP_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node qhm_qup1 =3D { .name =3D "qhm_qup1", - .id =3D SC8280XP_MASTER_QUP_1, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SC8280XP_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node qhm_qup2 =3D { .name =3D "qhm_qup2", - .id =3D SC8280XP_MASTER_QUP_2, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SC8280XP_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node qnm_a1noc_cfg =3D { .name =3D "qnm_a1noc_cfg", - .id =3D SC8280XP_MASTER_A1NOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SC8280XP_SLAVE_SERVICE_A1NOC }, + .link_nodes =3D { &srvc_aggre1_noc }, }; =20 static struct qcom_icc_node qxm_ipa =3D { .name =3D "qxm_ipa", - .id =3D SC8280XP_MASTER_IPA, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SC8280XP_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node xm_emac_1 =3D { .name =3D "xm_emac_1", - .id =3D SC8280XP_MASTER_EMAC_1, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SC8280XP_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node xm_sdc4 =3D { .name =3D "xm_sdc4", - .id =3D SC8280XP_MASTER_SDCC_4, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SC8280XP_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node xm_ufs_mem =3D { .name =3D "xm_ufs_mem", - .id =3D SC8280XP_MASTER_UFS_MEM, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SC8280XP_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node xm_usb3_0 =3D { .name =3D "xm_usb3_0", - .id =3D SC8280XP_MASTER_USB3_0, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SC8280XP_SLAVE_USB_NOC_SNOC }, + .link_nodes =3D { &qns_aggre_usb_snoc }, }; =20 static struct qcom_icc_node xm_usb3_1 =3D { .name =3D "xm_usb3_1", - .id =3D SC8280XP_MASTER_USB3_1, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SC8280XP_SLAVE_USB_NOC_SNOC }, + .link_nodes =3D { &qns_aggre_usb_snoc }, }; =20 static struct qcom_icc_node xm_usb3_mp =3D { .name =3D "xm_usb3_mp", - .id =3D SC8280XP_MASTER_USB3_MP, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SC8280XP_SLAVE_USB_NOC_SNOC }, + .link_nodes =3D { &qns_aggre_usb_snoc }, }; =20 static struct qcom_icc_node xm_usb4_host0 =3D { .name =3D "xm_usb4_host0", - .id =3D SC8280XP_MASTER_USB4_0, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SC8280XP_SLAVE_USB_NOC_SNOC }, + .link_nodes =3D { &qns_aggre_usb_snoc }, }; =20 static struct qcom_icc_node xm_usb4_host1 =3D { .name =3D "xm_usb4_host1", - .id =3D SC8280XP_MASTER_USB4_1, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SC8280XP_SLAVE_USB_NOC_SNOC }, + .link_nodes =3D { &qns_aggre_usb_snoc }, }; =20 static struct qcom_icc_node qhm_qdss_bam =3D { .name =3D "qhm_qdss_bam", - .id =3D SC8280XP_MASTER_QDSS_BAM, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SC8280XP_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qhm_qup0 =3D { .name =3D "qhm_qup0", - .id =3D SC8280XP_MASTER_QUP_0, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SC8280XP_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qnm_a2noc_cfg =3D { .name =3D "qnm_a2noc_cfg", - .id =3D SC8280XP_MASTER_A2NOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SC8280XP_SLAVE_SERVICE_A2NOC }, + .link_nodes =3D { &srvc_aggre2_noc }, }; =20 static struct qcom_icc_node qxm_crypto =3D { .name =3D "qxm_crypto", - .id =3D SC8280XP_MASTER_CRYPTO, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SC8280XP_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qxm_sensorss_q6 =3D { .name =3D "qxm_sensorss_q6", - .id =3D SC8280XP_MASTER_SENSORS_PROC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SC8280XP_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qxm_sp =3D { .name =3D "qxm_sp", - .id =3D SC8280XP_MASTER_SP, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SC8280XP_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node xm_emac_0 =3D { .name =3D "xm_emac_0", - .id =3D SC8280XP_MASTER_EMAC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SC8280XP_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node xm_pcie3_0 =3D { .name =3D "xm_pcie3_0", - .id =3D SC8280XP_MASTER_PCIE_0, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SC8280XP_SLAVE_ANOC_PCIE_GEM_NOC }, + .link_nodes =3D { &qns_pcie_gem_noc }, }; =20 static struct qcom_icc_node xm_pcie3_1 =3D { .name =3D "xm_pcie3_1", - .id =3D SC8280XP_MASTER_PCIE_1, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SC8280XP_SLAVE_ANOC_PCIE_GEM_NOC }, + .link_nodes =3D { &qns_pcie_gem_noc }, }; =20 static struct qcom_icc_node xm_pcie3_2a =3D { .name =3D "xm_pcie3_2a", - .id =3D SC8280XP_MASTER_PCIE_2A, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SC8280XP_SLAVE_ANOC_PCIE_GEM_NOC }, + .link_nodes =3D { &qns_pcie_gem_noc }, }; =20 static struct qcom_icc_node xm_pcie3_2b =3D { .name =3D "xm_pcie3_2b", - .id =3D SC8280XP_MASTER_PCIE_2B, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SC8280XP_SLAVE_ANOC_PCIE_GEM_NOC }, + .link_nodes =3D { &qns_pcie_gem_noc }, }; =20 static struct qcom_icc_node xm_pcie3_3a =3D { .name =3D "xm_pcie3_3a", - .id =3D SC8280XP_MASTER_PCIE_3A, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SC8280XP_SLAVE_ANOC_PCIE_GEM_NOC }, + .link_nodes =3D { &qns_pcie_gem_noc }, }; =20 static struct qcom_icc_node xm_pcie3_3b =3D { .name =3D "xm_pcie3_3b", - .id =3D SC8280XP_MASTER_PCIE_3B, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SC8280XP_SLAVE_ANOC_PCIE_GEM_NOC }, + .link_nodes =3D { &qns_pcie_gem_noc }, }; =20 static struct qcom_icc_node xm_pcie3_4 =3D { .name =3D "xm_pcie3_4", - .id =3D SC8280XP_MASTER_PCIE_4, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SC8280XP_SLAVE_ANOC_PCIE_GEM_NOC }, + .link_nodes =3D { &qns_pcie_gem_noc }, }; =20 static struct qcom_icc_node xm_qdss_etr =3D { .name =3D "xm_qdss_etr", - .id =3D SC8280XP_MASTER_QDSS_ETR, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SC8280XP_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node xm_sdc2 =3D { .name =3D "xm_sdc2", - .id =3D SC8280XP_MASTER_SDCC_2, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SC8280XP_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node xm_ufs_card =3D { .name =3D "xm_ufs_card", - .id =3D SC8280XP_MASTER_UFS_CARD, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SC8280XP_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qup0_core_master =3D { .name =3D "qup0_core_master", - .id =3D SC8280XP_MASTER_QUP_CORE_0, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SC8280XP_SLAVE_QUP_CORE_0 }, + .link_nodes =3D { &qup0_core_slave }, }; =20 static struct qcom_icc_node qup1_core_master =3D { .name =3D "qup1_core_master", - .id =3D SC8280XP_MASTER_QUP_CORE_1, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SC8280XP_SLAVE_QUP_CORE_1 }, + .link_nodes =3D { &qup1_core_slave }, }; =20 static struct qcom_icc_node qup2_core_master =3D { .name =3D "qup2_core_master", - .id =3D SC8280XP_MASTER_QUP_CORE_2, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SC8280XP_SLAVE_QUP_CORE_2 }, + .link_nodes =3D { &qup2_core_slave }, }; =20 static struct qcom_icc_node qnm_gemnoc_cnoc =3D { .name =3D "qnm_gemnoc_cnoc", - .id =3D SC8280XP_MASTER_GEM_NOC_CNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 76, - .links =3D { SC8280XP_SLAVE_AHB2PHY_0, - SC8280XP_SLAVE_AHB2PHY_1, - SC8280XP_SLAVE_AHB2PHY_2, - SC8280XP_SLAVE_AOSS, - SC8280XP_SLAVE_APPSS, - SC8280XP_SLAVE_CAMERA_CFG, - SC8280XP_SLAVE_CLK_CTL, - SC8280XP_SLAVE_CDSP_CFG, - SC8280XP_SLAVE_CDSP1_CFG, - SC8280XP_SLAVE_RBCPR_CX_CFG, - SC8280XP_SLAVE_RBCPR_MMCX_CFG, - SC8280XP_SLAVE_RBCPR_MX_CFG, - SC8280XP_SLAVE_CPR_NSPCX, - SC8280XP_SLAVE_CRYPTO_0_CFG, - SC8280XP_SLAVE_CX_RDPM, - SC8280XP_SLAVE_DCC_CFG, - SC8280XP_SLAVE_DISPLAY_CFG, - SC8280XP_SLAVE_DISPLAY1_CFG, - SC8280XP_SLAVE_EMAC_CFG, - SC8280XP_SLAVE_EMAC1_CFG, - SC8280XP_SLAVE_GFX3D_CFG, - SC8280XP_SLAVE_HWKM, - SC8280XP_SLAVE_IMEM_CFG, - SC8280XP_SLAVE_IPA_CFG, - SC8280XP_SLAVE_IPC_ROUTER_CFG, - SC8280XP_SLAVE_LPASS, - SC8280XP_SLAVE_MX_RDPM, - SC8280XP_SLAVE_MXC_RDPM, - SC8280XP_SLAVE_PCIE_0_CFG, - SC8280XP_SLAVE_PCIE_1_CFG, - SC8280XP_SLAVE_PCIE_2A_CFG, - SC8280XP_SLAVE_PCIE_2B_CFG, - SC8280XP_SLAVE_PCIE_3A_CFG, - SC8280XP_SLAVE_PCIE_3B_CFG, - SC8280XP_SLAVE_PCIE_4_CFG, - SC8280XP_SLAVE_PCIE_RSC_CFG, - SC8280XP_SLAVE_PDM, - SC8280XP_SLAVE_PIMEM_CFG, - SC8280XP_SLAVE_PKA_WRAPPER_CFG, - SC8280XP_SLAVE_PMU_WRAPPER_CFG, - SC8280XP_SLAVE_QDSS_CFG, - SC8280XP_SLAVE_QSPI_0, - SC8280XP_SLAVE_QUP_0, - SC8280XP_SLAVE_QUP_1, - SC8280XP_SLAVE_QUP_2, - SC8280XP_SLAVE_SDCC_2, - SC8280XP_SLAVE_SDCC_4, - SC8280XP_SLAVE_SECURITY, - SC8280XP_SLAVE_SMMUV3_CFG, - SC8280XP_SLAVE_SMSS_CFG, - SC8280XP_SLAVE_SPSS_CFG, - SC8280XP_SLAVE_TCSR, - SC8280XP_SLAVE_TLMM, - SC8280XP_SLAVE_UFS_CARD_CFG, - SC8280XP_SLAVE_UFS_MEM_CFG, - SC8280XP_SLAVE_USB3_0, - SC8280XP_SLAVE_USB3_1, - SC8280XP_SLAVE_USB3_MP, - SC8280XP_SLAVE_USB4_0, - SC8280XP_SLAVE_USB4_1, - SC8280XP_SLAVE_VENUS_CFG, - SC8280XP_SLAVE_VSENSE_CTRL_CFG, - SC8280XP_SLAVE_VSENSE_CTRL_R_CFG, - SC8280XP_SLAVE_A1NOC_CFG, - SC8280XP_SLAVE_A2NOC_CFG, - SC8280XP_SLAVE_ANOC_PCIE_BRIDGE_CFG, - SC8280XP_SLAVE_DDRSS_CFG, - SC8280XP_SLAVE_CNOC_MNOC_CFG, - SC8280XP_SLAVE_SNOC_CFG, - SC8280XP_SLAVE_SNOC_SF_BRIDGE_CFG, - SC8280XP_SLAVE_IMEM, - SC8280XP_SLAVE_PIMEM, - SC8280XP_SLAVE_SERVICE_CNOC, - SC8280XP_SLAVE_QDSS_STM, - SC8280XP_SLAVE_SMSS, - SC8280XP_SLAVE_TCU - }, + .link_nodes =3D { &qhs_ahb2phy0, + &qhs_ahb2phy1, + &qhs_ahb2phy2, + &qhs_aoss, + &qhs_apss, + &qhs_camera_cfg, + &qhs_clk_ctl, + &qhs_compute0_cfg, + &qhs_compute1_cfg, + &qhs_cpr_cx, + &qhs_cpr_mmcx, + &qhs_cpr_mx, + &qhs_cpr_nspcx, + &qhs_crypto0_cfg, + &qhs_cx_rdpm, + &qhs_dcc_cfg, + &qhs_display0_cfg, + &qhs_display1_cfg, + &qhs_emac0_cfg, + &qhs_emac1_cfg, + &qhs_gpuss_cfg, + &qhs_hwkm, + &qhs_imem_cfg, + &qhs_ipa, + &qhs_ipc_router, + &qhs_lpass_cfg, + &qhs_mx_rdpm, + &qhs_mxc_rdpm, + &qhs_pcie0_cfg, + &qhs_pcie1_cfg, + &qhs_pcie2a_cfg, + &qhs_pcie2b_cfg, + &qhs_pcie3a_cfg, + &qhs_pcie3b_cfg, + &qhs_pcie4_cfg, + &qhs_pcie_rsc_cfg, + &qhs_pdm, + &qhs_pimem_cfg, + &qhs_pka_wrapper_cfg, + &qhs_pmu_wrapper_cfg, + &qhs_qdss_cfg, + &qhs_qspi, + &qhs_qup0, + &qhs_qup1, + &qhs_qup2, + &qhs_sdc2, + &qhs_sdc4, + &qhs_security, + &qhs_smmuv3_cfg, + &qhs_smss_cfg, + &qhs_spss_cfg, + &qhs_tcsr, + &qhs_tlmm, + &qhs_ufs_card_cfg, + &qhs_ufs_mem_cfg, + &qhs_usb3_0, + &qhs_usb3_1, + &qhs_usb3_mp, + &qhs_usb4_host_0, + &qhs_usb4_host_1, + &qhs_venus_cfg, + &qhs_vsense_ctrl_cfg, + &qhs_vsense_ctrl_r_cfg, + &qns_a1_noc_cfg, + &qns_a2_noc_cfg, + &qns_anoc_pcie_bridge_cfg, + &qns_ddrss_cfg, + &qns_mnoc_cfg, + &qns_snoc_cfg, + &qns_snoc_sf_bridge_cfg, + &qxs_imem, + &qxs_pimem, + &srvc_cnoc, + &xs_qdss_stm, + &xs_smss, + &xs_sys_tcu_cfg, + NULL }, }; =20 static struct qcom_icc_node qnm_gemnoc_pcie =3D { .name =3D "qnm_gemnoc_pcie", - .id =3D SC8280XP_MASTER_GEM_NOC_PCIE_SNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 7, - .links =3D { SC8280XP_SLAVE_PCIE_0, - SC8280XP_SLAVE_PCIE_1, - SC8280XP_SLAVE_PCIE_2A, - SC8280XP_SLAVE_PCIE_2B, - SC8280XP_SLAVE_PCIE_3A, - SC8280XP_SLAVE_PCIE_3B, - SC8280XP_SLAVE_PCIE_4 - }, + .link_nodes =3D { &xs_pcie_0, + &xs_pcie_1, + &xs_pcie_2a, + &xs_pcie_2b, + &xs_pcie_3a, + &xs_pcie_3b, + &xs_pcie_4 }, }; =20 static struct qcom_icc_node qnm_cnoc_dc_noc =3D { .name =3D "qnm_cnoc_dc_noc", - .id =3D SC8280XP_MASTER_CNOC_DC_NOC, .channels =3D 1, .buswidth =3D 4, .num_links =3D 2, - .links =3D { SC8280XP_SLAVE_LLCC_CFG, - SC8280XP_SLAVE_GEM_NOC_CFG - }, + .link_nodes =3D { &qhs_llcc, + &qns_gemnoc }, }; =20 static struct qcom_icc_node alm_gpu_tcu =3D { .name =3D "alm_gpu_tcu", - .id =3D SC8280XP_MASTER_GPU_TCU, .channels =3D 1, .buswidth =3D 8, .num_links =3D 2, - .links =3D { SC8280XP_SLAVE_GEM_NOC_CNOC, - SC8280XP_SLAVE_LLCC - }, + .link_nodes =3D { &qns_gem_noc_cnoc, + &qns_llcc }, }; =20 static struct qcom_icc_node alm_pcie_tcu =3D { .name =3D "alm_pcie_tcu", - .id =3D SC8280XP_MASTER_PCIE_TCU, .channels =3D 1, .buswidth =3D 8, .num_links =3D 2, - .links =3D { SC8280XP_SLAVE_GEM_NOC_CNOC, - SC8280XP_SLAVE_LLCC - }, + .link_nodes =3D { &qns_gem_noc_cnoc, + &qns_llcc }, }; =20 static struct qcom_icc_node alm_sys_tcu =3D { .name =3D "alm_sys_tcu", - .id =3D SC8280XP_MASTER_SYS_TCU, .channels =3D 1, .buswidth =3D 8, .num_links =3D 2, - .links =3D { SC8280XP_SLAVE_GEM_NOC_CNOC, - SC8280XP_SLAVE_LLCC - }, + .link_nodes =3D { &qns_gem_noc_cnoc, + &qns_llcc }, }; =20 static struct qcom_icc_node chm_apps =3D { .name =3D "chm_apps", - .id =3D SC8280XP_MASTER_APPSS_PROC, .channels =3D 2, .buswidth =3D 32, .num_links =3D 3, - .links =3D { SC8280XP_SLAVE_GEM_NOC_CNOC, - SC8280XP_SLAVE_LLCC, - SC8280XP_SLAVE_GEM_NOC_PCIE_CNOC - }, + .link_nodes =3D { &qns_gem_noc_cnoc, + &qns_llcc, + &qns_pcie }, }; =20 static struct qcom_icc_node qnm_cmpnoc0 =3D { .name =3D "qnm_cmpnoc0", - .id =3D SC8280XP_MASTER_COMPUTE_NOC, .channels =3D 2, .buswidth =3D 32, .num_links =3D 2, - .links =3D { SC8280XP_SLAVE_GEM_NOC_CNOC, - SC8280XP_SLAVE_LLCC - }, + .link_nodes =3D { &qns_gem_noc_cnoc, + &qns_llcc }, }; =20 static struct qcom_icc_node qnm_cmpnoc1 =3D { .name =3D "qnm_cmpnoc1", - .id =3D SC8280XP_MASTER_COMPUTE_NOC_1, .channels =3D 2, .buswidth =3D 32, .num_links =3D 2, - .links =3D { SC8280XP_SLAVE_GEM_NOC_CNOC, - SC8280XP_SLAVE_LLCC - }, + .link_nodes =3D { &qns_gem_noc_cnoc, + &qns_llcc }, }; =20 static struct qcom_icc_node qnm_gemnoc_cfg =3D { .name =3D "qnm_gemnoc_cfg", - .id =3D SC8280XP_MASTER_GEM_NOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 3, - .links =3D { SC8280XP_SLAVE_SERVICE_GEM_NOC_1, - SC8280XP_SLAVE_SERVICE_GEM_NOC_2, - SC8280XP_SLAVE_SERVICE_GEM_NOC - }, + .link_nodes =3D { &srvc_even_gemnoc, + &srvc_odd_gemnoc, + &srvc_sys_gemnoc }, }; =20 static struct qcom_icc_node qnm_gpu =3D { .name =3D "qnm_gpu", - .id =3D SC8280XP_MASTER_GFX3D, .channels =3D 4, .buswidth =3D 32, .num_links =3D 2, - .links =3D { SC8280XP_SLAVE_GEM_NOC_CNOC, - SC8280XP_SLAVE_LLCC - }, + .link_nodes =3D { &qns_gem_noc_cnoc, + &qns_llcc }, }; =20 static struct qcom_icc_node qnm_mnoc_hf =3D { .name =3D "qnm_mnoc_hf", - .id =3D SC8280XP_MASTER_MNOC_HF_MEM_NOC, .channels =3D 2, .buswidth =3D 32, .num_links =3D 2, - .links =3D { SC8280XP_SLAVE_LLCC, - SC8280XP_SLAVE_GEM_NOC_PCIE_CNOC - }, + .link_nodes =3D { &qns_llcc, + &qns_pcie }, }; =20 static struct qcom_icc_node qnm_mnoc_sf =3D { .name =3D "qnm_mnoc_sf", - .id =3D SC8280XP_MASTER_MNOC_SF_MEM_NOC, .channels =3D 2, .buswidth =3D 32, .num_links =3D 2, - .links =3D { SC8280XP_SLAVE_GEM_NOC_CNOC, - SC8280XP_SLAVE_LLCC - }, + .link_nodes =3D { &qns_gem_noc_cnoc, + &qns_llcc }, }; =20 static struct qcom_icc_node qnm_pcie =3D { .name =3D "qnm_pcie", - .id =3D SC8280XP_MASTER_ANOC_PCIE_GEM_NOC, .channels =3D 1, .buswidth =3D 32, .num_links =3D 2, - .links =3D { SC8280XP_SLAVE_GEM_NOC_CNOC, - SC8280XP_SLAVE_LLCC - }, + .link_nodes =3D { &qns_gem_noc_cnoc, + &qns_llcc }, }; =20 static struct qcom_icc_node qnm_snoc_gc =3D { .name =3D "qnm_snoc_gc", - .id =3D SC8280XP_MASTER_SNOC_GC_MEM_NOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SC8280XP_SLAVE_LLCC }, + .link_nodes =3D { &qns_llcc }, }; =20 static struct qcom_icc_node qnm_snoc_sf =3D { .name =3D "qnm_snoc_sf", - .id =3D SC8280XP_MASTER_SNOC_SF_MEM_NOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 3, - .links =3D { SC8280XP_SLAVE_GEM_NOC_CNOC, - SC8280XP_SLAVE_LLCC, - SC8280XP_SLAVE_GEM_NOC_PCIE_CNOC }, + .link_nodes =3D { &qns_gem_noc_cnoc, + &qns_llcc, + &qns_pcie }, }; =20 static struct qcom_icc_node qhm_config_noc =3D { .name =3D "qhm_config_noc", - .id =3D SC8280XP_MASTER_CNOC_LPASS_AG_NOC, .channels =3D 1, .buswidth =3D 4, .num_links =3D 6, - .links =3D { SC8280XP_SLAVE_LPASS_CORE_CFG, - SC8280XP_SLAVE_LPASS_LPI_CFG, - SC8280XP_SLAVE_LPASS_MPU_CFG, - SC8280XP_SLAVE_LPASS_TOP_CFG, - SC8280XP_SLAVE_SERVICES_LPASS_AML_NOC, - SC8280XP_SLAVE_SERVICE_LPASS_AG_NOC - }, + .link_nodes =3D { &qhs_lpass_core, + &qhs_lpass_lpi, + &qhs_lpass_mpu, + &qhs_lpass_top, + &srvc_niu_aml_noc, + &srvc_niu_lpass_agnoc }, }; =20 static struct qcom_icc_node qxm_lpass_dsp =3D { .name =3D "qxm_lpass_dsp", - .id =3D SC8280XP_MASTER_LPASS_PROC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 4, - .links =3D { SC8280XP_SLAVE_LPASS_TOP_CFG, - SC8280XP_SLAVE_LPASS_SNOC, - SC8280XP_SLAVE_SERVICES_LPASS_AML_NOC, - SC8280XP_SLAVE_SERVICE_LPASS_AG_NOC - }, + .link_nodes =3D { &qhs_lpass_top, + &qns_sysnoc, + &srvc_niu_aml_noc, + &srvc_niu_lpass_agnoc }, }; =20 static struct qcom_icc_node llcc_mc =3D { .name =3D "llcc_mc", - .id =3D SC8280XP_MASTER_LLCC, .channels =3D 8, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SC8280XP_SLAVE_EBI1 }, + .link_nodes =3D { &ebi }, }; =20 static struct qcom_icc_node qnm_camnoc_hf =3D { .name =3D "qnm_camnoc_hf", - .id =3D SC8280XP_MASTER_CAMNOC_HF, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SC8280XP_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_hf }, }; =20 static struct qcom_icc_node qnm_mdp0_0 =3D { .name =3D "qnm_mdp0_0", - .id =3D SC8280XP_MASTER_MDP0, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SC8280XP_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_hf }, }; =20 static struct qcom_icc_node qnm_mdp0_1 =3D { .name =3D "qnm_mdp0_1", - .id =3D SC8280XP_MASTER_MDP1, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SC8280XP_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_hf }, }; =20 static struct qcom_icc_node qnm_mdp1_0 =3D { .name =3D "qnm_mdp1_0", - .id =3D SC8280XP_MASTER_MDP_CORE1_0, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SC8280XP_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_hf }, }; =20 static struct qcom_icc_node qnm_mdp1_1 =3D { .name =3D "qnm_mdp1_1", - .id =3D SC8280XP_MASTER_MDP_CORE1_1, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SC8280XP_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_hf }, }; =20 static struct qcom_icc_node qnm_mnoc_cfg =3D { .name =3D "qnm_mnoc_cfg", - .id =3D SC8280XP_MASTER_CNOC_MNOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SC8280XP_SLAVE_SERVICE_MNOC }, + .link_nodes =3D { &srvc_mnoc }, }; =20 static struct qcom_icc_node qnm_rot_0 =3D { .name =3D "qnm_rot_0", - .id =3D SC8280XP_MASTER_ROTATOR, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SC8280XP_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static struct qcom_icc_node qnm_rot_1 =3D { .name =3D "qnm_rot_1", - .id =3D SC8280XP_MASTER_ROTATOR_1, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SC8280XP_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static struct qcom_icc_node qnm_video0 =3D { .name =3D "qnm_video0", - .id =3D SC8280XP_MASTER_VIDEO_P0, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SC8280XP_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static struct qcom_icc_node qnm_video1 =3D { .name =3D "qnm_video1", - .id =3D SC8280XP_MASTER_VIDEO_P1, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SC8280XP_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static struct qcom_icc_node qnm_video_cvp =3D { .name =3D "qnm_video_cvp", - .id =3D SC8280XP_MASTER_VIDEO_PROC, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SC8280XP_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static struct qcom_icc_node qxm_camnoc_icp =3D { .name =3D "qxm_camnoc_icp", - .id =3D SC8280XP_MASTER_CAMNOC_ICP, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SC8280XP_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static struct qcom_icc_node qxm_camnoc_sf =3D { .name =3D "qxm_camnoc_sf", - .id =3D SC8280XP_MASTER_CAMNOC_SF, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SC8280XP_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static struct qcom_icc_node qhm_nsp_noc_config =3D { .name =3D "qhm_nsp_noc_config", - .id =3D SC8280XP_MASTER_CDSP_NOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SC8280XP_SLAVE_SERVICE_NSP_NOC }, + .link_nodes =3D { &service_nsp_noc }, }; =20 static struct qcom_icc_node qxm_nsp =3D { .name =3D "qxm_nsp", - .id =3D SC8280XP_MASTER_CDSP_PROC, .channels =3D 2, .buswidth =3D 32, .num_links =3D 2, - .links =3D { SC8280XP_SLAVE_CDSP_MEM_NOC, - SC8280XP_SLAVE_NSP_XFR - }, + .link_nodes =3D { &qns_nsp_gemnoc, + &qxs_nsp_xfr }, }; =20 static struct qcom_icc_node qhm_nspb_noc_config =3D { .name =3D "qhm_nspb_noc_config", - .id =3D SC8280XP_MASTER_CDSPB_NOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SC8280XP_SLAVE_SERVICE_NSPB_NOC }, + .link_nodes =3D { &service_nspb_noc }, }; =20 static struct qcom_icc_node qxm_nspb =3D { .name =3D "qxm_nspb", - .id =3D SC8280XP_MASTER_CDSP_PROC_B, .channels =3D 2, .buswidth =3D 32, .num_links =3D 2, - .links =3D { SC8280XP_SLAVE_CDSPB_MEM_NOC, - SC8280XP_SLAVE_NSPB_XFR - }, + .link_nodes =3D { &qns_nspb_gemnoc, + &qxs_nspb_xfr }, }; =20 static struct qcom_icc_node qnm_aggre1_noc =3D { .name =3D "qnm_aggre1_noc", - .id =3D SC8280XP_MASTER_A1NOC_SNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SC8280XP_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes =3D { &qns_gemnoc_sf }, }; =20 static struct qcom_icc_node qnm_aggre2_noc =3D { .name =3D "qnm_aggre2_noc", - .id =3D SC8280XP_MASTER_A2NOC_SNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SC8280XP_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes =3D { &qns_gemnoc_sf }, }; =20 static struct qcom_icc_node qnm_aggre_usb_noc =3D { .name =3D "qnm_aggre_usb_noc", - .id =3D SC8280XP_MASTER_USB_NOC_SNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SC8280XP_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes =3D { &qns_gemnoc_sf }, }; =20 static struct qcom_icc_node qnm_lpass_noc =3D { .name =3D "qnm_lpass_noc", - .id =3D SC8280XP_MASTER_LPASS_ANOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SC8280XP_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes =3D { &qns_gemnoc_sf }, }; =20 static struct qcom_icc_node qnm_snoc_cfg =3D { .name =3D "qnm_snoc_cfg", - .id =3D SC8280XP_MASTER_SNOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SC8280XP_SLAVE_SERVICE_SNOC }, + .link_nodes =3D { &srvc_snoc }, }; =20 static struct qcom_icc_node qxm_pimem =3D { .name =3D "qxm_pimem", - .id =3D SC8280XP_MASTER_PIMEM, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SC8280XP_SLAVE_SNOC_GEM_NOC_GC }, + .link_nodes =3D { &qns_gemnoc_gc }, }; =20 static struct qcom_icc_node xm_gic =3D { .name =3D "xm_gic", - .id =3D SC8280XP_MASTER_GIC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SC8280XP_SLAVE_SNOC_GEM_NOC_GC }, + .link_nodes =3D { &qns_gemnoc_gc }, }; =20 static struct qcom_icc_node qns_a1noc_snoc =3D { .name =3D "qns_a1noc_snoc", - .id =3D SC8280XP_SLAVE_A1NOC_SNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SC8280XP_MASTER_A1NOC_SNOC }, + .link_nodes =3D { &qnm_aggre1_noc }, }; =20 static struct qcom_icc_node qns_aggre_usb_snoc =3D { .name =3D "qns_aggre_usb_snoc", - .id =3D SC8280XP_SLAVE_USB_NOC_SNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SC8280XP_MASTER_USB_NOC_SNOC }, + .link_nodes =3D { &qnm_aggre_usb_noc }, }; =20 static struct qcom_icc_node srvc_aggre1_noc =3D { .name =3D "srvc_aggre1_noc", - .id =3D SC8280XP_SLAVE_SERVICE_A1NOC, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qns_a2noc_snoc =3D { .name =3D "qns_a2noc_snoc", - .id =3D SC8280XP_SLAVE_A2NOC_SNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SC8280XP_MASTER_A2NOC_SNOC }, + .link_nodes =3D { &qnm_aggre2_noc }, }; =20 static struct qcom_icc_node qns_pcie_gem_noc =3D { .name =3D "qns_pcie_gem_noc", - .id =3D SC8280XP_SLAVE_ANOC_PCIE_GEM_NOC, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SC8280XP_MASTER_ANOC_PCIE_GEM_NOC }, + .link_nodes =3D { &qnm_pcie }, }; =20 static struct qcom_icc_node srvc_aggre2_noc =3D { .name =3D "srvc_aggre2_noc", - .id =3D SC8280XP_SLAVE_SERVICE_A2NOC, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qup0_core_slave =3D { .name =3D "qup0_core_slave", - .id =3D SC8280XP_SLAVE_QUP_CORE_0, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qup1_core_slave =3D { .name =3D "qup1_core_slave", - .id =3D SC8280XP_SLAVE_QUP_CORE_1, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qup2_core_slave =3D { .name =3D "qup2_core_slave", - .id =3D SC8280XP_SLAVE_QUP_CORE_2, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_ahb2phy0 =3D { .name =3D "qhs_ahb2phy0", - .id =3D SC8280XP_SLAVE_AHB2PHY_0, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_ahb2phy1 =3D { .name =3D "qhs_ahb2phy1", - .id =3D SC8280XP_SLAVE_AHB2PHY_1, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_ahb2phy2 =3D { .name =3D "qhs_ahb2phy2", - .id =3D SC8280XP_SLAVE_AHB2PHY_2, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_aoss =3D { .name =3D "qhs_aoss", - .id =3D SC8280XP_SLAVE_AOSS, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_apss =3D { .name =3D "qhs_apss", - .id =3D SC8280XP_SLAVE_APPSS, .channels =3D 1, .buswidth =3D 8, }; =20 static struct qcom_icc_node qhs_camera_cfg =3D { .name =3D "qhs_camera_cfg", - .id =3D SC8280XP_SLAVE_CAMERA_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_clk_ctl =3D { .name =3D "qhs_clk_ctl", - .id =3D SC8280XP_SLAVE_CLK_CTL, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_compute0_cfg =3D { .name =3D "qhs_compute0_cfg", - .id =3D SC8280XP_SLAVE_CDSP_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SC8280XP_MASTER_CDSP_NOC_CFG }, + .link_nodes =3D { &qhm_nsp_noc_config }, }; =20 static struct qcom_icc_node qhs_compute1_cfg =3D { .name =3D "qhs_compute1_cfg", - .id =3D SC8280XP_SLAVE_CDSP1_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SC8280XP_MASTER_CDSPB_NOC_CFG }, + .link_nodes =3D { &qhm_nspb_noc_config }, }; =20 static struct qcom_icc_node qhs_cpr_cx =3D { .name =3D "qhs_cpr_cx", - .id =3D SC8280XP_SLAVE_RBCPR_CX_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_cpr_mmcx =3D { .name =3D "qhs_cpr_mmcx", - .id =3D SC8280XP_SLAVE_RBCPR_MMCX_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_cpr_mx =3D { .name =3D "qhs_cpr_mx", - .id =3D SC8280XP_SLAVE_RBCPR_MX_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_cpr_nspcx =3D { .name =3D "qhs_cpr_nspcx", - .id =3D SC8280XP_SLAVE_CPR_NSPCX, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_crypto0_cfg =3D { .name =3D "qhs_crypto0_cfg", - .id =3D SC8280XP_SLAVE_CRYPTO_0_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_cx_rdpm =3D { .name =3D "qhs_cx_rdpm", - .id =3D SC8280XP_SLAVE_CX_RDPM, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_dcc_cfg =3D { .name =3D "qhs_dcc_cfg", - .id =3D SC8280XP_SLAVE_DCC_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_display0_cfg =3D { .name =3D "qhs_display0_cfg", - .id =3D SC8280XP_SLAVE_DISPLAY_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_display1_cfg =3D { .name =3D "qhs_display1_cfg", - .id =3D SC8280XP_SLAVE_DISPLAY1_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_emac0_cfg =3D { .name =3D "qhs_emac0_cfg", - .id =3D SC8280XP_SLAVE_EMAC_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_emac1_cfg =3D { .name =3D "qhs_emac1_cfg", - .id =3D SC8280XP_SLAVE_EMAC1_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_gpuss_cfg =3D { .name =3D "qhs_gpuss_cfg", - .id =3D SC8280XP_SLAVE_GFX3D_CFG, .channels =3D 1, .buswidth =3D 8, }; =20 static struct qcom_icc_node qhs_hwkm =3D { .name =3D "qhs_hwkm", - .id =3D SC8280XP_SLAVE_HWKM, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_imem_cfg =3D { .name =3D "qhs_imem_cfg", - .id =3D SC8280XP_SLAVE_IMEM_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_ipa =3D { .name =3D "qhs_ipa", - .id =3D SC8280XP_SLAVE_IPA_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_ipc_router =3D { .name =3D "qhs_ipc_router", - .id =3D SC8280XP_SLAVE_IPC_ROUTER_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_lpass_cfg =3D { .name =3D "qhs_lpass_cfg", - .id =3D SC8280XP_SLAVE_LPASS, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SC8280XP_MASTER_CNOC_LPASS_AG_NOC }, + .link_nodes =3D { &qhm_config_noc }, }; =20 static struct qcom_icc_node qhs_mx_rdpm =3D { .name =3D "qhs_mx_rdpm", - .id =3D SC8280XP_SLAVE_MX_RDPM, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_mxc_rdpm =3D { .name =3D "qhs_mxc_rdpm", - .id =3D SC8280XP_SLAVE_MXC_RDPM, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_pcie0_cfg =3D { .name =3D "qhs_pcie0_cfg", - .id =3D SC8280XP_SLAVE_PCIE_0_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_pcie1_cfg =3D { .name =3D "qhs_pcie1_cfg", - .id =3D SC8280XP_SLAVE_PCIE_1_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_pcie2a_cfg =3D { .name =3D "qhs_pcie2a_cfg", - .id =3D SC8280XP_SLAVE_PCIE_2A_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_pcie2b_cfg =3D { .name =3D "qhs_pcie2b_cfg", - .id =3D SC8280XP_SLAVE_PCIE_2B_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_pcie3a_cfg =3D { .name =3D "qhs_pcie3a_cfg", - .id =3D SC8280XP_SLAVE_PCIE_3A_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_pcie3b_cfg =3D { .name =3D "qhs_pcie3b_cfg", - .id =3D SC8280XP_SLAVE_PCIE_3B_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_pcie4_cfg =3D { .name =3D "qhs_pcie4_cfg", - .id =3D SC8280XP_SLAVE_PCIE_4_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_pcie_rsc_cfg =3D { .name =3D "qhs_pcie_rsc_cfg", - .id =3D SC8280XP_SLAVE_PCIE_RSC_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_pdm =3D { .name =3D "qhs_pdm", - .id =3D SC8280XP_SLAVE_PDM, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_pimem_cfg =3D { .name =3D "qhs_pimem_cfg", - .id =3D SC8280XP_SLAVE_PIMEM_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_pka_wrapper_cfg =3D { .name =3D "qhs_pka_wrapper_cfg", - .id =3D SC8280XP_SLAVE_PKA_WRAPPER_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_pmu_wrapper_cfg =3D { .name =3D "qhs_pmu_wrapper_cfg", - .id =3D SC8280XP_SLAVE_PMU_WRAPPER_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_qdss_cfg =3D { .name =3D "qhs_qdss_cfg", - .id =3D SC8280XP_SLAVE_QDSS_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_qspi =3D { .name =3D "qhs_qspi", - .id =3D SC8280XP_SLAVE_QSPI_0, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_qup0 =3D { .name =3D "qhs_qup0", - .id =3D SC8280XP_SLAVE_QUP_0, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_qup1 =3D { .name =3D "qhs_qup1", - .id =3D SC8280XP_SLAVE_QUP_1, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_qup2 =3D { .name =3D "qhs_qup2", - .id =3D SC8280XP_SLAVE_QUP_2, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_sdc2 =3D { .name =3D "qhs_sdc2", - .id =3D SC8280XP_SLAVE_SDCC_2, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_sdc4 =3D { .name =3D "qhs_sdc4", - .id =3D SC8280XP_SLAVE_SDCC_4, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_security =3D { .name =3D "qhs_security", - .id =3D SC8280XP_SLAVE_SECURITY, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_smmuv3_cfg =3D { .name =3D "qhs_smmuv3_cfg", - .id =3D SC8280XP_SLAVE_SMMUV3_CFG, .channels =3D 1, .buswidth =3D 8, }; =20 static struct qcom_icc_node qhs_smss_cfg =3D { .name =3D "qhs_smss_cfg", - .id =3D SC8280XP_SLAVE_SMSS_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_spss_cfg =3D { .name =3D "qhs_spss_cfg", - .id =3D SC8280XP_SLAVE_SPSS_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_tcsr =3D { .name =3D "qhs_tcsr", - .id =3D SC8280XP_SLAVE_TCSR, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_tlmm =3D { .name =3D "qhs_tlmm", - .id =3D SC8280XP_SLAVE_TLMM, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_ufs_card_cfg =3D { .name =3D "qhs_ufs_card_cfg", - .id =3D SC8280XP_SLAVE_UFS_CARD_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_ufs_mem_cfg =3D { .name =3D "qhs_ufs_mem_cfg", - .id =3D SC8280XP_SLAVE_UFS_MEM_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_usb3_0 =3D { .name =3D "qhs_usb3_0", - .id =3D SC8280XP_SLAVE_USB3_0, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_usb3_1 =3D { .name =3D "qhs_usb3_1", - .id =3D SC8280XP_SLAVE_USB3_1, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_usb3_mp =3D { .name =3D "qhs_usb3_mp", - .id =3D SC8280XP_SLAVE_USB3_MP, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_usb4_host_0 =3D { .name =3D "qhs_usb4_host_0", - .id =3D SC8280XP_SLAVE_USB4_0, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_usb4_host_1 =3D { .name =3D "qhs_usb4_host_1", - .id =3D SC8280XP_SLAVE_USB4_1, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_venus_cfg =3D { .name =3D "qhs_venus_cfg", - .id =3D SC8280XP_SLAVE_VENUS_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_vsense_ctrl_cfg =3D { .name =3D "qhs_vsense_ctrl_cfg", - .id =3D SC8280XP_SLAVE_VSENSE_CTRL_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_vsense_ctrl_r_cfg =3D { .name =3D "qhs_vsense_ctrl_r_cfg", - .id =3D SC8280XP_SLAVE_VSENSE_CTRL_R_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qns_a1_noc_cfg =3D { .name =3D "qns_a1_noc_cfg", - .id =3D SC8280XP_SLAVE_A1NOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SC8280XP_MASTER_A1NOC_CFG }, + .link_nodes =3D { &qnm_a1noc_cfg }, }; =20 static struct qcom_icc_node qns_a2_noc_cfg =3D { .name =3D "qns_a2_noc_cfg", - .id =3D SC8280XP_SLAVE_A2NOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SC8280XP_MASTER_A2NOC_CFG }, + .link_nodes =3D { &qnm_a2noc_cfg }, }; =20 static struct qcom_icc_node qns_anoc_pcie_bridge_cfg =3D { .name =3D "qns_anoc_pcie_bridge_cfg", - .id =3D SC8280XP_SLAVE_ANOC_PCIE_BRIDGE_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qns_ddrss_cfg =3D { .name =3D "qns_ddrss_cfg", - .id =3D SC8280XP_SLAVE_DDRSS_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SC8280XP_MASTER_CNOC_DC_NOC }, + .link_nodes =3D { &qnm_cnoc_dc_noc }, }; =20 static struct qcom_icc_node qns_mnoc_cfg =3D { .name =3D "qns_mnoc_cfg", - .id =3D SC8280XP_SLAVE_CNOC_MNOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SC8280XP_MASTER_CNOC_MNOC_CFG }, + .link_nodes =3D { &qnm_mnoc_cfg }, }; =20 static struct qcom_icc_node qns_snoc_cfg =3D { .name =3D "qns_snoc_cfg", - .id =3D SC8280XP_SLAVE_SNOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SC8280XP_MASTER_SNOC_CFG }, + .link_nodes =3D { &qnm_snoc_cfg }, }; =20 static struct qcom_icc_node qns_snoc_sf_bridge_cfg =3D { .name =3D "qns_snoc_sf_bridge_cfg", - .id =3D SC8280XP_SLAVE_SNOC_SF_BRIDGE_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qxs_imem =3D { .name =3D "qxs_imem", - .id =3D SC8280XP_SLAVE_IMEM, .channels =3D 1, .buswidth =3D 8, }; =20 static struct qcom_icc_node qxs_pimem =3D { .name =3D "qxs_pimem", - .id =3D SC8280XP_SLAVE_PIMEM, .channels =3D 1, .buswidth =3D 8, }; =20 static struct qcom_icc_node srvc_cnoc =3D { .name =3D "srvc_cnoc", - .id =3D SC8280XP_SLAVE_SERVICE_CNOC, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node xs_pcie_0 =3D { .name =3D "xs_pcie_0", - .id =3D SC8280XP_SLAVE_PCIE_0, .channels =3D 1, .buswidth =3D 16, }; =20 static struct qcom_icc_node xs_pcie_1 =3D { .name =3D "xs_pcie_1", - .id =3D SC8280XP_SLAVE_PCIE_1, .channels =3D 1, .buswidth =3D 16, }; =20 static struct qcom_icc_node xs_pcie_2a =3D { .name =3D "xs_pcie_2a", - .id =3D SC8280XP_SLAVE_PCIE_2A, .channels =3D 1, .buswidth =3D 16, }; =20 static struct qcom_icc_node xs_pcie_2b =3D { .name =3D "xs_pcie_2b", - .id =3D SC8280XP_SLAVE_PCIE_2B, .channels =3D 1, .buswidth =3D 8, }; =20 static struct qcom_icc_node xs_pcie_3a =3D { .name =3D "xs_pcie_3a", - .id =3D SC8280XP_SLAVE_PCIE_3A, .channels =3D 1, .buswidth =3D 16, }; =20 static struct qcom_icc_node xs_pcie_3b =3D { .name =3D "xs_pcie_3b", - .id =3D SC8280XP_SLAVE_PCIE_3B, .channels =3D 1, .buswidth =3D 8, }; =20 static struct qcom_icc_node xs_pcie_4 =3D { .name =3D "xs_pcie_4", - .id =3D SC8280XP_SLAVE_PCIE_4, .channels =3D 1, .buswidth =3D 8, }; =20 static struct qcom_icc_node xs_qdss_stm =3D { .name =3D "xs_qdss_stm", - .id =3D SC8280XP_SLAVE_QDSS_STM, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node xs_smss =3D { .name =3D "xs_smss", - .id =3D SC8280XP_SLAVE_SMSS, .channels =3D 1, .buswidth =3D 8, }; =20 static struct qcom_icc_node xs_sys_tcu_cfg =3D { .name =3D "xs_sys_tcu_cfg", - .id =3D SC8280XP_SLAVE_TCU, .channels =3D 1, .buswidth =3D 8, }; =20 static struct qcom_icc_node qhs_llcc =3D { .name =3D "qhs_llcc", - .id =3D SC8280XP_SLAVE_LLCC_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qns_gemnoc =3D { .name =3D "qns_gemnoc", - .id =3D SC8280XP_SLAVE_GEM_NOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SC8280XP_MASTER_GEM_NOC_CFG }, + .link_nodes =3D { &qnm_gemnoc_cfg }, }; =20 static struct qcom_icc_node qns_gem_noc_cnoc =3D { .name =3D "qns_gem_noc_cnoc", - .id =3D SC8280XP_SLAVE_GEM_NOC_CNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SC8280XP_MASTER_GEM_NOC_CNOC }, + .link_nodes =3D { &qnm_gemnoc_cnoc }, }; =20 static struct qcom_icc_node qns_llcc =3D { .name =3D "qns_llcc", - .id =3D SC8280XP_SLAVE_LLCC, .channels =3D 8, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SC8280XP_MASTER_LLCC }, + .link_nodes =3D { &llcc_mc }, }; =20 static struct qcom_icc_node qns_pcie =3D { .name =3D "qns_pcie", - .id =3D SC8280XP_SLAVE_GEM_NOC_PCIE_CNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SC8280XP_MASTER_GEM_NOC_PCIE_SNOC }, + .link_nodes =3D { &qnm_gemnoc_pcie }, }; =20 static struct qcom_icc_node srvc_even_gemnoc =3D { .name =3D "srvc_even_gemnoc", - .id =3D SC8280XP_SLAVE_SERVICE_GEM_NOC_1, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node srvc_odd_gemnoc =3D { .name =3D "srvc_odd_gemnoc", - .id =3D SC8280XP_SLAVE_SERVICE_GEM_NOC_2, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node srvc_sys_gemnoc =3D { .name =3D "srvc_sys_gemnoc", - .id =3D SC8280XP_SLAVE_SERVICE_GEM_NOC, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_lpass_core =3D { .name =3D "qhs_lpass_core", - .id =3D SC8280XP_SLAVE_LPASS_CORE_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_lpass_lpi =3D { .name =3D "qhs_lpass_lpi", - .id =3D SC8280XP_SLAVE_LPASS_LPI_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_lpass_mpu =3D { .name =3D "qhs_lpass_mpu", - .id =3D SC8280XP_SLAVE_LPASS_MPU_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_lpass_top =3D { .name =3D "qhs_lpass_top", - .id =3D SC8280XP_SLAVE_LPASS_TOP_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qns_sysnoc =3D { .name =3D "qns_sysnoc", - .id =3D SC8280XP_SLAVE_LPASS_SNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SC8280XP_MASTER_LPASS_ANOC }, + .link_nodes =3D { &qnm_lpass_noc }, }; =20 static struct qcom_icc_node srvc_niu_aml_noc =3D { .name =3D "srvc_niu_aml_noc", - .id =3D SC8280XP_SLAVE_SERVICES_LPASS_AML_NOC, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node srvc_niu_lpass_agnoc =3D { .name =3D "srvc_niu_lpass_agnoc", - .id =3D SC8280XP_SLAVE_SERVICE_LPASS_AG_NOC, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node ebi =3D { .name =3D "ebi", - .id =3D SC8280XP_SLAVE_EBI1, .channels =3D 8, .buswidth =3D 4, }; =20 static struct qcom_icc_node qns_mem_noc_hf =3D { .name =3D "qns_mem_noc_hf", - .id =3D SC8280XP_SLAVE_MNOC_HF_MEM_NOC, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SC8280XP_MASTER_MNOC_HF_MEM_NOC }, + .link_nodes =3D { &qnm_mnoc_hf }, }; =20 static struct qcom_icc_node qns_mem_noc_sf =3D { .name =3D "qns_mem_noc_sf", - .id =3D SC8280XP_SLAVE_MNOC_SF_MEM_NOC, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SC8280XP_MASTER_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qnm_mnoc_sf }, }; =20 static struct qcom_icc_node srvc_mnoc =3D { .name =3D "srvc_mnoc", - .id =3D SC8280XP_SLAVE_SERVICE_MNOC, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qns_nsp_gemnoc =3D { .name =3D "qns_nsp_gemnoc", - .id =3D SC8280XP_SLAVE_CDSP_MEM_NOC, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SC8280XP_MASTER_COMPUTE_NOC }, + .link_nodes =3D { &qnm_cmpnoc0 }, }; =20 static struct qcom_icc_node qxs_nsp_xfr =3D { .name =3D "qxs_nsp_xfr", - .id =3D SC8280XP_SLAVE_NSP_XFR, .channels =3D 1, .buswidth =3D 32, }; =20 static struct qcom_icc_node service_nsp_noc =3D { .name =3D "service_nsp_noc", - .id =3D SC8280XP_SLAVE_SERVICE_NSP_NOC, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qns_nspb_gemnoc =3D { .name =3D "qns_nspb_gemnoc", - .id =3D SC8280XP_SLAVE_CDSPB_MEM_NOC, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SC8280XP_MASTER_COMPUTE_NOC_1 }, + .link_nodes =3D { &qnm_cmpnoc1 }, }; =20 static struct qcom_icc_node qxs_nspb_xfr =3D { .name =3D "qxs_nspb_xfr", - .id =3D SC8280XP_SLAVE_NSPB_XFR, .channels =3D 1, .buswidth =3D 32, }; =20 static struct qcom_icc_node service_nspb_noc =3D { .name =3D "service_nspb_noc", - .id =3D SC8280XP_SLAVE_SERVICE_NSPB_NOC, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qns_gemnoc_gc =3D { .name =3D "qns_gemnoc_gc", - .id =3D SC8280XP_SLAVE_SNOC_GEM_NOC_GC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SC8280XP_MASTER_SNOC_GC_MEM_NOC }, + .link_nodes =3D { &qnm_snoc_gc }, }; =20 static struct qcom_icc_node qns_gemnoc_sf =3D { .name =3D "qns_gemnoc_sf", - .id =3D SC8280XP_SLAVE_SNOC_GEM_NOC_SF, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SC8280XP_MASTER_SNOC_SF_MEM_NOC }, + .link_nodes =3D { &qnm_snoc_sf }, }; =20 static struct qcom_icc_node srvc_snoc =3D { .name =3D "srvc_snoc", - .id =3D SC8280XP_SLAVE_SERVICE_SNOC, .channels =3D 1, .buswidth =3D 4, }; @@ -2015,6 +1998,7 @@ static struct qcom_icc_node * const aggre1_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sc8280xp_aggre1_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D aggre1_noc_nodes, .num_nodes =3D ARRAY_SIZE(aggre1_noc_nodes), .bcms =3D aggre1_noc_bcms, @@ -2051,6 +2035,7 @@ static struct qcom_icc_node * const aggre2_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sc8280xp_aggre2_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D aggre2_noc_nodes, .num_nodes =3D ARRAY_SIZE(aggre2_noc_nodes), .bcms =3D aggre2_noc_bcms, @@ -2073,6 +2058,7 @@ static struct qcom_icc_node * const clk_virt_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sc8280xp_clk_virt =3D { + .alloc_dyn_id =3D true, .nodes =3D clk_virt_nodes, .num_nodes =3D ARRAY_SIZE(clk_virt_nodes), .bcms =3D clk_virt_bcms, @@ -2177,6 +2163,7 @@ static struct qcom_icc_node * const config_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sc8280xp_config_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D config_noc_nodes, .num_nodes =3D ARRAY_SIZE(config_noc_nodes), .bcms =3D config_noc_bcms, @@ -2193,6 +2180,7 @@ static struct qcom_icc_node * const dc_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sc8280xp_dc_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D dc_noc_nodes, .num_nodes =3D ARRAY_SIZE(dc_noc_nodes), .bcms =3D dc_noc_bcms, @@ -2227,6 +2215,7 @@ static struct qcom_icc_node * const gem_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sc8280xp_gem_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D gem_noc_nodes, .num_nodes =3D ARRAY_SIZE(gem_noc_nodes), .bcms =3D gem_noc_bcms, @@ -2250,6 +2239,7 @@ static struct qcom_icc_node * const lpass_ag_noc_node= s[] =3D { }; =20 static const struct qcom_icc_desc sc8280xp_lpass_ag_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D lpass_ag_noc_nodes, .num_nodes =3D ARRAY_SIZE(lpass_ag_noc_nodes), .bcms =3D lpass_ag_noc_bcms, @@ -2267,6 +2257,7 @@ static struct qcom_icc_node * const mc_virt_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sc8280xp_mc_virt =3D { + .alloc_dyn_id =3D true, .nodes =3D mc_virt_nodes, .num_nodes =3D ARRAY_SIZE(mc_virt_nodes), .bcms =3D mc_virt_bcms, @@ -2298,6 +2289,7 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sc8280xp_mmss_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D mmss_noc_nodes, .num_nodes =3D ARRAY_SIZE(mmss_noc_nodes), .bcms =3D mmss_noc_bcms, @@ -2318,6 +2310,7 @@ static struct qcom_icc_node * const nspa_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sc8280xp_nspa_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D nspa_noc_nodes, .num_nodes =3D ARRAY_SIZE(nspa_noc_nodes), .bcms =3D nspa_noc_bcms, @@ -2338,6 +2331,7 @@ static struct qcom_icc_node * const nspb_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sc8280xp_nspb_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D nspb_noc_nodes, .num_nodes =3D ARRAY_SIZE(nspb_noc_nodes), .bcms =3D nspb_noc_bcms, @@ -2367,6 +2361,7 @@ static struct qcom_icc_node * const system_noc_main_n= odes[] =3D { }; =20 static const struct qcom_icc_desc sc8280xp_system_noc_main =3D { + .alloc_dyn_id =3D true, .nodes =3D system_noc_main_nodes, .num_nodes =3D ARRAY_SIZE(system_noc_main_nodes), .bcms =3D system_noc_main_bcms, diff --git a/drivers/interconnect/qcom/sc8280xp.h b/drivers/interconnect/qc= om/sc8280xp.h deleted file mode 100644 index c5c410fd5ec3c4d1bd0660091e1c4948fc019347..000000000000000000000000000= 0000000000000 --- a/drivers/interconnect/qcom/sc8280xp.h +++ /dev/null @@ -1,209 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2021, The Linux Foundation. All rights reserved. - */ - -#ifndef __DRIVERS_INTERCONNECT_QCOM_SC8280XP_H -#define __DRIVERS_INTERCONNECT_QCOM_SC8280XP_H - -#define SC8280XP_MASTER_GPU_TCU 0 -#define SC8280XP_MASTER_PCIE_TCU 1 -#define SC8280XP_MASTER_SYS_TCU 2 -#define SC8280XP_MASTER_APPSS_PROC 3 -/* 4 was used by SLAVE_IPA_CORE, now represented as RPMh clock */ -#define SC8280XP_MASTER_LLCC 5 -#define SC8280XP_MASTER_CNOC_LPASS_AG_NOC 6 -#define SC8280XP_MASTER_CDSP_NOC_CFG 7 -#define SC8280XP_MASTER_CDSPB_NOC_CFG 8 -#define SC8280XP_MASTER_QDSS_BAM 9 -#define SC8280XP_MASTER_QSPI_0 10 -#define SC8280XP_MASTER_QUP_0 11 -#define SC8280XP_MASTER_QUP_1 12 -#define SC8280XP_MASTER_QUP_2 13 -#define SC8280XP_MASTER_A1NOC_CFG 14 -#define SC8280XP_MASTER_A2NOC_CFG 15 -#define SC8280XP_MASTER_A1NOC_SNOC 16 -#define SC8280XP_MASTER_A2NOC_SNOC 17 -#define SC8280XP_MASTER_USB_NOC_SNOC 18 -#define SC8280XP_MASTER_CAMNOC_HF 19 -#define SC8280XP_MASTER_COMPUTE_NOC 20 -#define SC8280XP_MASTER_COMPUTE_NOC_1 21 -#define SC8280XP_MASTER_CNOC_DC_NOC 22 -#define SC8280XP_MASTER_GEM_NOC_CFG 23 -#define SC8280XP_MASTER_GEM_NOC_CNOC 24 -#define SC8280XP_MASTER_GEM_NOC_PCIE_SNOC 25 -#define SC8280XP_MASTER_GFX3D 26 -#define SC8280XP_MASTER_LPASS_ANOC 27 -#define SC8280XP_MASTER_MDP0 28 -#define SC8280XP_MASTER_MDP1 29 -#define SC8280XP_MASTER_MDP_CORE1_0 30 -#define SC8280XP_MASTER_MDP_CORE1_1 31 -#define SC8280XP_MASTER_CNOC_MNOC_CFG 32 -#define SC8280XP_MASTER_MNOC_HF_MEM_NOC 33 -#define SC8280XP_MASTER_MNOC_SF_MEM_NOC 34 -#define SC8280XP_MASTER_ANOC_PCIE_GEM_NOC 35 -#define SC8280XP_MASTER_ROTATOR 36 -#define SC8280XP_MASTER_ROTATOR_1 37 -#define SC8280XP_MASTER_SNOC_CFG 38 -#define SC8280XP_MASTER_SNOC_GC_MEM_NOC 39 -#define SC8280XP_MASTER_SNOC_SF_MEM_NOC 40 -#define SC8280XP_MASTER_VIDEO_P0 41 -#define SC8280XP_MASTER_VIDEO_P1 42 -#define SC8280XP_MASTER_VIDEO_PROC 43 -#define SC8280XP_MASTER_QUP_CORE_0 44 -#define SC8280XP_MASTER_QUP_CORE_1 45 -#define SC8280XP_MASTER_QUP_CORE_2 46 -#define SC8280XP_MASTER_CAMNOC_ICP 47 -#define SC8280XP_MASTER_CAMNOC_SF 48 -#define SC8280XP_MASTER_CRYPTO 49 -#define SC8280XP_MASTER_IPA 50 -#define SC8280XP_MASTER_LPASS_PROC 51 -#define SC8280XP_MASTER_CDSP_PROC 52 -#define SC8280XP_MASTER_CDSP_PROC_B 53 -#define SC8280XP_MASTER_PIMEM 54 -#define SC8280XP_MASTER_SENSORS_PROC 55 -#define SC8280XP_MASTER_SP 56 -#define SC8280XP_MASTER_EMAC 57 -#define SC8280XP_MASTER_EMAC_1 58 -#define SC8280XP_MASTER_GIC 59 -#define SC8280XP_MASTER_PCIE_0 60 -#define SC8280XP_MASTER_PCIE_1 61 -#define SC8280XP_MASTER_PCIE_2A 62 -#define SC8280XP_MASTER_PCIE_2B 63 -#define SC8280XP_MASTER_PCIE_3A 64 -#define SC8280XP_MASTER_PCIE_3B 65 -#define SC8280XP_MASTER_PCIE_4 66 -#define SC8280XP_MASTER_QDSS_ETR 67 -#define SC8280XP_MASTER_SDCC_2 68 -#define SC8280XP_MASTER_SDCC_4 69 -#define SC8280XP_MASTER_UFS_CARD 70 -#define SC8280XP_MASTER_UFS_MEM 71 -#define SC8280XP_MASTER_USB3_0 72 -#define SC8280XP_MASTER_USB3_1 73 -#define SC8280XP_MASTER_USB3_MP 74 -#define SC8280XP_MASTER_USB4_0 75 -#define SC8280XP_MASTER_USB4_1 76 -#define SC8280XP_SLAVE_EBI1 512 -/* 513 was used by SLAVE_IPA_CORE, now represented as RPMh clock */ -#define SC8280XP_SLAVE_AHB2PHY_0 514 -#define SC8280XP_SLAVE_AHB2PHY_1 515 -#define SC8280XP_SLAVE_AHB2PHY_2 516 -#define SC8280XP_SLAVE_AOSS 517 -#define SC8280XP_SLAVE_APPSS 518 -#define SC8280XP_SLAVE_CAMERA_CFG 519 -#define SC8280XP_SLAVE_CLK_CTL 520 -#define SC8280XP_SLAVE_CDSP_CFG 521 -#define SC8280XP_SLAVE_CDSP1_CFG 522 -#define SC8280XP_SLAVE_RBCPR_CX_CFG 523 -#define SC8280XP_SLAVE_RBCPR_MMCX_CFG 524 -#define SC8280XP_SLAVE_RBCPR_MX_CFG 525 -#define SC8280XP_SLAVE_CPR_NSPCX 526 -#define SC8280XP_SLAVE_CRYPTO_0_CFG 527 -#define SC8280XP_SLAVE_CX_RDPM 528 -#define SC8280XP_SLAVE_DCC_CFG 529 -#define SC8280XP_SLAVE_DISPLAY_CFG 530 -#define SC8280XP_SLAVE_DISPLAY1_CFG 531 -#define SC8280XP_SLAVE_EMAC_CFG 532 -#define SC8280XP_SLAVE_EMAC1_CFG 533 -#define SC8280XP_SLAVE_GFX3D_CFG 534 -#define SC8280XP_SLAVE_HWKM 535 -#define SC8280XP_SLAVE_IMEM_CFG 536 -#define SC8280XP_SLAVE_IPA_CFG 537 -#define SC8280XP_SLAVE_IPC_ROUTER_CFG 538 -#define SC8280XP_SLAVE_LLCC_CFG 539 -#define SC8280XP_SLAVE_LPASS 540 -#define SC8280XP_SLAVE_LPASS_CORE_CFG 541 -#define SC8280XP_SLAVE_LPASS_LPI_CFG 542 -#define SC8280XP_SLAVE_LPASS_MPU_CFG 543 -#define SC8280XP_SLAVE_LPASS_TOP_CFG 544 -#define SC8280XP_SLAVE_MX_RDPM 545 -#define SC8280XP_SLAVE_MXC_RDPM 546 -#define SC8280XP_SLAVE_PCIE_0_CFG 547 -#define SC8280XP_SLAVE_PCIE_1_CFG 548 -#define SC8280XP_SLAVE_PCIE_2A_CFG 549 -#define SC8280XP_SLAVE_PCIE_2B_CFG 550 -#define SC8280XP_SLAVE_PCIE_3A_CFG 551 -#define SC8280XP_SLAVE_PCIE_3B_CFG 552 -#define SC8280XP_SLAVE_PCIE_4_CFG 553 -#define SC8280XP_SLAVE_PCIE_RSC_CFG 554 -#define SC8280XP_SLAVE_PDM 555 -#define SC8280XP_SLAVE_PIMEM_CFG 556 -#define SC8280XP_SLAVE_PKA_WRAPPER_CFG 557 -#define SC8280XP_SLAVE_PMU_WRAPPER_CFG 558 -#define SC8280XP_SLAVE_QDSS_CFG 559 -#define SC8280XP_SLAVE_QSPI_0 560 -#define SC8280XP_SLAVE_QUP_0 561 -#define SC8280XP_SLAVE_QUP_1 562 -#define SC8280XP_SLAVE_QUP_2 563 -#define SC8280XP_SLAVE_SDCC_2 564 -#define SC8280XP_SLAVE_SDCC_4 565 -#define SC8280XP_SLAVE_SECURITY 566 -#define SC8280XP_SLAVE_SMMUV3_CFG 567 -#define SC8280XP_SLAVE_SMSS_CFG 568 -#define SC8280XP_SLAVE_SPSS_CFG 569 -#define SC8280XP_SLAVE_TCSR 570 -#define SC8280XP_SLAVE_TLMM 571 -#define SC8280XP_SLAVE_UFS_CARD_CFG 572 -#define SC8280XP_SLAVE_UFS_MEM_CFG 573 -#define SC8280XP_SLAVE_USB3_0 574 -#define SC8280XP_SLAVE_USB3_1 575 -#define SC8280XP_SLAVE_USB3_MP 576 -#define SC8280XP_SLAVE_USB4_0 577 -#define SC8280XP_SLAVE_USB4_1 578 -#define SC8280XP_SLAVE_VENUS_CFG 579 -#define SC8280XP_SLAVE_VSENSE_CTRL_CFG 580 -#define SC8280XP_SLAVE_VSENSE_CTRL_R_CFG 581 -#define SC8280XP_SLAVE_A1NOC_CFG 582 -#define SC8280XP_SLAVE_A1NOC_SNOC 583 -#define SC8280XP_SLAVE_A2NOC_CFG 584 -#define SC8280XP_SLAVE_A2NOC_SNOC 585 -#define SC8280XP_SLAVE_USB_NOC_SNOC 586 -#define SC8280XP_SLAVE_ANOC_PCIE_BRIDGE_CFG 587 -#define SC8280XP_SLAVE_DDRSS_CFG 588 -#define SC8280XP_SLAVE_GEM_NOC_CNOC 589 -#define SC8280XP_SLAVE_GEM_NOC_CFG 590 -#define SC8280XP_SLAVE_SNOC_GEM_NOC_GC 591 -#define SC8280XP_SLAVE_SNOC_GEM_NOC_SF 592 -#define SC8280XP_SLAVE_LLCC 593 -#define SC8280XP_SLAVE_MNOC_HF_MEM_NOC 594 -#define SC8280XP_SLAVE_MNOC_SF_MEM_NOC 595 -#define SC8280XP_SLAVE_CNOC_MNOC_CFG 596 -#define SC8280XP_SLAVE_CDSP_MEM_NOC 597 -#define SC8280XP_SLAVE_CDSPB_MEM_NOC 598 -#define SC8280XP_SLAVE_GEM_NOC_PCIE_CNOC 599 -#define SC8280XP_SLAVE_ANOC_PCIE_GEM_NOC 600 -#define SC8280XP_SLAVE_SNOC_CFG 601 -#define SC8280XP_SLAVE_SNOC_SF_BRIDGE_CFG 602 -#define SC8280XP_SLAVE_LPASS_SNOC 603 -#define SC8280XP_SLAVE_QUP_CORE_0 604 -#define SC8280XP_SLAVE_QUP_CORE_1 605 -#define SC8280XP_SLAVE_QUP_CORE_2 606 -#define SC8280XP_SLAVE_IMEM 607 -#define SC8280XP_SLAVE_NSP_XFR 608 -#define SC8280XP_SLAVE_NSPB_XFR 609 -#define SC8280XP_SLAVE_PIMEM 610 -#define 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This gives more flexibility and also allows us to drop the .num_links member, saving from possible errors related to it being not set or set incorrectly. Signed-off-by: Dmitry Baryshkov --- drivers/interconnect/qcom/sdm845.c | 774 ++++++++++++++++++---------------= ---- drivers/interconnect/qcom/sdm845.h | 140 ------- 2 files changed, 381 insertions(+), 533 deletions(-) diff --git a/drivers/interconnect/qcom/sdm845.c b/drivers/interconnect/qcom= /sdm845.c index 855802be93fea1d999bc8a885f36c3c318e1d86d..83d7a611cdf72d4b1cc17f86455= 106574a13cc9b 100644 --- a/drivers/interconnect/qcom/sdm845.c +++ b/drivers/interconnect/qcom/sdm845.c @@ -14,1251 +14,1231 @@ =20 #include "bcm-voter.h" #include "icc-rpmh.h" -#include "sdm845.h" + +static struct qcom_icc_node qhm_a1noc_cfg; +static struct qcom_icc_node qhm_qup1; +static struct qcom_icc_node qhm_tsif; +static struct qcom_icc_node xm_sdc2; +static struct qcom_icc_node xm_sdc4; +static struct qcom_icc_node xm_ufs_card; +static struct qcom_icc_node xm_ufs_mem; +static struct qcom_icc_node xm_pcie_0; +static struct qcom_icc_node qhm_a2noc_cfg; +static struct qcom_icc_node qhm_qdss_bam; +static struct qcom_icc_node qhm_qup2; +static struct qcom_icc_node qnm_cnoc; +static struct qcom_icc_node qxm_crypto; +static struct qcom_icc_node qxm_ipa; +static struct qcom_icc_node xm_pcie3_1; +static struct qcom_icc_node xm_qdss_etr; +static struct qcom_icc_node xm_usb3_0; +static struct qcom_icc_node xm_usb3_1; +static struct qcom_icc_node qxm_camnoc_hf0_uncomp; +static struct qcom_icc_node qxm_camnoc_hf1_uncomp; +static struct qcom_icc_node qxm_camnoc_sf_uncomp; +static struct qcom_icc_node qhm_spdm; +static struct qcom_icc_node qhm_tic; +static struct qcom_icc_node qnm_snoc; +static struct qcom_icc_node xm_qdss_dap; +static struct qcom_icc_node qhm_cnoc; +static struct qcom_icc_node acm_l3; +static struct qcom_icc_node pm_gnoc_cfg; +static struct qcom_icc_node llcc_mc; +static struct qcom_icc_node acm_tcu; +static struct qcom_icc_node qhm_memnoc_cfg; +static struct qcom_icc_node qnm_apps; +static struct qcom_icc_node qnm_mnoc_hf; +static struct qcom_icc_node qnm_mnoc_sf; +static struct qcom_icc_node qnm_snoc_gc; +static struct qcom_icc_node qnm_snoc_sf; +static struct qcom_icc_node qxm_gpu; +static struct qcom_icc_node qhm_mnoc_cfg; +static struct qcom_icc_node qxm_camnoc_hf0; +static struct qcom_icc_node qxm_camnoc_hf1; +static struct qcom_icc_node qxm_camnoc_sf; +static struct qcom_icc_node qxm_mdp0; +static struct qcom_icc_node qxm_mdp1; +static struct qcom_icc_node qxm_rot; +static struct qcom_icc_node qxm_venus0; +static struct qcom_icc_node qxm_venus1; +static struct qcom_icc_node qxm_venus_arm9; +static struct qcom_icc_node qhm_snoc_cfg; +static struct qcom_icc_node qnm_aggre1_noc; +static struct qcom_icc_node qnm_aggre2_noc; +static struct qcom_icc_node qnm_gladiator_sodv; +static struct qcom_icc_node qnm_memnoc; +static struct qcom_icc_node qnm_pcie_anoc; +static struct qcom_icc_node qxm_pimem; +static struct qcom_icc_node xm_gic; +static struct qcom_icc_node qns_a1noc_snoc; +static struct qcom_icc_node srvc_aggre1_noc; +static struct qcom_icc_node qns_pcie_a1noc_snoc; +static struct qcom_icc_node qns_a2noc_snoc; +static struct qcom_icc_node qns_pcie_snoc; +static struct qcom_icc_node srvc_aggre2_noc; +static struct qcom_icc_node qns_camnoc_uncomp; +static struct qcom_icc_node qhs_a1_noc_cfg; +static struct qcom_icc_node qhs_a2_noc_cfg; +static struct qcom_icc_node qhs_aop; +static struct qcom_icc_node qhs_aoss; +static struct qcom_icc_node qhs_camera_cfg; +static struct qcom_icc_node qhs_clk_ctl; +static struct qcom_icc_node qhs_compute_dsp_cfg; +static struct qcom_icc_node qhs_cpr_cx; +static struct qcom_icc_node qhs_crypto0_cfg; +static struct qcom_icc_node qhs_dcc_cfg; +static struct qcom_icc_node qhs_ddrss_cfg; +static struct qcom_icc_node qhs_display_cfg; +static struct qcom_icc_node qhs_glm; +static struct qcom_icc_node qhs_gpuss_cfg; +static struct qcom_icc_node qhs_imem_cfg; +static struct qcom_icc_node qhs_ipa; +static struct qcom_icc_node qhs_mnoc_cfg; +static struct qcom_icc_node qhs_pcie0_cfg; +static struct qcom_icc_node qhs_pcie_gen3_cfg; +static struct qcom_icc_node qhs_pdm; +static struct qcom_icc_node qhs_phy_refgen_south; +static struct qcom_icc_node qhs_pimem_cfg; +static struct qcom_icc_node qhs_prng; +static struct qcom_icc_node qhs_qdss_cfg; +static struct qcom_icc_node qhs_qupv3_north; +static struct qcom_icc_node qhs_qupv3_south; +static struct qcom_icc_node qhs_sdc2; +static struct qcom_icc_node qhs_sdc4; +static struct qcom_icc_node qhs_snoc_cfg; +static struct qcom_icc_node qhs_spdm; +static struct qcom_icc_node qhs_spss_cfg; +static struct qcom_icc_node qhs_tcsr; +static struct qcom_icc_node qhs_tlmm_north; +static struct qcom_icc_node qhs_tlmm_south; +static struct qcom_icc_node qhs_tsif; +static struct qcom_icc_node qhs_ufs_card_cfg; +static struct qcom_icc_node qhs_ufs_mem_cfg; +static struct qcom_icc_node qhs_usb3_0; +static struct qcom_icc_node qhs_usb3_1; +static struct qcom_icc_node qhs_venus_cfg; +static struct qcom_icc_node qhs_vsense_ctrl_cfg; +static struct qcom_icc_node qns_cnoc_a2noc; +static struct qcom_icc_node srvc_cnoc; +static struct qcom_icc_node qhs_llcc; +static struct qcom_icc_node qhs_memnoc; +static struct qcom_icc_node qns_gladiator_sodv; +static struct qcom_icc_node qns_gnoc_memnoc; +static struct qcom_icc_node srvc_gnoc; +static struct qcom_icc_node ebi; +static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg; +static struct qcom_icc_node qns_apps_io; +static struct qcom_icc_node qns_llcc; +static struct qcom_icc_node qns_memnoc_snoc; +static struct qcom_icc_node srvc_memnoc; +static struct qcom_icc_node qns2_mem_noc; +static struct qcom_icc_node qns_mem_noc_hf; +static struct qcom_icc_node srvc_mnoc; +static struct qcom_icc_node qhs_apss; +static struct qcom_icc_node qns_cnoc; +static struct qcom_icc_node qns_memnoc_gc; +static struct qcom_icc_node qns_memnoc_sf; +static struct qcom_icc_node qxs_imem; +static struct qcom_icc_node qxs_pcie; +static struct qcom_icc_node qxs_pcie_gen3; +static struct qcom_icc_node qxs_pimem; +static struct qcom_icc_node srvc_snoc; +static struct qcom_icc_node xs_qdss_stm; +static struct qcom_icc_node xs_sys_tcu_cfg; =20 static struct qcom_icc_node qhm_a1noc_cfg =3D { .name =3D "qhm_a1noc_cfg", - .id =3D SDM845_MASTER_A1NOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SDM845_SLAVE_SERVICE_A1NOC }, + .link_nodes =3D { &srvc_aggre1_noc }, }; =20 static struct qcom_icc_node qhm_qup1 =3D { .name =3D "qhm_qup1", - .id =3D SDM845_MASTER_BLSP_1, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SDM845_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node qhm_tsif =3D { .name =3D "qhm_tsif", - .id =3D SDM845_MASTER_TSIF, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SDM845_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node xm_sdc2 =3D { .name =3D "xm_sdc2", - .id =3D SDM845_MASTER_SDCC_2, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SDM845_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node xm_sdc4 =3D { .name =3D "xm_sdc4", - .id =3D SDM845_MASTER_SDCC_4, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SDM845_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node xm_ufs_card =3D { .name =3D "xm_ufs_card", - .id =3D SDM845_MASTER_UFS_CARD, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SDM845_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node xm_ufs_mem =3D { .name =3D "xm_ufs_mem", - .id =3D SDM845_MASTER_UFS_MEM, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SDM845_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node xm_pcie_0 =3D { .name =3D "xm_pcie_0", - .id =3D SDM845_MASTER_PCIE_0, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SDM845_SLAVE_ANOC_PCIE_A1NOC_SNOC }, + .link_nodes =3D { &qns_pcie_a1noc_snoc }, }; =20 static struct qcom_icc_node qhm_a2noc_cfg =3D { .name =3D "qhm_a2noc_cfg", - .id =3D SDM845_MASTER_A2NOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SDM845_SLAVE_SERVICE_A2NOC }, + .link_nodes =3D { &srvc_aggre2_noc }, }; =20 static struct qcom_icc_node qhm_qdss_bam =3D { .name =3D "qhm_qdss_bam", - .id =3D SDM845_MASTER_QDSS_BAM, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SDM845_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qhm_qup2 =3D { .name =3D "qhm_qup2", - .id =3D SDM845_MASTER_BLSP_2, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SDM845_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qnm_cnoc =3D { .name =3D "qnm_cnoc", - .id =3D SDM845_MASTER_CNOC_A2NOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SDM845_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qxm_crypto =3D { .name =3D "qxm_crypto", - .id =3D SDM845_MASTER_CRYPTO, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SDM845_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qxm_ipa =3D { .name =3D "qxm_ipa", - .id =3D SDM845_MASTER_IPA, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SDM845_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node xm_pcie3_1 =3D { .name =3D "xm_pcie3_1", - .id =3D SDM845_MASTER_PCIE_1, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SDM845_SLAVE_ANOC_PCIE_SNOC }, + .link_nodes =3D { &qns_pcie_snoc }, }; =20 static struct qcom_icc_node xm_qdss_etr =3D { .name =3D "xm_qdss_etr", - .id =3D SDM845_MASTER_QDSS_ETR, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SDM845_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node xm_usb3_0 =3D { .name =3D "xm_usb3_0", - .id =3D SDM845_MASTER_USB3_0, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SDM845_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node xm_usb3_1 =3D { .name =3D "xm_usb3_1", - .id =3D SDM845_MASTER_USB3_1, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SDM845_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qxm_camnoc_hf0_uncomp =3D { .name =3D "qxm_camnoc_hf0_uncomp", - .id =3D SDM845_MASTER_CAMNOC_HF0_UNCOMP, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SDM845_SLAVE_CAMNOC_UNCOMP }, + .link_nodes =3D { &qns_camnoc_uncomp }, }; =20 static struct qcom_icc_node qxm_camnoc_hf1_uncomp =3D { .name =3D "qxm_camnoc_hf1_uncomp", - .id =3D SDM845_MASTER_CAMNOC_HF1_UNCOMP, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SDM845_SLAVE_CAMNOC_UNCOMP }, + .link_nodes =3D { &qns_camnoc_uncomp }, }; =20 static struct qcom_icc_node qxm_camnoc_sf_uncomp =3D { .name =3D "qxm_camnoc_sf_uncomp", - .id =3D SDM845_MASTER_CAMNOC_SF_UNCOMP, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SDM845_SLAVE_CAMNOC_UNCOMP }, + .link_nodes =3D { &qns_camnoc_uncomp }, }; =20 static struct qcom_icc_node qhm_spdm =3D { .name =3D "qhm_spdm", - .id =3D SDM845_MASTER_SPDM, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SDM845_SLAVE_CNOC_A2NOC }, + .link_nodes =3D { &qns_cnoc_a2noc }, }; =20 static struct qcom_icc_node qhm_tic =3D { .name =3D "qhm_tic", - .id =3D SDM845_MASTER_TIC, .channels =3D 1, .buswidth =3D 4, .num_links =3D 43, - .links =3D { SDM845_SLAVE_A1NOC_CFG, - SDM845_SLAVE_A2NOC_CFG, - SDM845_SLAVE_AOP, - SDM845_SLAVE_AOSS, - SDM845_SLAVE_CAMERA_CFG, - SDM845_SLAVE_CLK_CTL, - SDM845_SLAVE_CDSP_CFG, - SDM845_SLAVE_RBCPR_CX_CFG, - SDM845_SLAVE_CRYPTO_0_CFG, - SDM845_SLAVE_DCC_CFG, - SDM845_SLAVE_CNOC_DDRSS, - SDM845_SLAVE_DISPLAY_CFG, - SDM845_SLAVE_GLM, - SDM845_SLAVE_GFX3D_CFG, - SDM845_SLAVE_IMEM_CFG, - SDM845_SLAVE_IPA_CFG, - SDM845_SLAVE_CNOC_MNOC_CFG, - SDM845_SLAVE_PCIE_0_CFG, - SDM845_SLAVE_PCIE_1_CFG, - SDM845_SLAVE_PDM, - SDM845_SLAVE_SOUTH_PHY_CFG, - SDM845_SLAVE_PIMEM_CFG, - SDM845_SLAVE_PRNG, - SDM845_SLAVE_QDSS_CFG, - SDM845_SLAVE_BLSP_2, - SDM845_SLAVE_BLSP_1, - SDM845_SLAVE_SDCC_2, - SDM845_SLAVE_SDCC_4, - SDM845_SLAVE_SNOC_CFG, - SDM845_SLAVE_SPDM_WRAPPER, - SDM845_SLAVE_SPSS_CFG, - SDM845_SLAVE_TCSR, - SDM845_SLAVE_TLMM_NORTH, - SDM845_SLAVE_TLMM_SOUTH, - SDM845_SLAVE_TSIF, - SDM845_SLAVE_UFS_CARD_CFG, - SDM845_SLAVE_UFS_MEM_CFG, - SDM845_SLAVE_USB3_0, - SDM845_SLAVE_USB3_1, - SDM845_SLAVE_VENUS_CFG, - SDM845_SLAVE_VSENSE_CTRL_CFG, - SDM845_SLAVE_CNOC_A2NOC, - SDM845_SLAVE_SERVICE_CNOC - }, + .link_nodes =3D { &qhs_a1_noc_cfg, + &qhs_a2_noc_cfg, + &qhs_aop, + &qhs_aoss, + &qhs_camera_cfg, + &qhs_clk_ctl, + &qhs_compute_dsp_cfg, + &qhs_cpr_cx, + &qhs_crypto0_cfg, + &qhs_dcc_cfg, + &qhs_ddrss_cfg, + &qhs_display_cfg, + &qhs_glm, + &qhs_gpuss_cfg, + &qhs_imem_cfg, + &qhs_ipa, + &qhs_mnoc_cfg, + &qhs_pcie0_cfg, + &qhs_pcie_gen3_cfg, + &qhs_pdm, + &qhs_phy_refgen_south, + &qhs_pimem_cfg, + &qhs_prng, + &qhs_qdss_cfg, + &qhs_qupv3_north, + &qhs_qupv3_south, + &qhs_sdc2, + &qhs_sdc4, + &qhs_snoc_cfg, + &qhs_spdm, + &qhs_spss_cfg, + &qhs_tcsr, + &qhs_tlmm_north, + &qhs_tlmm_south, + &qhs_tsif, + &qhs_ufs_card_cfg, + &qhs_ufs_mem_cfg, + &qhs_usb3_0, + &qhs_usb3_1, + &qhs_venus_cfg, + &qhs_vsense_ctrl_cfg, + &qns_cnoc_a2noc, + &srvc_cnoc }, }; =20 static struct qcom_icc_node qnm_snoc =3D { .name =3D "qnm_snoc", - .id =3D SDM845_MASTER_SNOC_CNOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 42, - .links =3D { SDM845_SLAVE_A1NOC_CFG, - SDM845_SLAVE_A2NOC_CFG, - SDM845_SLAVE_AOP, - SDM845_SLAVE_AOSS, - SDM845_SLAVE_CAMERA_CFG, - SDM845_SLAVE_CLK_CTL, - SDM845_SLAVE_CDSP_CFG, - SDM845_SLAVE_RBCPR_CX_CFG, - SDM845_SLAVE_CRYPTO_0_CFG, - SDM845_SLAVE_DCC_CFG, - SDM845_SLAVE_CNOC_DDRSS, - SDM845_SLAVE_DISPLAY_CFG, - SDM845_SLAVE_GLM, - SDM845_SLAVE_GFX3D_CFG, - SDM845_SLAVE_IMEM_CFG, - SDM845_SLAVE_IPA_CFG, - SDM845_SLAVE_CNOC_MNOC_CFG, - SDM845_SLAVE_PCIE_0_CFG, - SDM845_SLAVE_PCIE_1_CFG, - SDM845_SLAVE_PDM, - SDM845_SLAVE_SOUTH_PHY_CFG, - SDM845_SLAVE_PIMEM_CFG, - SDM845_SLAVE_PRNG, - SDM845_SLAVE_QDSS_CFG, - SDM845_SLAVE_BLSP_2, - SDM845_SLAVE_BLSP_1, - SDM845_SLAVE_SDCC_2, - SDM845_SLAVE_SDCC_4, - SDM845_SLAVE_SNOC_CFG, - SDM845_SLAVE_SPDM_WRAPPER, - SDM845_SLAVE_SPSS_CFG, - SDM845_SLAVE_TCSR, - SDM845_SLAVE_TLMM_NORTH, - SDM845_SLAVE_TLMM_SOUTH, - SDM845_SLAVE_TSIF, - SDM845_SLAVE_UFS_CARD_CFG, - SDM845_SLAVE_UFS_MEM_CFG, - SDM845_SLAVE_USB3_0, - SDM845_SLAVE_USB3_1, - SDM845_SLAVE_VENUS_CFG, - SDM845_SLAVE_VSENSE_CTRL_CFG, - SDM845_SLAVE_SERVICE_CNOC - }, + .link_nodes =3D { &qhs_a1_noc_cfg, + &qhs_a2_noc_cfg, + &qhs_aop, + &qhs_aoss, + &qhs_camera_cfg, + &qhs_clk_ctl, + &qhs_compute_dsp_cfg, + &qhs_cpr_cx, + &qhs_crypto0_cfg, + &qhs_dcc_cfg, + &qhs_ddrss_cfg, + &qhs_display_cfg, + &qhs_glm, + &qhs_gpuss_cfg, + &qhs_imem_cfg, + &qhs_ipa, + &qhs_mnoc_cfg, + &qhs_pcie0_cfg, + &qhs_pcie_gen3_cfg, + &qhs_pdm, + &qhs_phy_refgen_south, + &qhs_pimem_cfg, + &qhs_prng, + &qhs_qdss_cfg, + &qhs_qupv3_north, + &qhs_qupv3_south, + &qhs_sdc2, + &qhs_sdc4, + &qhs_snoc_cfg, + &qhs_spdm, + &qhs_spss_cfg, + &qhs_tcsr, + &qhs_tlmm_north, + &qhs_tlmm_south, + &qhs_tsif, + &qhs_ufs_card_cfg, + &qhs_ufs_mem_cfg, + &qhs_usb3_0, + &qhs_usb3_1, + &qhs_venus_cfg, + &qhs_vsense_ctrl_cfg, + &srvc_cnoc }, }; =20 static struct qcom_icc_node xm_qdss_dap =3D { .name =3D "xm_qdss_dap", - .id =3D SDM845_MASTER_QDSS_DAP, .channels =3D 1, .buswidth =3D 8, .num_links =3D 43, - .links =3D { SDM845_SLAVE_A1NOC_CFG, - SDM845_SLAVE_A2NOC_CFG, - SDM845_SLAVE_AOP, - SDM845_SLAVE_AOSS, - SDM845_SLAVE_CAMERA_CFG, - SDM845_SLAVE_CLK_CTL, - SDM845_SLAVE_CDSP_CFG, - SDM845_SLAVE_RBCPR_CX_CFG, - SDM845_SLAVE_CRYPTO_0_CFG, - SDM845_SLAVE_DCC_CFG, - SDM845_SLAVE_CNOC_DDRSS, - SDM845_SLAVE_DISPLAY_CFG, - SDM845_SLAVE_GLM, - SDM845_SLAVE_GFX3D_CFG, - SDM845_SLAVE_IMEM_CFG, - SDM845_SLAVE_IPA_CFG, - SDM845_SLAVE_CNOC_MNOC_CFG, - SDM845_SLAVE_PCIE_0_CFG, - SDM845_SLAVE_PCIE_1_CFG, - SDM845_SLAVE_PDM, - SDM845_SLAVE_SOUTH_PHY_CFG, - SDM845_SLAVE_PIMEM_CFG, - SDM845_SLAVE_PRNG, - SDM845_SLAVE_QDSS_CFG, - SDM845_SLAVE_BLSP_2, - SDM845_SLAVE_BLSP_1, - SDM845_SLAVE_SDCC_2, - SDM845_SLAVE_SDCC_4, - SDM845_SLAVE_SNOC_CFG, - SDM845_SLAVE_SPDM_WRAPPER, - SDM845_SLAVE_SPSS_CFG, - SDM845_SLAVE_TCSR, - SDM845_SLAVE_TLMM_NORTH, - SDM845_SLAVE_TLMM_SOUTH, - SDM845_SLAVE_TSIF, - SDM845_SLAVE_UFS_CARD_CFG, - SDM845_SLAVE_UFS_MEM_CFG, - SDM845_SLAVE_USB3_0, - SDM845_SLAVE_USB3_1, - SDM845_SLAVE_VENUS_CFG, - SDM845_SLAVE_VSENSE_CTRL_CFG, - SDM845_SLAVE_CNOC_A2NOC, - SDM845_SLAVE_SERVICE_CNOC - }, + .link_nodes =3D { &qhs_a1_noc_cfg, + &qhs_a2_noc_cfg, + &qhs_aop, + &qhs_aoss, + &qhs_camera_cfg, + &qhs_clk_ctl, + &qhs_compute_dsp_cfg, + &qhs_cpr_cx, + &qhs_crypto0_cfg, + &qhs_dcc_cfg, + &qhs_ddrss_cfg, + &qhs_display_cfg, + &qhs_glm, + &qhs_gpuss_cfg, + &qhs_imem_cfg, + &qhs_ipa, + &qhs_mnoc_cfg, + &qhs_pcie0_cfg, + &qhs_pcie_gen3_cfg, + &qhs_pdm, + &qhs_phy_refgen_south, + &qhs_pimem_cfg, + &qhs_prng, + &qhs_qdss_cfg, + &qhs_qupv3_north, + &qhs_qupv3_south, + &qhs_sdc2, + &qhs_sdc4, + &qhs_snoc_cfg, + &qhs_spdm, + &qhs_spss_cfg, + &qhs_tcsr, + &qhs_tlmm_north, + &qhs_tlmm_south, + &qhs_tsif, + &qhs_ufs_card_cfg, + &qhs_ufs_mem_cfg, + &qhs_usb3_0, + &qhs_usb3_1, + &qhs_venus_cfg, + &qhs_vsense_ctrl_cfg, + &qns_cnoc_a2noc, + &srvc_cnoc }, }; =20 static struct qcom_icc_node qhm_cnoc =3D { .name =3D "qhm_cnoc", - .id =3D SDM845_MASTER_CNOC_DC_NOC, .channels =3D 1, .buswidth =3D 4, .num_links =3D 2, - .links =3D { SDM845_SLAVE_LLCC_CFG, - SDM845_SLAVE_MEM_NOC_CFG - }, + .link_nodes =3D { &qhs_llcc, + &qhs_memnoc }, }; =20 static struct qcom_icc_node acm_l3 =3D { .name =3D "acm_l3", - .id =3D SDM845_MASTER_APPSS_PROC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 3, - .links =3D { SDM845_SLAVE_GNOC_SNOC, - SDM845_SLAVE_GNOC_MEM_NOC, - SDM845_SLAVE_SERVICE_GNOC - }, + .link_nodes =3D { &qns_gladiator_sodv, + &qns_gnoc_memnoc, + &srvc_gnoc }, }; =20 static struct qcom_icc_node pm_gnoc_cfg =3D { .name =3D "pm_gnoc_cfg", - .id =3D SDM845_MASTER_GNOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SDM845_SLAVE_SERVICE_GNOC }, + .link_nodes =3D { &srvc_gnoc }, }; =20 static struct qcom_icc_node llcc_mc =3D { .name =3D "llcc_mc", - .id =3D SDM845_MASTER_LLCC, .channels =3D 4, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SDM845_SLAVE_EBI1 }, + .link_nodes =3D { &ebi }, }; =20 static struct qcom_icc_node acm_tcu =3D { .name =3D "acm_tcu", - .id =3D SDM845_MASTER_TCU_0, .channels =3D 1, .buswidth =3D 8, .num_links =3D 3, - .links =3D { SDM845_SLAVE_MEM_NOC_GNOC, - SDM845_SLAVE_LLCC, - SDM845_SLAVE_MEM_NOC_SNOC - }, + .link_nodes =3D { &qns_apps_io, + &qns_llcc, + &qns_memnoc_snoc }, }; =20 static struct qcom_icc_node qhm_memnoc_cfg =3D { .name =3D "qhm_memnoc_cfg", - .id =3D SDM845_MASTER_MEM_NOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 2, - .links =3D { SDM845_SLAVE_MSS_PROC_MS_MPU_CFG, - SDM845_SLAVE_SERVICE_MEM_NOC - }, + .link_nodes =3D { &qhs_mdsp_ms_mpu_cfg, + &srvc_memnoc }, }; =20 static struct qcom_icc_node qnm_apps =3D { .name =3D "qnm_apps", - .id =3D SDM845_MASTER_GNOC_MEM_NOC, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SDM845_SLAVE_LLCC }, + .link_nodes =3D { &qns_llcc }, }; =20 static struct qcom_icc_node qnm_mnoc_hf =3D { .name =3D "qnm_mnoc_hf", - .id =3D SDM845_MASTER_MNOC_HF_MEM_NOC, .channels =3D 2, .buswidth =3D 32, .num_links =3D 2, - .links =3D { SDM845_SLAVE_MEM_NOC_GNOC, - SDM845_SLAVE_LLCC - }, + .link_nodes =3D { &qns_apps_io, + &qns_llcc }, }; =20 static struct qcom_icc_node qnm_mnoc_sf =3D { .name =3D "qnm_mnoc_sf", - .id =3D SDM845_MASTER_MNOC_SF_MEM_NOC, .channels =3D 1, .buswidth =3D 32, .num_links =3D 3, - .links =3D { SDM845_SLAVE_MEM_NOC_GNOC, - SDM845_SLAVE_LLCC, - SDM845_SLAVE_MEM_NOC_SNOC - }, + .link_nodes =3D { &qns_apps_io, + &qns_llcc, + &qns_memnoc_snoc }, }; =20 static struct qcom_icc_node qnm_snoc_gc =3D { .name =3D "qnm_snoc_gc", - .id =3D SDM845_MASTER_SNOC_GC_MEM_NOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SDM845_SLAVE_LLCC }, + .link_nodes =3D { &qns_llcc }, }; =20 static struct qcom_icc_node qnm_snoc_sf =3D { .name =3D "qnm_snoc_sf", - .id =3D SDM845_MASTER_SNOC_SF_MEM_NOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 2, - .links =3D { SDM845_SLAVE_MEM_NOC_GNOC, - SDM845_SLAVE_LLCC - }, + .link_nodes =3D { &qns_apps_io, + &qns_llcc }, }; =20 static struct qcom_icc_node qxm_gpu =3D { .name =3D "qxm_gpu", - .id =3D SDM845_MASTER_GFX3D, .channels =3D 2, .buswidth =3D 32, .num_links =3D 3, - .links =3D { SDM845_SLAVE_MEM_NOC_GNOC, - SDM845_SLAVE_LLCC, - SDM845_SLAVE_MEM_NOC_SNOC - }, + .link_nodes =3D { &qns_apps_io, + &qns_llcc, + &qns_memnoc_snoc }, }; =20 static struct qcom_icc_node qhm_mnoc_cfg =3D { .name =3D "qhm_mnoc_cfg", - .id =3D SDM845_MASTER_CNOC_MNOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SDM845_SLAVE_SERVICE_MNOC }, + .link_nodes =3D { &srvc_mnoc }, }; =20 static struct qcom_icc_node qxm_camnoc_hf0 =3D { .name =3D "qxm_camnoc_hf0", - .id =3D SDM845_MASTER_CAMNOC_HF0, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SDM845_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_hf }, }; =20 static struct qcom_icc_node qxm_camnoc_hf1 =3D { .name =3D "qxm_camnoc_hf1", - .id =3D SDM845_MASTER_CAMNOC_HF1, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SDM845_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_hf }, }; =20 static struct qcom_icc_node qxm_camnoc_sf =3D { .name =3D "qxm_camnoc_sf", - .id =3D SDM845_MASTER_CAMNOC_SF, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SDM845_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns2_mem_noc }, }; =20 static struct qcom_icc_node qxm_mdp0 =3D { .name =3D "qxm_mdp0", - .id =3D SDM845_MASTER_MDP0, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SDM845_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_hf }, }; =20 static struct qcom_icc_node qxm_mdp1 =3D { .name =3D "qxm_mdp1", - .id =3D SDM845_MASTER_MDP1, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SDM845_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_hf }, }; =20 static struct qcom_icc_node qxm_rot =3D { .name =3D "qxm_rot", - .id =3D SDM845_MASTER_ROTATOR, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SDM845_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns2_mem_noc }, }; =20 static struct qcom_icc_node qxm_venus0 =3D { .name =3D "qxm_venus0", - .id =3D SDM845_MASTER_VIDEO_P0, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SDM845_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns2_mem_noc }, }; =20 static struct qcom_icc_node qxm_venus1 =3D { .name =3D "qxm_venus1", - .id =3D SDM845_MASTER_VIDEO_P1, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SDM845_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns2_mem_noc }, }; =20 static struct qcom_icc_node qxm_venus_arm9 =3D { .name =3D "qxm_venus_arm9", - .id =3D SDM845_MASTER_VIDEO_PROC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SDM845_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns2_mem_noc }, }; =20 static struct qcom_icc_node qhm_snoc_cfg =3D { .name =3D "qhm_snoc_cfg", - .id =3D SDM845_MASTER_SNOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SDM845_SLAVE_SERVICE_SNOC }, + .link_nodes =3D { &srvc_snoc }, }; =20 static struct qcom_icc_node qnm_aggre1_noc =3D { .name =3D "qnm_aggre1_noc", - .id =3D SDM845_MASTER_A1NOC_SNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 6, - .links =3D { SDM845_SLAVE_APPSS, - SDM845_SLAVE_SNOC_CNOC, - SDM845_SLAVE_SNOC_MEM_NOC_SF, - SDM845_SLAVE_IMEM, - SDM845_SLAVE_PIMEM, - SDM845_SLAVE_QDSS_STM - }, + .link_nodes =3D { &qhs_apss, + &qns_cnoc, + &qns_memnoc_sf, + &qxs_imem, + &qxs_pimem, + &xs_qdss_stm }, }; =20 static struct qcom_icc_node qnm_aggre2_noc =3D { .name =3D "qnm_aggre2_noc", - .id =3D SDM845_MASTER_A2NOC_SNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 9, - .links =3D { SDM845_SLAVE_APPSS, - SDM845_SLAVE_SNOC_CNOC, - SDM845_SLAVE_SNOC_MEM_NOC_SF, - SDM845_SLAVE_IMEM, - SDM845_SLAVE_PCIE_0, - SDM845_SLAVE_PCIE_1, - SDM845_SLAVE_PIMEM, - SDM845_SLAVE_QDSS_STM, - SDM845_SLAVE_TCU - }, + .link_nodes =3D { &qhs_apss, + &qns_cnoc, + &qns_memnoc_sf, + &qxs_imem, + &qxs_pcie, + &qxs_pcie_gen3, + &qxs_pimem, + &xs_qdss_stm, + &xs_sys_tcu_cfg }, }; =20 static struct qcom_icc_node qnm_gladiator_sodv =3D { .name =3D "qnm_gladiator_sodv", - .id =3D SDM845_MASTER_GNOC_SNOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 8, - .links =3D { SDM845_SLAVE_APPSS, - SDM845_SLAVE_SNOC_CNOC, - SDM845_SLAVE_IMEM, - SDM845_SLAVE_PCIE_0, - SDM845_SLAVE_PCIE_1, - SDM845_SLAVE_PIMEM, - SDM845_SLAVE_QDSS_STM, - SDM845_SLAVE_TCU - }, + .link_nodes =3D { &qhs_apss, + &qns_cnoc, + &qxs_imem, + &qxs_pcie, + &qxs_pcie_gen3, + &qxs_pimem, + &xs_qdss_stm, + &xs_sys_tcu_cfg }, }; =20 static struct qcom_icc_node qnm_memnoc =3D { .name =3D "qnm_memnoc", - .id =3D SDM845_MASTER_MEM_NOC_SNOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 5, - .links =3D { SDM845_SLAVE_APPSS, - SDM845_SLAVE_SNOC_CNOC, - SDM845_SLAVE_IMEM, - SDM845_SLAVE_PIMEM, - SDM845_SLAVE_QDSS_STM - }, + .link_nodes =3D { &qhs_apss, + &qns_cnoc, + &qxs_imem, + &qxs_pimem, + &xs_qdss_stm }, }; =20 static struct qcom_icc_node qnm_pcie_anoc =3D { .name =3D "qnm_pcie_anoc", - .id =3D SDM845_MASTER_ANOC_PCIE_SNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 5, - .links =3D { SDM845_SLAVE_APPSS, - SDM845_SLAVE_SNOC_CNOC, - SDM845_SLAVE_SNOC_MEM_NOC_SF, - SDM845_SLAVE_IMEM, - SDM845_SLAVE_QDSS_STM - }, + .link_nodes =3D { &qhs_apss, + &qns_cnoc, + &qns_memnoc_sf, + &qxs_imem, + &xs_qdss_stm }, }; =20 static struct qcom_icc_node qxm_pimem =3D { .name =3D "qxm_pimem", - .id =3D SDM845_MASTER_PIMEM, .channels =3D 1, .buswidth =3D 8, .num_links =3D 2, - .links =3D { SDM845_SLAVE_SNOC_MEM_NOC_GC, - SDM845_SLAVE_IMEM - }, + .link_nodes =3D { &qns_memnoc_gc, + &qxs_imem }, }; =20 static struct qcom_icc_node xm_gic =3D { .name =3D "xm_gic", - .id =3D SDM845_MASTER_GIC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 2, - .links =3D { SDM845_SLAVE_SNOC_MEM_NOC_GC, - SDM845_SLAVE_IMEM - }, + .link_nodes =3D { &qns_memnoc_gc, + &qxs_imem }, }; =20 static struct qcom_icc_node qns_a1noc_snoc =3D { .name =3D "qns_a1noc_snoc", - .id =3D SDM845_SLAVE_A1NOC_SNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SDM845_MASTER_A1NOC_SNOC }, + .link_nodes =3D { &qnm_aggre1_noc }, }; =20 static struct qcom_icc_node srvc_aggre1_noc =3D { .name =3D "srvc_aggre1_noc", - .id =3D SDM845_SLAVE_SERVICE_A1NOC, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 1, - .links =3D { 0 }, }; =20 static struct qcom_icc_node qns_pcie_a1noc_snoc =3D { .name =3D "qns_pcie_a1noc_snoc", - .id =3D SDM845_SLAVE_ANOC_PCIE_A1NOC_SNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SDM845_MASTER_ANOC_PCIE_SNOC }, + .link_nodes =3D { &qnm_pcie_anoc }, }; =20 static struct qcom_icc_node qns_a2noc_snoc =3D { .name =3D "qns_a2noc_snoc", - .id =3D SDM845_SLAVE_A2NOC_SNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SDM845_MASTER_A2NOC_SNOC }, + .link_nodes =3D { &qnm_aggre2_noc }, }; =20 static struct qcom_icc_node qns_pcie_snoc =3D { .name =3D "qns_pcie_snoc", - .id =3D SDM845_SLAVE_ANOC_PCIE_SNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SDM845_MASTER_ANOC_PCIE_SNOC }, + .link_nodes =3D { &qnm_pcie_anoc }, }; =20 static struct qcom_icc_node srvc_aggre2_noc =3D { .name =3D "srvc_aggre2_noc", - .id =3D SDM845_SLAVE_SERVICE_A2NOC, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qns_camnoc_uncomp =3D { .name =3D "qns_camnoc_uncomp", - .id =3D SDM845_SLAVE_CAMNOC_UNCOMP, .channels =3D 1, .buswidth =3D 32, }; =20 static struct qcom_icc_node qhs_a1_noc_cfg =3D { .name =3D "qhs_a1_noc_cfg", - .id =3D SDM845_SLAVE_A1NOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SDM845_MASTER_A1NOC_CFG }, + .link_nodes =3D { &qhm_a1noc_cfg }, }; =20 static struct qcom_icc_node qhs_a2_noc_cfg =3D { .name =3D "qhs_a2_noc_cfg", - .id =3D SDM845_SLAVE_A2NOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SDM845_MASTER_A2NOC_CFG }, + .link_nodes =3D { &qhm_a2noc_cfg }, }; =20 static struct qcom_icc_node qhs_aop =3D { .name =3D "qhs_aop", - .id =3D SDM845_SLAVE_AOP, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_aoss =3D { .name =3D "qhs_aoss", - .id =3D SDM845_SLAVE_AOSS, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_camera_cfg =3D { .name =3D "qhs_camera_cfg", - .id =3D SDM845_SLAVE_CAMERA_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_clk_ctl =3D { .name =3D "qhs_clk_ctl", - .id =3D SDM845_SLAVE_CLK_CTL, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_compute_dsp_cfg =3D { .name =3D "qhs_compute_dsp_cfg", - .id =3D SDM845_SLAVE_CDSP_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_cpr_cx =3D { .name =3D "qhs_cpr_cx", - .id =3D SDM845_SLAVE_RBCPR_CX_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_crypto0_cfg =3D { .name =3D "qhs_crypto0_cfg", - .id =3D SDM845_SLAVE_CRYPTO_0_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_dcc_cfg =3D { .name =3D "qhs_dcc_cfg", - .id =3D SDM845_SLAVE_DCC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SDM845_MASTER_CNOC_DC_NOC }, + .link_nodes =3D { &qhm_cnoc }, }; =20 static struct qcom_icc_node qhs_ddrss_cfg =3D { .name =3D "qhs_ddrss_cfg", - .id =3D SDM845_SLAVE_CNOC_DDRSS, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_display_cfg =3D { .name =3D "qhs_display_cfg", - .id =3D SDM845_SLAVE_DISPLAY_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_glm =3D { .name =3D "qhs_glm", - .id =3D SDM845_SLAVE_GLM, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_gpuss_cfg =3D { .name =3D "qhs_gpuss_cfg", - .id =3D SDM845_SLAVE_GFX3D_CFG, .channels =3D 1, .buswidth =3D 8, }; =20 static struct qcom_icc_node qhs_imem_cfg =3D { .name =3D "qhs_imem_cfg", - .id =3D SDM845_SLAVE_IMEM_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_ipa =3D { .name =3D "qhs_ipa", - .id =3D SDM845_SLAVE_IPA_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_mnoc_cfg =3D { .name =3D "qhs_mnoc_cfg", - .id =3D SDM845_SLAVE_CNOC_MNOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SDM845_MASTER_CNOC_MNOC_CFG }, + .link_nodes =3D { &qhm_mnoc_cfg }, }; =20 static struct qcom_icc_node qhs_pcie0_cfg =3D { .name =3D "qhs_pcie0_cfg", - .id =3D SDM845_SLAVE_PCIE_0_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_pcie_gen3_cfg =3D { .name =3D "qhs_pcie_gen3_cfg", - .id =3D SDM845_SLAVE_PCIE_1_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_pdm =3D { .name =3D "qhs_pdm", - .id =3D SDM845_SLAVE_PDM, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_phy_refgen_south =3D { .name =3D "qhs_phy_refgen_south", - .id =3D SDM845_SLAVE_SOUTH_PHY_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_pimem_cfg =3D { .name =3D "qhs_pimem_cfg", - .id =3D SDM845_SLAVE_PIMEM_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_prng =3D { .name =3D "qhs_prng", - .id =3D SDM845_SLAVE_PRNG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_qdss_cfg =3D { .name =3D "qhs_qdss_cfg", - .id =3D SDM845_SLAVE_QDSS_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_qupv3_north =3D { .name =3D "qhs_qupv3_north", - .id =3D SDM845_SLAVE_BLSP_2, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_qupv3_south =3D { .name =3D "qhs_qupv3_south", - .id =3D SDM845_SLAVE_BLSP_1, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_sdc2 =3D { .name =3D "qhs_sdc2", - .id =3D SDM845_SLAVE_SDCC_2, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_sdc4 =3D { .name =3D "qhs_sdc4", - .id =3D SDM845_SLAVE_SDCC_4, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_snoc_cfg =3D { .name =3D "qhs_snoc_cfg", - .id =3D SDM845_SLAVE_SNOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SDM845_MASTER_SNOC_CFG }, + .link_nodes =3D { &qhm_snoc_cfg }, }; =20 static struct qcom_icc_node qhs_spdm =3D { .name =3D "qhs_spdm", - .id =3D SDM845_SLAVE_SPDM_WRAPPER, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_spss_cfg =3D { .name =3D "qhs_spss_cfg", - .id =3D SDM845_SLAVE_SPSS_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_tcsr =3D { .name =3D "qhs_tcsr", - .id =3D SDM845_SLAVE_TCSR, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_tlmm_north =3D { .name =3D "qhs_tlmm_north", - .id =3D SDM845_SLAVE_TLMM_NORTH, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_tlmm_south =3D { .name =3D "qhs_tlmm_south", - .id =3D SDM845_SLAVE_TLMM_SOUTH, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_tsif =3D { .name =3D "qhs_tsif", - .id =3D SDM845_SLAVE_TSIF, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_ufs_card_cfg =3D { .name =3D "qhs_ufs_card_cfg", - .id =3D SDM845_SLAVE_UFS_CARD_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_ufs_mem_cfg =3D { .name =3D "qhs_ufs_mem_cfg", - .id =3D SDM845_SLAVE_UFS_MEM_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_usb3_0 =3D { .name =3D "qhs_usb3_0", - .id =3D SDM845_SLAVE_USB3_0, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_usb3_1 =3D { .name =3D "qhs_usb3_1", - .id =3D SDM845_SLAVE_USB3_1, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_venus_cfg =3D { .name =3D "qhs_venus_cfg", - .id =3D SDM845_SLAVE_VENUS_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_vsense_ctrl_cfg =3D { .name =3D "qhs_vsense_ctrl_cfg", - .id =3D SDM845_SLAVE_VSENSE_CTRL_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qns_cnoc_a2noc =3D { .name =3D "qns_cnoc_a2noc", - .id =3D SDM845_SLAVE_CNOC_A2NOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SDM845_MASTER_CNOC_A2NOC }, + .link_nodes =3D { &qnm_cnoc }, }; =20 static struct qcom_icc_node srvc_cnoc =3D { .name =3D "srvc_cnoc", - .id =3D SDM845_SLAVE_SERVICE_CNOC, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_llcc =3D { .name =3D "qhs_llcc", - .id =3D SDM845_SLAVE_LLCC_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_memnoc =3D { .name =3D "qhs_memnoc", - .id =3D SDM845_SLAVE_MEM_NOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SDM845_MASTER_MEM_NOC_CFG }, + .link_nodes =3D { &qhm_memnoc_cfg }, }; =20 static struct qcom_icc_node qns_gladiator_sodv =3D { .name =3D "qns_gladiator_sodv", - .id =3D SDM845_SLAVE_GNOC_SNOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SDM845_MASTER_GNOC_SNOC }, + .link_nodes =3D { &qnm_gladiator_sodv }, }; =20 static struct qcom_icc_node qns_gnoc_memnoc =3D { .name =3D "qns_gnoc_memnoc", - .id =3D SDM845_SLAVE_GNOC_MEM_NOC, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SDM845_MASTER_GNOC_MEM_NOC }, + .link_nodes =3D { &qnm_apps }, }; =20 static struct qcom_icc_node srvc_gnoc =3D { .name =3D "srvc_gnoc", - .id =3D SDM845_SLAVE_SERVICE_GNOC, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node ebi =3D { .name =3D "ebi", - .id =3D SDM845_SLAVE_EBI1, .channels =3D 4, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg =3D { .name =3D "qhs_mdsp_ms_mpu_cfg", - .id =3D SDM845_SLAVE_MSS_PROC_MS_MPU_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qns_apps_io =3D { .name =3D "qns_apps_io", - .id =3D SDM845_SLAVE_MEM_NOC_GNOC, .channels =3D 1, .buswidth =3D 32, }; =20 static struct qcom_icc_node qns_llcc =3D { .name =3D "qns_llcc", - .id =3D SDM845_SLAVE_LLCC, .channels =3D 4, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SDM845_MASTER_LLCC }, + .link_nodes =3D { &llcc_mc }, }; =20 static struct qcom_icc_node qns_memnoc_snoc =3D { .name =3D "qns_memnoc_snoc", - .id =3D SDM845_SLAVE_MEM_NOC_SNOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SDM845_MASTER_MEM_NOC_SNOC }, + .link_nodes =3D { &qnm_memnoc }, }; =20 static struct qcom_icc_node srvc_memnoc =3D { .name =3D "srvc_memnoc", - .id =3D SDM845_SLAVE_SERVICE_MEM_NOC, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qns2_mem_noc =3D { .name =3D "qns2_mem_noc", - .id =3D SDM845_SLAVE_MNOC_SF_MEM_NOC, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SDM845_MASTER_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qnm_mnoc_sf }, }; =20 static struct qcom_icc_node qns_mem_noc_hf =3D { .name =3D "qns_mem_noc_hf", - .id =3D SDM845_SLAVE_MNOC_HF_MEM_NOC, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SDM845_MASTER_MNOC_HF_MEM_NOC }, + .link_nodes =3D { &qnm_mnoc_hf }, }; =20 static struct qcom_icc_node srvc_mnoc =3D { .name =3D "srvc_mnoc", - .id =3D SDM845_SLAVE_SERVICE_MNOC, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_apss =3D { .name =3D "qhs_apss", - .id =3D SDM845_SLAVE_APPSS, .channels =3D 1, .buswidth =3D 8, }; =20 static struct qcom_icc_node qns_cnoc =3D { .name =3D "qns_cnoc", - .id =3D SDM845_SLAVE_SNOC_CNOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SDM845_MASTER_SNOC_CNOC }, + .link_nodes =3D { &qnm_snoc }, }; =20 static struct qcom_icc_node qns_memnoc_gc =3D { .name =3D "qns_memnoc_gc", - .id =3D SDM845_SLAVE_SNOC_MEM_NOC_GC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SDM845_MASTER_SNOC_GC_MEM_NOC }, + .link_nodes =3D { &qnm_snoc_gc }, }; =20 static struct qcom_icc_node qns_memnoc_sf =3D { .name =3D "qns_memnoc_sf", - .id =3D SDM845_SLAVE_SNOC_MEM_NOC_SF, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SDM845_MASTER_SNOC_SF_MEM_NOC }, + .link_nodes =3D { &qnm_snoc_sf }, }; =20 static struct qcom_icc_node qxs_imem =3D { .name =3D "qxs_imem", - .id =3D SDM845_SLAVE_IMEM, .channels =3D 1, .buswidth =3D 8, }; =20 static struct qcom_icc_node qxs_pcie =3D { .name =3D "qxs_pcie", - .id =3D SDM845_SLAVE_PCIE_0, .channels =3D 1, .buswidth =3D 8, }; =20 static struct qcom_icc_node qxs_pcie_gen3 =3D { .name =3D "qxs_pcie_gen3", - .id =3D SDM845_SLAVE_PCIE_1, .channels =3D 1, .buswidth =3D 8, }; =20 static struct qcom_icc_node qxs_pimem =3D { .name =3D "qxs_pimem", - .id =3D SDM845_SLAVE_PIMEM, .channels =3D 1, .buswidth =3D 8, }; =20 static struct qcom_icc_node srvc_snoc =3D { .name =3D "srvc_snoc", - .id =3D SDM845_SLAVE_SERVICE_SNOC, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node xs_qdss_stm =3D { .name =3D "xs_qdss_stm", - .id =3D SDM845_SLAVE_QDSS_STM, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node xs_sys_tcu_cfg =3D { .name =3D "xs_sys_tcu_cfg", - .id =3D SDM845_SLAVE_TCU, .channels =3D 1, .buswidth =3D 8, }; @@ -1534,6 +1514,7 @@ static struct qcom_icc_node * const aggre1_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sdm845_aggre1_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D aggre1_noc_nodes, .num_nodes =3D ARRAY_SIZE(aggre1_noc_nodes), .bcms =3D aggre1_noc_bcms, @@ -1563,6 +1544,7 @@ static struct qcom_icc_node * const aggre2_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sdm845_aggre2_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D aggre2_noc_nodes, .num_nodes =3D ARRAY_SIZE(aggre2_noc_nodes), .bcms =3D aggre2_noc_bcms, @@ -1624,6 +1606,7 @@ static struct qcom_icc_node * const config_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sdm845_config_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D config_noc_nodes, .num_nodes =3D ARRAY_SIZE(config_noc_nodes), .bcms =3D config_noc_bcms, @@ -1640,6 +1623,7 @@ static struct qcom_icc_node * const dc_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sdm845_dc_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D dc_noc_nodes, .num_nodes =3D ARRAY_SIZE(dc_noc_nodes), .bcms =3D dc_noc_bcms, @@ -1658,6 +1642,7 @@ static struct qcom_icc_node * const gladiator_noc_nod= es[] =3D { }; =20 static const struct qcom_icc_desc sdm845_gladiator_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D gladiator_noc_nodes, .num_nodes =3D ARRAY_SIZE(gladiator_noc_nodes), .bcms =3D gladiator_noc_bcms, @@ -1693,6 +1678,7 @@ static struct qcom_icc_node * const mem_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sdm845_mem_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D mem_noc_nodes, .num_nodes =3D ARRAY_SIZE(mem_noc_nodes), .bcms =3D mem_noc_bcms, @@ -1727,6 +1713,7 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sdm845_mmss_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D mmss_noc_nodes, .num_nodes =3D ARRAY_SIZE(mmss_noc_nodes), .bcms =3D mmss_noc_bcms, @@ -1773,6 +1760,7 @@ static struct qcom_icc_node * const system_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sdm845_system_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D system_noc_nodes, .num_nodes =3D ARRAY_SIZE(system_noc_nodes), .bcms =3D system_noc_bcms, diff --git a/drivers/interconnect/qcom/sdm845.h b/drivers/interconnect/qcom= /sdm845.h deleted file mode 100644 index bc7e425ce9852288da16c49345e77f6374267365..000000000000000000000000000= 0000000000000 --- a/drivers/interconnect/qcom/sdm845.h +++ /dev/null @@ -1,140 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2020, The Linux Foundation. All rights reserved. - */ - -#ifndef __DRIVERS_INTERCONNECT_QCOM_SDM845_H__ -#define __DRIVERS_INTERCONNECT_QCOM_SDM845_H__ - -#define SDM845_MASTER_A1NOC_CFG 1 -#define SDM845_MASTER_BLSP_1 2 -#define SDM845_MASTER_TSIF 3 -#define SDM845_MASTER_SDCC_2 4 -#define SDM845_MASTER_SDCC_4 5 -#define SDM845_MASTER_UFS_CARD 6 -#define SDM845_MASTER_UFS_MEM 7 -#define SDM845_MASTER_PCIE_0 8 -#define SDM845_MASTER_A2NOC_CFG 9 -#define SDM845_MASTER_QDSS_BAM 10 -#define SDM845_MASTER_BLSP_2 11 -#define SDM845_MASTER_CNOC_A2NOC 12 -#define SDM845_MASTER_CRYPTO 13 -#define SDM845_MASTER_IPA 14 -#define SDM845_MASTER_PCIE_1 15 -#define SDM845_MASTER_QDSS_ETR 16 -#define SDM845_MASTER_USB3_0 17 -#define SDM845_MASTER_USB3_1 18 -#define SDM845_MASTER_CAMNOC_HF0_UNCOMP 19 -#define SDM845_MASTER_CAMNOC_HF1_UNCOMP 20 -#define SDM845_MASTER_CAMNOC_SF_UNCOMP 21 -#define SDM845_MASTER_SPDM 22 -#define SDM845_MASTER_TIC 23 -#define SDM845_MASTER_SNOC_CNOC 24 -#define SDM845_MASTER_QDSS_DAP 25 -#define SDM845_MASTER_CNOC_DC_NOC 26 -#define SDM845_MASTER_APPSS_PROC 27 -#define SDM845_MASTER_GNOC_CFG 28 -#define SDM845_MASTER_LLCC 29 -#define SDM845_MASTER_TCU_0 30 -#define SDM845_MASTER_MEM_NOC_CFG 31 -#define SDM845_MASTER_GNOC_MEM_NOC 32 -#define SDM845_MASTER_MNOC_HF_MEM_NOC 33 -#define SDM845_MASTER_MNOC_SF_MEM_NOC 34 -#define SDM845_MASTER_SNOC_GC_MEM_NOC 35 -#define SDM845_MASTER_SNOC_SF_MEM_NOC 36 -#define SDM845_MASTER_GFX3D 37 -#define SDM845_MASTER_CNOC_MNOC_CFG 38 -#define SDM845_MASTER_CAMNOC_HF0 39 -#define SDM845_MASTER_CAMNOC_HF1 40 -#define SDM845_MASTER_CAMNOC_SF 41 -#define SDM845_MASTER_MDP0 42 -#define SDM845_MASTER_MDP1 43 -#define SDM845_MASTER_ROTATOR 44 -#define SDM845_MASTER_VIDEO_P0 45 -#define SDM845_MASTER_VIDEO_P1 46 -#define SDM845_MASTER_VIDEO_PROC 47 -#define SDM845_MASTER_SNOC_CFG 48 -#define SDM845_MASTER_A1NOC_SNOC 49 -#define SDM845_MASTER_A2NOC_SNOC 50 -#define SDM845_MASTER_GNOC_SNOC 51 -#define SDM845_MASTER_MEM_NOC_SNOC 52 -#define SDM845_MASTER_ANOC_PCIE_SNOC 53 -#define SDM845_MASTER_PIMEM 54 -#define SDM845_MASTER_GIC 55 -#define SDM845_SLAVE_A1NOC_SNOC 56 -#define SDM845_SLAVE_SERVICE_A1NOC 57 -#define SDM845_SLAVE_ANOC_PCIE_A1NOC_SNOC 58 -#define SDM845_SLAVE_A2NOC_SNOC 59 -#define SDM845_SLAVE_ANOC_PCIE_SNOC 60 -#define SDM845_SLAVE_SERVICE_A2NOC 61 -#define SDM845_SLAVE_CAMNOC_UNCOMP 62 -#define SDM845_SLAVE_A1NOC_CFG 63 -#define SDM845_SLAVE_A2NOC_CFG 64 -#define SDM845_SLAVE_AOP 65 -#define SDM845_SLAVE_AOSS 66 -#define SDM845_SLAVE_CAMERA_CFG 67 -#define SDM845_SLAVE_CLK_CTL 68 -#define SDM845_SLAVE_CDSP_CFG 69 -#define SDM845_SLAVE_RBCPR_CX_CFG 70 -#define SDM845_SLAVE_CRYPTO_0_CFG 71 -#define SDM845_SLAVE_DCC_CFG 72 -#define SDM845_SLAVE_CNOC_DDRSS 73 -#define SDM845_SLAVE_DISPLAY_CFG 74 -#define SDM845_SLAVE_GLM 75 -#define SDM845_SLAVE_GFX3D_CFG 76 -#define SDM845_SLAVE_IMEM_CFG 77 -#define SDM845_SLAVE_IPA_CFG 78 -#define SDM845_SLAVE_CNOC_MNOC_CFG 79 -#define SDM845_SLAVE_PCIE_0_CFG 80 -#define SDM845_SLAVE_PCIE_1_CFG 81 -#define SDM845_SLAVE_PDM 82 -#define SDM845_SLAVE_SOUTH_PHY_CFG 83 -#define SDM845_SLAVE_PIMEM_CFG 84 -#define SDM845_SLAVE_PRNG 85 -#define SDM845_SLAVE_QDSS_CFG 86 -#define SDM845_SLAVE_BLSP_2 87 -#define SDM845_SLAVE_BLSP_1 88 -#define SDM845_SLAVE_SDCC_2 89 -#define SDM845_SLAVE_SDCC_4 90 -#define SDM845_SLAVE_SNOC_CFG 91 -#define SDM845_SLAVE_SPDM_WRAPPER 92 -#define SDM845_SLAVE_SPSS_CFG 93 -#define SDM845_SLAVE_TCSR 94 -#define SDM845_SLAVE_TLMM_NORTH 95 -#define SDM845_SLAVE_TLMM_SOUTH 96 -#define SDM845_SLAVE_TSIF 97 -#define SDM845_SLAVE_UFS_CARD_CFG 98 -#define SDM845_SLAVE_UFS_MEM_CFG 99 -#define SDM845_SLAVE_USB3_0 100 -#define SDM845_SLAVE_USB3_1 101 -#define SDM845_SLAVE_VENUS_CFG 102 -#define SDM845_SLAVE_VSENSE_CTRL_CFG 103 -#define SDM845_SLAVE_CNOC_A2NOC 104 -#define SDM845_SLAVE_SERVICE_CNOC 105 -#define SDM845_SLAVE_LLCC_CFG 106 -#define SDM845_SLAVE_MEM_NOC_CFG 107 -#define SDM845_SLAVE_GNOC_SNOC 108 -#define SDM845_SLAVE_GNOC_MEM_NOC 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This gives more flexibility and also allows us to drop the .num_links member, saving from possible errors related to it being not set or set incorrectly. Signed-off-by: Dmitry Baryshkov --- drivers/interconnect/qcom/sm8250.c | 736 ++++++++++++++++++---------------= ---- drivers/interconnect/qcom/sm8250.h | 168 --------- 2 files changed, 361 insertions(+), 543 deletions(-) diff --git a/drivers/interconnect/qcom/sm8250.c b/drivers/interconnect/qcom= /sm8250.c index cc1b14c1352910fd450c334fa90f2a0b390bb9bc..2ed112eab155e1f9be1a4b5336b= 998639d0e298b 100644 --- a/drivers/interconnect/qcom/sm8250.c +++ b/drivers/interconnect/qcom/sm8250.c @@ -14,1383 +14,1369 @@ =20 #include "bcm-voter.h" #include "icc-rpmh.h" -#include "sm8250.h" + +static struct qcom_icc_node qhm_a1noc_cfg; +static struct qcom_icc_node qhm_qspi; +static struct qcom_icc_node qhm_qup1; +static struct qcom_icc_node qhm_qup2; +static struct qcom_icc_node qhm_tsif; +static struct qcom_icc_node xm_pcie3_modem; +static struct qcom_icc_node xm_sdc4; +static struct qcom_icc_node xm_ufs_mem; +static struct qcom_icc_node xm_usb3_0; +static struct qcom_icc_node xm_usb3_1; +static struct qcom_icc_node qhm_a2noc_cfg; +static struct qcom_icc_node qhm_qdss_bam; +static struct qcom_icc_node qhm_qup0; +static struct qcom_icc_node qnm_cnoc; +static struct qcom_icc_node qxm_crypto; +static struct qcom_icc_node qxm_ipa; +static struct qcom_icc_node xm_pcie3_0; +static struct qcom_icc_node xm_pcie3_1; +static struct qcom_icc_node xm_qdss_etr; +static struct qcom_icc_node xm_sdc2; +static struct qcom_icc_node xm_ufs_card; +static struct qcom_icc_node qnm_npu; +static struct qcom_icc_node qnm_snoc; +static struct qcom_icc_node xm_qdss_dap; +static struct qcom_icc_node qhm_cnoc_dc_noc; +static struct qcom_icc_node alm_gpu_tcu; +static struct qcom_icc_node alm_sys_tcu; +static struct qcom_icc_node chm_apps; +static struct qcom_icc_node qhm_gemnoc_cfg; +static struct qcom_icc_node qnm_cmpnoc; +static struct qcom_icc_node qnm_gpu; +static struct qcom_icc_node qnm_mnoc_hf; +static struct qcom_icc_node qnm_mnoc_sf; +static struct qcom_icc_node qnm_pcie; +static struct qcom_icc_node qnm_snoc_gc; +static struct qcom_icc_node qnm_snoc_sf; +static struct qcom_icc_node llcc_mc; +static struct qcom_icc_node qhm_mnoc_cfg; +static struct qcom_icc_node qnm_camnoc_hf; +static struct qcom_icc_node qnm_camnoc_icp; +static struct qcom_icc_node qnm_camnoc_sf; +static struct qcom_icc_node qnm_video0; +static struct qcom_icc_node qnm_video1; +static struct qcom_icc_node qnm_video_cvp; +static struct qcom_icc_node qxm_mdp0; +static struct qcom_icc_node qxm_mdp1; +static struct qcom_icc_node qxm_rot; +static struct qcom_icc_node amm_npu_sys; +static struct qcom_icc_node amm_npu_sys_cdp_w; +static struct qcom_icc_node qhm_cfg; +static struct qcom_icc_node qhm_snoc_cfg; +static struct qcom_icc_node qnm_aggre1_noc; +static struct qcom_icc_node qnm_aggre2_noc; +static struct qcom_icc_node qnm_gemnoc; +static struct qcom_icc_node qnm_gemnoc_pcie; +static struct qcom_icc_node qxm_pimem; +static struct qcom_icc_node xm_gic; +static struct qcom_icc_node qns_a1noc_snoc; +static struct qcom_icc_node qns_pcie_modem_mem_noc; +static struct qcom_icc_node srvc_aggre1_noc; +static struct qcom_icc_node qns_a2noc_snoc; +static struct qcom_icc_node qns_pcie_mem_noc; +static struct qcom_icc_node srvc_aggre2_noc; +static struct qcom_icc_node qns_cdsp_mem_noc; +static struct qcom_icc_node qhs_a1_noc_cfg; +static struct qcom_icc_node qhs_a2_noc_cfg; +static struct qcom_icc_node qhs_ahb2phy0; +static struct qcom_icc_node qhs_ahb2phy1; +static struct qcom_icc_node qhs_aoss; +static struct qcom_icc_node qhs_camera_cfg; +static struct qcom_icc_node qhs_clk_ctl; +static struct qcom_icc_node qhs_compute_dsp; +static struct qcom_icc_node qhs_cpr_cx; +static struct qcom_icc_node qhs_cpr_mmcx; +static struct qcom_icc_node qhs_cpr_mx; +static struct qcom_icc_node qhs_crypto0_cfg; +static struct qcom_icc_node qhs_cx_rdpm; +static struct qcom_icc_node qhs_dcc_cfg; +static struct qcom_icc_node qhs_ddrss_cfg; +static struct qcom_icc_node qhs_display_cfg; +static struct qcom_icc_node qhs_gpuss_cfg; +static struct qcom_icc_node qhs_imem_cfg; +static struct qcom_icc_node qhs_ipa; +static struct qcom_icc_node qhs_ipc_router; +static struct qcom_icc_node qhs_lpass_cfg; +static struct qcom_icc_node qhs_mnoc_cfg; +static struct qcom_icc_node qhs_npu_cfg; +static struct qcom_icc_node qhs_pcie0_cfg; +static struct qcom_icc_node qhs_pcie1_cfg; +static struct qcom_icc_node qhs_pcie_modem_cfg; +static struct qcom_icc_node qhs_pdm; +static struct qcom_icc_node qhs_pimem_cfg; +static struct qcom_icc_node qhs_prng; +static struct qcom_icc_node qhs_qdss_cfg; +static struct qcom_icc_node qhs_qspi; +static struct qcom_icc_node qhs_qup0; +static struct qcom_icc_node qhs_qup1; +static struct qcom_icc_node qhs_qup2; +static struct qcom_icc_node qhs_sdc2; +static struct qcom_icc_node qhs_sdc4; +static struct qcom_icc_node qhs_snoc_cfg; +static struct qcom_icc_node qhs_tcsr; +static struct qcom_icc_node qhs_tlmm0; +static struct qcom_icc_node qhs_tlmm1; +static struct qcom_icc_node qhs_tlmm2; +static struct qcom_icc_node qhs_tsif; +static struct qcom_icc_node qhs_ufs_card_cfg; +static struct qcom_icc_node qhs_ufs_mem_cfg; +static struct qcom_icc_node qhs_usb3_0; +static struct qcom_icc_node qhs_usb3_1; +static struct qcom_icc_node qhs_venus_cfg; +static struct qcom_icc_node qhs_vsense_ctrl_cfg; +static struct qcom_icc_node qns_cnoc_a2noc; +static struct qcom_icc_node srvc_cnoc; +static struct qcom_icc_node qhs_llcc; +static struct qcom_icc_node qhs_memnoc; +static struct qcom_icc_node qns_gem_noc_snoc; +static struct qcom_icc_node qns_llcc; +static struct qcom_icc_node qns_sys_pcie; +static struct qcom_icc_node srvc_even_gemnoc; +static struct qcom_icc_node srvc_odd_gemnoc; +static struct qcom_icc_node srvc_sys_gemnoc; +static struct qcom_icc_node ebi; +static struct qcom_icc_node qns_mem_noc_hf; +static struct qcom_icc_node qns_mem_noc_sf; +static struct qcom_icc_node srvc_mnoc; +static struct qcom_icc_node qhs_cal_dp0; +static struct qcom_icc_node qhs_cal_dp1; +static struct qcom_icc_node qhs_cp; +static struct qcom_icc_node qhs_dma_bwmon; +static struct qcom_icc_node qhs_dpm; +static struct qcom_icc_node qhs_isense; +static struct qcom_icc_node qhs_llm; +static struct qcom_icc_node qhs_tcm; +static struct qcom_icc_node qns_npu_sys; +static struct qcom_icc_node srvc_noc; +static struct qcom_icc_node qhs_apss; +static struct qcom_icc_node qns_cnoc; +static struct qcom_icc_node qns_gemnoc_gc; +static struct qcom_icc_node qns_gemnoc_sf; +static struct qcom_icc_node qxs_imem; +static struct qcom_icc_node qxs_pimem; +static struct qcom_icc_node srvc_snoc; +static struct qcom_icc_node xs_pcie_0; +static struct qcom_icc_node xs_pcie_1; +static struct qcom_icc_node xs_pcie_modem; +static struct qcom_icc_node xs_qdss_stm; +static struct qcom_icc_node xs_sys_tcu_cfg; +static struct qcom_icc_node qup0_core_master; +static struct qcom_icc_node qup1_core_master; +static struct qcom_icc_node qup2_core_master; +static struct qcom_icc_node qup0_core_slave; +static struct qcom_icc_node qup1_core_slave; +static struct qcom_icc_node qup2_core_slave; =20 static struct qcom_icc_node qhm_a1noc_cfg =3D { .name =3D "qhm_a1noc_cfg", - .id =3D SM8250_MASTER_A1NOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8250_SLAVE_SERVICE_A1NOC }, + .link_nodes =3D { &srvc_aggre1_noc }, }; =20 static struct qcom_icc_node qhm_qspi =3D { .name =3D "qhm_qspi", - .id =3D SM8250_MASTER_QSPI_0, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8250_A1NOC_SNOC_SLV }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node qhm_qup1 =3D { .name =3D "qhm_qup1", - .id =3D SM8250_MASTER_QUP_1, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8250_A1NOC_SNOC_SLV }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node qhm_qup2 =3D { .name =3D "qhm_qup2", - .id =3D SM8250_MASTER_QUP_2, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8250_A1NOC_SNOC_SLV }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node qhm_tsif =3D { .name =3D "qhm_tsif", - .id =3D SM8250_MASTER_TSIF, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8250_A1NOC_SNOC_SLV }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node xm_pcie3_modem =3D { .name =3D "xm_pcie3_modem", - .id =3D SM8250_MASTER_PCIE_2, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8250_SLAVE_ANOC_PCIE_GEM_NOC_1 }, + .link_nodes =3D { &qns_pcie_modem_mem_noc }, }; =20 static struct qcom_icc_node xm_sdc4 =3D { .name =3D "xm_sdc4", - .id =3D SM8250_MASTER_SDCC_4, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8250_A1NOC_SNOC_SLV }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node xm_ufs_mem =3D { .name =3D "xm_ufs_mem", - .id =3D SM8250_MASTER_UFS_MEM, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8250_A1NOC_SNOC_SLV }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node xm_usb3_0 =3D { .name =3D "xm_usb3_0", - .id =3D SM8250_MASTER_USB3, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8250_A1NOC_SNOC_SLV }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node xm_usb3_1 =3D { .name =3D "xm_usb3_1", - .id =3D SM8250_MASTER_USB3_1, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8250_A1NOC_SNOC_SLV }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node qhm_a2noc_cfg =3D { .name =3D "qhm_a2noc_cfg", - .id =3D SM8250_MASTER_A2NOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8250_SLAVE_SERVICE_A2NOC }, + .link_nodes =3D { &srvc_aggre2_noc }, }; =20 static struct qcom_icc_node qhm_qdss_bam =3D { .name =3D "qhm_qdss_bam", - .id =3D SM8250_MASTER_QDSS_BAM, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8250_A2NOC_SNOC_SLV }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qhm_qup0 =3D { .name =3D "qhm_qup0", - .id =3D SM8250_MASTER_QUP_0, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8250_A2NOC_SNOC_SLV }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qnm_cnoc =3D { .name =3D "qnm_cnoc", - .id =3D SM8250_MASTER_CNOC_A2NOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8250_A2NOC_SNOC_SLV }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qxm_crypto =3D { .name =3D "qxm_crypto", - .id =3D SM8250_MASTER_CRYPTO_CORE_0, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8250_A2NOC_SNOC_SLV }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qxm_ipa =3D { .name =3D "qxm_ipa", - .id =3D SM8250_MASTER_IPA, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8250_A2NOC_SNOC_SLV }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node xm_pcie3_0 =3D { .name =3D "xm_pcie3_0", - .id =3D SM8250_MASTER_PCIE, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8250_SLAVE_ANOC_PCIE_GEM_NOC }, + .link_nodes =3D { &qns_pcie_mem_noc }, }; =20 static struct qcom_icc_node xm_pcie3_1 =3D { .name =3D "xm_pcie3_1", - .id =3D SM8250_MASTER_PCIE_1, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8250_SLAVE_ANOC_PCIE_GEM_NOC }, + .link_nodes =3D { &qns_pcie_mem_noc }, }; =20 static struct qcom_icc_node xm_qdss_etr =3D { .name =3D "xm_qdss_etr", - .id =3D SM8250_MASTER_QDSS_ETR, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8250_A2NOC_SNOC_SLV }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node xm_sdc2 =3D { .name =3D "xm_sdc2", - .id =3D SM8250_MASTER_SDCC_2, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8250_A2NOC_SNOC_SLV }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node xm_ufs_card =3D { .name =3D "xm_ufs_card", - .id =3D SM8250_MASTER_UFS_CARD, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8250_A2NOC_SNOC_SLV }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qnm_npu =3D { .name =3D "qnm_npu", - .id =3D SM8250_MASTER_NPU, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8250_SLAVE_CDSP_MEM_NOC }, + .link_nodes =3D { &qns_cdsp_mem_noc }, }; =20 static struct qcom_icc_node qnm_snoc =3D { .name =3D "qnm_snoc", - .id =3D SM8250_SNOC_CNOC_MAS, .channels =3D 1, .buswidth =3D 8, .num_links =3D 49, - .links =3D { SM8250_SLAVE_CDSP_CFG, - SM8250_SLAVE_CAMERA_CFG, - SM8250_SLAVE_TLMM_SOUTH, - SM8250_SLAVE_TLMM_NORTH, - SM8250_SLAVE_SDCC_4, - SM8250_SLAVE_TLMM_WEST, - SM8250_SLAVE_SDCC_2, - SM8250_SLAVE_CNOC_MNOC_CFG, - SM8250_SLAVE_UFS_MEM_CFG, - SM8250_SLAVE_SNOC_CFG, - SM8250_SLAVE_PDM, - SM8250_SLAVE_CX_RDPM, - SM8250_SLAVE_PCIE_1_CFG, - SM8250_SLAVE_A2NOC_CFG, - SM8250_SLAVE_QDSS_CFG, - SM8250_SLAVE_DISPLAY_CFG, - SM8250_SLAVE_PCIE_2_CFG, - SM8250_SLAVE_TCSR, - SM8250_SLAVE_DCC_CFG, - SM8250_SLAVE_CNOC_DDRSS, - SM8250_SLAVE_IPC_ROUTER_CFG, - SM8250_SLAVE_PCIE_0_CFG, - SM8250_SLAVE_RBCPR_MMCX_CFG, - SM8250_SLAVE_NPU_CFG, - SM8250_SLAVE_AHB2PHY_SOUTH, - SM8250_SLAVE_AHB2PHY_NORTH, - SM8250_SLAVE_GRAPHICS_3D_CFG, - SM8250_SLAVE_VENUS_CFG, - SM8250_SLAVE_TSIF, - SM8250_SLAVE_IPA_CFG, - SM8250_SLAVE_IMEM_CFG, - SM8250_SLAVE_USB3, - SM8250_SLAVE_SERVICE_CNOC, - SM8250_SLAVE_UFS_CARD_CFG, - SM8250_SLAVE_USB3_1, - SM8250_SLAVE_LPASS, - SM8250_SLAVE_RBCPR_CX_CFG, - SM8250_SLAVE_A1NOC_CFG, - SM8250_SLAVE_AOSS, - SM8250_SLAVE_PRNG, - SM8250_SLAVE_VSENSE_CTRL_CFG, - SM8250_SLAVE_QSPI_0, - SM8250_SLAVE_CRYPTO_0_CFG, - SM8250_SLAVE_PIMEM_CFG, - SM8250_SLAVE_RBCPR_MX_CFG, - SM8250_SLAVE_QUP_0, - SM8250_SLAVE_QUP_1, - SM8250_SLAVE_QUP_2, - SM8250_SLAVE_CLK_CTL - }, + .link_nodes =3D { &qhs_compute_dsp, + &qhs_camera_cfg, + &qhs_tlmm1, + &qhs_tlmm0, + &qhs_sdc4, + &qhs_tlmm2, + &qhs_sdc2, + &qhs_mnoc_cfg, + &qhs_ufs_mem_cfg, + &qhs_snoc_cfg, + &qhs_pdm, + &qhs_cx_rdpm, + &qhs_pcie1_cfg, + &qhs_a2_noc_cfg, + &qhs_qdss_cfg, + &qhs_display_cfg, + &qhs_pcie_modem_cfg, + &qhs_tcsr, + &qhs_dcc_cfg, + &qhs_ddrss_cfg, + &qhs_ipc_router, + &qhs_pcie0_cfg, + &qhs_cpr_mmcx, + &qhs_npu_cfg, + &qhs_ahb2phy0, + &qhs_ahb2phy1, + &qhs_gpuss_cfg, + &qhs_venus_cfg, + &qhs_tsif, + &qhs_ipa, + &qhs_imem_cfg, + &qhs_usb3_0, + &srvc_cnoc, + &qhs_ufs_card_cfg, + &qhs_usb3_1, + &qhs_lpass_cfg, + &qhs_cpr_cx, + &qhs_a1_noc_cfg, + &qhs_aoss, + &qhs_prng, + &qhs_vsense_ctrl_cfg, + &qhs_qspi, + &qhs_crypto0_cfg, + &qhs_pimem_cfg, + &qhs_cpr_mx, + &qhs_qup0, + &qhs_qup1, + &qhs_qup2, + &qhs_clk_ctl }, }; =20 static struct qcom_icc_node xm_qdss_dap =3D { .name =3D "xm_qdss_dap", - .id =3D SM8250_MASTER_QDSS_DAP, .channels =3D 1, .buswidth =3D 8, .num_links =3D 50, - .links =3D { SM8250_SLAVE_CDSP_CFG, - SM8250_SLAVE_CAMERA_CFG, - SM8250_SLAVE_TLMM_SOUTH, - SM8250_SLAVE_TLMM_NORTH, - SM8250_SLAVE_SDCC_4, - SM8250_SLAVE_TLMM_WEST, - SM8250_SLAVE_SDCC_2, - SM8250_SLAVE_CNOC_MNOC_CFG, - SM8250_SLAVE_UFS_MEM_CFG, - SM8250_SLAVE_SNOC_CFG, - SM8250_SLAVE_PDM, - SM8250_SLAVE_CX_RDPM, - SM8250_SLAVE_PCIE_1_CFG, - SM8250_SLAVE_A2NOC_CFG, - SM8250_SLAVE_QDSS_CFG, - SM8250_SLAVE_DISPLAY_CFG, - SM8250_SLAVE_PCIE_2_CFG, - SM8250_SLAVE_TCSR, - SM8250_SLAVE_DCC_CFG, - SM8250_SLAVE_CNOC_DDRSS, - SM8250_SLAVE_IPC_ROUTER_CFG, - SM8250_SLAVE_CNOC_A2NOC, - SM8250_SLAVE_PCIE_0_CFG, - SM8250_SLAVE_RBCPR_MMCX_CFG, - SM8250_SLAVE_NPU_CFG, - SM8250_SLAVE_AHB2PHY_SOUTH, - SM8250_SLAVE_AHB2PHY_NORTH, - SM8250_SLAVE_GRAPHICS_3D_CFG, - SM8250_SLAVE_VENUS_CFG, - SM8250_SLAVE_TSIF, - SM8250_SLAVE_IPA_CFG, - SM8250_SLAVE_IMEM_CFG, - SM8250_SLAVE_USB3, - SM8250_SLAVE_SERVICE_CNOC, - SM8250_SLAVE_UFS_CARD_CFG, - SM8250_SLAVE_USB3_1, - SM8250_SLAVE_LPASS, - SM8250_SLAVE_RBCPR_CX_CFG, - SM8250_SLAVE_A1NOC_CFG, - SM8250_SLAVE_AOSS, - SM8250_SLAVE_PRNG, - SM8250_SLAVE_VSENSE_CTRL_CFG, - SM8250_SLAVE_QSPI_0, - SM8250_SLAVE_CRYPTO_0_CFG, - SM8250_SLAVE_PIMEM_CFG, - SM8250_SLAVE_RBCPR_MX_CFG, - SM8250_SLAVE_QUP_0, - SM8250_SLAVE_QUP_1, - SM8250_SLAVE_QUP_2, - SM8250_SLAVE_CLK_CTL - }, + .link_nodes =3D { &qhs_compute_dsp, + &qhs_camera_cfg, + &qhs_tlmm1, + &qhs_tlmm0, + &qhs_sdc4, + &qhs_tlmm2, + &qhs_sdc2, + &qhs_mnoc_cfg, + &qhs_ufs_mem_cfg, + &qhs_snoc_cfg, + &qhs_pdm, + &qhs_cx_rdpm, + &qhs_pcie1_cfg, + &qhs_a2_noc_cfg, + &qhs_qdss_cfg, + &qhs_display_cfg, + &qhs_pcie_modem_cfg, + &qhs_tcsr, + &qhs_dcc_cfg, + &qhs_ddrss_cfg, + &qhs_ipc_router, + &qns_cnoc_a2noc, + &qhs_pcie0_cfg, + &qhs_cpr_mmcx, + &qhs_npu_cfg, + &qhs_ahb2phy0, + &qhs_ahb2phy1, + &qhs_gpuss_cfg, + &qhs_venus_cfg, + &qhs_tsif, + &qhs_ipa, + &qhs_imem_cfg, + &qhs_usb3_0, + &srvc_cnoc, + &qhs_ufs_card_cfg, + &qhs_usb3_1, + &qhs_lpass_cfg, + &qhs_cpr_cx, + &qhs_a1_noc_cfg, + &qhs_aoss, + &qhs_prng, + &qhs_vsense_ctrl_cfg, + &qhs_qspi, + &qhs_crypto0_cfg, + &qhs_pimem_cfg, + &qhs_cpr_mx, + &qhs_qup0, + &qhs_qup1, + &qhs_qup2, + &qhs_clk_ctl }, }; =20 static struct qcom_icc_node qhm_cnoc_dc_noc =3D { .name =3D "qhm_cnoc_dc_noc", - .id =3D SM8250_MASTER_CNOC_DC_NOC, .channels =3D 1, .buswidth =3D 4, .num_links =3D 2, - .links =3D { SM8250_SLAVE_GEM_NOC_CFG, - SM8250_SLAVE_LLCC_CFG - }, + .link_nodes =3D { &qhs_memnoc, + &qhs_llcc }, }; =20 static struct qcom_icc_node alm_gpu_tcu =3D { .name =3D "alm_gpu_tcu", - .id =3D SM8250_MASTER_GPU_TCU, .channels =3D 1, .buswidth =3D 8, .num_links =3D 2, - .links =3D { SM8250_SLAVE_LLCC, - SM8250_SLAVE_GEM_NOC_SNOC - }, + .link_nodes =3D { &qns_llcc, + &qns_gem_noc_snoc }, }; =20 static struct qcom_icc_node alm_sys_tcu =3D { .name =3D "alm_sys_tcu", - .id =3D SM8250_MASTER_SYS_TCU, .channels =3D 1, .buswidth =3D 8, .num_links =3D 2, - .links =3D { SM8250_SLAVE_LLCC, - SM8250_SLAVE_GEM_NOC_SNOC - }, + .link_nodes =3D { &qns_llcc, + &qns_gem_noc_snoc }, }; =20 static struct qcom_icc_node chm_apps =3D { .name =3D "chm_apps", - .id =3D SM8250_MASTER_AMPSS_M0, .channels =3D 2, .buswidth =3D 32, .num_links =3D 3, - .links =3D { SM8250_SLAVE_LLCC, - SM8250_SLAVE_GEM_NOC_SNOC, - SM8250_SLAVE_MEM_NOC_PCIE_SNOC - }, + .link_nodes =3D { &qns_llcc, + &qns_gem_noc_snoc, + &qns_sys_pcie }, }; =20 static struct qcom_icc_node qhm_gemnoc_cfg =3D { .name =3D "qhm_gemnoc_cfg", - .id =3D SM8250_MASTER_GEM_NOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 3, - .links =3D { SM8250_SLAVE_SERVICE_GEM_NOC_2, - SM8250_SLAVE_SERVICE_GEM_NOC_1, - SM8250_SLAVE_SERVICE_GEM_NOC - }, + .link_nodes =3D { &srvc_odd_gemnoc, + &srvc_even_gemnoc, + &srvc_sys_gemnoc }, }; =20 static struct qcom_icc_node qnm_cmpnoc =3D { .name =3D "qnm_cmpnoc", - .id =3D SM8250_MASTER_COMPUTE_NOC, .channels =3D 2, .buswidth =3D 32, .num_links =3D 2, - .links =3D { SM8250_SLAVE_LLCC, - SM8250_SLAVE_GEM_NOC_SNOC - }, + .link_nodes =3D { &qns_llcc, + &qns_gem_noc_snoc }, }; =20 static struct qcom_icc_node qnm_gpu =3D { .name =3D "qnm_gpu", - .id =3D SM8250_MASTER_GRAPHICS_3D, .channels =3D 2, .buswidth =3D 32, .num_links =3D 2, - .links =3D { SM8250_SLAVE_LLCC, - SM8250_SLAVE_GEM_NOC_SNOC }, + .link_nodes =3D { &qns_llcc, + &qns_gem_noc_snoc }, }; =20 static struct qcom_icc_node qnm_mnoc_hf =3D { .name =3D "qnm_mnoc_hf", - .id =3D SM8250_MASTER_MNOC_HF_MEM_NOC, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8250_SLAVE_LLCC }, + .link_nodes =3D { &qns_llcc }, }; =20 static struct qcom_icc_node qnm_mnoc_sf =3D { .name =3D "qnm_mnoc_sf", - .id =3D SM8250_MASTER_MNOC_SF_MEM_NOC, .channels =3D 2, .buswidth =3D 32, .num_links =3D 2, - .links =3D { SM8250_SLAVE_LLCC, - SM8250_SLAVE_GEM_NOC_SNOC - }, + .link_nodes =3D { &qns_llcc, + &qns_gem_noc_snoc }, }; =20 static struct qcom_icc_node qnm_pcie =3D { .name =3D "qnm_pcie", - .id =3D SM8250_MASTER_ANOC_PCIE_GEM_NOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 2, - .links =3D { SM8250_SLAVE_LLCC, - SM8250_SLAVE_GEM_NOC_SNOC - }, + .link_nodes =3D { &qns_llcc, + &qns_gem_noc_snoc }, }; =20 static struct qcom_icc_node qnm_snoc_gc =3D { .name =3D "qnm_snoc_gc", - .id =3D SM8250_MASTER_SNOC_GC_MEM_NOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8250_SLAVE_LLCC }, + .link_nodes =3D { &qns_llcc }, }; =20 static struct qcom_icc_node qnm_snoc_sf =3D { .name =3D "qnm_snoc_sf", - .id =3D SM8250_MASTER_SNOC_SF_MEM_NOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 3, - .links =3D { SM8250_SLAVE_LLCC, - SM8250_SLAVE_GEM_NOC_SNOC, - SM8250_SLAVE_MEM_NOC_PCIE_SNOC - }, + .link_nodes =3D { &qns_llcc, + &qns_gem_noc_snoc, + &qns_sys_pcie }, }; =20 static struct qcom_icc_node llcc_mc =3D { .name =3D "llcc_mc", - .id =3D SM8250_MASTER_LLCC, .channels =3D 4, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8250_SLAVE_EBI_CH0 }, + .link_nodes =3D { &ebi }, }; =20 static struct qcom_icc_node qhm_mnoc_cfg =3D { .name =3D "qhm_mnoc_cfg", - .id =3D SM8250_MASTER_CNOC_MNOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8250_SLAVE_SERVICE_MNOC }, + .link_nodes =3D { &srvc_mnoc }, }; =20 static struct qcom_icc_node qnm_camnoc_hf =3D { .name =3D "qnm_camnoc_hf", - .id =3D SM8250_MASTER_CAMNOC_HF, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8250_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_hf }, }; =20 static struct qcom_icc_node qnm_camnoc_icp =3D { .name =3D "qnm_camnoc_icp", - .id =3D SM8250_MASTER_CAMNOC_ICP, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8250_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static struct qcom_icc_node qnm_camnoc_sf =3D { .name =3D "qnm_camnoc_sf", - .id =3D SM8250_MASTER_CAMNOC_SF, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8250_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static struct qcom_icc_node qnm_video0 =3D { .name =3D "qnm_video0", - .id =3D SM8250_MASTER_VIDEO_P0, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8250_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static struct qcom_icc_node qnm_video1 =3D { .name =3D "qnm_video1", - .id =3D SM8250_MASTER_VIDEO_P1, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8250_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static struct qcom_icc_node qnm_video_cvp =3D { .name =3D "qnm_video_cvp", - .id =3D SM8250_MASTER_VIDEO_PROC, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8250_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static struct qcom_icc_node qxm_mdp0 =3D { .name =3D "qxm_mdp0", - .id =3D SM8250_MASTER_MDP_PORT0, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8250_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_hf }, }; =20 static struct qcom_icc_node qxm_mdp1 =3D { .name =3D "qxm_mdp1", - .id =3D SM8250_MASTER_MDP_PORT1, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8250_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_hf }, }; =20 static struct qcom_icc_node qxm_rot =3D { .name =3D "qxm_rot", - .id =3D SM8250_MASTER_ROTATOR, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8250_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static struct qcom_icc_node amm_npu_sys =3D { .name =3D "amm_npu_sys", - .id =3D SM8250_MASTER_NPU_SYS, .channels =3D 4, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8250_SLAVE_NPU_COMPUTE_NOC }, + .link_nodes =3D { &qns_npu_sys }, }; =20 static struct qcom_icc_node amm_npu_sys_cdp_w =3D { .name =3D "amm_npu_sys_cdp_w", - .id =3D SM8250_MASTER_NPU_CDP, .channels =3D 2, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM8250_SLAVE_NPU_COMPUTE_NOC }, + .link_nodes =3D { &qns_npu_sys }, }; =20 static struct qcom_icc_node qhm_cfg =3D { .name =3D "qhm_cfg", - .id =3D SM8250_MASTER_NPU_NOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 9, - .links =3D { SM8250_SLAVE_SERVICE_NPU_NOC, - SM8250_SLAVE_ISENSE_CFG, - SM8250_SLAVE_NPU_LLM_CFG, - SM8250_SLAVE_NPU_INT_DMA_BWMON_CFG, - SM8250_SLAVE_NPU_CP, - SM8250_SLAVE_NPU_TCM, - SM8250_SLAVE_NPU_CAL_DP0, - SM8250_SLAVE_NPU_CAL_DP1, - SM8250_SLAVE_NPU_DPM - }, + .link_nodes =3D { &srvc_noc, + &qhs_isense, + &qhs_llm, + &qhs_dma_bwmon, + &qhs_cp, + &qhs_tcm, + &qhs_cal_dp0, + &qhs_cal_dp1, + &qhs_dpm }, }; =20 static struct qcom_icc_node qhm_snoc_cfg =3D { .name =3D "qhm_snoc_cfg", - .id =3D SM8250_MASTER_SNOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8250_SLAVE_SERVICE_SNOC }, + .link_nodes =3D { &srvc_snoc }, }; =20 static struct qcom_icc_node qnm_aggre1_noc =3D { .name =3D "qnm_aggre1_noc", - .id =3D SM8250_A1NOC_SNOC_MAS, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM8250_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes =3D { &qns_gemnoc_sf }, }; =20 static struct qcom_icc_node qnm_aggre2_noc =3D { .name =3D "qnm_aggre2_noc", - .id =3D SM8250_A2NOC_SNOC_MAS, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM8250_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes =3D { &qns_gemnoc_sf }, }; =20 static struct qcom_icc_node qnm_gemnoc =3D { .name =3D "qnm_gemnoc", - .id =3D SM8250_MASTER_GEM_NOC_SNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 6, - .links =3D { SM8250_SLAVE_PIMEM, - SM8250_SLAVE_OCIMEM, - SM8250_SLAVE_APPSS, - SM8250_SNOC_CNOC_SLV, - SM8250_SLAVE_TCU, - SM8250_SLAVE_QDSS_STM - }, + .link_nodes =3D { &qxs_pimem, + &qxs_imem, + &qhs_apss, + &qns_cnoc, + &xs_sys_tcu_cfg, + &xs_qdss_stm }, }; =20 static struct qcom_icc_node qnm_gemnoc_pcie =3D { .name =3D "qnm_gemnoc_pcie", - .id =3D SM8250_MASTER_GEM_NOC_PCIE_SNOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 3, - .links =3D { SM8250_SLAVE_PCIE_2, - SM8250_SLAVE_PCIE_0, - SM8250_SLAVE_PCIE_1 - }, + .link_nodes =3D { &xs_pcie_modem, + &xs_pcie_0, + &xs_pcie_1 }, }; =20 static struct qcom_icc_node qxm_pimem =3D { .name =3D "qxm_pimem", - .id =3D SM8250_MASTER_PIMEM, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8250_SLAVE_SNOC_GEM_NOC_GC }, + .link_nodes =3D { &qns_gemnoc_gc }, }; =20 static struct qcom_icc_node xm_gic =3D { .name =3D "xm_gic", - .id =3D SM8250_MASTER_GIC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8250_SLAVE_SNOC_GEM_NOC_GC }, + .link_nodes =3D { &qns_gemnoc_gc }, }; =20 static struct qcom_icc_node qns_a1noc_snoc =3D { .name =3D "qns_a1noc_snoc", - .id =3D SM8250_A1NOC_SNOC_SLV, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM8250_A1NOC_SNOC_MAS }, + .link_nodes =3D { &qnm_aggre1_noc }, }; =20 static struct qcom_icc_node qns_pcie_modem_mem_noc =3D { .name =3D "qns_pcie_modem_mem_noc", - .id =3D SM8250_SLAVE_ANOC_PCIE_GEM_NOC_1, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM8250_MASTER_ANOC_PCIE_GEM_NOC }, + .link_nodes =3D { &qnm_pcie }, }; =20 static struct qcom_icc_node srvc_aggre1_noc =3D { .name =3D "srvc_aggre1_noc", - .id =3D SM8250_SLAVE_SERVICE_A1NOC, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qns_a2noc_snoc =3D { .name =3D "qns_a2noc_snoc", - .id =3D SM8250_A2NOC_SNOC_SLV, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM8250_A2NOC_SNOC_MAS }, + .link_nodes =3D { &qnm_aggre2_noc }, }; =20 static struct qcom_icc_node qns_pcie_mem_noc =3D { .name =3D "qns_pcie_mem_noc", - .id =3D SM8250_SLAVE_ANOC_PCIE_GEM_NOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM8250_MASTER_ANOC_PCIE_GEM_NOC }, + .link_nodes =3D { &qnm_pcie }, }; =20 static struct qcom_icc_node srvc_aggre2_noc =3D { .name =3D "srvc_aggre2_noc", - .id =3D SM8250_SLAVE_SERVICE_A2NOC, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qns_cdsp_mem_noc =3D { .name =3D "qns_cdsp_mem_noc", - .id =3D SM8250_SLAVE_CDSP_MEM_NOC, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8250_MASTER_COMPUTE_NOC }, + .link_nodes =3D { &qnm_cmpnoc }, }; =20 static struct qcom_icc_node qhs_a1_noc_cfg =3D { .name =3D "qhs_a1_noc_cfg", - .id =3D SM8250_SLAVE_A1NOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8250_MASTER_A1NOC_CFG }, + .link_nodes =3D { &qhm_a1noc_cfg }, }; =20 static struct qcom_icc_node qhs_a2_noc_cfg =3D { .name =3D "qhs_a2_noc_cfg", - .id =3D SM8250_SLAVE_A2NOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8250_MASTER_A2NOC_CFG }, + .link_nodes =3D { &qhm_a2noc_cfg }, }; =20 static struct qcom_icc_node qhs_ahb2phy0 =3D { .name =3D "qhs_ahb2phy0", - .id =3D SM8250_SLAVE_AHB2PHY_SOUTH, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_ahb2phy1 =3D { .name =3D "qhs_ahb2phy1", - .id =3D SM8250_SLAVE_AHB2PHY_NORTH, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_aoss =3D { .name =3D "qhs_aoss", - .id =3D SM8250_SLAVE_AOSS, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_camera_cfg =3D { .name =3D "qhs_camera_cfg", - .id =3D SM8250_SLAVE_CAMERA_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_clk_ctl =3D { .name =3D "qhs_clk_ctl", - .id =3D SM8250_SLAVE_CLK_CTL, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_compute_dsp =3D { .name =3D "qhs_compute_dsp", - .id =3D SM8250_SLAVE_CDSP_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_cpr_cx =3D { .name =3D "qhs_cpr_cx", - .id =3D SM8250_SLAVE_RBCPR_CX_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_cpr_mmcx =3D { .name =3D "qhs_cpr_mmcx", - .id =3D SM8250_SLAVE_RBCPR_MMCX_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_cpr_mx =3D { .name =3D "qhs_cpr_mx", - .id =3D SM8250_SLAVE_RBCPR_MX_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_crypto0_cfg =3D { .name =3D "qhs_crypto0_cfg", - .id =3D SM8250_SLAVE_CRYPTO_0_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_cx_rdpm =3D { .name =3D "qhs_cx_rdpm", - .id =3D SM8250_SLAVE_CX_RDPM, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_dcc_cfg =3D { .name =3D "qhs_dcc_cfg", - .id =3D SM8250_SLAVE_DCC_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_ddrss_cfg =3D { .name =3D "qhs_ddrss_cfg", - .id =3D SM8250_SLAVE_CNOC_DDRSS, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8250_MASTER_CNOC_DC_NOC }, + .link_nodes =3D { &qhm_cnoc_dc_noc }, }; =20 static struct qcom_icc_node qhs_display_cfg =3D { .name =3D "qhs_display_cfg", - .id =3D SM8250_SLAVE_DISPLAY_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_gpuss_cfg =3D { .name =3D "qhs_gpuss_cfg", - .id =3D SM8250_SLAVE_GRAPHICS_3D_CFG, .channels =3D 1, .buswidth =3D 8, }; =20 static struct qcom_icc_node qhs_imem_cfg =3D { .name =3D "qhs_imem_cfg", - .id =3D SM8250_SLAVE_IMEM_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_ipa =3D { .name =3D "qhs_ipa", - .id =3D SM8250_SLAVE_IPA_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_ipc_router =3D { .name =3D "qhs_ipc_router", - .id =3D SM8250_SLAVE_IPC_ROUTER_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_lpass_cfg =3D { .name =3D "qhs_lpass_cfg", - .id =3D SM8250_SLAVE_LPASS, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_mnoc_cfg =3D { .name =3D "qhs_mnoc_cfg", - .id =3D SM8250_SLAVE_CNOC_MNOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8250_MASTER_CNOC_MNOC_CFG }, + .link_nodes =3D { &qhm_mnoc_cfg }, }; =20 static struct qcom_icc_node qhs_npu_cfg =3D { .name =3D "qhs_npu_cfg", - .id =3D SM8250_SLAVE_NPU_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8250_MASTER_NPU_NOC_CFG }, + .link_nodes =3D { &qhm_cfg }, }; =20 static struct qcom_icc_node qhs_pcie0_cfg =3D { .name =3D "qhs_pcie0_cfg", - .id =3D SM8250_SLAVE_PCIE_0_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_pcie1_cfg =3D { .name =3D "qhs_pcie1_cfg", - .id =3D SM8250_SLAVE_PCIE_1_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_pcie_modem_cfg =3D { .name =3D "qhs_pcie_modem_cfg", - .id =3D SM8250_SLAVE_PCIE_2_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_pdm =3D { .name =3D "qhs_pdm", - .id =3D SM8250_SLAVE_PDM, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_pimem_cfg =3D { .name =3D "qhs_pimem_cfg", - .id =3D SM8250_SLAVE_PIMEM_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_prng =3D { .name =3D "qhs_prng", - .id =3D SM8250_SLAVE_PRNG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_qdss_cfg =3D { .name =3D "qhs_qdss_cfg", - .id =3D SM8250_SLAVE_QDSS_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_qspi =3D { .name =3D "qhs_qspi", - .id =3D SM8250_SLAVE_QSPI_0, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_qup0 =3D { .name =3D "qhs_qup0", - .id =3D SM8250_SLAVE_QUP_0, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_qup1 =3D { .name =3D "qhs_qup1", - .id =3D SM8250_SLAVE_QUP_1, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_qup2 =3D { .name =3D "qhs_qup2", - .id =3D SM8250_SLAVE_QUP_2, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_sdc2 =3D { .name =3D "qhs_sdc2", - .id =3D SM8250_SLAVE_SDCC_2, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_sdc4 =3D { .name =3D "qhs_sdc4", - .id =3D SM8250_SLAVE_SDCC_4, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_snoc_cfg =3D { .name =3D "qhs_snoc_cfg", - .id =3D SM8250_SLAVE_SNOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8250_MASTER_SNOC_CFG }, + .link_nodes =3D { &qhm_snoc_cfg }, }; =20 static struct qcom_icc_node qhs_tcsr =3D { .name =3D "qhs_tcsr", - .id =3D SM8250_SLAVE_TCSR, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_tlmm0 =3D { .name =3D "qhs_tlmm0", - .id =3D SM8250_SLAVE_TLMM_NORTH, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_tlmm1 =3D { .name =3D "qhs_tlmm1", - .id =3D SM8250_SLAVE_TLMM_SOUTH, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_tlmm2 =3D { .name =3D "qhs_tlmm2", - .id =3D SM8250_SLAVE_TLMM_WEST, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_tsif =3D { .name =3D "qhs_tsif", - .id =3D SM8250_SLAVE_TSIF, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_ufs_card_cfg =3D { .name =3D "qhs_ufs_card_cfg", - .id =3D SM8250_SLAVE_UFS_CARD_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_ufs_mem_cfg =3D { .name =3D "qhs_ufs_mem_cfg", - .id =3D SM8250_SLAVE_UFS_MEM_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_usb3_0 =3D { .name =3D "qhs_usb3_0", - .id =3D SM8250_SLAVE_USB3, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_usb3_1 =3D { .name =3D "qhs_usb3_1", - .id =3D SM8250_SLAVE_USB3_1, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_venus_cfg =3D { .name =3D "qhs_venus_cfg", - .id =3D SM8250_SLAVE_VENUS_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_vsense_ctrl_cfg =3D { .name =3D "qhs_vsense_ctrl_cfg", - .id =3D SM8250_SLAVE_VSENSE_CTRL_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qns_cnoc_a2noc =3D { .name =3D "qns_cnoc_a2noc", - .id =3D SM8250_SLAVE_CNOC_A2NOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8250_MASTER_CNOC_A2NOC }, + .link_nodes =3D { &qnm_cnoc }, }; =20 static struct qcom_icc_node srvc_cnoc =3D { .name =3D "srvc_cnoc", - .id =3D SM8250_SLAVE_SERVICE_CNOC, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_llcc =3D { .name =3D "qhs_llcc", - .id =3D SM8250_SLAVE_LLCC_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_memnoc =3D { .name =3D "qhs_memnoc", - .id =3D SM8250_SLAVE_GEM_NOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8250_MASTER_GEM_NOC_CFG }, + .link_nodes =3D { &qhm_gemnoc_cfg }, }; =20 static struct qcom_icc_node qns_gem_noc_snoc =3D { .name =3D "qns_gem_noc_snoc", - .id =3D SM8250_SLAVE_GEM_NOC_SNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM8250_MASTER_GEM_NOC_SNOC }, + .link_nodes =3D { &qnm_gemnoc }, }; =20 static struct qcom_icc_node qns_llcc =3D { .name =3D "qns_llcc", - .id =3D SM8250_SLAVE_LLCC, .channels =3D 4, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM8250_MASTER_LLCC }, + .link_nodes =3D { &llcc_mc }, }; =20 static struct qcom_icc_node qns_sys_pcie =3D { .name =3D "qns_sys_pcie", - .id =3D SM8250_SLAVE_MEM_NOC_PCIE_SNOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8250_MASTER_GEM_NOC_PCIE_SNOC }, + .link_nodes =3D { &qnm_gemnoc_pcie }, }; =20 static struct qcom_icc_node srvc_even_gemnoc =3D { .name =3D "srvc_even_gemnoc", - .id =3D SM8250_SLAVE_SERVICE_GEM_NOC_1, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node srvc_odd_gemnoc =3D { .name =3D "srvc_odd_gemnoc", - .id =3D SM8250_SLAVE_SERVICE_GEM_NOC_2, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node srvc_sys_gemnoc =3D { .name =3D "srvc_sys_gemnoc", - .id =3D SM8250_SLAVE_SERVICE_GEM_NOC, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node ebi =3D { .name =3D "ebi", - .id =3D SM8250_SLAVE_EBI_CH0, .channels =3D 4, .buswidth =3D 4, }; =20 static struct qcom_icc_node qns_mem_noc_hf =3D { .name =3D "qns_mem_noc_hf", - .id =3D SM8250_SLAVE_MNOC_HF_MEM_NOC, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8250_MASTER_MNOC_HF_MEM_NOC }, + .link_nodes =3D { &qnm_mnoc_hf }, }; =20 static struct qcom_icc_node qns_mem_noc_sf =3D { .name =3D "qns_mem_noc_sf", - .id =3D SM8250_SLAVE_MNOC_SF_MEM_NOC, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8250_MASTER_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qnm_mnoc_sf }, }; =20 static struct qcom_icc_node srvc_mnoc =3D { .name =3D "srvc_mnoc", - .id =3D SM8250_SLAVE_SERVICE_MNOC, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_cal_dp0 =3D { .name =3D "qhs_cal_dp0", - .id =3D SM8250_SLAVE_NPU_CAL_DP0, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_cal_dp1 =3D { .name =3D "qhs_cal_dp1", - .id =3D SM8250_SLAVE_NPU_CAL_DP1, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_cp =3D { .name =3D "qhs_cp", - .id =3D SM8250_SLAVE_NPU_CP, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_dma_bwmon =3D { .name =3D "qhs_dma_bwmon", - .id =3D SM8250_SLAVE_NPU_INT_DMA_BWMON_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_dpm =3D { .name =3D "qhs_dpm", - .id =3D SM8250_SLAVE_NPU_DPM, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_isense =3D { .name =3D "qhs_isense", - .id =3D SM8250_SLAVE_ISENSE_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_llm =3D { .name =3D "qhs_llm", - .id =3D SM8250_SLAVE_NPU_LLM_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_tcm =3D { .name =3D "qhs_tcm", - .id =3D SM8250_SLAVE_NPU_TCM, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qns_npu_sys =3D { .name =3D "qns_npu_sys", - .id =3D SM8250_SLAVE_NPU_COMPUTE_NOC, .channels =3D 2, .buswidth =3D 32, }; =20 static struct qcom_icc_node srvc_noc =3D { .name =3D "srvc_noc", - .id =3D SM8250_SLAVE_SERVICE_NPU_NOC, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_apss =3D { .name =3D "qhs_apss", - .id =3D SM8250_SLAVE_APPSS, .channels =3D 1, .buswidth =3D 8, }; =20 static struct qcom_icc_node qns_cnoc =3D { .name =3D "qns_cnoc", - .id =3D SM8250_SNOC_CNOC_SLV, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8250_SNOC_CNOC_MAS }, + .link_nodes =3D { &qnm_snoc }, }; =20 static struct qcom_icc_node qns_gemnoc_gc =3D { .name =3D "qns_gemnoc_gc", - .id =3D SM8250_SLAVE_SNOC_GEM_NOC_GC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8250_MASTER_SNOC_GC_MEM_NOC }, + .link_nodes =3D { &qnm_snoc_gc }, }; =20 static struct qcom_icc_node qns_gemnoc_sf =3D { .name =3D "qns_gemnoc_sf", - .id =3D SM8250_SLAVE_SNOC_GEM_NOC_SF, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM8250_MASTER_SNOC_SF_MEM_NOC }, + .link_nodes =3D { &qnm_snoc_sf }, }; =20 static struct qcom_icc_node qxs_imem =3D { .name =3D "qxs_imem", - .id =3D SM8250_SLAVE_OCIMEM, .channels =3D 1, .buswidth =3D 8, }; =20 static struct qcom_icc_node qxs_pimem =3D { .name =3D "qxs_pimem", - .id =3D SM8250_SLAVE_PIMEM, .channels =3D 1, .buswidth =3D 8, }; =20 static struct qcom_icc_node srvc_snoc =3D { .name =3D "srvc_snoc", - .id =3D SM8250_SLAVE_SERVICE_SNOC, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node xs_pcie_0 =3D { .name =3D "xs_pcie_0", - .id =3D SM8250_SLAVE_PCIE_0, .channels =3D 1, .buswidth =3D 8, }; =20 static struct qcom_icc_node xs_pcie_1 =3D { .name =3D "xs_pcie_1", - .id =3D SM8250_SLAVE_PCIE_1, .channels =3D 1, .buswidth =3D 8, }; =20 static struct qcom_icc_node xs_pcie_modem =3D { .name =3D "xs_pcie_modem", - .id =3D SM8250_SLAVE_PCIE_2, .channels =3D 1, .buswidth =3D 8, }; =20 static struct qcom_icc_node xs_qdss_stm =3D { .name =3D "xs_qdss_stm", - .id =3D SM8250_SLAVE_QDSS_STM, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node xs_sys_tcu_cfg =3D { .name =3D "xs_sys_tcu_cfg", - .id =3D SM8250_SLAVE_TCU, .channels =3D 1, .buswidth =3D 8, }; =20 static struct qcom_icc_node qup0_core_master =3D { .name =3D "qup0_core_master", - .id =3D SM8250_MASTER_QUP_CORE_0, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8250_SLAVE_QUP_CORE_0 }, + .link_nodes =3D { &qup0_core_slave }, }; =20 static struct qcom_icc_node qup1_core_master =3D { .name =3D "qup1_core_master", - .id =3D SM8250_MASTER_QUP_CORE_1, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8250_SLAVE_QUP_CORE_1 }, + .link_nodes =3D { &qup1_core_slave }, }; =20 static struct qcom_icc_node qup2_core_master =3D { .name =3D "qup2_core_master", - .id =3D SM8250_MASTER_QUP_CORE_2, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8250_SLAVE_QUP_CORE_2 }, + .link_nodes =3D { &qup2_core_slave }, }; =20 static struct qcom_icc_node qup0_core_slave =3D { .name =3D "qup0_core_slave", - .id =3D SM8250_SLAVE_QUP_CORE_0, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qup1_core_slave =3D { .name =3D "qup1_core_slave", - .id =3D SM8250_SLAVE_QUP_CORE_1, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qup2_core_slave =3D { .name =3D "qup2_core_slave", - .id =3D SM8250_SLAVE_QUP_CORE_2, .channels =3D 1, .buswidth =3D 4, }; diff --git a/drivers/interconnect/qcom/sm8250.h b/drivers/interconnect/qcom= /sm8250.h deleted file mode 100644 index 032665093c5bfe83e9dc6b444fc07fcf790e9993..000000000000000000000000000= 0000000000000 --- a/drivers/interconnect/qcom/sm8250.h +++ /dev/null @@ -1,168 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Qualcomm #define SM8250 interconnect IDs - * - * Copyright (c) 2020, The Linux Foundation. All rights reserved. - */ - -#ifndef __DRIVERS_INTERCONNECT_QCOM_SM8250_H -#define __DRIVERS_INTERCONNECT_QCOM_SM8250_H - -#define SM8250_A1NOC_SNOC_MAS 0 -#define SM8250_A1NOC_SNOC_SLV 1 -#define SM8250_A2NOC_SNOC_MAS 2 -#define SM8250_A2NOC_SNOC_SLV 3 -#define SM8250_MASTER_A1NOC_CFG 4 -#define SM8250_MASTER_A2NOC_CFG 5 -#define SM8250_MASTER_AMPSS_M0 6 -#define SM8250_MASTER_ANOC_PCIE_GEM_NOC 7 -#define SM8250_MASTER_CAMNOC_HF 8 -#define SM8250_MASTER_CAMNOC_ICP 9 -#define SM8250_MASTER_CAMNOC_SF 10 -#define SM8250_MASTER_CNOC_A2NOC 11 -#define SM8250_MASTER_CNOC_DC_NOC 12 -#define SM8250_MASTER_CNOC_MNOC_CFG 13 -#define SM8250_MASTER_COMPUTE_NOC 14 -#define SM8250_MASTER_CRYPTO_CORE_0 15 -#define SM8250_MASTER_GEM_NOC_CFG 16 -#define SM8250_MASTER_GEM_NOC_PCIE_SNOC 17 -#define SM8250_MASTER_GEM_NOC_SNOC 18 -#define SM8250_MASTER_GIC 19 -#define SM8250_MASTER_GPU_TCU 20 -#define SM8250_MASTER_GRAPHICS_3D 21 -#define SM8250_MASTER_IPA 22 -/* 23 was used by MASTER_IPA_CORE, now represented as RPMh clock */ -#define SM8250_MASTER_LLCC 24 -#define SM8250_MASTER_MDP_PORT0 25 -#define SM8250_MASTER_MDP_PORT1 26 -#define SM8250_MASTER_MNOC_HF_MEM_NOC 27 -#define SM8250_MASTER_MNOC_SF_MEM_NOC 28 -#define SM8250_MASTER_NPU 29 -#define SM8250_MASTER_NPU_CDP 30 -#define SM8250_MASTER_NPU_NOC_CFG 31 -#define SM8250_MASTER_NPU_SYS 32 -#define SM8250_MASTER_PCIE 33 -#define SM8250_MASTER_PCIE_1 34 -#define SM8250_MASTER_PCIE_2 35 -#define SM8250_MASTER_PIMEM 36 -#define SM8250_MASTER_QDSS_BAM 37 -#define SM8250_MASTER_QDSS_DAP 38 -#define SM8250_MASTER_QDSS_ETR 39 -#define SM8250_MASTER_QSPI_0 40 -#define SM8250_MASTER_QUP_0 41 -#define SM8250_MASTER_QUP_1 42 -#define SM8250_MASTER_QUP_2 43 -#define SM8250_MASTER_ROTATOR 44 -#define SM8250_MASTER_SDCC_2 45 -#define SM8250_MASTER_SDCC_4 46 -#define SM8250_MASTER_SNOC_CFG 47 -#define SM8250_MASTER_SNOC_GC_MEM_NOC 48 -#define SM8250_MASTER_SNOC_SF_MEM_NOC 49 -#define SM8250_MASTER_SYS_TCU 50 -#define SM8250_MASTER_TSIF 51 -#define SM8250_MASTER_UFS_CARD 52 -#define SM8250_MASTER_UFS_MEM 53 -#define SM8250_MASTER_USB3 54 -#define SM8250_MASTER_USB3_1 55 -#define SM8250_MASTER_VIDEO_P0 56 -#define SM8250_MASTER_VIDEO_P1 57 -#define SM8250_MASTER_VIDEO_PROC 58 -#define SM8250_SLAVE_A1NOC_CFG 59 -#define SM8250_SLAVE_A2NOC_CFG 60 -#define SM8250_SLAVE_AHB2PHY_NORTH 61 -#define SM8250_SLAVE_AHB2PHY_SOUTH 62 -#define SM8250_SLAVE_ANOC_PCIE_GEM_NOC 63 -#define SM8250_SLAVE_ANOC_PCIE_GEM_NOC_1 64 -#define SM8250_SLAVE_AOSS 65 -#define SM8250_SLAVE_APPSS 66 -#define SM8250_SLAVE_CAMERA_CFG 67 -#define SM8250_SLAVE_CDSP_CFG 68 -#define SM8250_SLAVE_CDSP_MEM_NOC 69 -#define SM8250_SLAVE_CLK_CTL 70 -#define SM8250_SLAVE_CNOC_A2NOC 71 -#define SM8250_SLAVE_CNOC_DDRSS 72 -#define SM8250_SLAVE_CNOC_MNOC_CFG 73 -#define SM8250_SLAVE_CRYPTO_0_CFG 74 -#define SM8250_SLAVE_CX_RDPM 75 -#define SM8250_SLAVE_DCC_CFG 76 -#define SM8250_SLAVE_DISPLAY_CFG 77 -#define SM8250_SLAVE_EBI_CH0 78 -#define SM8250_SLAVE_GEM_NOC_CFG 79 -#define SM8250_SLAVE_GEM_NOC_SNOC 80 -#define SM8250_SLAVE_GRAPHICS_3D_CFG 81 -#define SM8250_SLAVE_IMEM_CFG 82 -#define SM8250_SLAVE_IPA_CFG 83 -/* 84 was used by SLAVE_IPA_CORE, now represented as RPMh clock */ -#define SM8250_SLAVE_IPC_ROUTER_CFG 85 -#define SM8250_SLAVE_ISENSE_CFG 86 -#define SM8250_SLAVE_LLCC 87 -#define SM8250_SLAVE_LLCC_CFG 88 -#define SM8250_SLAVE_LPASS 89 -#define SM8250_SLAVE_MEM_NOC_PCIE_SNOC 90 -#define SM8250_SLAVE_MNOC_HF_MEM_NOC 91 -#define SM8250_SLAVE_MNOC_SF_MEM_NOC 92 -#define SM8250_SLAVE_NPU_CAL_DP0 93 -#define SM8250_SLAVE_NPU_CAL_DP1 94 -#define SM8250_SLAVE_NPU_CFG 95 -#define SM8250_SLAVE_NPU_COMPUTE_NOC 96 -#define SM8250_SLAVE_NPU_CP 97 -#define SM8250_SLAVE_NPU_DPM 98 -#define SM8250_SLAVE_NPU_INT_DMA_BWMON_CFG 99 -#define SM8250_SLAVE_NPU_LLM_CFG 100 -#define SM8250_SLAVE_NPU_TCM 101 -#define SM8250_SLAVE_OCIMEM 102 -#define SM8250_SLAVE_PCIE_0 103 -#define SM8250_SLAVE_PCIE_0_CFG 104 -#define SM8250_SLAVE_PCIE_1 105 -#define SM8250_SLAVE_PCIE_1_CFG 106 -#define SM8250_SLAVE_PCIE_2 107 -#define SM8250_SLAVE_PCIE_2_CFG 108 -#define SM8250_SLAVE_PDM 109 -#define SM8250_SLAVE_PIMEM 110 -#define SM8250_SLAVE_PIMEM_CFG 111 -#define SM8250_SLAVE_PRNG 112 -#define SM8250_SLAVE_QDSS_CFG 113 -#define SM8250_SLAVE_QDSS_STM 114 -#define SM8250_SLAVE_QSPI_0 115 -#define SM8250_SLAVE_QUP_0 116 -#define SM8250_SLAVE_QUP_1 117 -#define SM8250_SLAVE_QUP_2 118 -#define SM8250_SLAVE_RBCPR_CX_CFG 119 -#define SM8250_SLAVE_RBCPR_MMCX_CFG 120 -#define SM8250_SLAVE_RBCPR_MX_CFG 121 -#define SM8250_SLAVE_SDCC_2 122 -#define SM8250_SLAVE_SDCC_4 123 -#define SM8250_SLAVE_SERVICE_A1NOC 124 -#define SM8250_SLAVE_SERVICE_A2NOC 125 -#define SM8250_SLAVE_SERVICE_CNOC 126 -#define SM8250_SLAVE_SERVICE_GEM_NOC 127 -#define SM8250_SLAVE_SERVICE_GEM_NOC_1 128 -#define SM8250_SLAVE_SERVICE_GEM_NOC_2 129 -#define SM8250_SLAVE_SERVICE_MNOC 130 -#define SM8250_SLAVE_SERVICE_NPU_NOC 131 -#define SM8250_SLAVE_SERVICE_SNOC 132 -#define SM8250_SLAVE_SNOC_CFG 133 -#define SM8250_SLAVE_SNOC_GEM_NOC_GC 134 -#define SM8250_SLAVE_SNOC_GEM_NOC_SF 135 -#define SM8250_SLAVE_TCSR 136 -#define SM8250_SLAVE_TCU 137 -#define SM8250_SLAVE_TLMM_NORTH 138 -#define SM8250_SLAVE_TLMM_SOUTH 139 -#define SM8250_SLAVE_TLMM_WEST 140 -#define SM8250_SLAVE_TSIF 141 -#define SM8250_SLAVE_UFS_CARD_CFG 142 -#define SM8250_SLAVE_UFS_MEM_CFG 143 -#define SM8250_SLAVE_USB3 144 -#define SM8250_SLAVE_USB3_1 145 -#define SM8250_SLAVE_VENUS_CFG 146 -#define SM8250_SLAVE_VSENSE_CTRL_CFG 147 -#define SM8250_SNOC_CNOC_MAS 148 -#define SM8250_SNOC_CNOC_SLV 149 -#define SM8250_MASTER_QUP_CORE_0 150 -#define SM8250_MASTER_QUP_CORE_1 151 -#define SM8250_MASTER_QUP_CORE_2 152 -#define SM8250_SLAVE_QUP_CORE_0 153 -#define SM8250_SLAVE_QUP_CORE_1 154 -#define SM8250_SLAVE_QUP_CORE_2 155 - -#endif --=20 2.47.3 From nobody Mon Feb 9 06:05:00 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher 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This gives more flexibility and also allows us to drop the .num_links member, saving from possible errors related to it being not set or set incorrectly. Signed-off-by: Dmitry Baryshkov --- drivers/interconnect/qcom/x1e80100.c | 629 ++++++++++++++++---------------= ---- drivers/interconnect/qcom/x1e80100.h | 192 ----------- 2 files changed, 292 insertions(+), 529 deletions(-) diff --git a/drivers/interconnect/qcom/x1e80100.c b/drivers/interconnect/qc= om/x1e80100.c index 2c46fdb4a0543f8345e03dbfe83d3a7ab95bd17c..d5df26f02675de0150e2903df09= fe419a8bd8892 100644 --- a/drivers/interconnect/qcom/x1e80100.c +++ b/drivers/interconnect/qcom/x1e80100.c @@ -15,1342 +15,1278 @@ #include "bcm-voter.h" #include "icc-common.h" #include "icc-rpmh.h" -#include "x1e80100.h" + +static struct qcom_icc_node qhm_qspi; +static struct qcom_icc_node qhm_qup1; +static struct qcom_icc_node xm_sdc4; +static struct qcom_icc_node xm_ufs_mem; +static struct qcom_icc_node qhm_qup0; +static struct qcom_icc_node qhm_qup2; +static struct qcom_icc_node qxm_crypto; +static struct qcom_icc_node qxm_sp; +static struct qcom_icc_node xm_qdss_etr_0; +static struct qcom_icc_node xm_qdss_etr_1; +static struct qcom_icc_node xm_sdc2; +static struct qcom_icc_node qup0_core_master; +static struct qcom_icc_node qup1_core_master; +static struct qcom_icc_node qup2_core_master; +static struct qcom_icc_node qsm_cfg; +static struct qcom_icc_node qnm_gemnoc_cnoc; +static struct qcom_icc_node qnm_gemnoc_pcie; +static struct qcom_icc_node alm_gpu_tcu; +static struct qcom_icc_node alm_pcie_tcu; +static struct qcom_icc_node alm_sys_tcu; +static struct qcom_icc_node chm_apps; +static struct qcom_icc_node qnm_gpu; +static struct qcom_icc_node qnm_lpass; +static struct qcom_icc_node qnm_mnoc_hf; +static struct qcom_icc_node qnm_mnoc_sf; +static struct qcom_icc_node qnm_nsp_noc; +static struct qcom_icc_node qnm_pcie; +static struct qcom_icc_node qnm_snoc_sf; +static struct qcom_icc_node xm_gic; +static struct qcom_icc_node qnm_lpiaon_noc; +static struct qcom_icc_node qnm_lpass_lpinoc; +static struct qcom_icc_node qxm_lpinoc_dsp_axim; +static struct qcom_icc_node llcc_mc; +static struct qcom_icc_node qnm_av1_enc; +static struct qcom_icc_node qnm_camnoc_hf; +static struct qcom_icc_node qnm_camnoc_icp; +static struct qcom_icc_node qnm_camnoc_sf; +static struct qcom_icc_node qnm_eva; +static struct qcom_icc_node qnm_mdp; +static struct qcom_icc_node qnm_video; +static struct qcom_icc_node qnm_video_cv_cpu; +static struct qcom_icc_node qnm_video_v_cpu; +static struct qcom_icc_node qsm_mnoc_cfg; +static struct qcom_icc_node qxm_nsp; +static struct qcom_icc_node qnm_pcie_north_gem_noc; +static struct qcom_icc_node qnm_pcie_south_gem_noc; +static struct qcom_icc_node xm_pcie_3; +static struct qcom_icc_node xm_pcie_4; +static struct qcom_icc_node xm_pcie_5; +static struct qcom_icc_node xm_pcie_0; +static struct qcom_icc_node xm_pcie_1; +static struct qcom_icc_node xm_pcie_2; +static struct qcom_icc_node xm_pcie_6a; +static struct qcom_icc_node xm_pcie_6b; +static struct qcom_icc_node qnm_aggre1_noc; +static struct qcom_icc_node qnm_aggre2_noc; +static struct qcom_icc_node qnm_gic; +static struct qcom_icc_node qnm_usb_anoc; +static struct qcom_icc_node qnm_aggre_usb_north_snoc; +static struct qcom_icc_node qnm_aggre_usb_south_snoc; +static struct qcom_icc_node xm_usb2_0; +static struct qcom_icc_node xm_usb3_mp; +static struct qcom_icc_node xm_usb3_0; +static struct qcom_icc_node xm_usb3_1; +static struct qcom_icc_node xm_usb3_2; +static struct qcom_icc_node xm_usb4_0; +static struct qcom_icc_node xm_usb4_1; +static struct qcom_icc_node xm_usb4_2; +static struct qcom_icc_node qns_a1noc_snoc; +static struct qcom_icc_node qns_a2noc_snoc; +static struct qcom_icc_node qup0_core_slave; +static struct qcom_icc_node qup1_core_slave; +static struct qcom_icc_node qup2_core_slave; +static struct qcom_icc_node qhs_ahb2phy0; +static struct qcom_icc_node qhs_ahb2phy1; +static struct qcom_icc_node qhs_ahb2phy2; +static struct qcom_icc_node qhs_av1_enc_cfg; +static struct qcom_icc_node qhs_camera_cfg; +static struct qcom_icc_node qhs_clk_ctl; +static struct qcom_icc_node qhs_crypto0_cfg; +static struct qcom_icc_node qhs_display_cfg; +static struct qcom_icc_node qhs_gpuss_cfg; +static struct qcom_icc_node qhs_imem_cfg; +static struct qcom_icc_node qhs_ipc_router; +static struct qcom_icc_node qhs_pcie0_cfg; +static struct qcom_icc_node qhs_pcie1_cfg; +static struct qcom_icc_node qhs_pcie2_cfg; +static struct qcom_icc_node qhs_pcie3_cfg; +static struct qcom_icc_node qhs_pcie4_cfg; +static struct qcom_icc_node qhs_pcie5_cfg; +static struct qcom_icc_node qhs_pcie6a_cfg; +static struct qcom_icc_node qhs_pcie6b_cfg; +static struct qcom_icc_node qhs_pcie_rsc_cfg; +static struct qcom_icc_node qhs_pdm; +static struct qcom_icc_node qhs_prng; +static struct qcom_icc_node qhs_qdss_cfg; +static struct qcom_icc_node qhs_qspi; +static struct qcom_icc_node qhs_qup0; +static struct qcom_icc_node qhs_qup1; +static struct qcom_icc_node qhs_qup2; +static struct qcom_icc_node qhs_sdc2; +static struct qcom_icc_node qhs_sdc4; +static struct qcom_icc_node qhs_smmuv3_cfg; +static struct qcom_icc_node qhs_tcsr; +static struct qcom_icc_node qhs_tlmm; +static struct qcom_icc_node qhs_ufs_mem_cfg; +static struct qcom_icc_node qhs_usb2_0_cfg; +static struct qcom_icc_node qhs_usb3_0_cfg; +static struct qcom_icc_node qhs_usb3_1_cfg; +static struct qcom_icc_node qhs_usb3_2_cfg; +static struct qcom_icc_node qhs_usb3_mp_cfg; +static struct qcom_icc_node qhs_usb4_0_cfg; +static struct qcom_icc_node qhs_usb4_1_cfg; +static struct qcom_icc_node qhs_usb4_2_cfg; +static struct qcom_icc_node qhs_venus_cfg; +static struct qcom_icc_node qss_lpass_qtb_cfg; +static struct qcom_icc_node qss_mnoc_cfg; +static struct qcom_icc_node qss_nsp_qtb_cfg; +static struct qcom_icc_node xs_qdss_stm; +static struct qcom_icc_node xs_sys_tcu_cfg; +static struct qcom_icc_node qhs_aoss; +static struct qcom_icc_node qhs_tme_cfg; +static struct qcom_icc_node qns_apss; +static struct qcom_icc_node qss_cfg; +static struct qcom_icc_node qxs_boot_imem; +static struct qcom_icc_node qxs_imem; +static struct qcom_icc_node xs_pcie_0; +static struct qcom_icc_node xs_pcie_1; +static struct qcom_icc_node xs_pcie_2; +static struct qcom_icc_node xs_pcie_3; +static struct qcom_icc_node xs_pcie_4; +static struct qcom_icc_node xs_pcie_5; +static struct qcom_icc_node xs_pcie_6a; +static struct qcom_icc_node xs_pcie_6b; +static struct qcom_icc_node qns_gem_noc_cnoc; +static struct qcom_icc_node qns_llcc; +static struct qcom_icc_node qns_pcie; +static struct qcom_icc_node qns_lpass_ag_noc_gemnoc; +static struct qcom_icc_node qns_lpass_aggnoc; +static struct qcom_icc_node qns_lpi_aon_noc; +static struct qcom_icc_node ebi; +static struct qcom_icc_node qns_mem_noc_hf; +static struct qcom_icc_node qns_mem_noc_sf; +static struct qcom_icc_node srvc_mnoc; +static struct qcom_icc_node qns_nsp_gemnoc; +static struct qcom_icc_node qns_pcie_mem_noc; +static struct qcom_icc_node qns_pcie_north_gem_noc; +static struct qcom_icc_node qns_pcie_south_gem_noc; +static struct qcom_icc_node qns_gemnoc_sf; +static struct qcom_icc_node qns_aggre_usb_snoc; +static struct qcom_icc_node qns_aggre_usb_north_snoc; +static struct qcom_icc_node qns_aggre_usb_south_snoc; =20 static struct qcom_icc_node qhm_qspi =3D { .name =3D "qhm_qspi", - .id =3D X1E80100_MASTER_QSPI_0, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { X1E80100_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node qhm_qup1 =3D { .name =3D "qhm_qup1", - .id =3D X1E80100_MASTER_QUP_1, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { X1E80100_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node xm_sdc4 =3D { .name =3D "xm_sdc4", - .id =3D X1E80100_MASTER_SDCC_4, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { X1E80100_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node xm_ufs_mem =3D { .name =3D "xm_ufs_mem", - .id =3D X1E80100_MASTER_UFS_MEM, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { X1E80100_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node qhm_qup0 =3D { .name =3D "qhm_qup0", - .id =3D X1E80100_MASTER_QUP_0, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { X1E80100_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qhm_qup2 =3D { .name =3D "qhm_qup2", - .id =3D X1E80100_MASTER_QUP_2, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { X1E80100_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qxm_crypto =3D { .name =3D "qxm_crypto", - .id =3D X1E80100_MASTER_CRYPTO, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { X1E80100_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qxm_sp =3D { .name =3D "qxm_sp", - .id =3D X1E80100_MASTER_SP, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { X1E80100_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node xm_qdss_etr_0 =3D { .name =3D "xm_qdss_etr_0", - .id =3D X1E80100_MASTER_QDSS_ETR, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { X1E80100_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node xm_qdss_etr_1 =3D { .name =3D "xm_qdss_etr_1", - .id =3D X1E80100_MASTER_QDSS_ETR_1, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { X1E80100_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node xm_sdc2 =3D { .name =3D "xm_sdc2", - .id =3D X1E80100_MASTER_SDCC_2, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { X1E80100_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qup0_core_master =3D { .name =3D "qup0_core_master", - .id =3D X1E80100_MASTER_QUP_CORE_0, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { X1E80100_SLAVE_QUP_CORE_0 }, + .link_nodes =3D { &qup0_core_slave }, }; =20 static struct qcom_icc_node qup1_core_master =3D { .name =3D "qup1_core_master", - .id =3D X1E80100_MASTER_QUP_CORE_1, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { X1E80100_SLAVE_QUP_CORE_1 }, + .link_nodes =3D { &qup1_core_slave }, }; =20 static struct qcom_icc_node qup2_core_master =3D { .name =3D "qup2_core_master", - .id =3D X1E80100_MASTER_QUP_CORE_2, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { X1E80100_SLAVE_QUP_CORE_2 }, + .link_nodes =3D { &qup2_core_slave }, }; =20 static struct qcom_icc_node qsm_cfg =3D { .name =3D "qsm_cfg", - .id =3D X1E80100_MASTER_CNOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 47, - .links =3D { X1E80100_SLAVE_AHB2PHY_SOUTH, X1E80100_SLAVE_AHB2PHY_NORTH, - X1E80100_SLAVE_AHB2PHY_2, X1E80100_SLAVE_AV1_ENC_CFG, - X1E80100_SLAVE_CAMERA_CFG, X1E80100_SLAVE_CLK_CTL, - X1E80100_SLAVE_CRYPTO_0_CFG, X1E80100_SLAVE_DISPLAY_CFG, - X1E80100_SLAVE_GFX3D_CFG, X1E80100_SLAVE_IMEM_CFG, - X1E80100_SLAVE_IPC_ROUTER_CFG, X1E80100_SLAVE_PCIE_0_CFG, - X1E80100_SLAVE_PCIE_1_CFG, X1E80100_SLAVE_PCIE_2_CFG, - X1E80100_SLAVE_PCIE_3_CFG, X1E80100_SLAVE_PCIE_4_CFG, - X1E80100_SLAVE_PCIE_5_CFG, X1E80100_SLAVE_PCIE_6A_CFG, - X1E80100_SLAVE_PCIE_6B_CFG, X1E80100_SLAVE_PCIE_RSC_CFG, - X1E80100_SLAVE_PDM, X1E80100_SLAVE_PRNG, - X1E80100_SLAVE_QDSS_CFG, X1E80100_SLAVE_QSPI_0, - X1E80100_SLAVE_QUP_0, X1E80100_SLAVE_QUP_1, - X1E80100_SLAVE_QUP_2, X1E80100_SLAVE_SDCC_2, - X1E80100_SLAVE_SDCC_4, X1E80100_SLAVE_SMMUV3_CFG, - X1E80100_SLAVE_TCSR, X1E80100_SLAVE_TLMM, - X1E80100_SLAVE_UFS_MEM_CFG, X1E80100_SLAVE_USB2, - X1E80100_SLAVE_USB3_0, X1E80100_SLAVE_USB3_1, - X1E80100_SLAVE_USB3_2, X1E80100_SLAVE_USB3_MP, - X1E80100_SLAVE_USB4_0, X1E80100_SLAVE_USB4_1, - X1E80100_SLAVE_USB4_2, X1E80100_SLAVE_VENUS_CFG, - X1E80100_SLAVE_LPASS_QTB_CFG, X1E80100_SLAVE_CNOC_MNOC_CFG, - X1E80100_SLAVE_NSP_QTB_CFG, X1E80100_SLAVE_QDSS_STM, - X1E80100_SLAVE_TCU }, + .link_nodes =3D { &qhs_ahb2phy0, &qhs_ahb2phy1, + &qhs_ahb2phy2, &qhs_av1_enc_cfg, + &qhs_camera_cfg, &qhs_clk_ctl, + &qhs_crypto0_cfg, &qhs_display_cfg, + &qhs_gpuss_cfg, &qhs_imem_cfg, + &qhs_ipc_router, &qhs_pcie0_cfg, + &qhs_pcie1_cfg, &qhs_pcie2_cfg, + &qhs_pcie3_cfg, &qhs_pcie4_cfg, + &qhs_pcie5_cfg, &qhs_pcie6a_cfg, + &qhs_pcie6b_cfg, &qhs_pcie_rsc_cfg, + &qhs_pdm, &qhs_prng, + &qhs_qdss_cfg, &qhs_qspi, + &qhs_qup0, &qhs_qup1, + &qhs_qup2, &qhs_sdc2, + &qhs_sdc4, &qhs_smmuv3_cfg, + &qhs_tcsr, &qhs_tlmm, + &qhs_ufs_mem_cfg, &qhs_usb2_0_cfg, + &qhs_usb3_0_cfg, &qhs_usb3_1_cfg, + &qhs_usb3_2_cfg, &qhs_usb3_mp_cfg, + &qhs_usb4_0_cfg, &qhs_usb4_1_cfg, + &qhs_usb4_2_cfg, &qhs_venus_cfg, + &qss_lpass_qtb_cfg, &qss_mnoc_cfg, + &qss_nsp_qtb_cfg, &xs_qdss_stm, + &xs_sys_tcu_cfg }, }; =20 static struct qcom_icc_node qnm_gemnoc_cnoc =3D { .name =3D "qnm_gemnoc_cnoc", - .id =3D X1E80100_MASTER_GEM_NOC_CNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 6, - .links =3D { X1E80100_SLAVE_AOSS, X1E80100_SLAVE_TME_CFG, - X1E80100_SLAVE_APPSS, X1E80100_SLAVE_CNOC_CFG, - X1E80100_SLAVE_BOOT_IMEM, X1E80100_SLAVE_IMEM }, + .link_nodes =3D { &qhs_aoss, &qhs_tme_cfg, + &qns_apss, &qss_cfg, + &qxs_boot_imem, &qxs_imem }, }; =20 static struct qcom_icc_node qnm_gemnoc_pcie =3D { .name =3D "qnm_gemnoc_pcie", - .id =3D X1E80100_MASTER_GEM_NOC_PCIE_SNOC, .channels =3D 1, .buswidth =3D 32, .num_links =3D 8, - .links =3D { X1E80100_SLAVE_PCIE_0, X1E80100_SLAVE_PCIE_1, - X1E80100_SLAVE_PCIE_2, X1E80100_SLAVE_PCIE_3, - X1E80100_SLAVE_PCIE_4, X1E80100_SLAVE_PCIE_5, - X1E80100_SLAVE_PCIE_6A, X1E80100_SLAVE_PCIE_6B }, + .link_nodes =3D { &xs_pcie_0, &xs_pcie_1, + &xs_pcie_2, &xs_pcie_3, + &xs_pcie_4, &xs_pcie_5, + &xs_pcie_6a, &xs_pcie_6b }, }; =20 static struct qcom_icc_node alm_gpu_tcu =3D { .name =3D "alm_gpu_tcu", - .id =3D X1E80100_MASTER_GPU_TCU, .channels =3D 1, .buswidth =3D 8, .num_links =3D 2, - .links =3D { X1E80100_SLAVE_GEM_NOC_CNOC, X1E80100_SLAVE_LLCC }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; =20 static struct qcom_icc_node alm_pcie_tcu =3D { .name =3D "alm_pcie_tcu", - .id =3D X1E80100_MASTER_PCIE_TCU, .channels =3D 1, .buswidth =3D 8, .num_links =3D 2, - .links =3D { X1E80100_SLAVE_GEM_NOC_CNOC, X1E80100_SLAVE_LLCC }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; =20 static struct qcom_icc_node alm_sys_tcu =3D { .name =3D "alm_sys_tcu", - .id =3D X1E80100_MASTER_SYS_TCU, .channels =3D 1, .buswidth =3D 8, .num_links =3D 2, - .links =3D { X1E80100_SLAVE_GEM_NOC_CNOC, X1E80100_SLAVE_LLCC }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; =20 static struct qcom_icc_node chm_apps =3D { .name =3D "chm_apps", - .id =3D X1E80100_MASTER_APPSS_PROC, .channels =3D 6, .buswidth =3D 32, .num_links =3D 3, - .links =3D { X1E80100_SLAVE_GEM_NOC_CNOC, X1E80100_SLAVE_LLCC, - X1E80100_SLAVE_MEM_NOC_PCIE_SNOC }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, }; =20 static struct qcom_icc_node qnm_gpu =3D { .name =3D "qnm_gpu", - .id =3D X1E80100_MASTER_GFX3D, .channels =3D 4, .buswidth =3D 32, .num_links =3D 2, - .links =3D { X1E80100_SLAVE_GEM_NOC_CNOC, X1E80100_SLAVE_LLCC }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; =20 static struct qcom_icc_node qnm_lpass =3D { .name =3D "qnm_lpass", - .id =3D X1E80100_MASTER_LPASS_GEM_NOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 3, - .links =3D { X1E80100_SLAVE_GEM_NOC_CNOC, X1E80100_SLAVE_LLCC, - X1E80100_SLAVE_MEM_NOC_PCIE_SNOC }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, }; =20 static struct qcom_icc_node qnm_mnoc_hf =3D { .name =3D "qnm_mnoc_hf", - .id =3D X1E80100_MASTER_MNOC_HF_MEM_NOC, .channels =3D 2, .buswidth =3D 32, .num_links =3D 2, - .links =3D { X1E80100_SLAVE_GEM_NOC_CNOC, X1E80100_SLAVE_LLCC }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; =20 static struct qcom_icc_node qnm_mnoc_sf =3D { .name =3D "qnm_mnoc_sf", - .id =3D X1E80100_MASTER_MNOC_SF_MEM_NOC, .channels =3D 2, .buswidth =3D 32, .num_links =3D 2, - .links =3D { X1E80100_SLAVE_GEM_NOC_CNOC, X1E80100_SLAVE_LLCC }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; =20 static struct qcom_icc_node qnm_nsp_noc =3D { .name =3D "qnm_nsp_noc", - .id =3D X1E80100_MASTER_COMPUTE_NOC, .channels =3D 2, .buswidth =3D 32, .num_links =3D 3, - .links =3D { X1E80100_SLAVE_GEM_NOC_CNOC, X1E80100_SLAVE_LLCC, - X1E80100_SLAVE_MEM_NOC_PCIE_SNOC }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, }; =20 static struct qcom_icc_node qnm_pcie =3D { .name =3D "qnm_pcie", - .id =3D X1E80100_MASTER_ANOC_PCIE_GEM_NOC, .channels =3D 1, .buswidth =3D 64, .num_links =3D 2, - .links =3D { X1E80100_SLAVE_GEM_NOC_CNOC, X1E80100_SLAVE_LLCC }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; =20 static struct qcom_icc_node qnm_snoc_sf =3D { .name =3D "qnm_snoc_sf", - .id =3D X1E80100_MASTER_SNOC_SF_MEM_NOC, .channels =3D 1, .buswidth =3D 64, .num_links =3D 3, - .links =3D { X1E80100_SLAVE_GEM_NOC_CNOC, X1E80100_SLAVE_LLCC, - X1E80100_SLAVE_MEM_NOC_PCIE_SNOC }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, }; =20 static struct qcom_icc_node xm_gic =3D { .name =3D "xm_gic", - .id =3D X1E80100_MASTER_GIC2, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { X1E80100_SLAVE_LLCC }, + .link_nodes =3D { &qns_llcc }, }; =20 static struct qcom_icc_node qnm_lpiaon_noc =3D { .name =3D "qnm_lpiaon_noc", - .id =3D X1E80100_MASTER_LPIAON_NOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { X1E80100_SLAVE_LPASS_GEM_NOC }, + .link_nodes =3D { &qns_lpass_ag_noc_gemnoc }, }; =20 static struct qcom_icc_node qnm_lpass_lpinoc =3D { .name =3D "qnm_lpass_lpinoc", - .id =3D X1E80100_MASTER_LPASS_LPINOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { X1E80100_SLAVE_LPIAON_NOC_LPASS_AG_NOC }, + .link_nodes =3D { &qns_lpass_aggnoc }, }; =20 static struct qcom_icc_node qxm_lpinoc_dsp_axim =3D { .name =3D "qxm_lpinoc_dsp_axim", - .id =3D X1E80100_MASTER_LPASS_PROC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { X1E80100_SLAVE_LPICX_NOC_LPIAON_NOC }, + .link_nodes =3D { &qns_lpi_aon_noc }, }; =20 static struct qcom_icc_node llcc_mc =3D { .name =3D "llcc_mc", - .id =3D X1E80100_MASTER_LLCC, .channels =3D 8, .buswidth =3D 4, .num_links =3D 1, - .links =3D { X1E80100_SLAVE_EBI1 }, + .link_nodes =3D { &ebi }, }; =20 static struct qcom_icc_node qnm_av1_enc =3D { .name =3D "qnm_av1_enc", - .id =3D X1E80100_MASTER_AV1_ENC, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { X1E80100_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static struct qcom_icc_node qnm_camnoc_hf =3D { .name =3D "qnm_camnoc_hf", - .id =3D X1E80100_MASTER_CAMNOC_HF, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { X1E80100_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_hf }, }; =20 static struct qcom_icc_node qnm_camnoc_icp =3D { .name =3D "qnm_camnoc_icp", - .id =3D X1E80100_MASTER_CAMNOC_ICP, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { X1E80100_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static struct qcom_icc_node qnm_camnoc_sf =3D { .name =3D "qnm_camnoc_sf", - .id =3D X1E80100_MASTER_CAMNOC_SF, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { X1E80100_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static struct qcom_icc_node qnm_eva =3D { .name =3D "qnm_eva", - .id =3D X1E80100_MASTER_EVA, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { X1E80100_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static struct qcom_icc_node qnm_mdp =3D { .name =3D "qnm_mdp", - .id =3D X1E80100_MASTER_MDP, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { X1E80100_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_hf }, }; =20 static struct qcom_icc_node qnm_video =3D { .name =3D "qnm_video", - .id =3D X1E80100_MASTER_VIDEO, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { X1E80100_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static struct qcom_icc_node qnm_video_cv_cpu =3D { .name =3D "qnm_video_cv_cpu", - .id =3D X1E80100_MASTER_VIDEO_CV_PROC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { X1E80100_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static struct qcom_icc_node qnm_video_v_cpu =3D { .name =3D "qnm_video_v_cpu", - .id =3D X1E80100_MASTER_VIDEO_V_PROC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { X1E80100_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static struct qcom_icc_node qsm_mnoc_cfg =3D { .name =3D "qsm_mnoc_cfg", - .id =3D X1E80100_MASTER_CNOC_MNOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { X1E80100_SLAVE_SERVICE_MNOC }, + .link_nodes =3D { &srvc_mnoc }, }; =20 static struct qcom_icc_node qxm_nsp =3D { .name =3D "qxm_nsp", - .id =3D X1E80100_MASTER_CDSP_PROC, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { X1E80100_SLAVE_CDSP_MEM_NOC }, + .link_nodes =3D { &qns_nsp_gemnoc }, }; =20 static struct qcom_icc_node qnm_pcie_north_gem_noc =3D { .name =3D "qnm_pcie_north_gem_noc", - .id =3D X1E80100_MASTER_PCIE_NORTH, .channels =3D 1, .buswidth =3D 64, .num_links =3D 1, - .links =3D { X1E80100_SLAVE_ANOC_PCIE_GEM_NOC }, + .link_nodes =3D { &qns_pcie_mem_noc }, }; =20 static struct qcom_icc_node qnm_pcie_south_gem_noc =3D { .name =3D "qnm_pcie_south_gem_noc", - .id =3D X1E80100_MASTER_PCIE_SOUTH, .channels =3D 1, .buswidth =3D 64, .num_links =3D 1, - .links =3D { X1E80100_SLAVE_ANOC_PCIE_GEM_NOC }, + .link_nodes =3D { &qns_pcie_mem_noc }, }; =20 static struct qcom_icc_node xm_pcie_3 =3D { .name =3D "xm_pcie_3", - .id =3D X1E80100_MASTER_PCIE_3, .channels =3D 1, .buswidth =3D 64, .num_links =3D 1, - .links =3D { X1E80100_SLAVE_PCIE_NORTH }, + .link_nodes =3D { &qns_pcie_north_gem_noc }, }; =20 static struct qcom_icc_node xm_pcie_4 =3D { .name =3D "xm_pcie_4", - .id =3D X1E80100_MASTER_PCIE_4, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { X1E80100_SLAVE_PCIE_NORTH }, + .link_nodes =3D { &qns_pcie_north_gem_noc }, }; =20 static struct qcom_icc_node xm_pcie_5 =3D { .name =3D "xm_pcie_5", - .id =3D X1E80100_MASTER_PCIE_5, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { X1E80100_SLAVE_PCIE_NORTH }, + .link_nodes =3D { &qns_pcie_north_gem_noc }, }; =20 static struct qcom_icc_node xm_pcie_0 =3D { .name =3D "xm_pcie_0", - .id =3D X1E80100_MASTER_PCIE_0, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { X1E80100_SLAVE_PCIE_SOUTH }, + .link_nodes =3D { &qns_pcie_south_gem_noc }, }; =20 static struct qcom_icc_node xm_pcie_1 =3D { .name =3D "xm_pcie_1", - .id =3D X1E80100_MASTER_PCIE_1, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { X1E80100_SLAVE_PCIE_SOUTH }, + .link_nodes =3D { &qns_pcie_south_gem_noc }, }; =20 static struct qcom_icc_node xm_pcie_2 =3D { .name =3D "xm_pcie_2", - .id =3D X1E80100_MASTER_PCIE_2, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { X1E80100_SLAVE_PCIE_SOUTH }, + .link_nodes =3D { &qns_pcie_south_gem_noc }, }; =20 static struct qcom_icc_node xm_pcie_6a =3D { .name =3D "xm_pcie_6a", - .id =3D X1E80100_MASTER_PCIE_6A, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { X1E80100_SLAVE_PCIE_SOUTH }, + .link_nodes =3D { &qns_pcie_south_gem_noc }, }; =20 static struct qcom_icc_node xm_pcie_6b =3D { .name =3D "xm_pcie_6b", - .id =3D X1E80100_MASTER_PCIE_6B, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { X1E80100_SLAVE_PCIE_SOUTH }, + .link_nodes =3D { &qns_pcie_south_gem_noc }, }; =20 static struct qcom_icc_node qnm_aggre1_noc =3D { .name =3D "qnm_aggre1_noc", - .id =3D X1E80100_MASTER_A1NOC_SNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { X1E80100_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes =3D { &qns_gemnoc_sf }, }; =20 static struct qcom_icc_node qnm_aggre2_noc =3D { .name =3D "qnm_aggre2_noc", - .id =3D X1E80100_MASTER_A2NOC_SNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { X1E80100_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes =3D { &qns_gemnoc_sf }, }; =20 static struct qcom_icc_node qnm_gic =3D { .name =3D "qnm_gic", - .id =3D X1E80100_MASTER_GIC1, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { X1E80100_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes =3D { &qns_gemnoc_sf }, }; =20 static struct qcom_icc_node qnm_usb_anoc =3D { .name =3D "qnm_usb_anoc", - .id =3D X1E80100_MASTER_USB_NOC_SNOC, .channels =3D 1, .buswidth =3D 64, .num_links =3D 1, - .links =3D { X1E80100_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes =3D { &qns_gemnoc_sf }, }; =20 static struct qcom_icc_node qnm_aggre_usb_north_snoc =3D { .name =3D "qnm_aggre_usb_north_snoc", - .id =3D X1E80100_MASTER_AGGRE_USB_NORTH, .channels =3D 1, .buswidth =3D 64, .num_links =3D 1, - .links =3D { X1E80100_SLAVE_USB_NOC_SNOC }, + .link_nodes =3D { &qns_aggre_usb_snoc }, }; =20 static struct qcom_icc_node qnm_aggre_usb_south_snoc =3D { .name =3D "qnm_aggre_usb_south_snoc", - .id =3D X1E80100_MASTER_AGGRE_USB_SOUTH, .channels =3D 1, .buswidth =3D 64, .num_links =3D 1, - .links =3D { X1E80100_SLAVE_USB_NOC_SNOC }, + .link_nodes =3D { &qns_aggre_usb_snoc }, }; =20 static struct qcom_icc_node xm_usb2_0 =3D { .name =3D "xm_usb2_0", - .id =3D X1E80100_MASTER_USB2, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { X1E80100_SLAVE_AGGRE_USB_NORTH }, + .link_nodes =3D { &qns_aggre_usb_north_snoc }, }; =20 static struct qcom_icc_node xm_usb3_mp =3D { .name =3D "xm_usb3_mp", - .id =3D X1E80100_MASTER_USB3_MP, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { X1E80100_SLAVE_AGGRE_USB_NORTH }, + .link_nodes =3D { &qns_aggre_usb_north_snoc }, }; =20 static struct qcom_icc_node xm_usb3_0 =3D { .name =3D "xm_usb3_0", - .id =3D X1E80100_MASTER_USB3_0, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { X1E80100_SLAVE_AGGRE_USB_SOUTH }, + .link_nodes =3D { &qns_aggre_usb_south_snoc }, }; =20 static struct qcom_icc_node xm_usb3_1 =3D { .name =3D "xm_usb3_1", - .id =3D X1E80100_MASTER_USB3_1, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { X1E80100_SLAVE_AGGRE_USB_SOUTH }, + .link_nodes =3D { &qns_aggre_usb_south_snoc }, }; =20 static struct qcom_icc_node xm_usb3_2 =3D { .name =3D "xm_usb3_2", - .id =3D X1E80100_MASTER_USB3_2, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { X1E80100_SLAVE_AGGRE_USB_SOUTH }, + .link_nodes =3D { &qns_aggre_usb_south_snoc }, }; =20 static struct qcom_icc_node xm_usb4_0 =3D { .name =3D "xm_usb4_0", - .id =3D X1E80100_MASTER_USB4_0, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { X1E80100_SLAVE_AGGRE_USB_SOUTH }, + .link_nodes =3D { &qns_aggre_usb_south_snoc }, }; =20 static struct qcom_icc_node xm_usb4_1 =3D { .name =3D "xm_usb4_1", - .id =3D X1E80100_MASTER_USB4_1, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { X1E80100_SLAVE_AGGRE_USB_SOUTH }, + .link_nodes =3D { &qns_aggre_usb_south_snoc }, }; =20 static struct qcom_icc_node xm_usb4_2 =3D { .name =3D "xm_usb4_2", - .id =3D X1E80100_MASTER_USB4_2, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { X1E80100_SLAVE_AGGRE_USB_SOUTH }, + .link_nodes =3D { &qns_aggre_usb_south_snoc }, }; =20 static struct qcom_icc_node qns_a1noc_snoc =3D { .name =3D "qns_a1noc_snoc", - .id =3D X1E80100_SLAVE_A1NOC_SNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { X1E80100_MASTER_A1NOC_SNOC }, + .link_nodes =3D { &qnm_aggre1_noc }, }; =20 static struct qcom_icc_node qns_a2noc_snoc =3D { .name =3D "qns_a2noc_snoc", - .id =3D X1E80100_SLAVE_A2NOC_SNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { X1E80100_MASTER_A2NOC_SNOC }, + .link_nodes =3D { &qnm_aggre2_noc }, }; =20 static struct qcom_icc_node qup0_core_slave =3D { .name =3D "qup0_core_slave", - .id =3D X1E80100_SLAVE_QUP_CORE_0, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qup1_core_slave =3D { .name =3D "qup1_core_slave", - .id =3D X1E80100_SLAVE_QUP_CORE_1, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qup2_core_slave =3D { .name =3D "qup2_core_slave", - .id =3D X1E80100_SLAVE_QUP_CORE_2, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_ahb2phy0 =3D { .name =3D "qhs_ahb2phy0", - .id =3D X1E80100_SLAVE_AHB2PHY_SOUTH, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_ahb2phy1 =3D { .name =3D "qhs_ahb2phy1", - .id =3D X1E80100_SLAVE_AHB2PHY_NORTH, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_ahb2phy2 =3D { .name =3D "qhs_ahb2phy2", - .id =3D X1E80100_SLAVE_AHB2PHY_2, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_av1_enc_cfg =3D { .name =3D "qhs_av1_enc_cfg", - .id =3D X1E80100_SLAVE_AV1_ENC_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_camera_cfg =3D { .name =3D "qhs_camera_cfg", - .id =3D X1E80100_SLAVE_CAMERA_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_clk_ctl =3D { .name =3D "qhs_clk_ctl", - .id =3D X1E80100_SLAVE_CLK_CTL, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_crypto0_cfg =3D { .name =3D "qhs_crypto0_cfg", - .id =3D X1E80100_SLAVE_CRYPTO_0_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_display_cfg =3D { .name =3D "qhs_display_cfg", - .id =3D X1E80100_SLAVE_DISPLAY_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_gpuss_cfg =3D { .name =3D "qhs_gpuss_cfg", - .id =3D X1E80100_SLAVE_GFX3D_CFG, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_imem_cfg =3D { .name =3D "qhs_imem_cfg", - .id =3D X1E80100_SLAVE_IMEM_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_ipc_router =3D { .name =3D "qhs_ipc_router", - .id =3D X1E80100_SLAVE_IPC_ROUTER_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_pcie0_cfg =3D { .name =3D "qhs_pcie0_cfg", - .id =3D X1E80100_SLAVE_PCIE_0_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_pcie1_cfg =3D { .name =3D "qhs_pcie1_cfg", - .id =3D X1E80100_SLAVE_PCIE_1_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_pcie2_cfg =3D { .name =3D "qhs_pcie2_cfg", - .id =3D X1E80100_SLAVE_PCIE_2_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_pcie3_cfg =3D { .name =3D "qhs_pcie3_cfg", - .id =3D X1E80100_SLAVE_PCIE_3_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_pcie4_cfg =3D { .name =3D "qhs_pcie4_cfg", - .id =3D X1E80100_SLAVE_PCIE_4_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_pcie5_cfg =3D { .name =3D "qhs_pcie5_cfg", - .id =3D X1E80100_SLAVE_PCIE_5_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_pcie6a_cfg =3D { .name =3D "qhs_pcie6a_cfg", - .id =3D X1E80100_SLAVE_PCIE_6A_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_pcie6b_cfg =3D { .name =3D "qhs_pcie6b_cfg", - .id =3D X1E80100_SLAVE_PCIE_6B_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_pcie_rsc_cfg =3D { .name =3D "qhs_pcie_rsc_cfg", - .id =3D X1E80100_SLAVE_PCIE_RSC_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_pdm =3D { .name =3D "qhs_pdm", - .id =3D X1E80100_SLAVE_PDM, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_prng =3D { .name =3D "qhs_prng", - .id =3D X1E80100_SLAVE_PRNG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_qdss_cfg =3D { .name =3D "qhs_qdss_cfg", - .id =3D X1E80100_SLAVE_QDSS_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_qspi =3D { .name =3D "qhs_qspi", - .id =3D X1E80100_SLAVE_QSPI_0, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_qup0 =3D { .name =3D "qhs_qup0", - .id =3D X1E80100_SLAVE_QUP_0, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_qup1 =3D { .name =3D "qhs_qup1", - .id =3D X1E80100_SLAVE_QUP_1, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_qup2 =3D { .name =3D "qhs_qup2", - .id =3D X1E80100_SLAVE_QUP_2, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_sdc2 =3D { .name =3D "qhs_sdc2", - .id =3D X1E80100_SLAVE_SDCC_2, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_sdc4 =3D { .name =3D "qhs_sdc4", - .id =3D X1E80100_SLAVE_SDCC_4, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_smmuv3_cfg =3D { .name =3D "qhs_smmuv3_cfg", - .id =3D X1E80100_SLAVE_SMMUV3_CFG, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_tcsr =3D { .name =3D "qhs_tcsr", - .id =3D X1E80100_SLAVE_TCSR, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_tlmm =3D { .name =3D "qhs_tlmm", - .id =3D X1E80100_SLAVE_TLMM, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_ufs_mem_cfg =3D { .name =3D "qhs_ufs_mem_cfg", - .id =3D X1E80100_SLAVE_UFS_MEM_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_usb2_0_cfg =3D { .name =3D "qhs_usb2_0_cfg", - .id =3D X1E80100_SLAVE_USB2, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_usb3_0_cfg =3D { .name =3D "qhs_usb3_0_cfg", - .id =3D X1E80100_SLAVE_USB3_0, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_usb3_1_cfg =3D { .name =3D "qhs_usb3_1_cfg", - .id =3D X1E80100_SLAVE_USB3_1, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_usb3_2_cfg =3D { .name =3D "qhs_usb3_2_cfg", - .id =3D X1E80100_SLAVE_USB3_2, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_usb3_mp_cfg =3D { .name =3D "qhs_usb3_mp_cfg", - .id =3D X1E80100_SLAVE_USB3_MP, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_usb4_0_cfg =3D { .name =3D "qhs_usb4_0_cfg", - .id =3D X1E80100_SLAVE_USB4_0, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_usb4_1_cfg =3D { .name =3D "qhs_usb4_1_cfg", - .id =3D X1E80100_SLAVE_USB4_1, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_usb4_2_cfg =3D { .name =3D "qhs_usb4_2_cfg", - .id =3D X1E80100_SLAVE_USB4_2, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_venus_cfg =3D { .name =3D "qhs_venus_cfg", - .id =3D X1E80100_SLAVE_VENUS_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qss_lpass_qtb_cfg =3D { .name =3D "qss_lpass_qtb_cfg", - .id =3D X1E80100_SLAVE_LPASS_QTB_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qss_mnoc_cfg =3D { .name =3D "qss_mnoc_cfg", - .id =3D X1E80100_SLAVE_CNOC_MNOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { X1E80100_MASTER_CNOC_MNOC_CFG }, + .link_nodes =3D { &qsm_mnoc_cfg }, }; =20 static struct qcom_icc_node qss_nsp_qtb_cfg =3D { .name =3D "qss_nsp_qtb_cfg", - .id =3D X1E80100_SLAVE_NSP_QTB_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node xs_qdss_stm =3D { .name =3D "xs_qdss_stm", - .id =3D X1E80100_SLAVE_QDSS_STM, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node xs_sys_tcu_cfg =3D { .name =3D "xs_sys_tcu_cfg", - .id =3D X1E80100_SLAVE_TCU, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_aoss =3D { .name =3D "qhs_aoss", - .id =3D X1E80100_SLAVE_AOSS, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_tme_cfg =3D { .name =3D "qhs_tme_cfg", - .id =3D X1E80100_SLAVE_TME_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qns_apss =3D { .name =3D "qns_apss", - .id =3D X1E80100_SLAVE_APPSS, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 0, }; =20 static struct qcom_icc_node qss_cfg =3D { .name =3D "qss_cfg", - .id =3D X1E80100_SLAVE_CNOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { X1E80100_MASTER_CNOC_CFG }, + .link_nodes =3D { &qsm_cfg }, }; =20 static struct qcom_icc_node qxs_boot_imem =3D { .name =3D "qxs_boot_imem", - .id =3D X1E80100_SLAVE_BOOT_IMEM, .channels =3D 1, .buswidth =3D 16, - .num_links =3D 0, }; =20 static struct qcom_icc_node qxs_imem =3D { .name =3D "qxs_imem", - .id =3D X1E80100_SLAVE_IMEM, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 0, }; =20 static struct qcom_icc_node xs_pcie_0 =3D { .name =3D "xs_pcie_0", - .id =3D X1E80100_SLAVE_PCIE_0, .channels =3D 1, .buswidth =3D 16, - .num_links =3D 0, }; =20 static struct qcom_icc_node xs_pcie_1 =3D { .name =3D "xs_pcie_1", - .id =3D X1E80100_SLAVE_PCIE_1, .channels =3D 1, .buswidth =3D 16, - .num_links =3D 0, }; =20 static struct qcom_icc_node xs_pcie_2 =3D { .name =3D "xs_pcie_2", - .id =3D X1E80100_SLAVE_PCIE_2, .channels =3D 1, .buswidth =3D 16, - .num_links =3D 0, }; =20 static struct qcom_icc_node xs_pcie_3 =3D { .name =3D "xs_pcie_3", - .id =3D X1E80100_SLAVE_PCIE_3, .channels =3D 1, .buswidth =3D 64, - .num_links =3D 0, }; =20 static struct qcom_icc_node xs_pcie_4 =3D { .name =3D "xs_pcie_4", - .id =3D X1E80100_SLAVE_PCIE_4, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 0, }; =20 static struct qcom_icc_node xs_pcie_5 =3D { .name =3D "xs_pcie_5", - .id =3D X1E80100_SLAVE_PCIE_5, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 0, }; =20 static struct qcom_icc_node xs_pcie_6a =3D { .name =3D "xs_pcie_6a", - .id =3D X1E80100_SLAVE_PCIE_6A, .channels =3D 1, .buswidth =3D 32, - .num_links =3D 0, }; =20 static struct qcom_icc_node xs_pcie_6b =3D { .name =3D "xs_pcie_6b", - .id =3D X1E80100_SLAVE_PCIE_6B, .channels =3D 1, .buswidth =3D 16, - .num_links =3D 0, }; =20 static struct qcom_icc_node qns_gem_noc_cnoc =3D { .name =3D "qns_gem_noc_cnoc", - .id =3D X1E80100_SLAVE_GEM_NOC_CNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { X1E80100_MASTER_GEM_NOC_CNOC }, + .link_nodes =3D { &qnm_gemnoc_cnoc }, }; =20 static struct qcom_icc_node qns_llcc =3D { .name =3D "qns_llcc", - .id =3D X1E80100_SLAVE_LLCC, .channels =3D 8, .buswidth =3D 16, .num_links =3D 1, - .links =3D { X1E80100_MASTER_LLCC }, + .link_nodes =3D { &llcc_mc }, }; =20 static struct qcom_icc_node qns_pcie =3D { .name =3D "qns_pcie", - .id =3D X1E80100_SLAVE_MEM_NOC_PCIE_SNOC, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { X1E80100_MASTER_GEM_NOC_PCIE_SNOC }, + .link_nodes =3D { &qnm_gemnoc_pcie }, }; =20 static struct qcom_icc_node qns_lpass_ag_noc_gemnoc =3D { .name =3D "qns_lpass_ag_noc_gemnoc", - .id =3D X1E80100_SLAVE_LPASS_GEM_NOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { X1E80100_MASTER_LPASS_GEM_NOC }, + .link_nodes =3D { &qnm_lpass }, }; =20 static struct qcom_icc_node qns_lpass_aggnoc =3D { .name =3D "qns_lpass_aggnoc", - .id =3D X1E80100_SLAVE_LPIAON_NOC_LPASS_AG_NOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { X1E80100_MASTER_LPIAON_NOC }, + .link_nodes =3D { &qnm_lpiaon_noc }, }; =20 static struct qcom_icc_node qns_lpi_aon_noc =3D { .name =3D "qns_lpi_aon_noc", - .id =3D X1E80100_SLAVE_LPICX_NOC_LPIAON_NOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { X1E80100_MASTER_LPASS_LPINOC }, + .link_nodes =3D { &qnm_lpass_lpinoc }, }; =20 static struct qcom_icc_node ebi =3D { .name =3D "ebi", - .id =3D X1E80100_SLAVE_EBI1, .channels =3D 8, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qns_mem_noc_hf =3D { .name =3D "qns_mem_noc_hf", - .id =3D X1E80100_SLAVE_MNOC_HF_MEM_NOC, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { X1E80100_MASTER_MNOC_HF_MEM_NOC }, + .link_nodes =3D { &qnm_mnoc_hf }, }; =20 static struct qcom_icc_node qns_mem_noc_sf =3D { .name =3D "qns_mem_noc_sf", - .id =3D X1E80100_SLAVE_MNOC_SF_MEM_NOC, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { X1E80100_MASTER_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qnm_mnoc_sf }, }; =20 static struct qcom_icc_node srvc_mnoc =3D { .name =3D "srvc_mnoc", - .id =3D X1E80100_SLAVE_SERVICE_MNOC, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qns_nsp_gemnoc =3D { .name =3D "qns_nsp_gemnoc", - .id =3D X1E80100_SLAVE_CDSP_MEM_NOC, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { X1E80100_MASTER_COMPUTE_NOC }, + .link_nodes =3D { &qnm_nsp_noc }, }; =20 static struct qcom_icc_node qns_pcie_mem_noc =3D { .name =3D "qns_pcie_mem_noc", - .id =3D X1E80100_SLAVE_ANOC_PCIE_GEM_NOC, .channels =3D 1, .buswidth =3D 64, .num_links =3D 1, - .links =3D { X1E80100_MASTER_ANOC_PCIE_GEM_NOC }, + .link_nodes =3D { &qnm_pcie }, }; =20 static struct qcom_icc_node qns_pcie_north_gem_noc =3D { .name =3D "qns_pcie_north_gem_noc", - .id =3D X1E80100_SLAVE_PCIE_NORTH, .channels =3D 1, .buswidth =3D 64, .num_links =3D 1, - .links =3D { X1E80100_MASTER_PCIE_NORTH }, + .link_nodes =3D { &qnm_pcie_north_gem_noc }, }; =20 static struct qcom_icc_node qns_pcie_south_gem_noc =3D { .name =3D "qns_pcie_south_gem_noc", - .id =3D X1E80100_SLAVE_PCIE_SOUTH, .channels =3D 1, .buswidth =3D 64, .num_links =3D 1, - .links =3D { X1E80100_MASTER_PCIE_SOUTH }, + .link_nodes =3D { &qnm_pcie_south_gem_noc }, }; =20 static struct qcom_icc_node qns_gemnoc_sf =3D { .name =3D "qns_gemnoc_sf", - .id =3D X1E80100_SLAVE_SNOC_GEM_NOC_SF, .channels =3D 1, .buswidth =3D 64, .num_links =3D 1, - .links =3D { X1E80100_MASTER_SNOC_SF_MEM_NOC }, + .link_nodes =3D { &qnm_snoc_sf }, }; =20 static struct qcom_icc_node qns_aggre_usb_snoc =3D { .name =3D "qns_aggre_usb_snoc", - .id =3D X1E80100_SLAVE_USB_NOC_SNOC, .channels =3D 1, .buswidth =3D 64, .num_links =3D 1, - .links =3D { X1E80100_MASTER_USB_NOC_SNOC }, + .link_nodes =3D { &qnm_usb_anoc }, }; =20 static struct qcom_icc_node qns_aggre_usb_north_snoc =3D { .name =3D "qns_aggre_usb_north_snoc", - .id =3D X1E80100_SLAVE_AGGRE_USB_NORTH, .channels =3D 1, .buswidth =3D 64, .num_links =3D 1, - .links =3D { X1E80100_MASTER_AGGRE_USB_NORTH }, + .link_nodes =3D { &qnm_aggre_usb_north_snoc }, }; =20 static struct qcom_icc_node qns_aggre_usb_south_snoc =3D { .name =3D "qns_aggre_usb_south_snoc", - .id =3D X1E80100_SLAVE_AGGRE_USB_SOUTH, .channels =3D 1, .buswidth =3D 64, .num_links =3D 1, - .links =3D { X1E80100_MASTER_AGGRE_USB_SOUTH }, + .link_nodes =3D { &qnm_aggre_usb_south_snoc }, }; =20 static struct qcom_icc_bcm bcm_acv =3D { @@ -1531,6 +1467,7 @@ static struct qcom_icc_node * const aggre1_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc x1e80100_aggre1_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D aggre1_noc_nodes, .num_nodes =3D ARRAY_SIZE(aggre1_noc_nodes), .bcms =3D aggre1_noc_bcms, @@ -1553,6 +1490,7 @@ static struct qcom_icc_node * const aggre2_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc x1e80100_aggre2_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D aggre2_noc_nodes, .num_nodes =3D ARRAY_SIZE(aggre2_noc_nodes), .bcms =3D aggre2_noc_bcms, @@ -1575,6 +1513,7 @@ static struct qcom_icc_node * const clk_virt_nodes[] = =3D { }; =20 static const struct qcom_icc_desc x1e80100_clk_virt =3D { + .alloc_dyn_id =3D true, .nodes =3D clk_virt_nodes, .num_nodes =3D ARRAY_SIZE(clk_virt_nodes), .bcms =3D clk_virt_bcms, @@ -1638,6 +1577,7 @@ static struct qcom_icc_node * const cnoc_cfg_nodes[] = =3D { }; =20 static const struct qcom_icc_desc x1e80100_cnoc_cfg =3D { + .alloc_dyn_id =3D true, .nodes =3D cnoc_cfg_nodes, .num_nodes =3D ARRAY_SIZE(cnoc_cfg_nodes), .bcms =3D cnoc_cfg_bcms, @@ -1668,6 +1608,7 @@ static struct qcom_icc_node * const cnoc_main_nodes[]= =3D { }; =20 static const struct qcom_icc_desc x1e80100_cnoc_main =3D { + .alloc_dyn_id =3D true, .nodes =3D cnoc_main_nodes, .num_nodes =3D ARRAY_SIZE(cnoc_main_nodes), .bcms =3D cnoc_main_bcms, @@ -1698,6 +1639,7 @@ static struct qcom_icc_node * const gem_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc x1e80100_gem_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D gem_noc_nodes, .num_nodes =3D ARRAY_SIZE(gem_noc_nodes), .bcms =3D gem_noc_bcms, @@ -1713,6 +1655,7 @@ static struct qcom_icc_node * const lpass_ag_noc_node= s[] =3D { }; =20 static const struct qcom_icc_desc x1e80100_lpass_ag_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D lpass_ag_noc_nodes, .num_nodes =3D ARRAY_SIZE(lpass_ag_noc_nodes), .bcms =3D lpass_ag_noc_bcms, @@ -1729,6 +1672,7 @@ static struct qcom_icc_node * const lpass_lpiaon_noc_= nodes[] =3D { }; =20 static const struct qcom_icc_desc x1e80100_lpass_lpiaon_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D lpass_lpiaon_noc_nodes, .num_nodes =3D ARRAY_SIZE(lpass_lpiaon_noc_nodes), .bcms =3D lpass_lpiaon_noc_bcms, @@ -1744,6 +1688,7 @@ static struct qcom_icc_node * const lpass_lpicx_noc_n= odes[] =3D { }; =20 static const struct qcom_icc_desc x1e80100_lpass_lpicx_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D lpass_lpicx_noc_nodes, .num_nodes =3D ARRAY_SIZE(lpass_lpicx_noc_nodes), .bcms =3D lpass_lpicx_noc_bcms, @@ -1761,6 +1706,7 @@ static struct qcom_icc_node * const mc_virt_nodes[] = =3D { }; =20 static const struct qcom_icc_desc x1e80100_mc_virt =3D { + .alloc_dyn_id =3D true, .nodes =3D mc_virt_nodes, .num_nodes =3D ARRAY_SIZE(mc_virt_nodes), .bcms =3D mc_virt_bcms, @@ -1789,6 +1735,7 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc x1e80100_mmss_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D mmss_noc_nodes, .num_nodes =3D ARRAY_SIZE(mmss_noc_nodes), .bcms =3D mmss_noc_bcms, @@ -1805,6 +1752,7 @@ static struct qcom_icc_node * const nsp_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc x1e80100_nsp_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D nsp_noc_nodes, .num_nodes =3D ARRAY_SIZE(nsp_noc_nodes), .bcms =3D nsp_noc_bcms, @@ -1822,6 +1770,7 @@ static struct qcom_icc_node * const pcie_center_anoc_= nodes[] =3D { }; =20 static const struct qcom_icc_desc x1e80100_pcie_center_anoc =3D { + .alloc_dyn_id =3D true, .nodes =3D pcie_center_anoc_nodes, .num_nodes =3D ARRAY_SIZE(pcie_center_anoc_nodes), .bcms =3D pcie_center_anoc_bcms, @@ -1839,6 +1788,7 @@ static struct qcom_icc_node * const pcie_north_anoc_n= odes[] =3D { }; =20 static const struct qcom_icc_desc x1e80100_pcie_north_anoc =3D { + .alloc_dyn_id =3D true, .nodes =3D pcie_north_anoc_nodes, .num_nodes =3D ARRAY_SIZE(pcie_north_anoc_nodes), .bcms =3D pcie_north_anoc_bcms, @@ -1858,6 +1808,7 @@ static struct qcom_icc_node * const pcie_south_anoc_n= odes[] =3D { }; =20 static const struct qcom_icc_desc x1e80100_pcie_south_anoc =3D { + .alloc_dyn_id =3D true, .nodes =3D pcie_south_anoc_nodes, .num_nodes =3D ARRAY_SIZE(pcie_south_anoc_nodes), .bcms =3D pcie_south_anoc_bcms, @@ -1880,6 +1831,7 @@ static struct qcom_icc_node * const system_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc x1e80100_system_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D system_noc_nodes, .num_nodes =3D ARRAY_SIZE(system_noc_nodes), .bcms =3D system_noc_bcms, @@ -1896,6 +1848,7 @@ static struct qcom_icc_node * const usb_center_anoc_n= odes[] =3D { }; =20 static const struct qcom_icc_desc x1e80100_usb_center_anoc =3D { + .alloc_dyn_id =3D true, .nodes =3D usb_center_anoc_nodes, .num_nodes =3D ARRAY_SIZE(usb_center_anoc_nodes), .bcms =3D usb_center_anoc_bcms, @@ -1912,6 +1865,7 @@ static struct qcom_icc_node * const usb_north_anoc_no= des[] =3D { }; =20 static const struct qcom_icc_desc x1e80100_usb_north_anoc =3D { + .alloc_dyn_id =3D true, .nodes =3D usb_north_anoc_nodes, .num_nodes =3D ARRAY_SIZE(usb_north_anoc_nodes), .bcms =3D usb_north_anoc_bcms, @@ -1932,6 +1886,7 @@ static struct qcom_icc_node * const usb_south_anoc_no= des[] =3D { }; =20 static const struct qcom_icc_desc x1e80100_usb_south_anoc =3D { + .alloc_dyn_id =3D true, .nodes =3D usb_south_anoc_nodes, .num_nodes =3D ARRAY_SIZE(usb_south_anoc_nodes), .bcms =3D usb_south_anoc_bcms, diff --git a/drivers/interconnect/qcom/x1e80100.h b/drivers/interconnect/qc= om/x1e80100.h deleted file mode 100644 index 2e14264f4c2b01d6c4e3fe63a5f5252dc6d29641..000000000000000000000000000= 0000000000000 --- a/drivers/interconnect/qcom/x1e80100.h +++ /dev/null @@ -1,192 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * X1E80100 interconnect IDs - * - * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. - * Copyright (c) 2023, Linaro Limited - */ - -#ifndef __DRIVERS_INTERCONNECT_QCOM_X1E80100_H -#define __DRIVERS_INTERCONNECT_QCOM_X1E80100_H - -#define X1E80100_MASTER_A1NOC_SNOC 0 -#define X1E80100_MASTER_A2NOC_SNOC 1 -#define X1E80100_MASTER_ANOC_PCIE_GEM_NOC 2 -#define X1E80100_MASTER_ANOC_PCIE_GEM_NOC_DISP 3 -#define X1E80100_MASTER_APPSS_PROC 4 -#define X1E80100_MASTER_CAMNOC_HF 5 -#define X1E80100_MASTER_CAMNOC_ICP 6 -#define X1E80100_MASTER_CAMNOC_SF 7 -#define X1E80100_MASTER_CDSP_PROC 8 -#define X1E80100_MASTER_CNOC_CFG 9 -#define X1E80100_MASTER_CNOC_MNOC_CFG 10 -#define X1E80100_MASTER_COMPUTE_NOC 11 -#define X1E80100_MASTER_CRYPTO 12 -#define X1E80100_MASTER_GEM_NOC_CNOC 13 -#define X1E80100_MASTER_GEM_NOC_PCIE_SNOC 14 -#define X1E80100_MASTER_GFX3D 15 -#define X1E80100_MASTER_GPU_TCU 16 -#define X1E80100_MASTER_IPA 17 -#define X1E80100_MASTER_LLCC 18 -#define X1E80100_MASTER_LLCC_DISP 19 -#define X1E80100_MASTER_LPASS_GEM_NOC 20 -#define X1E80100_MASTER_LPASS_LPINOC 21 -#define X1E80100_MASTER_LPASS_PROC 22 -#define X1E80100_MASTER_LPIAON_NOC 23 -#define X1E80100_MASTER_MDP 24 -#define X1E80100_MASTER_MDP_DISP 25 -#define X1E80100_MASTER_MNOC_HF_MEM_NOC 26 -#define X1E80100_MASTER_MNOC_HF_MEM_NOC_DISP 27 -#define X1E80100_MASTER_MNOC_SF_MEM_NOC 28 -#define X1E80100_MASTER_PCIE_0 29 -#define X1E80100_MASTER_PCIE_1 30 -#define X1E80100_MASTER_QDSS_ETR 31 -#define X1E80100_MASTER_QDSS_ETR_1 32 -#define X1E80100_MASTER_QSPI_0 33 -#define X1E80100_MASTER_QUP_0 34 -#define X1E80100_MASTER_QUP_1 35 -#define X1E80100_MASTER_QUP_2 36 -#define X1E80100_MASTER_QUP_CORE_0 37 -#define X1E80100_MASTER_QUP_CORE_1 38 -#define X1E80100_MASTER_SDCC_2 39 -#define X1E80100_MASTER_SDCC_4 40 -#define X1E80100_MASTER_SNOC_SF_MEM_NOC 41 -#define X1E80100_MASTER_SP 42 -#define X1E80100_MASTER_SYS_TCU 43 -#define X1E80100_MASTER_UFS_MEM 44 -#define X1E80100_MASTER_USB3_0 45 -#define X1E80100_MASTER_VIDEO 46 -#define X1E80100_MASTER_VIDEO_CV_PROC 47 -#define X1E80100_MASTER_VIDEO_V_PROC 48 -#define X1E80100_SLAVE_A1NOC_SNOC 49 -#define X1E80100_SLAVE_A2NOC_SNOC 50 -#define X1E80100_SLAVE_AHB2PHY_NORTH 51 -#define X1E80100_SLAVE_AHB2PHY_SOUTH 52 -#define X1E80100_SLAVE_ANOC_PCIE_GEM_NOC 53 -#define X1E80100_SLAVE_AOSS 54 -#define X1E80100_SLAVE_APPSS 55 -#define X1E80100_SLAVE_BOOT_IMEM 56 -#define X1E80100_SLAVE_CAMERA_CFG 57 -#define X1E80100_SLAVE_CDSP_MEM_NOC 58 -#define X1E80100_SLAVE_CLK_CTL 59 -#define X1E80100_SLAVE_CNOC_CFG 60 -#define X1E80100_SLAVE_CNOC_MNOC_CFG 61 -#define X1E80100_SLAVE_CRYPTO_0_CFG 62 -#define X1E80100_SLAVE_DISPLAY_CFG 63 -#define X1E80100_SLAVE_EBI1 64 -#define X1E80100_SLAVE_EBI1_DISP 65 -#define X1E80100_SLAVE_GEM_NOC_CNOC 66 -#define X1E80100_SLAVE_GFX3D_CFG 67 -#define X1E80100_SLAVE_IMEM 68 -#define X1E80100_SLAVE_IMEM_CFG 69 -#define X1E80100_SLAVE_IPC_ROUTER_CFG 70 -#define X1E80100_SLAVE_LLCC 71 -#define X1E80100_SLAVE_LLCC_DISP 72 -#define X1E80100_SLAVE_LPASS_GEM_NOC 73 -#define X1E80100_SLAVE_LPASS_QTB_CFG 74 -#define X1E80100_SLAVE_LPIAON_NOC_LPASS_AG_NOC 75 -#define X1E80100_SLAVE_LPICX_NOC_LPIAON_NOC 76 -#define X1E80100_SLAVE_MEM_NOC_PCIE_SNOC 77 -#define X1E80100_SLAVE_MNOC_HF_MEM_NOC 78 -#define X1E80100_SLAVE_MNOC_HF_MEM_NOC_DISP 79 -#define X1E80100_SLAVE_MNOC_SF_MEM_NOC 80 -#define X1E80100_SLAVE_NSP_QTB_CFG 81 -#define X1E80100_SLAVE_PCIE_0 82 -#define X1E80100_SLAVE_PCIE_0_CFG 83 -#define X1E80100_SLAVE_PCIE_1 84 -#define X1E80100_SLAVE_PCIE_1_CFG 85 -#define X1E80100_SLAVE_PDM 86 -#define X1E80100_SLAVE_PRNG 87 -#define X1E80100_SLAVE_QDSS_CFG 88 -#define X1E80100_SLAVE_QDSS_STM 89 -#define X1E80100_SLAVE_QSPI_0 90 -#define X1E80100_SLAVE_QUP_1 91 -#define X1E80100_SLAVE_QUP_2 92 -#define X1E80100_SLAVE_QUP_CORE_0 93 -#define X1E80100_SLAVE_QUP_CORE_1 94 -#define X1E80100_SLAVE_QUP_CORE_2 95 -#define X1E80100_SLAVE_SDCC_2 96 -#define X1E80100_SLAVE_SDCC_4 97 -#define X1E80100_SLAVE_SERVICE_MNOC 98 -#define X1E80100_SLAVE_SNOC_GEM_NOC_SF 99 -#define X1E80100_SLAVE_TCSR 100 -#define X1E80100_SLAVE_TCU 101 -#define X1E80100_SLAVE_TLMM 102 -#define X1E80100_SLAVE_TME_CFG 103 -#define X1E80100_SLAVE_UFS_MEM_CFG 104 -#define X1E80100_SLAVE_USB3_0 105 -#define X1E80100_SLAVE_VENUS_CFG 106 -#define X1E80100_MASTER_DDR_PERF_MODE 107 -#define X1E80100_MASTER_QUP_CORE_2 108 -#define X1E80100_MASTER_PCIE_TCU 109 -#define X1E80100_MASTER_GIC2 110 -#define X1E80100_MASTER_AV1_ENC 111 -#define X1E80100_MASTER_EVA 112 -#define X1E80100_MASTER_PCIE_NORTH 113 -#define X1E80100_MASTER_PCIE_SOUTH 114 -#define X1E80100_MASTER_PCIE_3 115 -#define X1E80100_MASTER_PCIE_4 116 -#define X1E80100_MASTER_PCIE_5 117 -#define X1E80100_MASTER_PCIE_2 118 -#define X1E80100_MASTER_PCIE_6A 119 -#define X1E80100_MASTER_PCIE_6B 120 -#define X1E80100_MASTER_GIC1 121 -#define X1E80100_MASTER_USB_NOC_SNOC 122 -#define X1E80100_MASTER_AGGRE_USB_NORTH 123 -#define X1E80100_MASTER_AGGRE_USB_SOUTH 124 -#define X1E80100_MASTER_USB2 125 -#define X1E80100_MASTER_USB3_MP 126 -#define X1E80100_MASTER_USB3_1 127 -#define X1E80100_MASTER_USB3_2 128 -#define X1E80100_MASTER_USB4_0 129 -#define X1E80100_MASTER_USB4_1 130 -#define X1E80100_MASTER_USB4_2 131 -#define X1E80100_MASTER_ANOC_PCIE_GEM_NOC_PCIE 132 -#define X1E80100_MASTER_LLCC_PCIE 133 -#define X1E80100_MASTER_PCIE_NORTH_PCIE 134 -#define X1E80100_MASTER_PCIE_SOUTH_PCIE 135 -#define X1E80100_MASTER_PCIE_3_PCIE 136 -#define X1E80100_MASTER_PCIE_4_PCIE 137 -#define X1E80100_MASTER_PCIE_5_PCIE 138 -#define X1E80100_MASTER_PCIE_0_PCIE 139 -#define X1E80100_MASTER_PCIE_1_PCIE 140 -#define X1E80100_MASTER_PCIE_2_PCIE 141 -#define X1E80100_MASTER_PCIE_6A_PCIE 142 -#define X1E80100_MASTER_PCIE_6B_PCIE 143 -#define X1E80100_SLAVE_AHB2PHY_2 144 -#define X1E80100_SLAVE_AV1_ENC_CFG 145 -#define X1E80100_SLAVE_PCIE_2_CFG 146 -#define X1E80100_SLAVE_PCIE_3_CFG 147 -#define X1E80100_SLAVE_PCIE_4_CFG 148 -#define X1E80100_SLAVE_PCIE_5_CFG 149 -#define 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This gives more flexibility and also allows us to drop the .num_links member, saving from possible errors related to it being not set or set incorrectly. Signed-off-by: Dmitry Baryshkov --- drivers/interconnect/qcom/qcs615.c | 519 +++++++++++++++++----------------= ---- drivers/interconnect/qcom/qcs615.h | 128 --------- 2 files changed, 239 insertions(+), 408 deletions(-) diff --git a/drivers/interconnect/qcom/qcs615.c b/drivers/interconnect/qcom= /qcs615.c index 0549cfcbac64e4284ae5df1de3683985fffdcac8..fb0f623c0e645dce540afb9857c= 6f11a24a70cd8 100644 --- a/drivers/interconnect/qcom/qcs615.c +++ b/drivers/interconnect/qcom/qcs615.c @@ -13,1041 +13,992 @@ =20 #include "bcm-voter.h" #include "icc-rpmh.h" -#include "qcs615.h" + +static struct qcom_icc_node qhm_a1noc_cfg; +static struct qcom_icc_node qhm_qdss_bam; +static struct qcom_icc_node qhm_qspi; +static struct qcom_icc_node qhm_qup0; +static struct qcom_icc_node qhm_qup1; +static struct qcom_icc_node qnm_cnoc; +static struct qcom_icc_node qxm_crypto; +static struct qcom_icc_node qxm_ipa; +static struct qcom_icc_node xm_emac_avb; +static struct qcom_icc_node xm_pcie; +static struct qcom_icc_node xm_qdss_etr; +static struct qcom_icc_node xm_sdc1; +static struct qcom_icc_node xm_sdc2; +static struct qcom_icc_node xm_ufs_mem; +static struct qcom_icc_node xm_usb2; +static struct qcom_icc_node xm_usb3_0; +static struct qcom_icc_node qxm_camnoc_hf0_uncomp; +static struct qcom_icc_node qxm_camnoc_hf1_uncomp; +static struct qcom_icc_node qxm_camnoc_sf_uncomp; +static struct qcom_icc_node qhm_spdm; +static struct qcom_icc_node qnm_snoc; +static struct qcom_icc_node xm_qdss_dap; +static struct qcom_icc_node qhm_cnoc; +static struct qcom_icc_node acm_apps; +static struct qcom_icc_node acm_gpu_tcu; +static struct qcom_icc_node acm_sys_tcu; +static struct qcom_icc_node qhm_gemnoc_cfg; +static struct qcom_icc_node qnm_gpu; +static struct qcom_icc_node qnm_mnoc_hf; +static struct qcom_icc_node qnm_mnoc_sf; +static struct qcom_icc_node qnm_snoc_gc; +static struct qcom_icc_node qnm_snoc_sf; +static struct qcom_icc_node llcc_mc; +static struct qcom_icc_node qhm_mnoc_cfg; +static struct qcom_icc_node qxm_camnoc_hf0; +static struct qcom_icc_node qxm_camnoc_hf1; +static struct qcom_icc_node qxm_camnoc_sf; +static struct qcom_icc_node qxm_mdp0; +static struct qcom_icc_node qxm_rot; +static struct qcom_icc_node qxm_venus0; +static struct qcom_icc_node qxm_venus_arm9; +static struct qcom_icc_node qhm_snoc_cfg; +static struct qcom_icc_node qnm_aggre1_noc; +static struct qcom_icc_node qnm_gemnoc; +static struct qcom_icc_node qnm_gemnoc_pcie; +static struct qcom_icc_node qnm_lpass_anoc; +static struct qcom_icc_node qnm_pcie_anoc; +static struct qcom_icc_node qxm_pimem; +static struct qcom_icc_node xm_gic; +static struct qcom_icc_node qns_a1noc_snoc; +static struct qcom_icc_node qns_lpass_snoc; +static struct qcom_icc_node qns_pcie_snoc; +static struct qcom_icc_node srvc_aggre2_noc; +static struct qcom_icc_node qns_camnoc_uncomp; +static struct qcom_icc_node qhs_a1_noc_cfg; +static struct qcom_icc_node qhs_ahb2phy_east; +static struct qcom_icc_node qhs_ahb2phy_west; +static struct qcom_icc_node qhs_aop; +static struct qcom_icc_node qhs_aoss; +static struct qcom_icc_node qhs_camera_cfg; +static struct qcom_icc_node qhs_clk_ctl; +static struct qcom_icc_node qhs_cpr_cx; +static struct qcom_icc_node qhs_cpr_mx; +static struct qcom_icc_node qhs_crypto0_cfg; +static struct qcom_icc_node qhs_ddrss_cfg; +static struct qcom_icc_node qhs_display_cfg; +static struct qcom_icc_node qhs_emac_avb_cfg; +static struct qcom_icc_node qhs_glm; +static struct qcom_icc_node qhs_gpuss_cfg; +static struct qcom_icc_node qhs_imem_cfg; +static struct qcom_icc_node qhs_ipa; +static struct qcom_icc_node qhs_mnoc_cfg; +static struct qcom_icc_node qhs_pcie_config; +static struct qcom_icc_node qhs_pimem_cfg; +static struct qcom_icc_node qhs_prng; +static struct qcom_icc_node qhs_qdss_cfg; +static struct qcom_icc_node qhs_qspi; +static struct qcom_icc_node qhs_qup0; +static struct qcom_icc_node qhs_qup1; +static struct qcom_icc_node qhs_sdc1; +static struct qcom_icc_node qhs_sdc2; +static struct qcom_icc_node qhs_snoc_cfg; +static struct qcom_icc_node qhs_spdm; +static struct qcom_icc_node qhs_tcsr; +static struct qcom_icc_node qhs_tlmm_east; +static struct qcom_icc_node qhs_tlmm_south; +static struct qcom_icc_node qhs_tlmm_west; +static struct qcom_icc_node qhs_ufs_mem_cfg; +static struct qcom_icc_node qhs_usb2; +static struct qcom_icc_node qhs_usb3; +static struct qcom_icc_node qhs_venus_cfg; +static struct qcom_icc_node qhs_vsense_ctrl_cfg; +static struct qcom_icc_node qns_cnoc_a2noc; +static struct qcom_icc_node srvc_cnoc; +static struct qcom_icc_node qhs_dc_noc_gemnoc; +static struct qcom_icc_node qhs_llcc; +static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg; +static struct qcom_icc_node qns_gem_noc_snoc; +static struct qcom_icc_node qns_llcc; +static struct qcom_icc_node qns_sys_pcie; +static struct qcom_icc_node srvc_gemnoc; +static struct qcom_icc_node ebi; +static struct qcom_icc_node qns2_mem_noc; +static struct qcom_icc_node qns_mem_noc_hf; +static struct qcom_icc_node srvc_mnoc; +static struct qcom_icc_node qhs_apss; +static struct qcom_icc_node qns_cnoc; +static struct qcom_icc_node qns_gemnoc_sf; +static struct qcom_icc_node qns_memnoc_gc; +static struct qcom_icc_node qxs_imem; +static struct qcom_icc_node qxs_pimem; +static struct qcom_icc_node srvc_snoc; +static struct qcom_icc_node xs_pcie; +static struct qcom_icc_node xs_qdss_stm; +static struct qcom_icc_node xs_sys_tcu_cfg; =20 static struct qcom_icc_node qhm_a1noc_cfg =3D { .name =3D "qhm_a1noc_cfg", - .id =3D QCS615_MASTER_A1NOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { QCS615_SLAVE_SERVICE_A2NOC }, + .link_nodes =3D { &srvc_aggre2_noc }, }; =20 static struct qcom_icc_node qhm_qdss_bam =3D { .name =3D "qhm_qdss_bam", - .id =3D QCS615_MASTER_QDSS_BAM, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { QCS615_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node qhm_qspi =3D { .name =3D "qhm_qspi", - .id =3D QCS615_MASTER_QSPI, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { QCS615_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node qhm_qup0 =3D { .name =3D "qhm_qup0", - .id =3D QCS615_MASTER_QUP_0, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { QCS615_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node qhm_qup1 =3D { .name =3D "qhm_qup1", - .id =3D QCS615_MASTER_BLSP_1, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { QCS615_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node qnm_cnoc =3D { .name =3D "qnm_cnoc", - .id =3D QCS615_MASTER_CNOC_A2NOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { QCS615_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node qxm_crypto =3D { .name =3D "qxm_crypto", - .id =3D QCS615_MASTER_CRYPTO, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { QCS615_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node qxm_ipa =3D { .name =3D "qxm_ipa", - .id =3D QCS615_MASTER_IPA, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { QCS615_SLAVE_LPASS_SNOC }, + .link_nodes =3D { &qns_lpass_snoc }, }; =20 static struct qcom_icc_node xm_emac_avb =3D { .name =3D "xm_emac_avb", - .id =3D QCS615_MASTER_EMAC_EVB, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { QCS615_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node xm_pcie =3D { .name =3D "xm_pcie", - .id =3D QCS615_MASTER_PCIE, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { QCS615_SLAVE_ANOC_PCIE_SNOC }, + .link_nodes =3D { &qns_pcie_snoc }, }; =20 static struct qcom_icc_node xm_qdss_etr =3D { .name =3D "xm_qdss_etr", - .id =3D QCS615_MASTER_QDSS_ETR, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { QCS615_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node xm_sdc1 =3D { .name =3D "xm_sdc1", - .id =3D QCS615_MASTER_SDCC_1, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { QCS615_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node xm_sdc2 =3D { .name =3D "xm_sdc2", - .id =3D QCS615_MASTER_SDCC_2, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { QCS615_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node xm_ufs_mem =3D { .name =3D "xm_ufs_mem", - .id =3D QCS615_MASTER_UFS_MEM, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { QCS615_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node xm_usb2 =3D { .name =3D "xm_usb2", - .id =3D QCS615_MASTER_USB2, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { QCS615_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node xm_usb3_0 =3D { .name =3D "xm_usb3_0", - .id =3D QCS615_MASTER_USB3_0, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { QCS615_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node qxm_camnoc_hf0_uncomp =3D { .name =3D "qxm_camnoc_hf0_uncomp", - .id =3D QCS615_MASTER_CAMNOC_HF0_UNCOMP, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { QCS615_SLAVE_CAMNOC_UNCOMP }, + .link_nodes =3D { &qns_camnoc_uncomp }, }; =20 static struct qcom_icc_node qxm_camnoc_hf1_uncomp =3D { .name =3D "qxm_camnoc_hf1_uncomp", - .id =3D QCS615_MASTER_CAMNOC_HF1_UNCOMP, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { QCS615_SLAVE_CAMNOC_UNCOMP }, + .link_nodes =3D { &qns_camnoc_uncomp }, }; =20 static struct qcom_icc_node qxm_camnoc_sf_uncomp =3D { .name =3D "qxm_camnoc_sf_uncomp", - .id =3D QCS615_MASTER_CAMNOC_SF_UNCOMP, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { QCS615_SLAVE_CAMNOC_UNCOMP }, + .link_nodes =3D { &qns_camnoc_uncomp }, }; =20 static struct qcom_icc_node qhm_spdm =3D { .name =3D "qhm_spdm", - .id =3D QCS615_MASTER_SPDM, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { QCS615_SLAVE_CNOC_A2NOC }, + .link_nodes =3D { &qns_cnoc_a2noc }, }; =20 static struct qcom_icc_node qnm_snoc =3D { .name =3D "qnm_snoc", - .id =3D QCS615_MASTER_SNOC_CNOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 39, - .links =3D { QCS615_SLAVE_A1NOC_CFG, QCS615_SLAVE_AHB2PHY_EAST, - QCS615_SLAVE_AHB2PHY_WEST, QCS615_SLAVE_AOP, - QCS615_SLAVE_AOSS, QCS615_SLAVE_CAMERA_CFG, - QCS615_SLAVE_CLK_CTL, QCS615_SLAVE_RBCPR_CX_CFG, - QCS615_SLAVE_RBCPR_MX_CFG, QCS615_SLAVE_CRYPTO_0_CFG, - QCS615_SLAVE_CNOC_DDRSS, QCS615_SLAVE_DISPLAY_CFG, - QCS615_SLAVE_EMAC_AVB_CFG, QCS615_SLAVE_GLM, - QCS615_SLAVE_GFX3D_CFG, QCS615_SLAVE_IMEM_CFG, - QCS615_SLAVE_IPA_CFG, QCS615_SLAVE_CNOC_MNOC_CFG, - QCS615_SLAVE_PCIE_CFG, QCS615_SLAVE_PIMEM_CFG, - QCS615_SLAVE_PRNG, QCS615_SLAVE_QDSS_CFG, - QCS615_SLAVE_QSPI, QCS615_SLAVE_QUP_0, - QCS615_SLAVE_QUP_1, QCS615_SLAVE_SDCC_1, - QCS615_SLAVE_SDCC_2, QCS615_SLAVE_SNOC_CFG, - QCS615_SLAVE_SPDM_WRAPPER, QCS615_SLAVE_TCSR, - QCS615_SLAVE_TLMM_EAST, QCS615_SLAVE_TLMM_SOUTH, - QCS615_SLAVE_TLMM_WEST, QCS615_SLAVE_UFS_MEM_CFG, - QCS615_SLAVE_USB2, QCS615_SLAVE_USB3, - QCS615_SLAVE_VENUS_CFG, QCS615_SLAVE_VSENSE_CTRL_CFG, - QCS615_SLAVE_SERVICE_CNOC }, + .link_nodes =3D { &qhs_a1_noc_cfg, &qhs_ahb2phy_east, + &qhs_ahb2phy_west, &qhs_aop, + &qhs_aoss, &qhs_camera_cfg, + &qhs_clk_ctl, &qhs_cpr_cx, + &qhs_cpr_mx, &qhs_crypto0_cfg, + &qhs_ddrss_cfg, &qhs_display_cfg, + &qhs_emac_avb_cfg, &qhs_glm, + &qhs_gpuss_cfg, &qhs_imem_cfg, + &qhs_ipa, &qhs_mnoc_cfg, + &qhs_pcie_config, &qhs_pimem_cfg, + &qhs_prng, &qhs_qdss_cfg, + &qhs_qspi, &qhs_qup0, + &qhs_qup1, &qhs_sdc1, + &qhs_sdc2, &qhs_snoc_cfg, + &qhs_spdm, &qhs_tcsr, + &qhs_tlmm_east, &qhs_tlmm_south, + &qhs_tlmm_west, &qhs_ufs_mem_cfg, + &qhs_usb2, &qhs_usb3, + &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, + &srvc_cnoc }, }; =20 static struct qcom_icc_node xm_qdss_dap =3D { .name =3D "xm_qdss_dap", - .id =3D QCS615_MASTER_QDSS_DAP, .channels =3D 1, .buswidth =3D 8, .num_links =3D 40, - .links =3D { QCS615_SLAVE_A1NOC_CFG, QCS615_SLAVE_AHB2PHY_EAST, - QCS615_SLAVE_AHB2PHY_WEST, QCS615_SLAVE_AOP, - QCS615_SLAVE_AOSS, QCS615_SLAVE_CAMERA_CFG, - QCS615_SLAVE_CLK_CTL, QCS615_SLAVE_RBCPR_CX_CFG, - QCS615_SLAVE_RBCPR_MX_CFG, QCS615_SLAVE_CRYPTO_0_CFG, - QCS615_SLAVE_CNOC_DDRSS, QCS615_SLAVE_DISPLAY_CFG, - QCS615_SLAVE_EMAC_AVB_CFG, QCS615_SLAVE_GLM, - QCS615_SLAVE_GFX3D_CFG, QCS615_SLAVE_IMEM_CFG, - QCS615_SLAVE_IPA_CFG, QCS615_SLAVE_CNOC_MNOC_CFG, - QCS615_SLAVE_PCIE_CFG, QCS615_SLAVE_PIMEM_CFG, - QCS615_SLAVE_PRNG, QCS615_SLAVE_QDSS_CFG, - QCS615_SLAVE_QSPI, QCS615_SLAVE_QUP_0, - QCS615_SLAVE_QUP_1, QCS615_SLAVE_SDCC_1, - QCS615_SLAVE_SDCC_2, QCS615_SLAVE_SNOC_CFG, - QCS615_SLAVE_SPDM_WRAPPER, QCS615_SLAVE_TCSR, - QCS615_SLAVE_TLMM_EAST, QCS615_SLAVE_TLMM_SOUTH, - QCS615_SLAVE_TLMM_WEST, QCS615_SLAVE_UFS_MEM_CFG, - QCS615_SLAVE_USB2, QCS615_SLAVE_USB3, - QCS615_SLAVE_VENUS_CFG, QCS615_SLAVE_VSENSE_CTRL_CFG, - QCS615_SLAVE_CNOC_A2NOC, QCS615_SLAVE_SERVICE_CNOC }, + .link_nodes =3D { &qhs_a1_noc_cfg, &qhs_ahb2phy_east, + &qhs_ahb2phy_west, &qhs_aop, + &qhs_aoss, &qhs_camera_cfg, + &qhs_clk_ctl, &qhs_cpr_cx, + &qhs_cpr_mx, &qhs_crypto0_cfg, + &qhs_ddrss_cfg, &qhs_display_cfg, + &qhs_emac_avb_cfg, &qhs_glm, + &qhs_gpuss_cfg, &qhs_imem_cfg, + &qhs_ipa, &qhs_mnoc_cfg, + &qhs_pcie_config, &qhs_pimem_cfg, + &qhs_prng, &qhs_qdss_cfg, + &qhs_qspi, &qhs_qup0, + &qhs_qup1, &qhs_sdc1, + &qhs_sdc2, &qhs_snoc_cfg, + &qhs_spdm, &qhs_tcsr, + &qhs_tlmm_east, &qhs_tlmm_south, + &qhs_tlmm_west, &qhs_ufs_mem_cfg, + &qhs_usb2, &qhs_usb3, + &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, + &qns_cnoc_a2noc, &srvc_cnoc }, }; =20 static struct qcom_icc_node qhm_cnoc =3D { .name =3D "qhm_cnoc", - .id =3D QCS615_MASTER_CNOC_DC_NOC, .channels =3D 1, .buswidth =3D 4, .num_links =3D 2, - .links =3D { QCS615_SLAVE_DC_NOC_GEMNOC, QCS615_SLAVE_LLCC_CFG }, + .link_nodes =3D { &qhs_dc_noc_gemnoc, &qhs_llcc }, }; =20 static struct qcom_icc_node acm_apps =3D { .name =3D "acm_apps", - .id =3D QCS615_MASTER_APPSS_PROC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 3, - .links =3D { QCS615_SLAVE_GEM_NOC_SNOC, QCS615_SLAVE_LLCC, - QCS615_SLAVE_MEM_NOC_PCIE_SNOC }, + .link_nodes =3D { &qns_gem_noc_snoc, &qns_llcc, + &qns_sys_pcie }, }; =20 static struct qcom_icc_node acm_gpu_tcu =3D { .name =3D "acm_gpu_tcu", - .id =3D QCS615_MASTER_GPU_TCU, .channels =3D 1, .buswidth =3D 8, .num_links =3D 2, - .links =3D { QCS615_SLAVE_GEM_NOC_SNOC, QCS615_SLAVE_LLCC }, + .link_nodes =3D { &qns_gem_noc_snoc, &qns_llcc }, }; =20 static struct qcom_icc_node acm_sys_tcu =3D { .name =3D "acm_sys_tcu", - .id =3D QCS615_MASTER_SYS_TCU, .channels =3D 1, .buswidth =3D 8, .num_links =3D 2, - .links =3D { QCS615_SLAVE_GEM_NOC_SNOC, QCS615_SLAVE_LLCC }, + .link_nodes =3D { &qns_gem_noc_snoc, &qns_llcc }, }; =20 static struct qcom_icc_node qhm_gemnoc_cfg =3D { .name =3D "qhm_gemnoc_cfg", - .id =3D QCS615_MASTER_GEM_NOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 2, - .links =3D { QCS615_SLAVE_MSS_PROC_MS_MPU_CFG, QCS615_SLAVE_SERVICE_GEM_N= OC }, + .link_nodes =3D { &qhs_mdsp_ms_mpu_cfg, &srvc_gemnoc }, }; =20 static struct qcom_icc_node qnm_gpu =3D { .name =3D "qnm_gpu", - .id =3D QCS615_MASTER_GFX3D, .channels =3D 2, .buswidth =3D 32, .num_links =3D 2, - .links =3D { QCS615_SLAVE_GEM_NOC_SNOC, QCS615_SLAVE_LLCC }, + .link_nodes =3D { &qns_gem_noc_snoc, &qns_llcc }, }; =20 static struct qcom_icc_node qnm_mnoc_hf =3D { .name =3D "qnm_mnoc_hf", - .id =3D QCS615_MASTER_MNOC_HF_MEM_NOC, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { QCS615_SLAVE_LLCC }, + .link_nodes =3D { &qns_llcc }, }; =20 static struct qcom_icc_node qnm_mnoc_sf =3D { .name =3D "qnm_mnoc_sf", - .id =3D QCS615_MASTER_MNOC_SF_MEM_NOC, .channels =3D 1, .buswidth =3D 32, .num_links =3D 2, - .links =3D { QCS615_SLAVE_GEM_NOC_SNOC, QCS615_SLAVE_LLCC }, + .link_nodes =3D { &qns_gem_noc_snoc, &qns_llcc }, }; =20 static struct qcom_icc_node qnm_snoc_gc =3D { .name =3D "qnm_snoc_gc", - .id =3D QCS615_MASTER_SNOC_GC_MEM_NOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { QCS615_SLAVE_LLCC }, + .link_nodes =3D { &qns_llcc }, }; =20 static struct qcom_icc_node qnm_snoc_sf =3D { .name =3D "qnm_snoc_sf", - .id =3D QCS615_MASTER_SNOC_SF_MEM_NOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { QCS615_SLAVE_LLCC }, + .link_nodes =3D { &qns_llcc }, }; =20 static struct qcom_icc_node llcc_mc =3D { .name =3D "llcc_mc", - .id =3D QCS615_MASTER_LLCC, .channels =3D 2, .buswidth =3D 4, .num_links =3D 1, - .links =3D { QCS615_SLAVE_EBI1 }, + .link_nodes =3D { &ebi }, }; =20 static struct qcom_icc_node qhm_mnoc_cfg =3D { .name =3D "qhm_mnoc_cfg", - .id =3D QCS615_MASTER_CNOC_MNOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { QCS615_SLAVE_SERVICE_MNOC }, + .link_nodes =3D { &srvc_mnoc }, }; =20 static struct qcom_icc_node qxm_camnoc_hf0 =3D { .name =3D "qxm_camnoc_hf0", - .id =3D QCS615_MASTER_CAMNOC_HF0, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { QCS615_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_hf }, }; =20 static struct qcom_icc_node qxm_camnoc_hf1 =3D { .name =3D "qxm_camnoc_hf1", - .id =3D QCS615_MASTER_CAMNOC_HF1, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { QCS615_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_hf }, }; =20 static struct qcom_icc_node qxm_camnoc_sf =3D { .name =3D "qxm_camnoc_sf", - .id =3D QCS615_MASTER_CAMNOC_SF, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { QCS615_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns2_mem_noc }, }; =20 static struct qcom_icc_node qxm_mdp0 =3D { .name =3D "qxm_mdp0", - .id =3D QCS615_MASTER_MDP0, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { QCS615_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_hf }, }; =20 static struct qcom_icc_node qxm_rot =3D { .name =3D "qxm_rot", - .id =3D QCS615_MASTER_ROTATOR, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { QCS615_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns2_mem_noc }, }; =20 static struct qcom_icc_node qxm_venus0 =3D { .name =3D "qxm_venus0", - .id =3D QCS615_MASTER_VIDEO_P0, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { QCS615_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns2_mem_noc }, }; =20 static struct qcom_icc_node qxm_venus_arm9 =3D { .name =3D "qxm_venus_arm9", - .id =3D QCS615_MASTER_VIDEO_PROC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { QCS615_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns2_mem_noc }, }; =20 static struct qcom_icc_node qhm_snoc_cfg =3D { .name =3D "qhm_snoc_cfg", - .id =3D QCS615_MASTER_SNOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { QCS615_SLAVE_SERVICE_SNOC }, + .link_nodes =3D { &srvc_snoc }, }; =20 static struct qcom_icc_node qnm_aggre1_noc =3D { .name =3D "qnm_aggre1_noc", - .id =3D QCS615_MASTER_A1NOC_SNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 8, - .links =3D { QCS615_SLAVE_APPSS, QCS615_SLAVE_SNOC_CNOC, - QCS615_SLAVE_SNOC_GEM_NOC_SF, QCS615_SLAVE_IMEM, - QCS615_SLAVE_PIMEM, QCS615_SLAVE_PCIE_0, - QCS615_SLAVE_QDSS_STM, QCS615_SLAVE_TCU }, + .link_nodes =3D { &qhs_apss, &qns_cnoc, + &qns_gemnoc_sf, &qxs_imem, + &qxs_pimem, &xs_pcie, + &xs_qdss_stm, &xs_sys_tcu_cfg }, }; =20 static struct qcom_icc_node qnm_gemnoc =3D { .name =3D "qnm_gemnoc", - .id =3D QCS615_MASTER_GEM_NOC_SNOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 6, - .links =3D { QCS615_SLAVE_APPSS, QCS615_SLAVE_SNOC_CNOC, - QCS615_SLAVE_IMEM, QCS615_SLAVE_PIMEM, - QCS615_SLAVE_QDSS_STM, QCS615_SLAVE_TCU }, + .link_nodes =3D { &qhs_apss, &qns_cnoc, + &qxs_imem, &qxs_pimem, + &xs_qdss_stm, &xs_sys_tcu_cfg }, }; =20 static struct qcom_icc_node qnm_gemnoc_pcie =3D { .name =3D "qnm_gemnoc_pcie", - .id =3D QCS615_MASTER_GEM_NOC_PCIE_SNOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { QCS615_SLAVE_PCIE_0 }, + .link_nodes =3D { &xs_pcie }, }; =20 static struct qcom_icc_node qnm_lpass_anoc =3D { .name =3D "qnm_lpass_anoc", - .id =3D QCS615_MASTER_LPASS_ANOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 7, - .links =3D { QCS615_SLAVE_APPSS, QCS615_SLAVE_SNOC_CNOC, - QCS615_SLAVE_SNOC_GEM_NOC_SF, QCS615_SLAVE_IMEM, - QCS615_SLAVE_PIMEM, QCS615_SLAVE_PCIE_0, - QCS615_SLAVE_QDSS_STM }, + .link_nodes =3D { &qhs_apss, &qns_cnoc, + &qns_gemnoc_sf, &qxs_imem, + &qxs_pimem, &xs_pcie, + &xs_qdss_stm }, }; =20 static struct qcom_icc_node qnm_pcie_anoc =3D { .name =3D "qnm_pcie_anoc", - .id =3D QCS615_MASTER_ANOC_PCIE_SNOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 5, - .links =3D { QCS615_SLAVE_APPSS, QCS615_SLAVE_SNOC_CNOC, - QCS615_SLAVE_SNOC_GEM_NOC_SF, QCS615_SLAVE_IMEM, - QCS615_SLAVE_QDSS_STM }, + .link_nodes =3D { &qhs_apss, &qns_cnoc, + &qns_gemnoc_sf, &qxs_imem, + &xs_qdss_stm }, }; =20 static struct qcom_icc_node qxm_pimem =3D { .name =3D "qxm_pimem", - .id =3D QCS615_MASTER_PIMEM, .channels =3D 1, .buswidth =3D 8, .num_links =3D 2, - .links =3D { QCS615_SLAVE_SNOC_MEM_NOC_GC, QCS615_SLAVE_IMEM }, + .link_nodes =3D { &qns_memnoc_gc, &qxs_imem }, }; =20 static struct qcom_icc_node xm_gic =3D { .name =3D "xm_gic", - .id =3D QCS615_MASTER_GIC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 2, - .links =3D { QCS615_SLAVE_SNOC_MEM_NOC_GC, QCS615_SLAVE_IMEM }, + .link_nodes =3D { &qns_memnoc_gc, &qxs_imem }, }; =20 static struct qcom_icc_node qns_a1noc_snoc =3D { .name =3D "qns_a1noc_snoc", - .id =3D QCS615_SLAVE_A1NOC_SNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { QCS615_MASTER_A1NOC_SNOC }, + .link_nodes =3D { &qnm_aggre1_noc }, }; =20 static struct qcom_icc_node qns_lpass_snoc =3D { .name =3D "qns_lpass_snoc", - .id =3D QCS615_SLAVE_LPASS_SNOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { QCS615_MASTER_LPASS_ANOC }, + .link_nodes =3D { &qnm_lpass_anoc }, }; =20 static struct qcom_icc_node qns_pcie_snoc =3D { .name =3D "qns_pcie_snoc", - .id =3D QCS615_SLAVE_ANOC_PCIE_SNOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { QCS615_MASTER_ANOC_PCIE_SNOC }, + .link_nodes =3D { &qnm_pcie_anoc }, }; =20 static struct qcom_icc_node srvc_aggre2_noc =3D { .name =3D "srvc_aggre2_noc", - .id =3D QCS615_SLAVE_SERVICE_A2NOC, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qns_camnoc_uncomp =3D { .name =3D "qns_camnoc_uncomp", - .id =3D QCS615_SLAVE_CAMNOC_UNCOMP, .channels =3D 1, .buswidth =3D 32, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_a1_noc_cfg =3D { .name =3D "qhs_a1_noc_cfg", - .id =3D QCS615_SLAVE_A1NOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { QCS615_MASTER_A1NOC_CFG }, + .link_nodes =3D { &qhm_a1noc_cfg }, }; =20 static struct qcom_icc_node qhs_ahb2phy_east =3D { .name =3D "qhs_ahb2phy_east", - .id =3D QCS615_SLAVE_AHB2PHY_EAST, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_ahb2phy_west =3D { .name =3D "qhs_ahb2phy_west", - .id =3D QCS615_SLAVE_AHB2PHY_WEST, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_aop =3D { .name =3D "qhs_aop", - .id =3D QCS615_SLAVE_AOP, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_aoss =3D { .name =3D "qhs_aoss", - .id =3D QCS615_SLAVE_AOSS, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_camera_cfg =3D { .name =3D "qhs_camera_cfg", - .id =3D QCS615_SLAVE_CAMERA_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_clk_ctl =3D { .name =3D "qhs_clk_ctl", - .id =3D QCS615_SLAVE_CLK_CTL, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_cpr_cx =3D { .name =3D "qhs_cpr_cx", - .id =3D QCS615_SLAVE_RBCPR_CX_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_cpr_mx =3D { .name =3D "qhs_cpr_mx", - .id =3D QCS615_SLAVE_RBCPR_MX_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_crypto0_cfg =3D { .name =3D "qhs_crypto0_cfg", - .id =3D QCS615_SLAVE_CRYPTO_0_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_ddrss_cfg =3D { .name =3D "qhs_ddrss_cfg", - .id =3D QCS615_SLAVE_CNOC_DDRSS, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { QCS615_MASTER_CNOC_DC_NOC }, + .link_nodes =3D { &qhm_cnoc }, }; =20 static struct qcom_icc_node qhs_display_cfg =3D { .name =3D "qhs_display_cfg", - .id =3D QCS615_SLAVE_DISPLAY_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_emac_avb_cfg =3D { .name =3D "qhs_emac_avb_cfg", - .id =3D QCS615_SLAVE_EMAC_AVB_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_glm =3D { .name =3D "qhs_glm", - .id =3D QCS615_SLAVE_GLM, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_gpuss_cfg =3D { .name =3D "qhs_gpuss_cfg", - .id =3D QCS615_SLAVE_GFX3D_CFG, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_imem_cfg =3D { .name =3D "qhs_imem_cfg", - .id =3D QCS615_SLAVE_IMEM_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_ipa =3D { .name =3D "qhs_ipa", - .id =3D QCS615_SLAVE_IPA_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_mnoc_cfg =3D { .name =3D "qhs_mnoc_cfg", - .id =3D QCS615_SLAVE_CNOC_MNOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { QCS615_MASTER_CNOC_MNOC_CFG }, + .link_nodes =3D { &qhm_mnoc_cfg }, }; =20 static struct qcom_icc_node qhs_pcie_config =3D { .name =3D "qhs_pcie_config", - .id =3D QCS615_SLAVE_PCIE_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_pimem_cfg =3D { .name =3D "qhs_pimem_cfg", - .id =3D QCS615_SLAVE_PIMEM_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_prng =3D { .name =3D "qhs_prng", - .id =3D QCS615_SLAVE_PRNG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_qdss_cfg =3D { .name =3D "qhs_qdss_cfg", - .id =3D QCS615_SLAVE_QDSS_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_qspi =3D { .name =3D "qhs_qspi", - .id =3D QCS615_SLAVE_QSPI, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_qup0 =3D { .name =3D "qhs_qup0", - .id =3D QCS615_SLAVE_QUP_0, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_qup1 =3D { .name =3D "qhs_qup1", - .id =3D QCS615_SLAVE_QUP_1, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_sdc1 =3D { .name =3D "qhs_sdc1", - .id =3D QCS615_SLAVE_SDCC_1, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_sdc2 =3D { .name =3D "qhs_sdc2", - .id =3D QCS615_SLAVE_SDCC_2, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_snoc_cfg =3D { .name =3D "qhs_snoc_cfg", - .id =3D QCS615_SLAVE_SNOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { QCS615_MASTER_SNOC_CFG }, + .link_nodes =3D { &qhm_snoc_cfg }, }; =20 static struct qcom_icc_node qhs_spdm =3D { .name =3D "qhs_spdm", - .id =3D QCS615_SLAVE_SPDM_WRAPPER, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_tcsr =3D { .name =3D "qhs_tcsr", - .id =3D QCS615_SLAVE_TCSR, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_tlmm_east =3D { .name =3D "qhs_tlmm_east", - .id =3D QCS615_SLAVE_TLMM_EAST, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_tlmm_south =3D { .name =3D "qhs_tlmm_south", - .id =3D QCS615_SLAVE_TLMM_SOUTH, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_tlmm_west =3D { .name =3D "qhs_tlmm_west", - .id =3D QCS615_SLAVE_TLMM_WEST, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_ufs_mem_cfg =3D { .name =3D "qhs_ufs_mem_cfg", - .id =3D QCS615_SLAVE_UFS_MEM_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_usb2 =3D { .name =3D "qhs_usb2", - .id =3D QCS615_SLAVE_USB2, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_usb3 =3D { .name =3D "qhs_usb3", - .id =3D QCS615_SLAVE_USB3, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_venus_cfg =3D { .name =3D "qhs_venus_cfg", - .id =3D QCS615_SLAVE_VENUS_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_vsense_ctrl_cfg =3D { .name =3D "qhs_vsense_ctrl_cfg", - .id =3D QCS615_SLAVE_VSENSE_CTRL_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qns_cnoc_a2noc =3D { .name =3D "qns_cnoc_a2noc", - .id =3D QCS615_SLAVE_CNOC_A2NOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { QCS615_MASTER_CNOC_A2NOC }, + .link_nodes =3D { &qnm_cnoc }, }; =20 static struct qcom_icc_node srvc_cnoc =3D { .name =3D "srvc_cnoc", - .id =3D QCS615_SLAVE_SERVICE_CNOC, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_dc_noc_gemnoc =3D { .name =3D "qhs_dc_noc_gemnoc", - .id =3D QCS615_SLAVE_DC_NOC_GEMNOC, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { QCS615_MASTER_GEM_NOC_CFG }, + .link_nodes =3D { &qhm_gemnoc_cfg }, }; =20 static struct qcom_icc_node qhs_llcc =3D { .name =3D "qhs_llcc", - .id =3D QCS615_SLAVE_LLCC_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg =3D { .name =3D "qhs_mdsp_ms_mpu_cfg", - .id =3D QCS615_SLAVE_MSS_PROC_MS_MPU_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qns_gem_noc_snoc =3D { .name =3D "qns_gem_noc_snoc", - .id =3D QCS615_SLAVE_GEM_NOC_SNOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { QCS615_MASTER_GEM_NOC_SNOC }, + .link_nodes =3D { &qnm_gemnoc }, }; =20 static struct qcom_icc_node qns_llcc =3D { .name =3D "qns_llcc", - .id =3D QCS615_SLAVE_LLCC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { QCS615_MASTER_LLCC }, + .link_nodes =3D { &llcc_mc }, }; =20 static struct qcom_icc_node qns_sys_pcie =3D { .name =3D "qns_sys_pcie", - .id =3D QCS615_SLAVE_MEM_NOC_PCIE_SNOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { QCS615_MASTER_GEM_NOC_PCIE_SNOC }, + .link_nodes =3D { &qnm_gemnoc_pcie }, }; =20 static struct qcom_icc_node srvc_gemnoc =3D { .name =3D "srvc_gemnoc", - .id =3D QCS615_SLAVE_SERVICE_GEM_NOC, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node ebi =3D { .name =3D "ebi", - .id =3D QCS615_SLAVE_EBI1, .channels =3D 2, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qns2_mem_noc =3D { .name =3D "qns2_mem_noc", - .id =3D QCS615_SLAVE_MNOC_SF_MEM_NOC, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { QCS615_MASTER_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qnm_mnoc_sf }, }; =20 static struct qcom_icc_node qns_mem_noc_hf =3D { .name =3D "qns_mem_noc_hf", - .id =3D QCS615_SLAVE_MNOC_HF_MEM_NOC, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { QCS615_MASTER_MNOC_HF_MEM_NOC }, + .link_nodes =3D { &qnm_mnoc_hf }, }; =20 static struct qcom_icc_node srvc_mnoc =3D { .name =3D "srvc_mnoc", - .id =3D QCS615_SLAVE_SERVICE_MNOC, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_apss =3D { .name =3D "qhs_apss", - .id =3D QCS615_SLAVE_APPSS, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 0, }; =20 static struct qcom_icc_node qns_cnoc =3D { .name =3D "qns_cnoc", - .id =3D QCS615_SLAVE_SNOC_CNOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { QCS615_MASTER_SNOC_CNOC }, + .link_nodes =3D { &qnm_snoc }, }; =20 static struct qcom_icc_node qns_gemnoc_sf =3D { .name =3D "qns_gemnoc_sf", - .id =3D QCS615_SLAVE_SNOC_GEM_NOC_SF, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { QCS615_MASTER_SNOC_SF_MEM_NOC }, + .link_nodes =3D { &qnm_snoc_sf }, }; =20 static struct qcom_icc_node qns_memnoc_gc =3D { .name =3D "qns_memnoc_gc", - .id =3D QCS615_SLAVE_SNOC_MEM_NOC_GC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { QCS615_MASTER_SNOC_GC_MEM_NOC }, + .link_nodes =3D { &qnm_snoc_gc }, }; =20 static struct qcom_icc_node qxs_imem =3D { .name =3D "qxs_imem", - .id =3D QCS615_SLAVE_IMEM, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 0, }; =20 static struct qcom_icc_node qxs_pimem =3D { .name =3D "qxs_pimem", - .id =3D QCS615_SLAVE_PIMEM, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 0, }; =20 static struct qcom_icc_node srvc_snoc =3D { .name =3D "srvc_snoc", - .id =3D QCS615_SLAVE_SERVICE_SNOC, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node xs_pcie =3D { .name =3D "xs_pcie", - .id =3D QCS615_SLAVE_PCIE_0, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 0, }; =20 static struct qcom_icc_node xs_qdss_stm =3D { .name =3D "xs_qdss_stm", - .id =3D QCS615_SLAVE_QDSS_STM, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node xs_sys_tcu_cfg =3D { .name =3D "xs_sys_tcu_cfg", - .id =3D QCS615_SLAVE_TCU, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 0, }; =20 static struct qcom_icc_bcm bcm_acv =3D { @@ -1263,6 +1214,7 @@ static struct qcom_icc_node * const aggre1_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc qcs615_aggre1_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D aggre1_noc_nodes, .num_nodes =3D ARRAY_SIZE(aggre1_noc_nodes), .bcms =3D aggre1_noc_bcms, @@ -1281,6 +1233,7 @@ static struct qcom_icc_node * const camnoc_virt_nodes= [] =3D { }; =20 static const struct qcom_icc_desc qcs615_camnoc_virt =3D { + .alloc_dyn_id =3D true, .nodes =3D camnoc_virt_nodes, .num_nodes =3D ARRAY_SIZE(camnoc_virt_nodes), .bcms =3D camnoc_virt_bcms, @@ -1339,6 +1292,7 @@ static struct qcom_icc_node * const config_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc qcs615_config_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D config_noc_nodes, .num_nodes =3D ARRAY_SIZE(config_noc_nodes), .bcms =3D config_noc_bcms, @@ -1352,6 +1306,7 @@ static struct qcom_icc_node * const dc_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc qcs615_dc_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D dc_noc_nodes, .num_nodes =3D ARRAY_SIZE(dc_noc_nodes), }; @@ -1381,6 +1336,7 @@ static struct qcom_icc_node * const gem_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc qcs615_gem_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D gem_noc_nodes, .num_nodes =3D ARRAY_SIZE(gem_noc_nodes), .bcms =3D gem_noc_bcms, @@ -1398,6 +1354,7 @@ static struct qcom_icc_node * const mc_virt_nodes[] = =3D { }; =20 static const struct qcom_icc_desc qcs615_mc_virt =3D { + .alloc_dyn_id =3D true, .nodes =3D mc_virt_nodes, .num_nodes =3D ARRAY_SIZE(mc_virt_nodes), .bcms =3D mc_virt_bcms, @@ -1426,6 +1383,7 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc qcs615_mmss_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D mmss_noc_nodes, .num_nodes =3D ARRAY_SIZE(mmss_noc_nodes), .bcms =3D mmss_noc_bcms, @@ -1468,6 +1426,7 @@ static struct qcom_icc_node * const system_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc qcs615_system_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D system_noc_nodes, .num_nodes =3D ARRAY_SIZE(system_noc_nodes), .bcms =3D system_noc_bcms, diff --git a/drivers/interconnect/qcom/qcs615.h b/drivers/interconnect/qcom= /qcs615.h deleted file mode 100644 index 66e66c7e23d4ecaf92c2697e695980c3f8663664..000000000000000000000000000= 0000000000000 --- a/drivers/interconnect/qcom/qcs615.h +++ /dev/null @@ -1,128 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserve= d. - */ - -#ifndef __DRIVERS_INTERCONNECT_QCOM_QCS615_H -#define __DRIVERS_INTERCONNECT_QCOM_QCS615_H - -#define QCS615_MASTER_A1NOC_CFG 1 -#define QCS615_MASTER_A1NOC_SNOC 2 -#define QCS615_MASTER_ANOC_PCIE_SNOC 3 -#define QCS615_MASTER_APPSS_PROC 4 -#define QCS615_MASTER_BLSP_1 5 -#define QCS615_MASTER_CAMNOC_HF0 6 -#define QCS615_MASTER_CAMNOC_HF0_UNCOMP 7 -#define QCS615_MASTER_CAMNOC_HF1 8 -#define QCS615_MASTER_CAMNOC_HF1_UNCOMP 9 -#define QCS615_MASTER_CAMNOC_SF 10 -#define QCS615_MASTER_CAMNOC_SF_UNCOMP 11 -#define QCS615_MASTER_CNOC_A2NOC 12 -#define QCS615_MASTER_CNOC_DC_NOC 13 -#define QCS615_MASTER_CNOC_MNOC_CFG 14 -#define QCS615_MASTER_CRYPTO 15 -#define QCS615_MASTER_EMAC_EVB 16 -#define QCS615_MASTER_GEM_NOC_CFG 17 -#define QCS615_MASTER_GEM_NOC_PCIE_SNOC 18 -#define QCS615_MASTER_GEM_NOC_SNOC 19 -#define QCS615_MASTER_GFX3D 20 -#define QCS615_MASTER_GIC 21 -#define QCS615_MASTER_GPU_TCU 22 -#define QCS615_MASTER_IPA 23 -#define QCS615_MASTER_IPA_CORE 24 -#define QCS615_MASTER_LLCC 25 -#define QCS615_MASTER_LPASS_ANOC 26 -#define QCS615_MASTER_MDP0 27 -#define QCS615_MASTER_MNOC_HF_MEM_NOC 28 -#define QCS615_MASTER_MNOC_SF_MEM_NOC 29 -#define QCS615_MASTER_PCIE 30 -#define QCS615_MASTER_PIMEM 31 -#define QCS615_MASTER_QDSS_BAM 32 -#define QCS615_MASTER_QDSS_DAP 33 -#define QCS615_MASTER_QDSS_ETR 34 -#define QCS615_MASTER_QSPI 35 -#define QCS615_MASTER_QUP_0 36 -#define QCS615_MASTER_ROTATOR 37 -#define QCS615_MASTER_SDCC_1 38 -#define QCS615_MASTER_SDCC_2 39 -#define QCS615_MASTER_SNOC_CFG 40 -#define QCS615_MASTER_SNOC_CNOC 41 -#define QCS615_MASTER_SNOC_GC_MEM_NOC 42 -#define QCS615_MASTER_SNOC_SF_MEM_NOC 43 -#define QCS615_MASTER_SPDM 44 -#define QCS615_MASTER_SYS_TCU 45 -#define QCS615_MASTER_UFS_MEM 46 -#define QCS615_MASTER_USB2 47 -#define QCS615_MASTER_USB3_0 48 -#define QCS615_MASTER_VIDEO_P0 49 -#define QCS615_MASTER_VIDEO_PROC 50 -#define QCS615_SLAVE_A1NOC_CFG 51 -#define QCS615_SLAVE_A1NOC_SNOC 52 -#define QCS615_SLAVE_AHB2PHY_EAST 53 -#define QCS615_SLAVE_AHB2PHY_WEST 54 -#define QCS615_SLAVE_ANOC_PCIE_SNOC 55 -#define QCS615_SLAVE_AOP 56 -#define QCS615_SLAVE_AOSS 57 -#define QCS615_SLAVE_APPSS 58 -#define QCS615_SLAVE_CAMERA_CFG 59 -#define QCS615_SLAVE_CAMNOC_UNCOMP 60 -#define QCS615_SLAVE_CLK_CTL 61 -#define QCS615_SLAVE_CNOC_A2NOC 62 -#define QCS615_SLAVE_CNOC_DDRSS 63 -#define QCS615_SLAVE_CNOC_MNOC_CFG 64 -#define QCS615_SLAVE_CRYPTO_0_CFG 65 -#define QCS615_SLAVE_DC_NOC_GEMNOC 66 -#define QCS615_SLAVE_DISPLAY_CFG 67 -#define QCS615_SLAVE_EBI1 68 -#define QCS615_SLAVE_EMAC_AVB_CFG 69 -#define QCS615_SLAVE_GEM_NOC_SNOC 70 -#define QCS615_SLAVE_GFX3D_CFG 71 -#define QCS615_SLAVE_GLM 72 -#define QCS615_SLAVE_IMEM 73 -#define QCS615_SLAVE_IMEM_CFG 74 -#define QCS615_SLAVE_IPA_CFG 75 -#define QCS615_SLAVE_IPA_CORE 76 -#define QCS615_SLAVE_LLCC 77 -#define QCS615_SLAVE_LLCC_CFG 78 -#define QCS615_SLAVE_LPASS_SNOC 79 -#define QCS615_SLAVE_MEM_NOC_PCIE_SNOC 80 -#define QCS615_SLAVE_MNOC_HF_MEM_NOC 81 -#define QCS615_SLAVE_MNOC_SF_MEM_NOC 82 -#define QCS615_SLAVE_MSS_PROC_MS_MPU_CFG 83 -#define QCS615_SLAVE_PCIE_0 84 -#define QCS615_SLAVE_PCIE_CFG 85 -#define QCS615_SLAVE_PIMEM 86 -#define QCS615_SLAVE_PIMEM_CFG 87 -#define QCS615_SLAVE_PRNG 88 -#define QCS615_SLAVE_QDSS_CFG 89 -#define QCS615_SLAVE_QDSS_STM 90 -#define QCS615_SLAVE_QSPI 91 -#define QCS615_SLAVE_QUP_0 92 -#define QCS615_SLAVE_QUP_1 93 -#define QCS615_SLAVE_RBCPR_CX_CFG 94 -#define QCS615_SLAVE_RBCPR_MX_CFG 95 -#define QCS615_SLAVE_SDCC_1 96 -#define QCS615_SLAVE_SDCC_2 97 -#define QCS615_SLAVE_SERVICE_A2NOC 98 -#define QCS615_SLAVE_SERVICE_CNOC 99 -#define QCS615_SLAVE_SERVICE_GEM_NOC 100 -#define QCS615_SLAVE_SERVICE_MNOC 101 -#define QCS615_SLAVE_SERVICE_SNOC 102 -#define QCS615_SLAVE_SNOC_CFG 103 -#define QCS615_SLAVE_SNOC_CNOC 104 -#define QCS615_SLAVE_SNOC_GEM_NOC_SF 105 -#define QCS615_SLAVE_SNOC_MEM_NOC_GC 106 -#define QCS615_SLAVE_SPDM_WRAPPER 107 -#define QCS615_SLAVE_TCSR 108 -#define QCS615_SLAVE_TCU 109 -#define QCS615_SLAVE_TLMM_EAST 110 -#define QCS615_SLAVE_TLMM_SOUTH 111 -#define QCS615_SLAVE_TLMM_WEST 112 -#define QCS615_SLAVE_UFS_MEM_CFG 113 -#define QCS615_SLAVE_USB2 114 -#define QCS615_SLAVE_USB3 115 -#define QCS615_SLAVE_VENUS_CFG 116 -#define QCS615_SLAVE_VSENSE_CTRL_CFG 117 - -#endif - --=20 2.47.3 From nobody Mon Feb 9 06:05:00 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1883C279789 for ; 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This gives more flexibility and also allows us to drop the .num_links member, saving from possible errors related to it being not set or set incorrectly. Signed-off-by: Dmitry Baryshkov --- drivers/interconnect/qcom/qcs8300.c | 684 ++++++++++++++++----------------= ---- drivers/interconnect/qcom/qcs8300.h | 177 ---------- 2 files changed, 305 insertions(+), 556 deletions(-) diff --git a/drivers/interconnect/qcom/qcs8300.c b/drivers/interconnect/qco= m/qcs8300.c index e7a1b2fc69babe15b914da8d3a3769bfed110179..077f4beb4bd1ae0e508c0683296= f0a38cecc0471 100644 --- a/drivers/interconnect/qcom/qcs8300.c +++ b/drivers/interconnect/qcom/qcs8300.c @@ -13,1465 +13,1378 @@ =20 #include "bcm-voter.h" #include "icc-rpmh.h" -#include "qcs8300.h" + +static struct qcom_icc_node qxm_qup3; +static struct qcom_icc_node xm_emac_0; +static struct qcom_icc_node xm_sdc1; +static struct qcom_icc_node xm_ufs_mem; +static struct qcom_icc_node xm_usb2_2; +static struct qcom_icc_node xm_usb3_0; +static struct qcom_icc_node qhm_qdss_bam; +static struct qcom_icc_node qhm_qup0; +static struct qcom_icc_node qhm_qup1; +static struct qcom_icc_node qnm_cnoc_datapath; +static struct qcom_icc_node qxm_crypto_0; +static struct qcom_icc_node qxm_crypto_1; +static struct qcom_icc_node qxm_ipa; +static struct qcom_icc_node xm_qdss_etr_0; +static struct qcom_icc_node xm_qdss_etr_1; +static struct qcom_icc_node qup0_core_master; +static struct qcom_icc_node qup1_core_master; +static struct qcom_icc_node qup3_core_master; +static struct qcom_icc_node qnm_gemnoc_cnoc; +static struct qcom_icc_node qnm_gemnoc_pcie; +static struct qcom_icc_node qnm_cnoc_dc_noc; +static struct qcom_icc_node alm_gpu_tcu; +static struct qcom_icc_node alm_pcie_tcu; +static struct qcom_icc_node alm_sys_tcu; +static struct qcom_icc_node chm_apps; +static struct qcom_icc_node qnm_cmpnoc0; +static struct qcom_icc_node qnm_gemnoc_cfg; +static struct qcom_icc_node qnm_gpdsp_sail; +static struct qcom_icc_node qnm_gpu; +static struct qcom_icc_node qnm_mnoc_hf; +static struct qcom_icc_node qnm_mnoc_sf; +static struct qcom_icc_node qnm_pcie; +static struct qcom_icc_node qnm_snoc_gc; +static struct qcom_icc_node qnm_snoc_sf; +static struct qcom_icc_node qnm_sailss_md0; +static struct qcom_icc_node qxm_dsp0; +static struct qcom_icc_node qhm_config_noc; +static struct qcom_icc_node qxm_lpass_dsp; +static struct qcom_icc_node llcc_mc; +static struct qcom_icc_node qnm_camnoc_hf; +static struct qcom_icc_node qnm_camnoc_icp; +static struct qcom_icc_node qnm_camnoc_sf; +static struct qcom_icc_node qnm_mdp0_0; +static struct qcom_icc_node qnm_mdp0_1; +static struct qcom_icc_node qnm_mnoc_hf_cfg; +static struct qcom_icc_node qnm_mnoc_sf_cfg; +static struct qcom_icc_node qnm_video0; +static struct qcom_icc_node qnm_video_cvp; +static struct qcom_icc_node qnm_video_v_cpu; +static struct qcom_icc_node qhm_nsp_noc_config; +static struct qcom_icc_node qxm_nsp; +static struct qcom_icc_node xm_pcie3_0; +static struct qcom_icc_node xm_pcie3_1; +static struct qcom_icc_node qhm_gic; +static struct qcom_icc_node qnm_aggre1_noc; +static struct qcom_icc_node qnm_aggre2_noc; +static struct qcom_icc_node qnm_lpass_noc; +static struct qcom_icc_node qnm_snoc_cfg; +static struct qcom_icc_node qxm_pimem; +static struct qcom_icc_node xm_gic; +static struct qcom_icc_node qns_a1noc_snoc; +static struct qcom_icc_node qns_a2noc_snoc; +static struct qcom_icc_node qup0_core_slave; +static struct qcom_icc_node qup1_core_slave; +static struct qcom_icc_node qup3_core_slave; +static struct qcom_icc_node qhs_ahb2phy2; +static struct qcom_icc_node qhs_ahb2phy3; +static struct qcom_icc_node qhs_anoc_throttle_cfg; +static struct qcom_icc_node qhs_aoss; +static struct qcom_icc_node qhs_apss; +static struct qcom_icc_node qhs_boot_rom; +static struct qcom_icc_node qhs_camera_cfg; +static struct qcom_icc_node qhs_camera_nrt_throttle_cfg; +static struct qcom_icc_node qhs_camera_rt_throttle_cfg; +static struct qcom_icc_node qhs_clk_ctl; +static struct qcom_icc_node qhs_compute0_cfg; +static struct qcom_icc_node qhs_cpr_cx; +static struct qcom_icc_node qhs_cpr_mmcx; +static struct qcom_icc_node qhs_cpr_mx; +static struct qcom_icc_node qhs_cpr_nspcx; +static struct qcom_icc_node qhs_cpr_nsphmx; +static struct qcom_icc_node qhs_crypto0_cfg; +static struct qcom_icc_node qhs_cx_rdpm; +static struct qcom_icc_node qhs_display0_cfg; +static struct qcom_icc_node qhs_display0_rt_throttle_cfg; +static struct qcom_icc_node qhs_emac0_cfg; +static struct qcom_icc_node qhs_gp_dsp0_cfg; +static struct qcom_icc_node qhs_gpdsp0_throttle_cfg; +static struct qcom_icc_node qhs_gpu_tcu_throttle_cfg; +static struct qcom_icc_node qhs_gpuss_cfg; +static struct qcom_icc_node qhs_hwkm; +static struct qcom_icc_node qhs_imem_cfg; +static struct qcom_icc_node qhs_ipa; +static struct qcom_icc_node qhs_ipc_router; +static struct qcom_icc_node qhs_lpass_cfg; +static struct qcom_icc_node qhs_lpass_throttle_cfg; +static struct qcom_icc_node qhs_mx_rdpm; +static struct qcom_icc_node qhs_mxc_rdpm; +static struct qcom_icc_node qhs_pcie0_cfg; +static struct qcom_icc_node qhs_pcie1_cfg; +static struct qcom_icc_node qhs_pcie_tcu_throttle_cfg; +static struct qcom_icc_node qhs_pcie_throttle_cfg; +static struct qcom_icc_node qhs_pdm; +static struct qcom_icc_node qhs_pimem_cfg; +static struct qcom_icc_node qhs_pke_wrapper_cfg; +static struct qcom_icc_node qhs_qdss_cfg; +static struct qcom_icc_node qhs_qm_cfg; +static struct qcom_icc_node qhs_qm_mpu_cfg; +static struct qcom_icc_node qhs_qup0; +static struct qcom_icc_node qhs_qup1; +static struct qcom_icc_node qhs_qup3; +static struct qcom_icc_node qhs_sail_throttle_cfg; +static struct qcom_icc_node qhs_sdc1; +static struct qcom_icc_node qhs_security; +static struct qcom_icc_node qhs_snoc_throttle_cfg; +static struct qcom_icc_node qhs_tcsr; +static struct qcom_icc_node qhs_tlmm; +static struct qcom_icc_node qhs_tsc_cfg; +static struct qcom_icc_node qhs_ufs_mem_cfg; +static struct qcom_icc_node qhs_usb2_0; +static struct qcom_icc_node qhs_usb3_0; +static struct qcom_icc_node qhs_venus_cfg; +static struct qcom_icc_node qhs_venus_cvp_throttle_cfg; +static struct qcom_icc_node qhs_venus_v_cpu_throttle_cfg; +static struct qcom_icc_node qhs_venus_vcodec_throttle_cfg; +static struct qcom_icc_node qns_ddrss_cfg; +static struct qcom_icc_node qns_gpdsp_noc_cfg; +static struct qcom_icc_node qns_mnoc_hf_cfg; +static struct qcom_icc_node qns_mnoc_sf_cfg; +static struct qcom_icc_node qns_pcie_anoc_cfg; +static struct qcom_icc_node qns_snoc_cfg; +static struct qcom_icc_node qxs_boot_imem; +static struct qcom_icc_node qxs_imem; +static struct qcom_icc_node qxs_pimem; +static struct qcom_icc_node xs_pcie_0; +static struct qcom_icc_node xs_pcie_1; +static struct qcom_icc_node xs_qdss_stm; +static struct qcom_icc_node xs_sys_tcu_cfg; +static struct qcom_icc_node qhs_llcc; +static struct qcom_icc_node qns_gemnoc; +static struct qcom_icc_node qns_gem_noc_cnoc; +static struct qcom_icc_node qns_llcc; +static struct qcom_icc_node qns_pcie; +static struct qcom_icc_node srvc_even_gemnoc; +static struct qcom_icc_node srvc_odd_gemnoc; +static struct qcom_icc_node srvc_sys_gemnoc; +static struct qcom_icc_node srvc_sys_gemnoc_2; +static struct qcom_icc_node qns_gp_dsp_sail_noc; +static struct qcom_icc_node qhs_lpass_core; +static struct qcom_icc_node qhs_lpass_lpi; +static struct qcom_icc_node qhs_lpass_mpu; +static struct qcom_icc_node qhs_lpass_top; +static struct qcom_icc_node qns_sysnoc; +static struct qcom_icc_node srvc_niu_aml_noc; +static struct qcom_icc_node srvc_niu_lpass_agnoc; +static struct qcom_icc_node ebi; +static struct qcom_icc_node qns_mem_noc_hf; +static struct qcom_icc_node qns_mem_noc_sf; +static struct qcom_icc_node srvc_mnoc_hf; +static struct qcom_icc_node srvc_mnoc_sf; +static struct qcom_icc_node qns_hcp; +static struct qcom_icc_node qns_nsp_gemnoc; +static struct qcom_icc_node service_nsp_noc; +static struct qcom_icc_node qns_pcie_mem_noc; +static struct qcom_icc_node qns_gemnoc_gc; +static struct qcom_icc_node qns_gemnoc_sf; +static struct qcom_icc_node srvc_snoc; =20 static struct qcom_icc_node qxm_qup3 =3D { .name =3D "qxm_qup3", - .id =3D QCS8300_MASTER_QUP_3, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { QCS8300_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node xm_emac_0 =3D { .name =3D "xm_emac_0", - .id =3D QCS8300_MASTER_EMAC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { QCS8300_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node xm_sdc1 =3D { .name =3D "xm_sdc1", - .id =3D QCS8300_MASTER_SDC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { QCS8300_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node xm_ufs_mem =3D { .name =3D "xm_ufs_mem", - .id =3D QCS8300_MASTER_UFS_MEM, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { QCS8300_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node xm_usb2_2 =3D { .name =3D "xm_usb2_2", - .id =3D QCS8300_MASTER_USB2, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { QCS8300_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node xm_usb3_0 =3D { .name =3D "xm_usb3_0", - .id =3D QCS8300_MASTER_USB3_0, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { QCS8300_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node qhm_qdss_bam =3D { .name =3D "qhm_qdss_bam", - .id =3D QCS8300_MASTER_QDSS_BAM, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { QCS8300_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qhm_qup0 =3D { .name =3D "qhm_qup0", - .id =3D QCS8300_MASTER_QUP_0, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { QCS8300_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qhm_qup1 =3D { .name =3D "qhm_qup1", - .id =3D QCS8300_MASTER_QUP_1, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { QCS8300_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qnm_cnoc_datapath =3D { .name =3D "qnm_cnoc_datapath", - .id =3D QCS8300_MASTER_CNOC_A2NOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { QCS8300_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qxm_crypto_0 =3D { .name =3D "qxm_crypto_0", - .id =3D QCS8300_MASTER_CRYPTO_CORE0, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { QCS8300_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qxm_crypto_1 =3D { .name =3D "qxm_crypto_1", - .id =3D QCS8300_MASTER_CRYPTO_CORE1, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { QCS8300_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qxm_ipa =3D { .name =3D "qxm_ipa", - .id =3D QCS8300_MASTER_IPA, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { QCS8300_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node xm_qdss_etr_0 =3D { .name =3D "xm_qdss_etr_0", - .id =3D QCS8300_MASTER_QDSS_ETR_0, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { QCS8300_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node xm_qdss_etr_1 =3D { .name =3D "xm_qdss_etr_1", - .id =3D QCS8300_MASTER_QDSS_ETR_1, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { QCS8300_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qup0_core_master =3D { .name =3D "qup0_core_master", - .id =3D QCS8300_MASTER_QUP_CORE_0, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { QCS8300_SLAVE_QUP_CORE_0 }, + .link_nodes =3D { &qup0_core_slave }, }; =20 static struct qcom_icc_node qup1_core_master =3D { .name =3D "qup1_core_master", - .id =3D QCS8300_MASTER_QUP_CORE_1, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { QCS8300_SLAVE_QUP_CORE_1 }, + .link_nodes =3D { &qup1_core_slave }, }; =20 static struct qcom_icc_node qup3_core_master =3D { .name =3D "qup3_core_master", - .id =3D QCS8300_MASTER_QUP_CORE_3, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { QCS8300_SLAVE_QUP_CORE_3 }, + .link_nodes =3D { &qup3_core_slave }, }; =20 static struct qcom_icc_node qnm_gemnoc_cnoc =3D { .name =3D "qnm_gemnoc_cnoc", - .id =3D QCS8300_MASTER_GEM_NOC_CNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 71, - .links =3D { QCS8300_SLAVE_AHB2PHY_2, QCS8300_SLAVE_AHB2PHY_3, - QCS8300_SLAVE_ANOC_THROTTLE_CFG, QCS8300_SLAVE_AOSS, - QCS8300_SLAVE_APPSS, QCS8300_SLAVE_BOOT_ROM, - QCS8300_SLAVE_CAMERA_CFG, QCS8300_SLAVE_CAMERA_NRT_THROTTLE_CFG, - QCS8300_SLAVE_CAMERA_RT_THROTTLE_CFG, QCS8300_SLAVE_CLK_CTL, - QCS8300_SLAVE_CDSP_CFG, QCS8300_SLAVE_RBCPR_CX_CFG, - QCS8300_SLAVE_RBCPR_MMCX_CFG, QCS8300_SLAVE_RBCPR_MX_CFG, - QCS8300_SLAVE_CPR_NSPCX, QCS8300_SLAVE_CPR_NSPHMX, - QCS8300_SLAVE_CRYPTO_0_CFG, QCS8300_SLAVE_CX_RDPM, - QCS8300_SLAVE_DISPLAY_CFG, QCS8300_SLAVE_DISPLAY_RT_THROTTLE_CFG, - QCS8300_SLAVE_EMAC_CFG, QCS8300_SLAVE_GP_DSP0_CFG, - QCS8300_SLAVE_GPDSP0_THROTTLE_CFG, QCS8300_SLAVE_GPU_TCU_THROTTLE_CF= G, - QCS8300_SLAVE_GFX3D_CFG, QCS8300_SLAVE_HWKM, - QCS8300_SLAVE_IMEM_CFG, QCS8300_SLAVE_IPA_CFG, - QCS8300_SLAVE_IPC_ROUTER_CFG, QCS8300_SLAVE_LPASS, - QCS8300_SLAVE_LPASS_THROTTLE_CFG, QCS8300_SLAVE_MX_RDPM, - QCS8300_SLAVE_MXC_RDPM, QCS8300_SLAVE_PCIE_0_CFG, - QCS8300_SLAVE_PCIE_1_CFG, QCS8300_SLAVE_PCIE_TCU_THROTTLE_CFG, - QCS8300_SLAVE_PCIE_THROTTLE_CFG, QCS8300_SLAVE_PDM, - QCS8300_SLAVE_PIMEM_CFG, QCS8300_SLAVE_PKA_WRAPPER_CFG, - QCS8300_SLAVE_QDSS_CFG, QCS8300_SLAVE_QM_CFG, - QCS8300_SLAVE_QM_MPU_CFG, QCS8300_SLAVE_QUP_0, - QCS8300_SLAVE_QUP_1, QCS8300_SLAVE_QUP_3, - QCS8300_SLAVE_SAIL_THROTTLE_CFG, QCS8300_SLAVE_SDC1, - QCS8300_SLAVE_SECURITY, QCS8300_SLAVE_SNOC_THROTTLE_CFG, - QCS8300_SLAVE_TCSR, QCS8300_SLAVE_TLMM, - QCS8300_SLAVE_TSC_CFG, QCS8300_SLAVE_UFS_MEM_CFG, - QCS8300_SLAVE_USB2, QCS8300_SLAVE_USB3_0, - QCS8300_SLAVE_VENUS_CFG, QCS8300_SLAVE_VENUS_CVP_THROTTLE_CFG, - QCS8300_SLAVE_VENUS_V_CPU_THROTTLE_CFG, - QCS8300_SLAVE_VENUS_VCODEC_THROTTLE_CFG, - QCS8300_SLAVE_DDRSS_CFG, QCS8300_SLAVE_GPDSP_NOC_CFG, - QCS8300_SLAVE_CNOC_MNOC_HF_CFG, QCS8300_SLAVE_CNOC_MNOC_SF_CFG, - QCS8300_SLAVE_PCIE_ANOC_CFG, QCS8300_SLAVE_SNOC_CFG, - QCS8300_SLAVE_BOOT_IMEM, QCS8300_SLAVE_IMEM, - QCS8300_SLAVE_PIMEM, QCS8300_SLAVE_QDSS_STM, - QCS8300_SLAVE_TCU }, + .link_nodes =3D { &qhs_ahb2phy2, &qhs_ahb2phy3, + &qhs_anoc_throttle_cfg, &qhs_aoss, + &qhs_apss, &qhs_boot_rom, + &qhs_camera_cfg, &qhs_camera_nrt_throttle_cfg, + &qhs_camera_rt_throttle_cfg, &qhs_clk_ctl, + &qhs_compute0_cfg, &qhs_cpr_cx, + &qhs_cpr_mmcx, &qhs_cpr_mx, + &qhs_cpr_nspcx, &qhs_cpr_nsphmx, + &qhs_crypto0_cfg, &qhs_cx_rdpm, + &qhs_display0_cfg, &qhs_display0_rt_throttle_cfg, + &qhs_emac0_cfg, &qhs_gp_dsp0_cfg, + &qhs_gpdsp0_throttle_cfg, &qhs_gpu_tcu_throttle_cfg, + &qhs_gpuss_cfg, &qhs_hwkm, + &qhs_imem_cfg, &qhs_ipa, + &qhs_ipc_router, &qhs_lpass_cfg, + &qhs_lpass_throttle_cfg, &qhs_mx_rdpm, + &qhs_mxc_rdpm, &qhs_pcie0_cfg, + &qhs_pcie1_cfg, &qhs_pcie_tcu_throttle_cfg, + &qhs_pcie_throttle_cfg, &qhs_pdm, + &qhs_pimem_cfg, &qhs_pke_wrapper_cfg, + &qhs_qdss_cfg, &qhs_qm_cfg, + &qhs_qm_mpu_cfg, &qhs_qup0, + &qhs_qup1, &qhs_qup3, + &qhs_sail_throttle_cfg, &qhs_sdc1, + &qhs_security, &qhs_snoc_throttle_cfg, + &qhs_tcsr, &qhs_tlmm, + &qhs_tsc_cfg, &qhs_ufs_mem_cfg, + &qhs_usb2_0, &qhs_usb3_0, + &qhs_venus_cfg, &qhs_venus_cvp_throttle_cfg, + &qhs_venus_v_cpu_throttle_cfg, + &qhs_venus_vcodec_throttle_cfg, + &qns_ddrss_cfg, &qns_gpdsp_noc_cfg, + &qns_mnoc_hf_cfg, &qns_mnoc_sf_cfg, + &qns_pcie_anoc_cfg, &qns_snoc_cfg, + &qxs_boot_imem, &qxs_imem, + &qxs_pimem, &xs_qdss_stm, + &xs_sys_tcu_cfg }, }; =20 static struct qcom_icc_node qnm_gemnoc_pcie =3D { .name =3D "qnm_gemnoc_pcie", - .id =3D QCS8300_MASTER_GEM_NOC_PCIE_SNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 2, - .links =3D { QCS8300_SLAVE_PCIE_0, QCS8300_SLAVE_PCIE_1 }, + .link_nodes =3D { &xs_pcie_0, &xs_pcie_1 }, }; =20 static struct qcom_icc_node qnm_cnoc_dc_noc =3D { .name =3D "qnm_cnoc_dc_noc", - .id =3D QCS8300_MASTER_CNOC_DC_NOC, .channels =3D 1, .buswidth =3D 4, .num_links =3D 2, - .links =3D { QCS8300_SLAVE_LLCC_CFG, QCS8300_SLAVE_GEM_NOC_CFG }, + .link_nodes =3D { &qhs_llcc, &qns_gemnoc }, }; =20 static struct qcom_icc_node alm_gpu_tcu =3D { .name =3D "alm_gpu_tcu", - .id =3D QCS8300_MASTER_GPU_TCU, .channels =3D 1, .buswidth =3D 8, .num_links =3D 2, - .links =3D { QCS8300_SLAVE_GEM_NOC_CNOC, QCS8300_SLAVE_LLCC }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; =20 static struct qcom_icc_node alm_pcie_tcu =3D { .name =3D "alm_pcie_tcu", - .id =3D QCS8300_MASTER_PCIE_TCU, .channels =3D 1, .buswidth =3D 8, .num_links =3D 2, - .links =3D { QCS8300_SLAVE_GEM_NOC_CNOC, QCS8300_SLAVE_LLCC }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; =20 static struct qcom_icc_node alm_sys_tcu =3D { .name =3D "alm_sys_tcu", - .id =3D QCS8300_MASTER_SYS_TCU, .channels =3D 1, .buswidth =3D 8, .num_links =3D 2, - .links =3D { QCS8300_SLAVE_GEM_NOC_CNOC, QCS8300_SLAVE_LLCC }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; =20 static struct qcom_icc_node chm_apps =3D { .name =3D "chm_apps", - .id =3D QCS8300_MASTER_APPSS_PROC, .channels =3D 4, .buswidth =3D 32, .num_links =3D 3, - .links =3D { QCS8300_SLAVE_GEM_NOC_CNOC, QCS8300_SLAVE_LLCC, - QCS8300_SLAVE_GEM_NOC_PCIE_CNOC }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, }; =20 static struct qcom_icc_node qnm_cmpnoc0 =3D { .name =3D "qnm_cmpnoc0", - .id =3D QCS8300_MASTER_COMPUTE_NOC, .channels =3D 2, .buswidth =3D 32, .num_links =3D 2, - .links =3D { QCS8300_SLAVE_GEM_NOC_CNOC, QCS8300_SLAVE_LLCC }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; =20 static struct qcom_icc_node qnm_gemnoc_cfg =3D { .name =3D "qnm_gemnoc_cfg", - .id =3D QCS8300_MASTER_GEM_NOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 4, - .links =3D { QCS8300_SLAVE_SERVICE_GEM_NOC_1, QCS8300_SLAVE_SERVICE_GEM_N= OC_2, - QCS8300_SLAVE_SERVICE_GEM_NOC, QCS8300_SLAVE_SERVICE_GEM_NOC2 }, + .link_nodes =3D { &srvc_even_gemnoc, &srvc_odd_gemnoc, + &srvc_sys_gemnoc, &srvc_sys_gemnoc_2 }, }; =20 static struct qcom_icc_node qnm_gpdsp_sail =3D { .name =3D "qnm_gpdsp_sail", - .id =3D QCS8300_MASTER_GPDSP_SAIL, .channels =3D 1, .buswidth =3D 16, .num_links =3D 2, - .links =3D { QCS8300_SLAVE_GEM_NOC_CNOC, QCS8300_SLAVE_LLCC }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; =20 static struct qcom_icc_node qnm_gpu =3D { .name =3D "qnm_gpu", - .id =3D QCS8300_MASTER_GFX3D, .channels =3D 2, .buswidth =3D 32, .num_links =3D 2, - .links =3D { QCS8300_SLAVE_GEM_NOC_CNOC, QCS8300_SLAVE_LLCC }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; =20 static struct qcom_icc_node qnm_mnoc_hf =3D { .name =3D "qnm_mnoc_hf", - .id =3D QCS8300_MASTER_MNOC_HF_MEM_NOC, .channels =3D 2, .buswidth =3D 32, .num_links =3D 2, - .links =3D { QCS8300_SLAVE_LLCC, QCS8300_SLAVE_GEM_NOC_PCIE_CNOC }, + .link_nodes =3D { &qns_llcc, &qns_pcie }, }; =20 static struct qcom_icc_node qnm_mnoc_sf =3D { .name =3D "qnm_mnoc_sf", - .id =3D QCS8300_MASTER_MNOC_SF_MEM_NOC, .channels =3D 2, .buswidth =3D 32, .num_links =3D 3, - .links =3D { QCS8300_SLAVE_GEM_NOC_CNOC, QCS8300_SLAVE_LLCC, - QCS8300_SLAVE_GEM_NOC_PCIE_CNOC }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, }; =20 static struct qcom_icc_node qnm_pcie =3D { .name =3D "qnm_pcie", - .id =3D QCS8300_MASTER_ANOC_PCIE_GEM_NOC, .channels =3D 1, .buswidth =3D 32, .num_links =3D 2, - .links =3D { QCS8300_SLAVE_GEM_NOC_CNOC, QCS8300_SLAVE_LLCC }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; =20 static struct qcom_icc_node qnm_snoc_gc =3D { .name =3D "qnm_snoc_gc", - .id =3D QCS8300_MASTER_SNOC_GC_MEM_NOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { QCS8300_SLAVE_LLCC }, + .link_nodes =3D { &qns_llcc }, }; =20 static struct qcom_icc_node qnm_snoc_sf =3D { .name =3D "qnm_snoc_sf", - .id =3D QCS8300_MASTER_SNOC_SF_MEM_NOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 3, - .links =3D { QCS8300_SLAVE_GEM_NOC_CNOC, QCS8300_SLAVE_LLCC, - QCS8300_SLAVE_GEM_NOC_PCIE_CNOC }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, }; =20 static struct qcom_icc_node qnm_sailss_md0 =3D { .name =3D "qnm_sailss_md0", - .id =3D QCS8300_MASTER_SAILSS_MD0, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { QCS8300_SLAVE_GP_DSP_SAIL_NOC }, + .link_nodes =3D { &qns_gp_dsp_sail_noc }, }; =20 static struct qcom_icc_node qxm_dsp0 =3D { .name =3D "qxm_dsp0", - .id =3D QCS8300_MASTER_DSP0, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { QCS8300_SLAVE_GP_DSP_SAIL_NOC }, + .link_nodes =3D { &qns_gp_dsp_sail_noc }, }; =20 static struct qcom_icc_node qhm_config_noc =3D { .name =3D "qhm_config_noc", - .id =3D QCS8300_MASTER_CNOC_LPASS_AG_NOC, .channels =3D 1, .buswidth =3D 4, .num_links =3D 6, - .links =3D { QCS8300_SLAVE_LPASS_CORE_CFG, QCS8300_SLAVE_LPASS_LPI_CFG, - QCS8300_SLAVE_LPASS_MPU_CFG, QCS8300_SLAVE_LPASS_TOP_CFG, - QCS8300_SLAVE_SERVICES_LPASS_AML_NOC, QCS8300_SLAVE_SERVICE_LPASS_AG_= NOC }, + .link_nodes =3D { &qhs_lpass_core, &qhs_lpass_lpi, + &qhs_lpass_mpu, &qhs_lpass_top, + &srvc_niu_aml_noc, &srvc_niu_lpass_agnoc }, }; =20 static struct qcom_icc_node qxm_lpass_dsp =3D { .name =3D "qxm_lpass_dsp", - .id =3D QCS8300_MASTER_LPASS_PROC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 4, - .links =3D { QCS8300_SLAVE_LPASS_TOP_CFG, QCS8300_SLAVE_LPASS_SNOC, - QCS8300_SLAVE_SERVICES_LPASS_AML_NOC, QCS8300_SLAVE_SERVICE_LPASS_AG_= NOC }, + .link_nodes =3D { &qhs_lpass_top, &qns_sysnoc, + &srvc_niu_aml_noc, &srvc_niu_lpass_agnoc }, }; =20 static struct qcom_icc_node llcc_mc =3D { .name =3D "llcc_mc", - .id =3D QCS8300_MASTER_LLCC, .channels =3D 8, .buswidth =3D 4, .num_links =3D 1, - .links =3D { QCS8300_SLAVE_EBI1 }, + .link_nodes =3D { &ebi }, }; =20 static struct qcom_icc_node qnm_camnoc_hf =3D { .name =3D "qnm_camnoc_hf", - .id =3D QCS8300_MASTER_CAMNOC_HF, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { QCS8300_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_hf }, }; =20 static struct qcom_icc_node qnm_camnoc_icp =3D { .name =3D "qnm_camnoc_icp", - .id =3D QCS8300_MASTER_CAMNOC_ICP, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { QCS8300_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static struct qcom_icc_node qnm_camnoc_sf =3D { .name =3D "qnm_camnoc_sf", - .id =3D QCS8300_MASTER_CAMNOC_SF, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { QCS8300_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static struct qcom_icc_node qnm_mdp0_0 =3D { .name =3D "qnm_mdp0_0", - .id =3D QCS8300_MASTER_MDP0, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { QCS8300_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_hf }, }; =20 static struct qcom_icc_node qnm_mdp0_1 =3D { .name =3D "qnm_mdp0_1", - .id =3D QCS8300_MASTER_MDP1, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { QCS8300_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_hf }, }; =20 static struct qcom_icc_node qnm_mnoc_hf_cfg =3D { .name =3D "qnm_mnoc_hf_cfg", - .id =3D QCS8300_MASTER_CNOC_MNOC_HF_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { QCS8300_SLAVE_SERVICE_MNOC_HF }, + .link_nodes =3D { &srvc_mnoc_hf }, }; =20 static struct qcom_icc_node qnm_mnoc_sf_cfg =3D { .name =3D "qnm_mnoc_sf_cfg", - .id =3D QCS8300_MASTER_CNOC_MNOC_SF_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { QCS8300_SLAVE_SERVICE_MNOC_SF }, + .link_nodes =3D { &srvc_mnoc_sf }, }; =20 static struct qcom_icc_node qnm_video0 =3D { .name =3D "qnm_video0", - .id =3D QCS8300_MASTER_VIDEO_P0, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { QCS8300_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static struct qcom_icc_node qnm_video_cvp =3D { .name =3D "qnm_video_cvp", - .id =3D QCS8300_MASTER_VIDEO_PROC, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { QCS8300_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static struct qcom_icc_node qnm_video_v_cpu =3D { .name =3D "qnm_video_v_cpu", - .id =3D QCS8300_MASTER_VIDEO_V_PROC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { QCS8300_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static struct qcom_icc_node qhm_nsp_noc_config =3D { .name =3D "qhm_nsp_noc_config", - .id =3D QCS8300_MASTER_CDSP_NOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { QCS8300_SLAVE_SERVICE_NSP_NOC }, + .link_nodes =3D { &service_nsp_noc }, }; =20 static struct qcom_icc_node qxm_nsp =3D { .name =3D "qxm_nsp", - .id =3D QCS8300_MASTER_CDSP_PROC, .channels =3D 2, .buswidth =3D 32, - .num_links =3D 2, - .links =3D { QCS8300_SLAVE_HCP_A, QCS8300_SLAVE_CDSP_MEM_NOC }, + .num_links =3D 1, + .link_nodes =3D { &qns_hcp, &qns_nsp_gemnoc }, }; =20 static struct qcom_icc_node xm_pcie3_0 =3D { .name =3D "xm_pcie3_0", - .id =3D QCS8300_MASTER_PCIE_0, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { QCS8300_SLAVE_ANOC_PCIE_GEM_NOC }, + .link_nodes =3D { &qns_pcie_mem_noc }, }; =20 static struct qcom_icc_node xm_pcie3_1 =3D { .name =3D "xm_pcie3_1", - .id =3D QCS8300_MASTER_PCIE_1, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { QCS8300_SLAVE_ANOC_PCIE_GEM_NOC }, + .link_nodes =3D { &qns_pcie_mem_noc }, }; =20 static struct qcom_icc_node qhm_gic =3D { .name =3D "qhm_gic", - .id =3D QCS8300_MASTER_GIC_AHB, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { QCS8300_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes =3D { &qns_gemnoc_sf }, }; =20 static struct qcom_icc_node qnm_aggre1_noc =3D { .name =3D "qnm_aggre1_noc", - .id =3D QCS8300_MASTER_A1NOC_SNOC, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { QCS8300_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes =3D { &qns_gemnoc_sf }, }; =20 static struct qcom_icc_node qnm_aggre2_noc =3D { .name =3D "qnm_aggre2_noc", - .id =3D QCS8300_MASTER_A2NOC_SNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { QCS8300_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes =3D { &qns_gemnoc_sf }, }; =20 static struct qcom_icc_node qnm_lpass_noc =3D { .name =3D "qnm_lpass_noc", - .id =3D QCS8300_MASTER_LPASS_ANOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { QCS8300_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes =3D { &qns_gemnoc_sf }, }; =20 static struct qcom_icc_node qnm_snoc_cfg =3D { .name =3D "qnm_snoc_cfg", - .id =3D QCS8300_MASTER_SNOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { QCS8300_SLAVE_SERVICE_SNOC }, + .link_nodes =3D { &srvc_snoc }, }; =20 static struct qcom_icc_node qxm_pimem =3D { .name =3D "qxm_pimem", - .id =3D QCS8300_MASTER_PIMEM, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { QCS8300_SLAVE_SNOC_GEM_NOC_GC }, + .link_nodes =3D { &qns_gemnoc_gc }, }; =20 static struct qcom_icc_node xm_gic =3D { .name =3D "xm_gic", - .id =3D QCS8300_MASTER_GIC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { QCS8300_SLAVE_SNOC_GEM_NOC_GC }, + .link_nodes =3D { &qns_gemnoc_gc }, }; =20 static struct qcom_icc_node qns_a1noc_snoc =3D { .name =3D "qns_a1noc_snoc", - .id =3D QCS8300_SLAVE_A1NOC_SNOC, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { QCS8300_MASTER_A1NOC_SNOC }, + .link_nodes =3D { &qnm_aggre1_noc }, }; =20 static struct qcom_icc_node qns_a2noc_snoc =3D { .name =3D "qns_a2noc_snoc", - .id =3D QCS8300_SLAVE_A2NOC_SNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { QCS8300_MASTER_A2NOC_SNOC }, + .link_nodes =3D { &qnm_aggre2_noc }, }; =20 static struct qcom_icc_node qup0_core_slave =3D { .name =3D "qup0_core_slave", - .id =3D QCS8300_SLAVE_QUP_CORE_0, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qup1_core_slave =3D { .name =3D "qup1_core_slave", - .id =3D QCS8300_SLAVE_QUP_CORE_1, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qup3_core_slave =3D { .name =3D "qup3_core_slave", - .id =3D QCS8300_SLAVE_QUP_CORE_3, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_ahb2phy2 =3D { .name =3D "qhs_ahb2phy2", - .id =3D QCS8300_SLAVE_AHB2PHY_2, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_ahb2phy3 =3D { .name =3D "qhs_ahb2phy3", - .id =3D QCS8300_SLAVE_AHB2PHY_3, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_anoc_throttle_cfg =3D { .name =3D "qhs_anoc_throttle_cfg", - .id =3D QCS8300_SLAVE_ANOC_THROTTLE_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_aoss =3D { .name =3D "qhs_aoss", - .id =3D QCS8300_SLAVE_AOSS, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_apss =3D { .name =3D "qhs_apss", - .id =3D QCS8300_SLAVE_APPSS, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_boot_rom =3D { .name =3D "qhs_boot_rom", - .id =3D QCS8300_SLAVE_BOOT_ROM, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_camera_cfg =3D { .name =3D "qhs_camera_cfg", - .id =3D QCS8300_SLAVE_CAMERA_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_camera_nrt_throttle_cfg =3D { .name =3D "qhs_camera_nrt_throttle_cfg", - .id =3D QCS8300_SLAVE_CAMERA_NRT_THROTTLE_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_camera_rt_throttle_cfg =3D { .name =3D "qhs_camera_rt_throttle_cfg", - .id =3D QCS8300_SLAVE_CAMERA_RT_THROTTLE_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_clk_ctl =3D { .name =3D "qhs_clk_ctl", - .id =3D QCS8300_SLAVE_CLK_CTL, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_compute0_cfg =3D { .name =3D "qhs_compute0_cfg", - .id =3D QCS8300_SLAVE_CDSP_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { QCS8300_MASTER_CDSP_NOC_CFG }, + .link_nodes =3D { &qhm_nsp_noc_config }, }; =20 static struct qcom_icc_node qhs_cpr_cx =3D { .name =3D "qhs_cpr_cx", - .id =3D QCS8300_SLAVE_RBCPR_CX_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_cpr_mmcx =3D { .name =3D "qhs_cpr_mmcx", - .id =3D QCS8300_SLAVE_RBCPR_MMCX_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_cpr_mx =3D { .name =3D "qhs_cpr_mx", - .id =3D QCS8300_SLAVE_RBCPR_MX_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_cpr_nspcx =3D { .name =3D "qhs_cpr_nspcx", - .id =3D QCS8300_SLAVE_CPR_NSPCX, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_cpr_nsphmx =3D { .name =3D "qhs_cpr_nsphmx", - .id =3D QCS8300_SLAVE_CPR_NSPHMX, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_crypto0_cfg =3D { .name =3D "qhs_crypto0_cfg", - .id =3D QCS8300_SLAVE_CRYPTO_0_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_cx_rdpm =3D { .name =3D "qhs_cx_rdpm", - .id =3D QCS8300_SLAVE_CX_RDPM, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_display0_cfg =3D { .name =3D "qhs_display0_cfg", - .id =3D QCS8300_SLAVE_DISPLAY_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_display0_rt_throttle_cfg =3D { .name =3D "qhs_display0_rt_throttle_cfg", - .id =3D QCS8300_SLAVE_DISPLAY_RT_THROTTLE_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_emac0_cfg =3D { .name =3D "qhs_emac0_cfg", - .id =3D QCS8300_SLAVE_EMAC_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_gp_dsp0_cfg =3D { .name =3D "qhs_gp_dsp0_cfg", - .id =3D QCS8300_SLAVE_GP_DSP0_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_gpdsp0_throttle_cfg =3D { .name =3D "qhs_gpdsp0_throttle_cfg", - .id =3D QCS8300_SLAVE_GPDSP0_THROTTLE_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_gpu_tcu_throttle_cfg =3D { .name =3D "qhs_gpu_tcu_throttle_cfg", - .id =3D QCS8300_SLAVE_GPU_TCU_THROTTLE_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_gpuss_cfg =3D { .name =3D "qhs_gpuss_cfg", - .id =3D QCS8300_SLAVE_GFX3D_CFG, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_hwkm =3D { .name =3D "qhs_hwkm", - .id =3D QCS8300_SLAVE_HWKM, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_imem_cfg =3D { .name =3D "qhs_imem_cfg", - .id =3D QCS8300_SLAVE_IMEM_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_ipa =3D { .name =3D "qhs_ipa", - .id =3D QCS8300_SLAVE_IPA_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_ipc_router =3D { .name =3D "qhs_ipc_router", - .id =3D QCS8300_SLAVE_IPC_ROUTER_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_lpass_cfg =3D { .name =3D "qhs_lpass_cfg", - .id =3D QCS8300_SLAVE_LPASS, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { QCS8300_MASTER_CNOC_LPASS_AG_NOC }, + .link_nodes =3D { &qhm_config_noc }, }; =20 static struct qcom_icc_node qhs_lpass_throttle_cfg =3D { .name =3D "qhs_lpass_throttle_cfg", - .id =3D QCS8300_SLAVE_LPASS_THROTTLE_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_mx_rdpm =3D { .name =3D "qhs_mx_rdpm", - .id =3D QCS8300_SLAVE_MX_RDPM, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_mxc_rdpm =3D { .name =3D "qhs_mxc_rdpm", - .id =3D QCS8300_SLAVE_MXC_RDPM, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_pcie0_cfg =3D { .name =3D "qhs_pcie0_cfg", - .id =3D QCS8300_SLAVE_PCIE_0_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_pcie1_cfg =3D { .name =3D "qhs_pcie1_cfg", - .id =3D QCS8300_SLAVE_PCIE_1_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_pcie_tcu_throttle_cfg =3D { .name =3D "qhs_pcie_tcu_throttle_cfg", - .id =3D QCS8300_SLAVE_PCIE_TCU_THROTTLE_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_pcie_throttle_cfg =3D { .name =3D "qhs_pcie_throttle_cfg", - .id =3D QCS8300_SLAVE_PCIE_THROTTLE_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_pdm =3D { .name =3D "qhs_pdm", - .id =3D QCS8300_SLAVE_PDM, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_pimem_cfg =3D { .name =3D "qhs_pimem_cfg", - .id =3D QCS8300_SLAVE_PIMEM_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_pke_wrapper_cfg =3D { .name =3D "qhs_pke_wrapper_cfg", - .id =3D QCS8300_SLAVE_PKA_WRAPPER_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_qdss_cfg =3D { .name =3D "qhs_qdss_cfg", - .id =3D QCS8300_SLAVE_QDSS_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_qm_cfg =3D { .name =3D "qhs_qm_cfg", - .id =3D QCS8300_SLAVE_QM_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_qm_mpu_cfg =3D { .name =3D "qhs_qm_mpu_cfg", - .id =3D QCS8300_SLAVE_QM_MPU_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_qup0 =3D { .name =3D "qhs_qup0", - .id =3D QCS8300_SLAVE_QUP_0, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_qup1 =3D { .name =3D "qhs_qup1", - .id =3D QCS8300_SLAVE_QUP_1, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_qup3 =3D { .name =3D "qhs_qup3", - .id =3D QCS8300_SLAVE_QUP_3, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_sail_throttle_cfg =3D { .name =3D "qhs_sail_throttle_cfg", - .id =3D QCS8300_SLAVE_SAIL_THROTTLE_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_sdc1 =3D { .name =3D "qhs_sdc1", - .id =3D QCS8300_SLAVE_SDC1, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_security =3D { .name =3D "qhs_security", - .id =3D QCS8300_SLAVE_SECURITY, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_snoc_throttle_cfg =3D { .name =3D "qhs_snoc_throttle_cfg", - .id =3D QCS8300_SLAVE_SNOC_THROTTLE_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_tcsr =3D { .name =3D "qhs_tcsr", - .id =3D QCS8300_SLAVE_TCSR, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_tlmm =3D { .name =3D "qhs_tlmm", - .id =3D QCS8300_SLAVE_TLMM, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_tsc_cfg =3D { .name =3D "qhs_tsc_cfg", - .id =3D QCS8300_SLAVE_TSC_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_ufs_mem_cfg =3D { .name =3D "qhs_ufs_mem_cfg", - .id =3D QCS8300_SLAVE_UFS_MEM_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_usb2_0 =3D { .name =3D "qhs_usb2_0", - .id =3D QCS8300_SLAVE_USB2, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_usb3_0 =3D { .name =3D "qhs_usb3_0", - .id =3D QCS8300_SLAVE_USB3_0, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_venus_cfg =3D { .name =3D "qhs_venus_cfg", - .id =3D QCS8300_SLAVE_VENUS_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_venus_cvp_throttle_cfg =3D { .name =3D "qhs_venus_cvp_throttle_cfg", - .id =3D QCS8300_SLAVE_VENUS_CVP_THROTTLE_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_venus_v_cpu_throttle_cfg =3D { .name =3D "qhs_venus_v_cpu_throttle_cfg", - .id =3D QCS8300_SLAVE_VENUS_V_CPU_THROTTLE_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_venus_vcodec_throttle_cfg =3D { .name =3D "qhs_venus_vcodec_throttle_cfg", - .id =3D QCS8300_SLAVE_VENUS_VCODEC_THROTTLE_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qns_ddrss_cfg =3D { .name =3D "qns_ddrss_cfg", - .id =3D QCS8300_SLAVE_DDRSS_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { QCS8300_MASTER_CNOC_DC_NOC }, + .link_nodes =3D { &qnm_cnoc_dc_noc }, }; =20 static struct qcom_icc_node qns_gpdsp_noc_cfg =3D { .name =3D "qns_gpdsp_noc_cfg", - .id =3D QCS8300_SLAVE_GPDSP_NOC_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qns_mnoc_hf_cfg =3D { .name =3D "qns_mnoc_hf_cfg", - .id =3D QCS8300_SLAVE_CNOC_MNOC_HF_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { QCS8300_MASTER_CNOC_MNOC_HF_CFG }, + .link_nodes =3D { &qnm_mnoc_hf_cfg }, }; =20 static struct qcom_icc_node qns_mnoc_sf_cfg =3D { .name =3D "qns_mnoc_sf_cfg", - .id =3D QCS8300_SLAVE_CNOC_MNOC_SF_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { QCS8300_MASTER_CNOC_MNOC_SF_CFG }, + .link_nodes =3D { &qnm_mnoc_sf_cfg }, }; =20 static struct qcom_icc_node qns_pcie_anoc_cfg =3D { .name =3D "qns_pcie_anoc_cfg", - .id =3D QCS8300_SLAVE_PCIE_ANOC_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qns_snoc_cfg =3D { .name =3D "qns_snoc_cfg", - .id =3D QCS8300_SLAVE_SNOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { QCS8300_MASTER_SNOC_CFG }, + .link_nodes =3D { &qnm_snoc_cfg }, }; =20 static struct qcom_icc_node qxs_boot_imem =3D { .name =3D "qxs_boot_imem", - .id =3D QCS8300_SLAVE_BOOT_IMEM, .channels =3D 1, .buswidth =3D 16, - .num_links =3D 0, }; =20 static struct qcom_icc_node qxs_imem =3D { .name =3D "qxs_imem", - .id =3D QCS8300_SLAVE_IMEM, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 0, }; =20 static struct qcom_icc_node qxs_pimem =3D { .name =3D "qxs_pimem", - .id =3D QCS8300_SLAVE_PIMEM, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 0, }; =20 static struct qcom_icc_node xs_pcie_0 =3D { .name =3D "xs_pcie_0", - .id =3D QCS8300_SLAVE_PCIE_0, .channels =3D 1, .buswidth =3D 16, - .num_links =3D 0, }; =20 static struct qcom_icc_node xs_pcie_1 =3D { .name =3D "xs_pcie_1", - .id =3D QCS8300_SLAVE_PCIE_1, .channels =3D 1, .buswidth =3D 32, - .num_links =3D 0, }; =20 static struct qcom_icc_node xs_qdss_stm =3D { .name =3D "xs_qdss_stm", - .id =3D QCS8300_SLAVE_QDSS_STM, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node xs_sys_tcu_cfg =3D { .name =3D "xs_sys_tcu_cfg", - .id =3D QCS8300_SLAVE_TCU, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_llcc =3D { .name =3D "qhs_llcc", - .id =3D QCS8300_SLAVE_LLCC_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qns_gemnoc =3D { .name =3D "qns_gemnoc", - .id =3D QCS8300_SLAVE_GEM_NOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { QCS8300_MASTER_GEM_NOC_CFG }, + .link_nodes =3D { &qnm_gemnoc_cfg }, }; =20 static struct qcom_icc_node qns_gem_noc_cnoc =3D { .name =3D "qns_gem_noc_cnoc", - .id =3D QCS8300_SLAVE_GEM_NOC_CNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { QCS8300_MASTER_GEM_NOC_CNOC }, + .link_nodes =3D { &qnm_gemnoc_cnoc }, }; =20 static struct qcom_icc_node qns_llcc =3D { .name =3D "qns_llcc", - .id =3D QCS8300_SLAVE_LLCC, .channels =3D 4, .buswidth =3D 16, .num_links =3D 1, - .links =3D { QCS8300_MASTER_LLCC }, + .link_nodes =3D { &llcc_mc }, }; =20 static struct qcom_icc_node qns_pcie =3D { .name =3D "qns_pcie", - .id =3D QCS8300_SLAVE_GEM_NOC_PCIE_CNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { QCS8300_MASTER_GEM_NOC_PCIE_SNOC }, + .link_nodes =3D { &qnm_gemnoc_pcie }, }; =20 static struct qcom_icc_node srvc_even_gemnoc =3D { .name =3D "srvc_even_gemnoc", - .id =3D QCS8300_SLAVE_SERVICE_GEM_NOC_1, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node srvc_odd_gemnoc =3D { .name =3D "srvc_odd_gemnoc", - .id =3D QCS8300_SLAVE_SERVICE_GEM_NOC_2, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node srvc_sys_gemnoc =3D { .name =3D "srvc_sys_gemnoc", - .id =3D QCS8300_SLAVE_SERVICE_GEM_NOC, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node srvc_sys_gemnoc_2 =3D { .name =3D "srvc_sys_gemnoc_2", - .id =3D QCS8300_SLAVE_SERVICE_GEM_NOC2, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qns_gp_dsp_sail_noc =3D { .name =3D "qns_gp_dsp_sail_noc", - .id =3D QCS8300_SLAVE_GP_DSP_SAIL_NOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { QCS8300_MASTER_GPDSP_SAIL }, + .link_nodes =3D { &qnm_gpdsp_sail }, }; =20 static struct qcom_icc_node qhs_lpass_core =3D { .name =3D "qhs_lpass_core", - .id =3D QCS8300_SLAVE_LPASS_CORE_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_lpass_lpi =3D { .name =3D "qhs_lpass_lpi", - .id =3D QCS8300_SLAVE_LPASS_LPI_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_lpass_mpu =3D { .name =3D "qhs_lpass_mpu", - .id =3D QCS8300_SLAVE_LPASS_MPU_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_lpass_top =3D { .name =3D "qhs_lpass_top", - .id =3D QCS8300_SLAVE_LPASS_TOP_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qns_sysnoc =3D { .name =3D "qns_sysnoc", - .id =3D QCS8300_SLAVE_LPASS_SNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { QCS8300_MASTER_LPASS_ANOC }, + .link_nodes =3D { &qnm_lpass_noc }, }; =20 static struct qcom_icc_node srvc_niu_aml_noc =3D { .name =3D "srvc_niu_aml_noc", - .id =3D QCS8300_SLAVE_SERVICES_LPASS_AML_NOC, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node srvc_niu_lpass_agnoc =3D { .name =3D "srvc_niu_lpass_agnoc", - .id =3D QCS8300_SLAVE_SERVICE_LPASS_AG_NOC, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node ebi =3D { .name =3D "ebi", - .id =3D QCS8300_SLAVE_EBI1, .channels =3D 8, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qns_mem_noc_hf =3D { .name =3D "qns_mem_noc_hf", - .id =3D QCS8300_SLAVE_MNOC_HF_MEM_NOC, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { QCS8300_MASTER_MNOC_HF_MEM_NOC }, + .link_nodes =3D { &qnm_mnoc_hf }, }; =20 static struct qcom_icc_node qns_mem_noc_sf =3D { .name =3D "qns_mem_noc_sf", - .id =3D QCS8300_SLAVE_MNOC_SF_MEM_NOC, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { QCS8300_MASTER_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qnm_mnoc_sf }, }; =20 static struct qcom_icc_node srvc_mnoc_hf =3D { .name =3D "srvc_mnoc_hf", - .id =3D QCS8300_SLAVE_SERVICE_MNOC_HF, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node srvc_mnoc_sf =3D { .name =3D "srvc_mnoc_sf", - .id =3D QCS8300_SLAVE_SERVICE_MNOC_SF, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qns_hcp =3D { .name =3D "qns_hcp", - .id =3D QCS8300_SLAVE_HCP_A, .channels =3D 2, .buswidth =3D 32, - .num_links =3D 0, }; =20 static struct qcom_icc_node qns_nsp_gemnoc =3D { .name =3D "qns_nsp_gemnoc", - .id =3D QCS8300_SLAVE_CDSP_MEM_NOC, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { QCS8300_MASTER_COMPUTE_NOC }, + .link_nodes =3D { &qnm_cmpnoc0 }, }; =20 static struct qcom_icc_node service_nsp_noc =3D { .name =3D "service_nsp_noc", - .id =3D QCS8300_SLAVE_SERVICE_NSP_NOC, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qns_pcie_mem_noc =3D { .name =3D "qns_pcie_mem_noc", - .id =3D QCS8300_SLAVE_ANOC_PCIE_GEM_NOC, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { QCS8300_MASTER_ANOC_PCIE_GEM_NOC }, + .link_nodes =3D { &qnm_pcie }, }; =20 static struct qcom_icc_node qns_gemnoc_gc =3D { .name =3D "qns_gemnoc_gc", - .id =3D QCS8300_SLAVE_SNOC_GEM_NOC_GC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { QCS8300_MASTER_SNOC_GC_MEM_NOC }, + .link_nodes =3D { &qnm_snoc_gc }, }; =20 static struct qcom_icc_node qns_gemnoc_sf =3D { .name =3D "qns_gemnoc_sf", - .id =3D QCS8300_SLAVE_SNOC_GEM_NOC_SF, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { QCS8300_MASTER_SNOC_SF_MEM_NOC }, + .link_nodes =3D { &qnm_snoc_sf }, }; =20 static struct qcom_icc_node srvc_snoc =3D { .name =3D "srvc_snoc", - .id =3D QCS8300_SLAVE_SERVICE_SNOC, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_bcm bcm_acv =3D { @@ -1687,6 +1600,7 @@ static struct qcom_icc_node * const aggre1_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc qcs8300_aggre1_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D aggre1_noc_nodes, .num_nodes =3D ARRAY_SIZE(aggre1_noc_nodes), .bcms =3D aggre1_noc_bcms, @@ -1712,6 +1626,7 @@ static struct qcom_icc_node * const aggre2_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc qcs8300_aggre2_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D aggre2_noc_nodes, .num_nodes =3D ARRAY_SIZE(aggre2_noc_nodes), .bcms =3D aggre2_noc_bcms, @@ -1734,6 +1649,7 @@ static struct qcom_icc_node * const clk_virt_nodes[] = =3D { }; =20 static const struct qcom_icc_desc qcs8300_clk_virt =3D { + .alloc_dyn_id =3D true, .nodes =3D clk_virt_nodes, .num_nodes =3D ARRAY_SIZE(clk_virt_nodes), .bcms =3D clk_virt_bcms, @@ -1828,6 +1744,7 @@ static struct qcom_icc_node * const config_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc qcs8300_config_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D config_noc_nodes, .num_nodes =3D ARRAY_SIZE(config_noc_nodes), .bcms =3D config_noc_bcms, @@ -1841,6 +1758,7 @@ static struct qcom_icc_node * const dc_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc qcs8300_dc_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D dc_noc_nodes, .num_nodes =3D ARRAY_SIZE(dc_noc_nodes), }; @@ -1874,6 +1792,7 @@ static struct qcom_icc_node * const gem_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc qcs8300_gem_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D gem_noc_nodes, .num_nodes =3D ARRAY_SIZE(gem_noc_nodes), .bcms =3D gem_noc_bcms, @@ -1891,6 +1810,7 @@ static struct qcom_icc_node * const gpdsp_anoc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc qcs8300_gpdsp_anoc =3D { + .alloc_dyn_id =3D true, .nodes =3D gpdsp_anoc_nodes, .num_nodes =3D ARRAY_SIZE(gpdsp_anoc_nodes), .bcms =3D gpdsp_anoc_bcms, @@ -1914,6 +1834,7 @@ static struct qcom_icc_node * const lpass_ag_noc_node= s[] =3D { }; =20 static const struct qcom_icc_desc qcs8300_lpass_ag_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D lpass_ag_noc_nodes, .num_nodes =3D ARRAY_SIZE(lpass_ag_noc_nodes), .bcms =3D lpass_ag_noc_bcms, @@ -1931,6 +1852,7 @@ static struct qcom_icc_node * const mc_virt_nodes[] = =3D { }; =20 static const struct qcom_icc_desc qcs8300_mc_virt =3D { + .alloc_dyn_id =3D true, .nodes =3D mc_virt_nodes, .num_nodes =3D ARRAY_SIZE(mc_virt_nodes), .bcms =3D mc_virt_bcms, @@ -1960,6 +1882,7 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc qcs8300_mmss_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D mmss_noc_nodes, .num_nodes =3D ARRAY_SIZE(mmss_noc_nodes), .bcms =3D mmss_noc_bcms, @@ -1980,6 +1903,7 @@ static struct qcom_icc_node * const nspa_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc qcs8300_nspa_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D nspa_noc_nodes, .num_nodes =3D ARRAY_SIZE(nspa_noc_nodes), .bcms =3D nspa_noc_bcms, @@ -1997,6 +1921,7 @@ static struct qcom_icc_node * const pcie_anoc_nodes[]= =3D { }; =20 static const struct qcom_icc_desc qcs8300_pcie_anoc =3D { + .alloc_dyn_id =3D true, .nodes =3D pcie_anoc_nodes, .num_nodes =3D ARRAY_SIZE(pcie_anoc_nodes), .bcms =3D pcie_anoc_bcms, @@ -2025,6 +1950,7 @@ static struct qcom_icc_node * const system_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc qcs8300_system_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D system_noc_nodes, .num_nodes =3D ARRAY_SIZE(system_noc_nodes), .bcms =3D system_noc_bcms, diff --git a/drivers/interconnect/qcom/qcs8300.h b/drivers/interconnect/qco= m/qcs8300.h deleted file mode 100644 index 6b9e2b424c2ad0401f72d5fb8cfb7e0f48a1db85..000000000000000000000000000= 0000000000000 --- a/drivers/interconnect/qcom/qcs8300.h +++ /dev/null @@ -1,177 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserve= d. - */ - -#ifndef __DRIVERS_INTERCONNECT_QCOM_QCS8300_H -#define __DRIVERS_INTERCONNECT_QCOM_QCS8300_H - -#define QCS8300_MASTER_GPU_TCU 0 -#define QCS8300_MASTER_PCIE_TCU 1 -#define QCS8300_MASTER_SYS_TCU 2 -#define QCS8300_MASTER_APPSS_PROC 3 -#define QCS8300_MASTER_LLCC 4 -#define QCS8300_MASTER_CNOC_LPASS_AG_NOC 5 -#define QCS8300_MASTER_GIC_AHB 6 -#define QCS8300_MASTER_CDSP_NOC_CFG 7 -#define QCS8300_MASTER_QDSS_BAM 8 -#define QCS8300_MASTER_QUP_0 9 -#define QCS8300_MASTER_QUP_1 10 -#define QCS8300_MASTER_A1NOC_SNOC 11 -#define QCS8300_MASTER_A2NOC_SNOC 12 -#define QCS8300_MASTER_CAMNOC_HF 13 -#define QCS8300_MASTER_CAMNOC_ICP 14 -#define QCS8300_MASTER_CAMNOC_SF 15 -#define QCS8300_MASTER_COMPUTE_NOC 16 -#define QCS8300_MASTER_CNOC_A2NOC 17 -#define QCS8300_MASTER_CNOC_DC_NOC 18 -#define QCS8300_MASTER_GEM_NOC_CFG 19 -#define QCS8300_MASTER_GEM_NOC_CNOC 20 -#define QCS8300_MASTER_GEM_NOC_PCIE_SNOC 21 -#define QCS8300_MASTER_GPDSP_SAIL 22 -#define QCS8300_MASTER_GFX3D 23 -#define QCS8300_MASTER_LPASS_ANOC 24 -#define QCS8300_MASTER_MDP0 25 -#define QCS8300_MASTER_MDP1 26 -#define QCS8300_MASTER_MNOC_HF_MEM_NOC 27 -#define QCS8300_MASTER_CNOC_MNOC_HF_CFG 28 -#define QCS8300_MASTER_MNOC_SF_MEM_NOC 29 -#define QCS8300_MASTER_CNOC_MNOC_SF_CFG 30 -#define QCS8300_MASTER_ANOC_PCIE_GEM_NOC 31 -#define QCS8300_MASTER_SAILSS_MD0 32 -#define QCS8300_MASTER_SNOC_CFG 33 -#define QCS8300_MASTER_SNOC_GC_MEM_NOC 34 -#define QCS8300_MASTER_SNOC_SF_MEM_NOC 35 -#define QCS8300_MASTER_VIDEO_P0 36 -#define QCS8300_MASTER_VIDEO_PROC 37 -#define QCS8300_MASTER_VIDEO_V_PROC 38 -#define QCS8300_MASTER_QUP_CORE_0 39 -#define QCS8300_MASTER_QUP_CORE_1 40 -#define QCS8300_MASTER_QUP_CORE_3 41 -#define QCS8300_MASTER_CRYPTO_CORE0 42 -#define QCS8300_MASTER_CRYPTO_CORE1 43 -#define QCS8300_MASTER_DSP0 44 -#define QCS8300_MASTER_IPA 45 -#define QCS8300_MASTER_LPASS_PROC 46 -#define QCS8300_MASTER_CDSP_PROC 47 -#define QCS8300_MASTER_PIMEM 48 -#define QCS8300_MASTER_QUP_3 49 -#define QCS8300_MASTER_EMAC 50 -#define QCS8300_MASTER_GIC 51 -#define QCS8300_MASTER_PCIE_0 52 -#define QCS8300_MASTER_PCIE_1 53 -#define QCS8300_MASTER_QDSS_ETR_0 54 -#define QCS8300_MASTER_QDSS_ETR_1 55 -#define QCS8300_MASTER_SDC 56 -#define QCS8300_MASTER_UFS_MEM 57 -#define QCS8300_MASTER_USB2 58 -#define QCS8300_MASTER_USB3_0 59 -#define QCS8300_SLAVE_EBI1 60 -#define QCS8300_SLAVE_AHB2PHY_2 61 -#define QCS8300_SLAVE_AHB2PHY_3 62 -#define QCS8300_SLAVE_ANOC_THROTTLE_CFG 63 -#define QCS8300_SLAVE_AOSS 64 -#define QCS8300_SLAVE_APPSS 65 -#define QCS8300_SLAVE_BOOT_ROM 66 -#define QCS8300_SLAVE_CAMERA_CFG 67 -#define QCS8300_SLAVE_CAMERA_NRT_THROTTLE_CFG 68 -#define QCS8300_SLAVE_CAMERA_RT_THROTTLE_CFG 69 -#define QCS8300_SLAVE_CLK_CTL 70 -#define QCS8300_SLAVE_CDSP_CFG 71 -#define QCS8300_SLAVE_RBCPR_CX_CFG 72 -#define QCS8300_SLAVE_RBCPR_MMCX_CFG 73 -#define QCS8300_SLAVE_RBCPR_MX_CFG 74 -#define QCS8300_SLAVE_CPR_NSPCX 75 -#define QCS8300_SLAVE_CPR_NSPHMX 76 -#define QCS8300_SLAVE_CRYPTO_0_CFG 77 -#define QCS8300_SLAVE_CX_RDPM 78 -#define QCS8300_SLAVE_DISPLAY_CFG 79 -#define QCS8300_SLAVE_DISPLAY_RT_THROTTLE_CFG 80 -#define QCS8300_SLAVE_EMAC_CFG 81 -#define QCS8300_SLAVE_GP_DSP0_CFG 82 -#define QCS8300_SLAVE_GPDSP0_THROTTLE_CFG 83 -#define QCS8300_SLAVE_GPU_TCU_THROTTLE_CFG 84 -#define QCS8300_SLAVE_GFX3D_CFG 85 -#define QCS8300_SLAVE_HWKM 86 -#define QCS8300_SLAVE_IMEM_CFG 87 -#define QCS8300_SLAVE_IPA_CFG 88 -#define QCS8300_SLAVE_IPC_ROUTER_CFG 89 -#define QCS8300_SLAVE_LLCC_CFG 90 -#define QCS8300_SLAVE_LPASS 91 -#define QCS8300_SLAVE_LPASS_CORE_CFG 92 -#define QCS8300_SLAVE_LPASS_LPI_CFG 93 -#define QCS8300_SLAVE_LPASS_MPU_CFG 94 -#define QCS8300_SLAVE_LPASS_THROTTLE_CFG 95 -#define QCS8300_SLAVE_LPASS_TOP_CFG 96 -#define QCS8300_SLAVE_MX_RDPM 97 -#define QCS8300_SLAVE_MXC_RDPM 98 -#define QCS8300_SLAVE_PCIE_0_CFG 99 -#define QCS8300_SLAVE_PCIE_1_CFG 100 -#define QCS8300_SLAVE_PCIE_TCU_THROTTLE_CFG 101 -#define QCS8300_SLAVE_PCIE_THROTTLE_CFG 102 -#define QCS8300_SLAVE_PDM 103 -#define QCS8300_SLAVE_PIMEM_CFG 104 -#define QCS8300_SLAVE_PKA_WRAPPER_CFG 105 -#define QCS8300_SLAVE_QDSS_CFG 106 -#define QCS8300_SLAVE_QM_CFG 107 -#define QCS8300_SLAVE_QM_MPU_CFG 108 -#define QCS8300_SLAVE_QUP_0 109 -#define QCS8300_SLAVE_QUP_1 110 -#define QCS8300_SLAVE_QUP_3 111 -#define QCS8300_SLAVE_SAIL_THROTTLE_CFG 112 -#define QCS8300_SLAVE_SDC1 113 -#define QCS8300_SLAVE_SECURITY 114 -#define QCS8300_SLAVE_SNOC_THROTTLE_CFG 115 -#define QCS8300_SLAVE_TCSR 116 -#define QCS8300_SLAVE_TLMM 117 -#define QCS8300_SLAVE_TSC_CFG 118 -#define QCS8300_SLAVE_UFS_MEM_CFG 119 -#define QCS8300_SLAVE_USB2 120 -#define QCS8300_SLAVE_USB3_0 121 -#define QCS8300_SLAVE_VENUS_CFG 122 -#define QCS8300_SLAVE_VENUS_CVP_THROTTLE_CFG 123 -#define QCS8300_SLAVE_VENUS_V_CPU_THROTTLE_CFG 124 -#define QCS8300_SLAVE_VENUS_VCODEC_THROTTLE_CFG 125 -#define QCS8300_SLAVE_A1NOC_SNOC 126 -#define QCS8300_SLAVE_A2NOC_SNOC 127 -#define QCS8300_SLAVE_DDRSS_CFG 128 -#define QCS8300_SLAVE_GEM_NOC_CNOC 129 -#define QCS8300_SLAVE_GEM_NOC_CFG 130 -#define QCS8300_SLAVE_SNOC_GEM_NOC_GC 131 -#define QCS8300_SLAVE_SNOC_GEM_NOC_SF 132 -#define QCS8300_SLAVE_GP_DSP_SAIL_NOC 133 -#define QCS8300_SLAVE_GPDSP_NOC_CFG 134 -#define QCS8300_SLAVE_HCP_A 135 -#define QCS8300_SLAVE_LLCC 136 -#define QCS8300_SLAVE_MNOC_HF_MEM_NOC 137 -#define QCS8300_SLAVE_MNOC_SF_MEM_NOC 138 -#define QCS8300_SLAVE_CNOC_MNOC_HF_CFG 139 -#define QCS8300_SLAVE_CNOC_MNOC_SF_CFG 140 -#define QCS8300_SLAVE_CDSP_MEM_NOC 141 -#define QCS8300_SLAVE_GEM_NOC_PCIE_CNOC 142 -#define QCS8300_SLAVE_PCIE_ANOC_CFG 143 -#define QCS8300_SLAVE_ANOC_PCIE_GEM_NOC 144 -#define QCS8300_SLAVE_SNOC_CFG 145 -#define QCS8300_SLAVE_LPASS_SNOC 146 -#define QCS8300_SLAVE_QUP_CORE_0 147 -#define QCS8300_SLAVE_QUP_CORE_1 148 -#define QCS8300_SLAVE_QUP_CORE_3 149 -#define QCS8300_SLAVE_BOOT_IMEM 150 -#define QCS8300_SLAVE_IMEM 151 -#define QCS8300_SLAVE_PIMEM 152 -#define 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This gives more flexibility and also allows us to drop the .num_links member, saving from possible errors related to it being not set or set incorrectly. Signed-off-by: Dmitry Baryshkov --- drivers/interconnect/qcom/qdu1000.c | 352 ++++++++++++++++----------------= ---- drivers/interconnect/qcom/qdu1000.h | 95 ---------- 2 files changed, 155 insertions(+), 292 deletions(-) diff --git a/drivers/interconnect/qcom/qdu1000.c b/drivers/interconnect/qco= m/qdu1000.c index a7392eb73d4a990ec65e9d55f3d0429d05270802..4de0f17e4c57f77e9bd6f8bc710= 8359c4370c396 100644 --- a/drivers/interconnect/qcom/qdu1000.c +++ b/drivers/interconnect/qcom/qdu1000.c @@ -15,756 +15,710 @@ #include "bcm-voter.h" #include "icc-common.h" #include "icc-rpmh.h" -#include "qdu1000.h" + +static struct qcom_icc_node qup0_core_master; +static struct qcom_icc_node qup1_core_master; +static struct qcom_icc_node alm_sys_tcu; +static struct qcom_icc_node chm_apps; +static struct qcom_icc_node qnm_ecpri_dma; +static struct qcom_icc_node qnm_fec_2_gemnoc; +static struct qcom_icc_node qnm_pcie; +static struct qcom_icc_node qnm_snoc_gc; +static struct qcom_icc_node qnm_snoc_sf; +static struct qcom_icc_node qxm_mdsp; +static struct qcom_icc_node llcc_mc; +static struct qcom_icc_node qhm_gic; +static struct qcom_icc_node qhm_qdss_bam; +static struct qcom_icc_node qhm_qpic; +static struct qcom_icc_node qhm_qspi; +static struct qcom_icc_node qhm_qup0; +static struct qcom_icc_node qhm_qup1; +static struct qcom_icc_node qhm_system_noc_cfg; +static struct qcom_icc_node qnm_aggre_noc; +static struct qcom_icc_node qnm_aggre_noc_gsi; +static struct qcom_icc_node qnm_gemnoc_cnoc; +static struct qcom_icc_node qnm_gemnoc_modem_slave; +static struct qcom_icc_node qnm_gemnoc_pcie; +static struct qcom_icc_node qxm_crypto; +static struct qcom_icc_node qxm_ecpri_gsi; +static struct qcom_icc_node qxm_pimem; +static struct qcom_icc_node xm_ecpri_dma; +static struct qcom_icc_node xm_gic; +static struct qcom_icc_node xm_pcie; +static struct qcom_icc_node xm_qdss_etr0; +static struct qcom_icc_node xm_qdss_etr1; +static struct qcom_icc_node xm_sdc; +static struct qcom_icc_node xm_usb3; +static struct qcom_icc_node qup0_core_slave; +static struct qcom_icc_node qup1_core_slave; +static struct qcom_icc_node qns_gem_noc_cnoc; +static struct qcom_icc_node qns_llcc; +static struct qcom_icc_node qns_modem_slave; +static struct qcom_icc_node qns_pcie; +static struct qcom_icc_node ebi; +static struct qcom_icc_node qhs_ahb2phy0_south; +static struct qcom_icc_node qhs_ahb2phy1_north; +static struct qcom_icc_node qhs_ahb2phy2_east; +static struct qcom_icc_node qhs_aoss; +static struct qcom_icc_node qhs_clk_ctl; +static struct qcom_icc_node qhs_cpr_cx; +static struct qcom_icc_node qhs_cpr_mx; +static struct qcom_icc_node qhs_crypto_cfg; +static struct qcom_icc_node qhs_ecpri_cfg; +static struct qcom_icc_node qhs_imem_cfg; +static struct qcom_icc_node qhs_ipc_router; +static struct qcom_icc_node qhs_mss_cfg; +static struct qcom_icc_node qhs_pcie_cfg; +static struct qcom_icc_node qhs_pdm; +static struct qcom_icc_node qhs_pimem_cfg; +static struct qcom_icc_node qhs_prng; +static struct qcom_icc_node qhs_qdss_cfg; +static struct qcom_icc_node qhs_qpic; +static struct qcom_icc_node qhs_qspi; +static struct qcom_icc_node qhs_qup0; +static struct qcom_icc_node qhs_qup1; +static struct qcom_icc_node qhs_sdc2; +static struct qcom_icc_node qhs_smbus_cfg; +static struct qcom_icc_node qhs_system_noc_cfg; +static struct qcom_icc_node qhs_tcsr; +static struct qcom_icc_node qhs_tlmm; +static struct qcom_icc_node qhs_tme_cfg; +static struct qcom_icc_node qhs_tsc_cfg; +static struct qcom_icc_node qhs_usb3; +static struct qcom_icc_node qhs_vsense_ctrl_cfg; +static struct qcom_icc_node qns_a1noc_snoc; +static struct qcom_icc_node qns_anoc_snoc_gsi; +static struct qcom_icc_node qns_ddrss_cfg; +static struct qcom_icc_node qns_ecpri_gemnoc; +static struct qcom_icc_node qns_gemnoc_gc; +static struct qcom_icc_node qns_gemnoc_sf; +static struct qcom_icc_node qns_modem; +static struct qcom_icc_node qns_pcie_gemnoc; +static struct qcom_icc_node qxs_imem; +static struct qcom_icc_node qxs_pimem; +static struct qcom_icc_node srvc_system_noc; +static struct qcom_icc_node xs_ethernet_ss; +static struct qcom_icc_node xs_pcie; +static struct qcom_icc_node xs_qdss_stm; +static struct qcom_icc_node xs_sys_tcu_cfg; =20 static struct qcom_icc_node qup0_core_master =3D { .name =3D "qup0_core_master", - .id =3D QDU1000_MASTER_QUP_CORE_0, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { QDU1000_SLAVE_QUP_CORE_0 }, + .link_nodes =3D { &qup0_core_slave }, }; =20 static struct qcom_icc_node qup1_core_master =3D { .name =3D "qup1_core_master", - .id =3D QDU1000_MASTER_QUP_CORE_1, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { QDU1000_SLAVE_QUP_CORE_1 }, + .link_nodes =3D { &qup1_core_slave }, }; =20 static struct qcom_icc_node alm_sys_tcu =3D { .name =3D "alm_sys_tcu", - .id =3D QDU1000_MASTER_SYS_TCU, .channels =3D 1, .buswidth =3D 8, .num_links =3D 2, - .links =3D { QDU1000_SLAVE_GEM_NOC_CNOC, QDU1000_SLAVE_LLCC }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; =20 static struct qcom_icc_node chm_apps =3D { .name =3D "chm_apps", - .id =3D QDU1000_MASTER_APPSS_PROC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 4, - .links =3D { QDU1000_SLAVE_GEM_NOC_CNOC, QDU1000_SLAVE_LLCC, - QDU1000_SLAVE_GEMNOC_MODEM_CNOC, QDU1000_SLAVE_MEM_NOC_PCIE_SNOC - }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc, + &qns_modem_slave, &qns_pcie }, }; =20 static struct qcom_icc_node qnm_ecpri_dma =3D { .name =3D "qnm_ecpri_dma", - .id =3D QDU1000_MASTER_GEMNOC_ECPRI_DMA, .channels =3D 2, .buswidth =3D 32, .num_links =3D 2, - .links =3D { QDU1000_SLAVE_GEM_NOC_CNOC, QDU1000_SLAVE_LLCC }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; =20 static struct qcom_icc_node qnm_fec_2_gemnoc =3D { .name =3D "qnm_fec_2_gemnoc", - .id =3D QDU1000_MASTER_FEC_2_GEMNOC, .channels =3D 2, .buswidth =3D 32, .num_links =3D 2, - .links =3D { QDU1000_SLAVE_GEM_NOC_CNOC, QDU1000_SLAVE_LLCC }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; =20 static struct qcom_icc_node qnm_pcie =3D { .name =3D "qnm_pcie", - .id =3D QDU1000_MASTER_ANOC_PCIE_GEM_NOC, .channels =3D 1, .buswidth =3D 64, .num_links =3D 3, - .links =3D { QDU1000_SLAVE_GEM_NOC_CNOC, QDU1000_SLAVE_LLCC, - QDU1000_SLAVE_GEMNOC_MODEM_CNOC - }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc, + &qns_modem_slave }, }; =20 static struct qcom_icc_node qnm_snoc_gc =3D { .name =3D "qnm_snoc_gc", - .id =3D QDU1000_MASTER_SNOC_GC_MEM_NOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { QDU1000_SLAVE_LLCC }, + .link_nodes =3D { &qns_llcc }, }; =20 static struct qcom_icc_node qnm_snoc_sf =3D { .name =3D "qnm_snoc_sf", - .id =3D QDU1000_MASTER_SNOC_SF_MEM_NOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 4, - .links =3D { QDU1000_SLAVE_GEM_NOC_CNOC, QDU1000_SLAVE_LLCC, - QDU1000_SLAVE_GEMNOC_MODEM_CNOC, QDU1000_SLAVE_MEM_NOC_PCIE_SNOC - }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc, + &qns_modem_slave, &qns_pcie }, }; =20 static struct qcom_icc_node qxm_mdsp =3D { .name =3D "qxm_mdsp", - .id =3D QDU1000_MASTER_MSS_PROC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 3, - .links =3D { QDU1000_SLAVE_GEM_NOC_CNOC, QDU1000_SLAVE_LLCC, - QDU1000_SLAVE_MEM_NOC_PCIE_SNOC - }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, }; =20 static struct qcom_icc_node llcc_mc =3D { .name =3D "llcc_mc", - .id =3D QDU1000_MASTER_LLCC, .channels =3D 8, .buswidth =3D 4, .num_links =3D 1, - .links =3D { QDU1000_SLAVE_EBI1 }, + .link_nodes =3D { &ebi }, }; =20 static struct qcom_icc_node qhm_gic =3D { .name =3D "qhm_gic", - .id =3D QDU1000_MASTER_GIC_AHB, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { QDU1000_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes =3D { &qns_gemnoc_sf }, }; =20 static struct qcom_icc_node qhm_qdss_bam =3D { .name =3D "qhm_qdss_bam", - .id =3D QDU1000_MASTER_QDSS_BAM, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { QDU1000_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes =3D { &qns_gemnoc_sf }, }; =20 static struct qcom_icc_node qhm_qpic =3D { .name =3D "qhm_qpic", - .id =3D QDU1000_MASTER_QPIC, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { QDU1000_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node qhm_qspi =3D { .name =3D "qhm_qspi", - .id =3D QDU1000_MASTER_QSPI_0, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { QDU1000_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node qhm_qup0 =3D { .name =3D "qhm_qup0", - .id =3D QDU1000_MASTER_QUP_0, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { QDU1000_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node qhm_qup1 =3D { .name =3D "qhm_qup1", - .id =3D QDU1000_MASTER_QUP_1, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { QDU1000_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node qhm_system_noc_cfg =3D { .name =3D "qhm_system_noc_cfg", - .id =3D QDU1000_MASTER_SNOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { QDU1000_SLAVE_SERVICE_SNOC }, + .link_nodes =3D { &srvc_system_noc }, }; =20 static struct qcom_icc_node qnm_aggre_noc =3D { .name =3D "qnm_aggre_noc", - .id =3D QDU1000_MASTER_ANOC_SNOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { QDU1000_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes =3D { &qns_gemnoc_sf }, }; =20 static struct qcom_icc_node qnm_aggre_noc_gsi =3D { .name =3D "qnm_aggre_noc_gsi", - .id =3D QDU1000_MASTER_ANOC_GSI, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { QDU1000_SLAVE_SNOC_GEM_NOC_GC }, + .link_nodes =3D { &qns_gemnoc_gc }, }; =20 static struct qcom_icc_node qnm_gemnoc_cnoc =3D { .name =3D "qnm_gemnoc_cnoc", - .id =3D QDU1000_MASTER_GEM_NOC_CNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 36, - .links =3D { QDU1000_SLAVE_AHB2PHY_SOUTH, QDU1000_SLAVE_AHB2PHY_NORTH, - QDU1000_SLAVE_AHB2PHY_EAST, QDU1000_SLAVE_AOSS, - QDU1000_SLAVE_CLK_CTL, QDU1000_SLAVE_RBCPR_CX_CFG, - QDU1000_SLAVE_RBCPR_MX_CFG, QDU1000_SLAVE_CRYPTO_0_CFG, - QDU1000_SLAVE_ECPRI_CFG, QDU1000_SLAVE_IMEM_CFG, - QDU1000_SLAVE_IPC_ROUTER_CFG, QDU1000_SLAVE_CNOC_MSS, - QDU1000_SLAVE_PCIE_CFG, QDU1000_SLAVE_PDM, - QDU1000_SLAVE_PIMEM_CFG, QDU1000_SLAVE_PRNG, - QDU1000_SLAVE_QDSS_CFG, QDU1000_SLAVE_QPIC, - QDU1000_SLAVE_QSPI_0, QDU1000_SLAVE_QUP_0, - QDU1000_SLAVE_QUP_1, QDU1000_SLAVE_SDCC_2, - QDU1000_SLAVE_SMBUS_CFG, QDU1000_SLAVE_SNOC_CFG, - QDU1000_SLAVE_TCSR, QDU1000_SLAVE_TLMM, - QDU1000_SLAVE_TME_CFG, QDU1000_SLAVE_TSC_CFG, - QDU1000_SLAVE_USB3_0, QDU1000_SLAVE_VSENSE_CTRL_CFG, - QDU1000_SLAVE_DDRSS_CFG, QDU1000_SLAVE_IMEM, - QDU1000_SLAVE_PIMEM, QDU1000_SLAVE_ETHERNET_SS, - QDU1000_SLAVE_QDSS_STM, QDU1000_SLAVE_TCU - }, + .link_nodes =3D { &qhs_ahb2phy0_south, &qhs_ahb2phy1_north, + &qhs_ahb2phy2_east, &qhs_aoss, + &qhs_clk_ctl, &qhs_cpr_cx, + &qhs_cpr_mx, &qhs_crypto_cfg, + &qhs_ecpri_cfg, &qhs_imem_cfg, + &qhs_ipc_router, &qhs_mss_cfg, + &qhs_pcie_cfg, &qhs_pdm, + &qhs_pimem_cfg, &qhs_prng, + &qhs_qdss_cfg, &qhs_qpic, + &qhs_qspi, &qhs_qup0, + &qhs_qup1, &qhs_sdc2, + &qhs_smbus_cfg, &qhs_system_noc_cfg, + &qhs_tcsr, &qhs_tlmm, + &qhs_tme_cfg, &qhs_tsc_cfg, + &qhs_usb3, &qhs_vsense_ctrl_cfg, + &qns_ddrss_cfg, &qxs_imem, + &qxs_pimem, &xs_ethernet_ss, + &xs_qdss_stm, &xs_sys_tcu_cfg }, }; =20 static struct qcom_icc_node qnm_gemnoc_modem_slave =3D { .name =3D "qnm_gemnoc_modem_slave", - .id =3D QDU1000_MASTER_GEMNOC_MODEM_CNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { QDU1000_SLAVE_MODEM_OFFLINE }, + .link_nodes =3D { &qns_modem }, }; =20 static struct qcom_icc_node qnm_gemnoc_pcie =3D { .name =3D "qnm_gemnoc_pcie", - .id =3D QDU1000_MASTER_GEM_NOC_PCIE_SNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { QDU1000_SLAVE_PCIE_0 }, + .link_nodes =3D { &xs_pcie }, }; =20 static struct qcom_icc_node qxm_crypto =3D { .name =3D "qxm_crypto", - .id =3D QDU1000_MASTER_CRYPTO, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { QDU1000_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node qxm_ecpri_gsi =3D { .name =3D "qxm_ecpri_gsi", - .id =3D QDU1000_MASTER_ECPRI_GSI, .channels =3D 1, .buswidth =3D 8, .num_links =3D 2, - .links =3D { QDU1000_SLAVE_ANOC_SNOC_GSI, QDU1000_SLAVE_PCIE_0 }, + .link_nodes =3D { &qns_anoc_snoc_gsi, &xs_pcie }, }; =20 static struct qcom_icc_node qxm_pimem =3D { .name =3D "qxm_pimem", - .id =3D QDU1000_MASTER_PIMEM, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { QDU1000_SLAVE_SNOC_GEM_NOC_GC }, + .link_nodes =3D { &qns_gemnoc_gc }, }; =20 static struct qcom_icc_node xm_ecpri_dma =3D { .name =3D "xm_ecpri_dma", - .id =3D QDU1000_MASTER_SNOC_ECPRI_DMA, .channels =3D 2, .buswidth =3D 32, .num_links =3D 2, - .links =3D { QDU1000_SLAVE_ECPRI_GEMNOC, QDU1000_SLAVE_PCIE_0 }, + .link_nodes =3D { &qns_ecpri_gemnoc, &xs_pcie }, }; =20 static struct qcom_icc_node xm_gic =3D { .name =3D "xm_gic", - .id =3D QDU1000_MASTER_GIC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { QDU1000_SLAVE_SNOC_GEM_NOC_GC }, + .link_nodes =3D { &qns_gemnoc_gc }, }; =20 static struct qcom_icc_node xm_pcie =3D { .name =3D "xm_pcie", - .id =3D QDU1000_MASTER_PCIE, .channels =3D 1, .buswidth =3D 64, .num_links =3D 1, - .links =3D { QDU1000_SLAVE_ANOC_PCIE_GEM_NOC }, + .link_nodes =3D { &qns_pcie_gemnoc }, }; =20 static struct qcom_icc_node xm_qdss_etr0 =3D { .name =3D "xm_qdss_etr0", - .id =3D QDU1000_MASTER_QDSS_ETR, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { QDU1000_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes =3D { &qns_gemnoc_sf }, }; =20 static struct qcom_icc_node xm_qdss_etr1 =3D { .name =3D "xm_qdss_etr1", - .id =3D QDU1000_MASTER_QDSS_ETR_1, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { QDU1000_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes =3D { &qns_gemnoc_sf }, }; =20 static struct qcom_icc_node xm_sdc =3D { .name =3D "xm_sdc", - .id =3D QDU1000_MASTER_SDCC_1, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { QDU1000_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node xm_usb3 =3D { .name =3D "xm_usb3", - .id =3D QDU1000_MASTER_USB3, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { QDU1000_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node qup0_core_slave =3D { .name =3D "qup0_core_slave", - .id =3D QDU1000_SLAVE_QUP_CORE_0, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qup1_core_slave =3D { .name =3D "qup1_core_slave", - .id =3D QDU1000_SLAVE_QUP_CORE_1, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qns_gem_noc_cnoc =3D { .name =3D "qns_gem_noc_cnoc", - .id =3D QDU1000_SLAVE_GEM_NOC_CNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { QDU1000_MASTER_GEM_NOC_CNOC }, + .link_nodes =3D { &qnm_gemnoc_cnoc }, }; =20 static struct qcom_icc_node qns_llcc =3D { .name =3D "qns_llcc", - .id =3D QDU1000_SLAVE_LLCC, .channels =3D 8, .buswidth =3D 16, .num_links =3D 1, - .links =3D { QDU1000_MASTER_LLCC }, + .link_nodes =3D { &llcc_mc }, }; =20 static struct qcom_icc_node qns_modem_slave =3D { .name =3D "qns_modem_slave", - .id =3D QDU1000_SLAVE_GEMNOC_MODEM_CNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { QDU1000_MASTER_GEMNOC_MODEM_CNOC }, + .link_nodes =3D { &qnm_gemnoc_modem_slave }, }; =20 static struct qcom_icc_node qns_pcie =3D { .name =3D "qns_pcie", - .id =3D QDU1000_SLAVE_MEM_NOC_PCIE_SNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { QDU1000_MASTER_GEM_NOC_PCIE_SNOC }, + .link_nodes =3D { &qnm_gemnoc_pcie }, }; =20 static struct qcom_icc_node ebi =3D { .name =3D "ebi", - .id =3D QDU1000_SLAVE_EBI1, .channels =3D 8, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_ahb2phy0_south =3D { .name =3D "qhs_ahb2phy0_south", - .id =3D QDU1000_SLAVE_AHB2PHY_SOUTH, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_ahb2phy1_north =3D { .name =3D "qhs_ahb2phy1_north", - .id =3D QDU1000_SLAVE_AHB2PHY_NORTH, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_ahb2phy2_east =3D { .name =3D "qhs_ahb2phy2_east", - .id =3D QDU1000_SLAVE_AHB2PHY_EAST, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_aoss =3D { .name =3D "qhs_aoss", - .id =3D QDU1000_SLAVE_AOSS, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_clk_ctl =3D { .name =3D "qhs_clk_ctl", - .id =3D QDU1000_SLAVE_CLK_CTL, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_cpr_cx =3D { .name =3D "qhs_cpr_cx", - .id =3D QDU1000_SLAVE_RBCPR_CX_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_cpr_mx =3D { .name =3D "qhs_cpr_mx", - .id =3D QDU1000_SLAVE_RBCPR_MX_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_crypto_cfg =3D { .name =3D "qhs_crypto_cfg", - .id =3D QDU1000_SLAVE_CRYPTO_0_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_ecpri_cfg =3D { .name =3D "qhs_ecpri_cfg", - .id =3D QDU1000_SLAVE_ECPRI_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_imem_cfg =3D { .name =3D "qhs_imem_cfg", - .id =3D QDU1000_SLAVE_IMEM_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_ipc_router =3D { .name =3D "qhs_ipc_router", - .id =3D QDU1000_SLAVE_IPC_ROUTER_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_mss_cfg =3D { .name =3D "qhs_mss_cfg", - .id =3D QDU1000_SLAVE_CNOC_MSS, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_pcie_cfg =3D { .name =3D "qhs_pcie_cfg", - .id =3D QDU1000_SLAVE_PCIE_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_pdm =3D { .name =3D "qhs_pdm", - .id =3D QDU1000_SLAVE_PDM, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_pimem_cfg =3D { .name =3D "qhs_pimem_cfg", - .id =3D QDU1000_SLAVE_PIMEM_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_prng =3D { .name =3D "qhs_prng", - .id =3D QDU1000_SLAVE_PRNG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_qdss_cfg =3D { .name =3D "qhs_qdss_cfg", - .id =3D QDU1000_SLAVE_QDSS_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_qpic =3D { .name =3D "qhs_qpic", - .id =3D QDU1000_SLAVE_QPIC, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_qspi =3D { .name =3D "qhs_qspi", - .id =3D QDU1000_SLAVE_QSPI_0, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_qup0 =3D { .name =3D "qhs_qup0", - .id =3D QDU1000_SLAVE_QUP_0, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_qup1 =3D { .name =3D "qhs_qup1", - .id =3D QDU1000_SLAVE_QUP_1, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_sdc2 =3D { .name =3D "qhs_sdc2", - .id =3D QDU1000_SLAVE_SDCC_2, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_smbus_cfg =3D { .name =3D "qhs_smbus_cfg", - .id =3D QDU1000_SLAVE_SMBUS_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_system_noc_cfg =3D { .name =3D "qhs_system_noc_cfg", - .id =3D QDU1000_SLAVE_SNOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { QDU1000_MASTER_SNOC_CFG }, + .link_nodes =3D { &qhm_system_noc_cfg }, }; =20 static struct qcom_icc_node qhs_tcsr =3D { .name =3D "qhs_tcsr", - .id =3D QDU1000_SLAVE_TCSR, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_tlmm =3D { .name =3D "qhs_tlmm", - .id =3D QDU1000_SLAVE_TLMM, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_tme_cfg =3D { .name =3D "qhs_tme_cfg", - .id =3D QDU1000_SLAVE_TME_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_tsc_cfg =3D { .name =3D "qhs_tsc_cfg", - .id =3D QDU1000_SLAVE_TSC_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_usb3 =3D { .name =3D "qhs_usb3", - .id =3D QDU1000_SLAVE_USB3_0, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_vsense_ctrl_cfg =3D { .name =3D "qhs_vsense_ctrl_cfg", - .id =3D QDU1000_SLAVE_VSENSE_CTRL_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qns_a1noc_snoc =3D { .name =3D "qns_a1noc_snoc", - .id =3D QDU1000_SLAVE_A1NOC_SNOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { QDU1000_MASTER_ANOC_SNOC }, + .link_nodes =3D { &qnm_aggre_noc }, }; =20 static struct qcom_icc_node qns_anoc_snoc_gsi =3D { .name =3D "qns_anoc_snoc_gsi", - .id =3D QDU1000_SLAVE_ANOC_SNOC_GSI, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { QDU1000_MASTER_ANOC_GSI }, + .link_nodes =3D { &qnm_aggre_noc_gsi }, }; =20 static struct qcom_icc_node qns_ddrss_cfg =3D { .name =3D "qns_ddrss_cfg", - .id =3D QDU1000_SLAVE_DDRSS_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qns_ecpri_gemnoc =3D { .name =3D "qns_ecpri_gemnoc", - .id =3D QDU1000_SLAVE_ECPRI_GEMNOC, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { QDU1000_MASTER_GEMNOC_ECPRI_DMA }, + .link_nodes =3D { &qnm_ecpri_dma }, }; =20 static struct qcom_icc_node qns_gemnoc_gc =3D { .name =3D "qns_gemnoc_gc", - .id =3D QDU1000_SLAVE_SNOC_GEM_NOC_GC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { QDU1000_MASTER_SNOC_GC_MEM_NOC }, + .link_nodes =3D { &qnm_snoc_gc }, }; =20 static struct qcom_icc_node qns_gemnoc_sf =3D { .name =3D "qns_gemnoc_sf", - .id =3D QDU1000_SLAVE_SNOC_GEM_NOC_SF, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { QDU1000_MASTER_SNOC_SF_MEM_NOC }, + .link_nodes =3D { &qnm_snoc_sf }, }; =20 static struct qcom_icc_node qns_modem =3D { .name =3D "qns_modem", - .id =3D QDU1000_SLAVE_MODEM_OFFLINE, .channels =3D 1, .buswidth =3D 32, - .num_links =3D 0, }; =20 static struct qcom_icc_node qns_pcie_gemnoc =3D { .name =3D "qns_pcie_gemnoc", - .id =3D QDU1000_SLAVE_ANOC_PCIE_GEM_NOC, .channels =3D 1, .buswidth =3D 64, .num_links =3D 1, - .links =3D { QDU1000_MASTER_ANOC_PCIE_GEM_NOC }, + .link_nodes =3D { &qnm_pcie }, }; =20 static struct qcom_icc_node qxs_imem =3D { .name =3D "qxs_imem", - .id =3D QDU1000_SLAVE_IMEM, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 0, }; =20 static struct qcom_icc_node qxs_pimem =3D { .name =3D "qxs_pimem", - .id =3D QDU1000_SLAVE_PIMEM, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 0, }; =20 static struct qcom_icc_node srvc_system_noc =3D { .name =3D "srvc_system_noc", - .id =3D QDU1000_SLAVE_SERVICE_SNOC, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node xs_ethernet_ss =3D { .name =3D "xs_ethernet_ss", - .id =3D QDU1000_SLAVE_ETHERNET_SS, .channels =3D 1, .buswidth =3D 32, - .num_links =3D 0, }; =20 static struct qcom_icc_node xs_pcie =3D { .name =3D "xs_pcie", - .id =3D QDU1000_SLAVE_PCIE_0, .channels =3D 1, .buswidth =3D 64, - .num_links =3D 0, }; =20 static struct qcom_icc_node xs_qdss_stm =3D { .name =3D "xs_qdss_stm", - .id =3D QDU1000_SLAVE_QDSS_STM, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node xs_sys_tcu_cfg =3D { .name =3D "xs_sys_tcu_cfg", - .id =3D QDU1000_SLAVE_TCU, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 0, }; =20 static struct qcom_icc_bcm bcm_acv =3D { @@ -880,6 +834,7 @@ static struct qcom_icc_node * const clk_virt_nodes[] = =3D { }; =20 static const struct qcom_icc_desc qdu1000_clk_virt =3D { + .alloc_dyn_id =3D true, .nodes =3D clk_virt_nodes, .num_nodes =3D ARRAY_SIZE(clk_virt_nodes), .bcms =3D clk_virt_bcms, @@ -907,6 +862,7 @@ static struct qcom_icc_node * const gem_noc_nodes[] =3D= { }; =20 static const struct qcom_icc_desc qdu1000_gem_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D gem_noc_nodes, .num_nodes =3D ARRAY_SIZE(gem_noc_nodes), .bcms =3D gem_noc_bcms, @@ -924,6 +880,7 @@ static struct qcom_icc_node * const mc_virt_nodes[] =3D= { }; =20 static const struct qcom_icc_desc qdu1000_mc_virt =3D { + .alloc_dyn_id =3D true, .nodes =3D mc_virt_nodes, .num_nodes =3D ARRAY_SIZE(mc_virt_nodes), .bcms =3D mc_virt_bcms, @@ -1010,6 +967,7 @@ static struct qcom_icc_node * const system_noc_nodes[]= =3D { }; =20 static const struct qcom_icc_desc qdu1000_system_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D system_noc_nodes, .num_nodes =3D ARRAY_SIZE(system_noc_nodes), .bcms =3D system_noc_bcms, diff --git a/drivers/interconnect/qcom/qdu1000.h b/drivers/interconnect/qco= m/qdu1000.h deleted file mode 100644 index e75a6419df235353a5dcfbefe1cb3979ae966054..000000000000000000000000000= 0000000000000 --- a/drivers/interconnect/qcom/qdu1000.h +++ /dev/null @@ -1,95 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserve= d. - */ - -#ifndef __DRIVERS_INTERCONNECT_QCOM_QDU1000_H -#define __DRIVERS_INTERCONNECT_QCOM_QDU1000_H - -#define QDU1000_MASTER_SYS_TCU 0 -#define QDU1000_MASTER_APPSS_PROC 1 -#define QDU1000_MASTER_LLCC 2 -#define QDU1000_MASTER_GIC_AHB 3 -#define QDU1000_MASTER_QDSS_BAM 4 -#define QDU1000_MASTER_QPIC 5 -#define QDU1000_MASTER_QSPI_0 6 -#define QDU1000_MASTER_QUP_0 7 -#define QDU1000_MASTER_QUP_1 8 -#define QDU1000_MASTER_SNOC_CFG 9 -#define QDU1000_MASTER_ANOC_SNOC 10 -#define QDU1000_MASTER_ANOC_GSI 11 -#define QDU1000_MASTER_GEMNOC_ECPRI_DMA 12 -#define QDU1000_MASTER_FEC_2_GEMNOC 13 -#define QDU1000_MASTER_GEM_NOC_CNOC 14 -#define QDU1000_MASTER_GEMNOC_MODEM_CNOC 15 -#define QDU1000_MASTER_GEM_NOC_PCIE_SNOC 16 -#define QDU1000_MASTER_ANOC_PCIE_GEM_NOC 17 -#define QDU1000_MASTER_SNOC_GC_MEM_NOC 18 -#define QDU1000_MASTER_SNOC_SF_MEM_NOC 19 -#define QDU1000_MASTER_QUP_CORE_0 20 -#define QDU1000_MASTER_QUP_CORE_1 21 -#define QDU1000_MASTER_CRYPTO 22 -#define QDU1000_MASTER_ECPRI_GSI 23 -#define QDU1000_MASTER_MSS_PROC 24 -#define QDU1000_MASTER_PIMEM 25 -#define QDU1000_MASTER_SNOC_ECPRI_DMA 26 -#define QDU1000_MASTER_GIC 27 -#define QDU1000_MASTER_PCIE 28 -#define QDU1000_MASTER_QDSS_ETR 29 -#define QDU1000_MASTER_QDSS_ETR_1 30 -#define QDU1000_MASTER_SDCC_1 31 -#define QDU1000_MASTER_USB3 32 -#define QDU1000_SLAVE_EBI1 512 -#define QDU1000_SLAVE_AHB2PHY_SOUTH 513 -#define QDU1000_SLAVE_AHB2PHY_NORTH 514 -#define QDU1000_SLAVE_AHB2PHY_EAST 515 -#define QDU1000_SLAVE_AOSS 516 -#define QDU1000_SLAVE_CLK_CTL 517 -#define QDU1000_SLAVE_RBCPR_CX_CFG 518 -#define QDU1000_SLAVE_RBCPR_MX_CFG 519 -#define QDU1000_SLAVE_CRYPTO_0_CFG 520 -#define QDU1000_SLAVE_ECPRI_CFG 521 -#define QDU1000_SLAVE_IMEM_CFG 522 -#define QDU1000_SLAVE_IPC_ROUTER_CFG 523 -#define QDU1000_SLAVE_CNOC_MSS 524 -#define QDU1000_SLAVE_PCIE_CFG 525 -#define QDU1000_SLAVE_PDM 526 -#define QDU1000_SLAVE_PIMEM_CFG 527 -#define QDU1000_SLAVE_PRNG 528 -#define QDU1000_SLAVE_QDSS_CFG 529 -#define QDU1000_SLAVE_QPIC 530 -#define QDU1000_SLAVE_QSPI_0 531 -#define QDU1000_SLAVE_QUP_0 532 -#define QDU1000_SLAVE_QUP_1 533 -#define QDU1000_SLAVE_SDCC_2 534 -#define QDU1000_SLAVE_SMBUS_CFG 535 -#define QDU1000_SLAVE_SNOC_CFG 536 -#define QDU1000_SLAVE_TCSR 537 -#define QDU1000_SLAVE_TLMM 538 -#define QDU1000_SLAVE_TME_CFG 539 -#define QDU1000_SLAVE_TSC_CFG 540 -#define QDU1000_SLAVE_USB3_0 541 -#define QDU1000_SLAVE_VSENSE_CTRL_CFG 542 -#define QDU1000_SLAVE_A1NOC_SNOC 543 -#define QDU1000_SLAVE_ANOC_SNOC_GSI 544 -#define QDU1000_SLAVE_DDRSS_CFG 545 -#define QDU1000_SLAVE_ECPRI_GEMNOC 546 -#define QDU1000_SLAVE_GEM_NOC_CNOC 547 -#define QDU1000_SLAVE_SNOC_GEM_NOC_GC 548 -#define QDU1000_SLAVE_SNOC_GEM_NOC_SF 549 -#define QDU1000_SLAVE_LLCC 550 -#define QDU1000_SLAVE_MODEM_OFFLINE 551 -#define QDU1000_SLAVE_GEMNOC_MODEM_CNOC 552 -#define QDU1000_SLAVE_MEM_NOC_PCIE_SNOC 553 -#define QDU1000_SLAVE_ANOC_PCIE_GEM_NOC 554 -#define QDU1000_SLAVE_QUP_CORE_0 555 -#define QDU1000_SLAVE_QUP_CORE_1 556 -#define QDU1000_SLAVE_IMEM 557 -#define QDU1000_SLAVE_PIMEM 558 -#define QDU1000_SLAVE_SERVICE_SNOC 559 -#define QDU1000_SLAVE_ETHERNET_SS 560 -#define QDU1000_SLAVE_PCIE_0 561 -#define QDU1000_SLAVE_QDSS_STM 562 -#define QDU1000_SLAVE_TCU 563 - -#endif --=20 2.47.3 From nobody Mon Feb 9 06:05:00 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 91AE627E1DC for ; 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This gives more flexibility and also allows us to drop the .num_links member, saving from possible errors related to it being not set or set incorrectly. Signed-off-by: Dmitry Baryshkov --- drivers/interconnect/qcom/sar2130p.c | 639 +++++++++++++------------------= ---- 1 file changed, 238 insertions(+), 401 deletions(-) diff --git a/drivers/interconnect/qcom/sar2130p.c b/drivers/interconnect/qc= om/sar2130p.c index 9eac0ac7681273d6f4350f4431b81ce94dbada3f..a0b04929058f7e92a60e441b2cc= 82ee8984daf41 100644 --- a/drivers/interconnect/qcom/sar2130p.c +++ b/drivers/interconnect/qcom/sar2130p.c @@ -20,125 +20,123 @@ #include "icc-common.h" #include "icc-rpmh.h" =20 -enum { - SAR2130P_MASTER_QUP_CORE_0, - SAR2130P_MASTER_QUP_CORE_1, - SAR2130P_MASTER_GEM_NOC_CNOC, - SAR2130P_MASTER_GEM_NOC_PCIE_SNOC, - SAR2130P_MASTER_QDSS_DAP, - SAR2130P_MASTER_GPU_TCU, - SAR2130P_MASTER_SYS_TCU, - SAR2130P_MASTER_APPSS_PROC, - SAR2130P_MASTER_GFX3D, - SAR2130P_MASTER_MNOC_HF_MEM_NOC, - SAR2130P_MASTER_MNOC_SF_MEM_NOC, - SAR2130P_MASTER_COMPUTE_NOC, - SAR2130P_MASTER_ANOC_PCIE_GEM_NOC, - SAR2130P_MASTER_SNOC_GC_MEM_NOC, - SAR2130P_MASTER_SNOC_SF_MEM_NOC, - SAR2130P_MASTER_WLAN_Q6, - SAR2130P_MASTER_CNOC_LPASS_AG_NOC, - SAR2130P_MASTER_LPASS_PROC, - SAR2130P_MASTER_LLCC, - SAR2130P_MASTER_CAMNOC_HF, - SAR2130P_MASTER_CAMNOC_ICP, - SAR2130P_MASTER_CAMNOC_SF, - SAR2130P_MASTER_LSR, - SAR2130P_MASTER_MDP, - SAR2130P_MASTER_CNOC_MNOC_CFG, - SAR2130P_MASTER_VIDEO, - SAR2130P_MASTER_VIDEO_CV_PROC, - SAR2130P_MASTER_VIDEO_PROC, - SAR2130P_MASTER_VIDEO_V_PROC, - SAR2130P_MASTER_CDSP_NOC_CFG, - SAR2130P_MASTER_CDSP_PROC, - SAR2130P_MASTER_PCIE_0, - SAR2130P_MASTER_PCIE_1, - SAR2130P_MASTER_GIC_AHB, - SAR2130P_MASTER_QDSS_BAM, - SAR2130P_MASTER_QSPI_0, - SAR2130P_MASTER_QUP_0, - SAR2130P_MASTER_QUP_1, - SAR2130P_MASTER_A2NOC_SNOC, - SAR2130P_MASTER_CNOC_DATAPATH, - SAR2130P_MASTER_LPASS_ANOC, - SAR2130P_MASTER_SNOC_CFG, - SAR2130P_MASTER_CRYPTO, - SAR2130P_MASTER_PIMEM, - SAR2130P_MASTER_GIC, - SAR2130P_MASTER_QDSS_ETR, - SAR2130P_MASTER_QDSS_ETR_1, - SAR2130P_MASTER_SDCC_1, - SAR2130P_MASTER_USB3_0, - SAR2130P_SLAVE_QUP_CORE_0, - SAR2130P_SLAVE_QUP_CORE_1, - SAR2130P_SLAVE_AHB2PHY_SOUTH, - SAR2130P_SLAVE_AOSS, - SAR2130P_SLAVE_CAMERA_CFG, - SAR2130P_SLAVE_CLK_CTL, - SAR2130P_SLAVE_CDSP_CFG, - SAR2130P_SLAVE_RBCPR_CX_CFG, - SAR2130P_SLAVE_RBCPR_MMCX_CFG, - SAR2130P_SLAVE_RBCPR_MXA_CFG, - SAR2130P_SLAVE_RBCPR_MXC_CFG, - SAR2130P_SLAVE_CPR_NSPCX, - SAR2130P_SLAVE_CRYPTO_0_CFG, - SAR2130P_SLAVE_CX_RDPM, - SAR2130P_SLAVE_DISPLAY_CFG, - SAR2130P_SLAVE_GFX3D_CFG, - SAR2130P_SLAVE_IMEM_CFG, - SAR2130P_SLAVE_IPC_ROUTER_CFG, - SAR2130P_SLAVE_LPASS, - SAR2130P_SLAVE_MX_RDPM, - SAR2130P_SLAVE_PCIE_0_CFG, - SAR2130P_SLAVE_PCIE_1_CFG, - SAR2130P_SLAVE_PDM, - SAR2130P_SLAVE_PIMEM_CFG, - SAR2130P_SLAVE_PRNG, - SAR2130P_SLAVE_QDSS_CFG, - SAR2130P_SLAVE_QSPI_0, - SAR2130P_SLAVE_QUP_0, - SAR2130P_SLAVE_QUP_1, - SAR2130P_SLAVE_SDCC_1, - SAR2130P_SLAVE_TCSR, - SAR2130P_SLAVE_TLMM, - SAR2130P_SLAVE_TME_CFG, - SAR2130P_SLAVE_USB3_0, - SAR2130P_SLAVE_VENUS_CFG, - SAR2130P_SLAVE_VSENSE_CTRL_CFG, - SAR2130P_SLAVE_WLAN_Q6_CFG, - SAR2130P_SLAVE_DDRSS_CFG, - SAR2130P_SLAVE_CNOC_MNOC_CFG, - SAR2130P_SLAVE_SNOC_CFG, - SAR2130P_SLAVE_IMEM, - SAR2130P_SLAVE_PIMEM, - SAR2130P_SLAVE_SERVICE_CNOC, - SAR2130P_SLAVE_PCIE_0, - SAR2130P_SLAVE_PCIE_1, - SAR2130P_SLAVE_QDSS_STM, - SAR2130P_SLAVE_TCU, - SAR2130P_SLAVE_GEM_NOC_CNOC, - SAR2130P_SLAVE_LLCC, - SAR2130P_SLAVE_MEM_NOC_PCIE_SNOC, - SAR2130P_SLAVE_LPASS_CORE_CFG, - SAR2130P_SLAVE_LPASS_LPI_CFG, - SAR2130P_SLAVE_LPASS_MPU_CFG, - SAR2130P_SLAVE_LPASS_TOP_CFG, - SAR2130P_SLAVE_LPASS_SNOC, - SAR2130P_SLAVE_SERVICES_LPASS_AML_NOC, - SAR2130P_SLAVE_SERVICE_LPASS_AG_NOC, - SAR2130P_SLAVE_EBI1, - SAR2130P_SLAVE_MNOC_HF_MEM_NOC, - SAR2130P_SLAVE_MNOC_SF_MEM_NOC, - SAR2130P_SLAVE_SERVICE_MNOC, - SAR2130P_SLAVE_CDSP_MEM_NOC, - SAR2130P_SLAVE_SERVICE_NSP_NOC, - SAR2130P_SLAVE_ANOC_PCIE_GEM_NOC, - SAR2130P_SLAVE_A2NOC_SNOC, - SAR2130P_SLAVE_SNOC_GEM_NOC_GC, - SAR2130P_SLAVE_SNOC_GEM_NOC_SF, - SAR2130P_SLAVE_SERVICE_SNOC, -}; +static struct qcom_icc_node qup0_core_master; +static struct qcom_icc_node qup1_core_master; +static struct qcom_icc_node qnm_gemnoc_cnoc; +static struct qcom_icc_node qnm_gemnoc_pcie; +static struct qcom_icc_node xm_qdss_dap; +static struct qcom_icc_node alm_gpu_tcu; +static struct qcom_icc_node alm_sys_tcu; +static struct qcom_icc_node chm_apps; +static struct qcom_icc_node qnm_gpu; +static struct qcom_icc_node qnm_mnoc_hf; +static struct qcom_icc_node qnm_mnoc_sf; +static struct qcom_icc_node qnm_nsp_gemnoc; +static struct qcom_icc_node qnm_pcie; +static struct qcom_icc_node qnm_snoc_gc; +static struct qcom_icc_node qnm_snoc_sf; +static struct qcom_icc_node qxm_wlan_q6; +static struct qcom_icc_node qhm_config_noc; +static struct qcom_icc_node qxm_lpass_dsp; +static struct qcom_icc_node llcc_mc; +static struct qcom_icc_node qnm_camnoc_hf; +static struct qcom_icc_node qnm_camnoc_icp; +static struct qcom_icc_node qnm_camnoc_sf; +static struct qcom_icc_node qnm_lsr; +static struct qcom_icc_node qnm_mdp; +static struct qcom_icc_node qnm_mnoc_cfg; +static struct qcom_icc_node qnm_video; +static struct qcom_icc_node qnm_video_cv_cpu; +static struct qcom_icc_node qnm_video_cvp; +static struct qcom_icc_node qnm_video_v_cpu; +static struct qcom_icc_node qhm_nsp_noc_config; +static struct qcom_icc_node qxm_nsp; +static struct qcom_icc_node xm_pcie3_0; +static struct qcom_icc_node xm_pcie3_1; +static struct qcom_icc_node qhm_gic; +static struct qcom_icc_node qhm_qdss_bam; +static struct qcom_icc_node qhm_qspi; +static struct qcom_icc_node qhm_qup0; +static struct qcom_icc_node qhm_qup1; +static struct qcom_icc_node qnm_aggre2_noc; +static struct qcom_icc_node qnm_cnoc_datapath; +static struct qcom_icc_node qnm_lpass_noc; +static struct qcom_icc_node qnm_snoc_cfg; +static struct qcom_icc_node qxm_crypto; +static struct qcom_icc_node qxm_pimem; +static struct qcom_icc_node xm_gic; +static struct qcom_icc_node xm_qdss_etr_0; +static struct qcom_icc_node xm_qdss_etr_1; +static struct qcom_icc_node xm_sdc1; +static struct qcom_icc_node xm_usb3_0; +static struct qcom_icc_node qup0_core_slave; +static struct qcom_icc_node qup1_core_slave; +static struct qcom_icc_node qhs_ahb2phy0; +static struct qcom_icc_node qhs_aoss; +static struct qcom_icc_node qhs_camera_cfg; +static struct qcom_icc_node qhs_clk_ctl; +static struct qcom_icc_node qhs_compute_cfg; +static struct qcom_icc_node qhs_cpr_cx; +static struct qcom_icc_node qhs_cpr_mmcx; +static struct qcom_icc_node qhs_cpr_mxa; +static struct qcom_icc_node qhs_cpr_mxc; +static struct qcom_icc_node qhs_cpr_nspcx; +static struct qcom_icc_node qhs_crypto0_cfg; +static struct qcom_icc_node qhs_cx_rdpm; +static struct qcom_icc_node qhs_display_cfg; +static struct qcom_icc_node qhs_gpuss_cfg; +static struct qcom_icc_node qhs_imem_cfg; +static struct qcom_icc_node qhs_ipc_router; +static struct qcom_icc_node qhs_lpass_cfg; +static struct qcom_icc_node qhs_mx_rdpm; +static struct qcom_icc_node qhs_pcie0_cfg; +static struct qcom_icc_node qhs_pcie1_cfg; +static struct qcom_icc_node qhs_pdm; +static struct qcom_icc_node qhs_pimem_cfg; +static struct qcom_icc_node qhs_prng; +static struct qcom_icc_node qhs_qdss_cfg; +static struct qcom_icc_node qhs_qspi; +static struct qcom_icc_node qhs_qup0; +static struct qcom_icc_node qhs_qup1; +static struct qcom_icc_node qhs_sdc1; +static struct qcom_icc_node qhs_tcsr; +static struct qcom_icc_node qhs_tlmm; +static struct qcom_icc_node qhs_tme_cfg; +static struct qcom_icc_node qhs_usb3_0; +static struct qcom_icc_node qhs_venus_cfg; +static struct qcom_icc_node qhs_vsense_ctrl_cfg; +static struct qcom_icc_node qhs_wlan_q6; +static struct qcom_icc_node qns_ddrss_cfg; +static struct qcom_icc_node qns_mnoc_cfg; +static struct qcom_icc_node qns_snoc_cfg; +static struct qcom_icc_node qxs_imem; +static struct qcom_icc_node qxs_pimem; +static struct qcom_icc_node srvc_cnoc; +static struct qcom_icc_node xs_pcie_0; +static struct qcom_icc_node xs_pcie_1; +static struct qcom_icc_node xs_qdss_stm; +static struct qcom_icc_node xs_sys_tcu_cfg; +static struct qcom_icc_node qns_gem_noc_cnoc; +static struct qcom_icc_node qns_llcc; +static struct qcom_icc_node qns_pcie; +static struct qcom_icc_node qhs_lpass_core; +static struct qcom_icc_node qhs_lpass_lpi; +static struct qcom_icc_node qhs_lpass_mpu; +static struct qcom_icc_node qhs_lpass_top; +static struct qcom_icc_node qns_sysnoc; +static struct qcom_icc_node srvc_niu_aml_noc; +static struct qcom_icc_node srvc_niu_lpass_agnoc; +static struct qcom_icc_node ebi; +static struct qcom_icc_node qns_mem_noc_hf; +static struct qcom_icc_node qns_mem_noc_sf; +static struct qcom_icc_node srvc_mnoc; +static struct qcom_icc_node qns_nsp_gemnoc; +static struct qcom_icc_node service_nsp_noc; +static struct qcom_icc_node qns_pcie_mem_noc; +static struct qcom_icc_node qns_a2noc_snoc; +static struct qcom_icc_node qns_gemnoc_gc; +static struct qcom_icc_node qns_gemnoc_sf; +static struct qcom_icc_node srvc_snoc; =20 static const struct regmap_config icc_regmap_config =3D { .reg_bits =3D 32, @@ -149,89 +147,84 @@ static const struct regmap_config icc_regmap_config = =3D { =20 static struct qcom_icc_node qup0_core_master =3D { .name =3D "qup0_core_master", - .id =3D SAR2130P_MASTER_QUP_CORE_0, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SAR2130P_SLAVE_QUP_CORE_0 }, + .link_nodes =3D { &qup0_core_slave }, }; =20 static struct qcom_icc_node qup1_core_master =3D { .name =3D "qup1_core_master", - .id =3D SAR2130P_MASTER_QUP_CORE_1, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SAR2130P_SLAVE_QUP_CORE_1 }, + .link_nodes =3D { &qup1_core_slave }, }; =20 static struct qcom_icc_node qnm_gemnoc_cnoc =3D { .name =3D "qnm_gemnoc_cnoc", - .id =3D SAR2130P_MASTER_GEM_NOC_CNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 43, - .links =3D { SAR2130P_SLAVE_AHB2PHY_SOUTH, SAR2130P_SLAVE_AOSS, - SAR2130P_SLAVE_CAMERA_CFG, SAR2130P_SLAVE_CLK_CTL, - SAR2130P_SLAVE_CDSP_CFG, SAR2130P_SLAVE_RBCPR_CX_CFG, - SAR2130P_SLAVE_RBCPR_MMCX_CFG, SAR2130P_SLAVE_RBCPR_MXA_CFG, - SAR2130P_SLAVE_RBCPR_MXC_CFG, SAR2130P_SLAVE_CPR_NSPCX, - SAR2130P_SLAVE_CRYPTO_0_CFG, SAR2130P_SLAVE_CX_RDPM, - SAR2130P_SLAVE_DISPLAY_CFG, SAR2130P_SLAVE_GFX3D_CFG, - SAR2130P_SLAVE_IMEM_CFG, SAR2130P_SLAVE_IPC_ROUTER_CFG, - SAR2130P_SLAVE_LPASS, SAR2130P_SLAVE_MX_RDPM, - SAR2130P_SLAVE_PCIE_0_CFG, SAR2130P_SLAVE_PCIE_1_CFG, - SAR2130P_SLAVE_PDM, SAR2130P_SLAVE_PIMEM_CFG, - SAR2130P_SLAVE_PRNG, SAR2130P_SLAVE_QDSS_CFG, - SAR2130P_SLAVE_QSPI_0, SAR2130P_SLAVE_QUP_0, - SAR2130P_SLAVE_QUP_1, SAR2130P_SLAVE_SDCC_1, - SAR2130P_SLAVE_TCSR, SAR2130P_SLAVE_TLMM, - SAR2130P_SLAVE_TME_CFG, SAR2130P_SLAVE_USB3_0, - SAR2130P_SLAVE_VENUS_CFG, SAR2130P_SLAVE_VSENSE_CTRL_CFG, - SAR2130P_SLAVE_WLAN_Q6_CFG, SAR2130P_SLAVE_DDRSS_CFG, - SAR2130P_SLAVE_CNOC_MNOC_CFG, SAR2130P_SLAVE_SNOC_CFG, - SAR2130P_SLAVE_IMEM, SAR2130P_SLAVE_PIMEM, - SAR2130P_SLAVE_SERVICE_CNOC, SAR2130P_SLAVE_QDSS_STM, - SAR2130P_SLAVE_TCU }, + .link_nodes =3D { &qhs_ahb2phy0, &qhs_aoss, + &qhs_camera_cfg, &qhs_clk_ctl, + &qhs_compute_cfg, &qhs_cpr_cx, + &qhs_cpr_mmcx, &qhs_cpr_mxa, + &qhs_cpr_mxc, &qhs_cpr_nspcx, + &qhs_crypto0_cfg, &qhs_cx_rdpm, + &qhs_display_cfg, &qhs_gpuss_cfg, + &qhs_imem_cfg, &qhs_ipc_router, + &qhs_lpass_cfg, &qhs_mx_rdpm, + &qhs_pcie0_cfg, &qhs_pcie1_cfg, + &qhs_pdm, &qhs_pimem_cfg, + &qhs_prng, &qhs_qdss_cfg, + &qhs_qspi, &qhs_qup0, + &qhs_qup1, &qhs_sdc1, + &qhs_tcsr, &qhs_tlmm, + &qhs_tme_cfg, &qhs_usb3_0, + &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, + &qhs_wlan_q6, &qns_ddrss_cfg, + &qns_mnoc_cfg, &qns_snoc_cfg, + &qxs_imem, &qxs_pimem, + &srvc_cnoc, &xs_qdss_stm, + &xs_sys_tcu_cfg }, }; =20 static struct qcom_icc_node qnm_gemnoc_pcie =3D { .name =3D "qnm_gemnoc_pcie", - .id =3D SAR2130P_MASTER_GEM_NOC_PCIE_SNOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 2, - .links =3D { SAR2130P_SLAVE_PCIE_0, SAR2130P_SLAVE_PCIE_1 }, + .link_nodes =3D { &xs_pcie_0, &xs_pcie_1 }, }; =20 static struct qcom_icc_node xm_qdss_dap =3D { .name =3D "xm_qdss_dap", - .id =3D SAR2130P_MASTER_QDSS_DAP, .channels =3D 1, .buswidth =3D 8, .num_links =3D 43, - .links =3D { SAR2130P_SLAVE_AHB2PHY_SOUTH, SAR2130P_SLAVE_AOSS, - SAR2130P_SLAVE_CAMERA_CFG, SAR2130P_SLAVE_CLK_CTL, - SAR2130P_SLAVE_CDSP_CFG, SAR2130P_SLAVE_RBCPR_CX_CFG, - SAR2130P_SLAVE_RBCPR_MMCX_CFG, SAR2130P_SLAVE_RBCPR_MXA_CFG, - SAR2130P_SLAVE_RBCPR_MXC_CFG, SAR2130P_SLAVE_CPR_NSPCX, - SAR2130P_SLAVE_CRYPTO_0_CFG, SAR2130P_SLAVE_CX_RDPM, - SAR2130P_SLAVE_DISPLAY_CFG, SAR2130P_SLAVE_GFX3D_CFG, - SAR2130P_SLAVE_IMEM_CFG, SAR2130P_SLAVE_IPC_ROUTER_CFG, - SAR2130P_SLAVE_LPASS, SAR2130P_SLAVE_MX_RDPM, - SAR2130P_SLAVE_PCIE_0_CFG, SAR2130P_SLAVE_PCIE_1_CFG, - SAR2130P_SLAVE_PDM, SAR2130P_SLAVE_PIMEM_CFG, - SAR2130P_SLAVE_PRNG, SAR2130P_SLAVE_QDSS_CFG, - SAR2130P_SLAVE_QSPI_0, SAR2130P_SLAVE_QUP_0, - SAR2130P_SLAVE_QUP_1, SAR2130P_SLAVE_SDCC_1, - SAR2130P_SLAVE_TCSR, SAR2130P_SLAVE_TLMM, - SAR2130P_SLAVE_TME_CFG, SAR2130P_SLAVE_USB3_0, - SAR2130P_SLAVE_VENUS_CFG, SAR2130P_SLAVE_VSENSE_CTRL_CFG, - SAR2130P_SLAVE_WLAN_Q6_CFG, SAR2130P_SLAVE_DDRSS_CFG, - SAR2130P_SLAVE_CNOC_MNOC_CFG, SAR2130P_SLAVE_SNOC_CFG, - SAR2130P_SLAVE_IMEM, SAR2130P_SLAVE_PIMEM, - SAR2130P_SLAVE_SERVICE_CNOC, SAR2130P_SLAVE_QDSS_STM, - SAR2130P_SLAVE_TCU }, + .link_nodes =3D { &qhs_ahb2phy0, &qhs_aoss, + &qhs_camera_cfg, &qhs_clk_ctl, + &qhs_compute_cfg, &qhs_cpr_cx, + &qhs_cpr_mmcx, &qhs_cpr_mxa, + &qhs_cpr_mxc, &qhs_cpr_nspcx, + &qhs_crypto0_cfg, &qhs_cx_rdpm, + &qhs_display_cfg, &qhs_gpuss_cfg, + &qhs_imem_cfg, &qhs_ipc_router, + &qhs_lpass_cfg, &qhs_mx_rdpm, + &qhs_pcie0_cfg, &qhs_pcie1_cfg, + &qhs_pdm, &qhs_pimem_cfg, + &qhs_prng, &qhs_qdss_cfg, + &qhs_qspi, &qhs_qup0, + &qhs_qup1, &qhs_sdc1, + &qhs_tcsr, &qhs_tlmm, + &qhs_tme_cfg, &qhs_usb3_0, + &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, + &qhs_wlan_q6, &qns_ddrss_cfg, + &qns_mnoc_cfg, &qns_snoc_cfg, + &qxs_imem, &qxs_pimem, + &srvc_cnoc, &xs_qdss_stm, + &xs_sys_tcu_cfg }, }; =20 static const struct qcom_icc_qosbox alm_gpu_tcu_qos =3D { @@ -244,12 +237,11 @@ static const struct qcom_icc_qosbox alm_gpu_tcu_qos = =3D { =20 static struct qcom_icc_node alm_gpu_tcu =3D { .name =3D "alm_gpu_tcu", - .id =3D SAR2130P_MASTER_GPU_TCU, .channels =3D 1, .buswidth =3D 8, .qosbox =3D &alm_gpu_tcu_qos, .num_links =3D 2, - .links =3D { SAR2130P_SLAVE_GEM_NOC_CNOC, SAR2130P_SLAVE_LLCC }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; =20 static const struct qcom_icc_qosbox alm_sys_tcu_qos =3D { @@ -262,22 +254,20 @@ static const struct qcom_icc_qosbox alm_sys_tcu_qos = =3D { =20 static struct qcom_icc_node alm_sys_tcu =3D { .name =3D "alm_sys_tcu", - .id =3D SAR2130P_MASTER_SYS_TCU, .channels =3D 1, .buswidth =3D 8, .qosbox =3D &alm_sys_tcu_qos, .num_links =3D 2, - .links =3D { SAR2130P_SLAVE_GEM_NOC_CNOC, SAR2130P_SLAVE_LLCC }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; =20 static struct qcom_icc_node chm_apps =3D { .name =3D "chm_apps", - .id =3D SAR2130P_MASTER_APPSS_PROC, .channels =3D 1, .buswidth =3D 32, .num_links =3D 3, - .links =3D { SAR2130P_SLAVE_GEM_NOC_CNOC, SAR2130P_SLAVE_LLCC, - SAR2130P_SLAVE_MEM_NOC_PCIE_SNOC }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, }; =20 static const struct qcom_icc_qosbox qnm_gpu_qos =3D { @@ -290,12 +280,11 @@ static const struct qcom_icc_qosbox qnm_gpu_qos =3D { =20 static struct qcom_icc_node qnm_gpu =3D { .name =3D "qnm_gpu", - .id =3D SAR2130P_MASTER_GFX3D, .channels =3D 2, .buswidth =3D 32, .qosbox =3D &qnm_gpu_qos, .num_links =3D 2, - .links =3D { SAR2130P_SLAVE_GEM_NOC_CNOC, SAR2130P_SLAVE_LLCC }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; =20 static const struct qcom_icc_qosbox qnm_mnoc_hf_qos =3D { @@ -307,12 +296,11 @@ static const struct qcom_icc_qosbox qnm_mnoc_hf_qos = =3D { =20 static struct qcom_icc_node qnm_mnoc_hf =3D { .name =3D "qnm_mnoc_hf", - .id =3D SAR2130P_MASTER_MNOC_HF_MEM_NOC, .channels =3D 2, .buswidth =3D 32, .qosbox =3D &qnm_mnoc_hf_qos, .num_links =3D 2, - .links =3D { SAR2130P_SLAVE_GEM_NOC_CNOC, SAR2130P_SLAVE_LLCC }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; =20 static const struct qcom_icc_qosbox qnm_mnoc_sf_qos =3D { @@ -324,12 +312,11 @@ static const struct qcom_icc_qosbox qnm_mnoc_sf_qos = =3D { =20 static struct qcom_icc_node qnm_mnoc_sf =3D { .name =3D "qnm_mnoc_sf", - .id =3D SAR2130P_MASTER_MNOC_SF_MEM_NOC, .channels =3D 1, .buswidth =3D 32, .qosbox =3D &qnm_mnoc_sf_qos, .num_links =3D 2, - .links =3D { SAR2130P_SLAVE_GEM_NOC_CNOC, SAR2130P_SLAVE_LLCC }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; =20 static const struct qcom_icc_qosbox qnm_nsp_gemnoc_qos =3D { @@ -342,12 +329,11 @@ static const struct qcom_icc_qosbox qnm_nsp_gemnoc_qo= s =3D { =20 static struct qcom_icc_node qnm_nsp_gemnoc =3D { .name =3D "qnm_nsp_gemnoc", - .id =3D SAR2130P_MASTER_COMPUTE_NOC, .channels =3D 2, .buswidth =3D 32, .qosbox =3D &qnm_nsp_gemnoc_qos, .num_links =3D 2, - .links =3D { SAR2130P_SLAVE_GEM_NOC_CNOC, SAR2130P_SLAVE_LLCC }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; =20 static const struct qcom_icc_qosbox qnm_pcie_qos =3D { @@ -359,12 +345,11 @@ static const struct qcom_icc_qosbox qnm_pcie_qos =3D { =20 static struct qcom_icc_node qnm_pcie =3D { .name =3D "qnm_pcie", - .id =3D SAR2130P_MASTER_ANOC_PCIE_GEM_NOC, .channels =3D 1, .buswidth =3D 16, .qosbox =3D &qnm_pcie_qos, .num_links =3D 2, - .links =3D { SAR2130P_SLAVE_GEM_NOC_CNOC, SAR2130P_SLAVE_LLCC }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; =20 static const struct qcom_icc_qosbox qnm_snoc_gc_qos =3D { @@ -376,12 +361,11 @@ static const struct qcom_icc_qosbox qnm_snoc_gc_qos = =3D { =20 static struct qcom_icc_node qnm_snoc_gc =3D { .name =3D "qnm_snoc_gc", - .id =3D SAR2130P_MASTER_SNOC_GC_MEM_NOC, .channels =3D 1, .buswidth =3D 8, .qosbox =3D &qnm_snoc_gc_qos, .num_links =3D 1, - .links =3D { SAR2130P_SLAVE_LLCC }, + .link_nodes =3D { &qns_llcc }, }; =20 static const struct qcom_icc_qosbox qnm_snoc_sf_qos =3D { @@ -393,53 +377,48 @@ static const struct qcom_icc_qosbox qnm_snoc_sf_qos = =3D { =20 static struct qcom_icc_node qnm_snoc_sf =3D { .name =3D "qnm_snoc_sf", - .id =3D SAR2130P_MASTER_SNOC_SF_MEM_NOC, .channels =3D 1, .buswidth =3D 16, .qosbox =3D &qnm_snoc_sf_qos, .num_links =3D 3, - .links =3D { SAR2130P_SLAVE_GEM_NOC_CNOC, SAR2130P_SLAVE_LLCC, - SAR2130P_SLAVE_MEM_NOC_PCIE_SNOC }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, }; =20 static struct qcom_icc_node qxm_wlan_q6 =3D { .name =3D "qxm_wlan_q6", - .id =3D SAR2130P_MASTER_WLAN_Q6, .channels =3D 1, .buswidth =3D 8, .num_links =3D 3, - .links =3D { SAR2130P_SLAVE_GEM_NOC_CNOC, SAR2130P_SLAVE_LLCC, - SAR2130P_SLAVE_MEM_NOC_PCIE_SNOC }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, }; =20 static struct qcom_icc_node qhm_config_noc =3D { .name =3D "qhm_config_noc", - .id =3D SAR2130P_MASTER_CNOC_LPASS_AG_NOC, .channels =3D 1, .buswidth =3D 4, .num_links =3D 6, - .links =3D { SAR2130P_SLAVE_LPASS_CORE_CFG, SAR2130P_SLAVE_LPASS_LPI_CFG, - SAR2130P_SLAVE_LPASS_MPU_CFG, SAR2130P_SLAVE_LPASS_TOP_CFG, - SAR2130P_SLAVE_SERVICES_LPASS_AML_NOC, SAR2130P_SLAVE_SERVICE_LPASS_A= G_NOC }, + .link_nodes =3D { &qhs_lpass_core, &qhs_lpass_lpi, + &qhs_lpass_mpu, &qhs_lpass_top, + &srvc_niu_aml_noc, &srvc_niu_lpass_agnoc }, }; =20 static struct qcom_icc_node qxm_lpass_dsp =3D { .name =3D "qxm_lpass_dsp", - .id =3D SAR2130P_MASTER_LPASS_PROC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 4, - .links =3D { SAR2130P_SLAVE_LPASS_TOP_CFG, SAR2130P_SLAVE_LPASS_SNOC, - SAR2130P_SLAVE_SERVICES_LPASS_AML_NOC, SAR2130P_SLAVE_SERVICE_LPASS_A= G_NOC }, + .link_nodes =3D { &qhs_lpass_top, &qns_sysnoc, + &srvc_niu_aml_noc, &srvc_niu_lpass_agnoc }, }; =20 static struct qcom_icc_node llcc_mc =3D { .name =3D "llcc_mc", - .id =3D SAR2130P_MASTER_LLCC, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SAR2130P_SLAVE_EBI1 }, + .link_nodes =3D { &ebi }, }; =20 static const struct qcom_icc_qosbox qnm_camnoc_hf_qos =3D { @@ -451,12 +430,11 @@ static const struct qcom_icc_qosbox qnm_camnoc_hf_qos= =3D { =20 static struct qcom_icc_node qnm_camnoc_hf =3D { .name =3D "qnm_camnoc_hf", - .id =3D SAR2130P_MASTER_CAMNOC_HF, .channels =3D 1, .buswidth =3D 32, .qosbox =3D &qnm_camnoc_hf_qos, .num_links =3D 1, - .links =3D { SAR2130P_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_hf }, }; =20 static const struct qcom_icc_qosbox qnm_camnoc_icp_qos =3D { @@ -468,12 +446,11 @@ static const struct qcom_icc_qosbox qnm_camnoc_icp_qo= s =3D { =20 static struct qcom_icc_node qnm_camnoc_icp =3D { .name =3D "qnm_camnoc_icp", - .id =3D SAR2130P_MASTER_CAMNOC_ICP, .channels =3D 1, .buswidth =3D 8, .qosbox =3D &qnm_camnoc_icp_qos, .num_links =3D 1, - .links =3D { SAR2130P_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static const struct qcom_icc_qosbox qnm_camnoc_sf_qos =3D { @@ -485,12 +462,11 @@ static const struct qcom_icc_qosbox qnm_camnoc_sf_qos= =3D { =20 static struct qcom_icc_node qnm_camnoc_sf =3D { .name =3D "qnm_camnoc_sf", - .id =3D SAR2130P_MASTER_CAMNOC_SF, .channels =3D 1, .buswidth =3D 32, .qosbox =3D &qnm_camnoc_sf_qos, .num_links =3D 1, - .links =3D { SAR2130P_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static const struct qcom_icc_qosbox qnm_lsr_qos =3D { @@ -502,12 +478,11 @@ static const struct qcom_icc_qosbox qnm_lsr_qos =3D { =20 static struct qcom_icc_node qnm_lsr =3D { .name =3D "qnm_lsr", - .id =3D SAR2130P_MASTER_LSR, .channels =3D 2, .buswidth =3D 32, .qosbox =3D &qnm_lsr_qos, .num_links =3D 1, - .links =3D { SAR2130P_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_hf }, }; =20 static const struct qcom_icc_qosbox qnm_mdp_qos =3D { @@ -519,21 +494,19 @@ static const struct qcom_icc_qosbox qnm_mdp_qos =3D { =20 static struct qcom_icc_node qnm_mdp =3D { .name =3D "qnm_mdp", - .id =3D SAR2130P_MASTER_MDP, .channels =3D 2, .buswidth =3D 32, .qosbox =3D &qnm_mdp_qos, .num_links =3D 1, - .links =3D { SAR2130P_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_hf }, }; =20 static struct qcom_icc_node qnm_mnoc_cfg =3D { .name =3D "qnm_mnoc_cfg", - .id =3D SAR2130P_MASTER_CNOC_MNOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SAR2130P_SLAVE_SERVICE_MNOC }, + .link_nodes =3D { &srvc_mnoc }, }; =20 static const struct qcom_icc_qosbox qnm_video_qos =3D { @@ -545,12 +518,11 @@ static const struct qcom_icc_qosbox qnm_video_qos =3D= { =20 static struct qcom_icc_node qnm_video =3D { .name =3D "qnm_video", - .id =3D SAR2130P_MASTER_VIDEO, .channels =3D 2, .buswidth =3D 32, .qosbox =3D &qnm_video_qos, .num_links =3D 1, - .links =3D { SAR2130P_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static const struct qcom_icc_qosbox qnm_video_cv_cpu_qos =3D { @@ -562,12 +534,11 @@ static const struct qcom_icc_qosbox qnm_video_cv_cpu_= qos =3D { =20 static struct qcom_icc_node qnm_video_cv_cpu =3D { .name =3D "qnm_video_cv_cpu", - .id =3D SAR2130P_MASTER_VIDEO_CV_PROC, .channels =3D 1, .buswidth =3D 8, .qosbox =3D &qnm_video_cv_cpu_qos, .num_links =3D 1, - .links =3D { SAR2130P_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static const struct qcom_icc_qosbox qnm_video_cvp_qos =3D { @@ -579,12 +550,11 @@ static const struct qcom_icc_qosbox qnm_video_cvp_qos= =3D { =20 static struct qcom_icc_node qnm_video_cvp =3D { .name =3D "qnm_video_cvp", - .id =3D SAR2130P_MASTER_VIDEO_PROC, .channels =3D 1, .buswidth =3D 32, .qosbox =3D &qnm_video_cvp_qos, .num_links =3D 1, - .links =3D { SAR2130P_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static const struct qcom_icc_qosbox qnm_video_v_cpu_qos =3D { @@ -596,30 +566,27 @@ static const struct qcom_icc_qosbox qnm_video_v_cpu_q= os =3D { =20 static struct qcom_icc_node qnm_video_v_cpu =3D { .name =3D "qnm_video_v_cpu", - .id =3D SAR2130P_MASTER_VIDEO_V_PROC, .channels =3D 1, .buswidth =3D 8, .qosbox =3D &qnm_video_v_cpu_qos, .num_links =3D 1, - .links =3D { SAR2130P_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static struct qcom_icc_node qhm_nsp_noc_config =3D { .name =3D "qhm_nsp_noc_config", - .id =3D SAR2130P_MASTER_CDSP_NOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SAR2130P_SLAVE_SERVICE_NSP_NOC }, + .link_nodes =3D { &service_nsp_noc }, }; =20 static struct qcom_icc_node qxm_nsp =3D { .name =3D "qxm_nsp", - .id =3D SAR2130P_MASTER_CDSP_PROC, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SAR2130P_SLAVE_CDSP_MEM_NOC }, + .link_nodes =3D { &qns_nsp_gemnoc }, }; =20 static const struct qcom_icc_qosbox xm_pcie3_0_qos =3D { @@ -632,12 +599,11 @@ static const struct qcom_icc_qosbox xm_pcie3_0_qos = =3D { =20 static struct qcom_icc_node xm_pcie3_0 =3D { .name =3D "xm_pcie3_0", - .id =3D SAR2130P_MASTER_PCIE_0, .channels =3D 1, .buswidth =3D 8, .qosbox =3D &xm_pcie3_0_qos, .num_links =3D 1, - .links =3D { SAR2130P_SLAVE_ANOC_PCIE_GEM_NOC }, + .link_nodes =3D { &qns_pcie_mem_noc }, }; =20 static const struct qcom_icc_qosbox xm_pcie3_1_qos =3D { @@ -650,12 +616,11 @@ static const struct qcom_icc_qosbox xm_pcie3_1_qos = =3D { =20 static struct qcom_icc_node xm_pcie3_1 =3D { .name =3D "xm_pcie3_1", - .id =3D SAR2130P_MASTER_PCIE_1, .channels =3D 1, .buswidth =3D 8, .qosbox =3D &xm_pcie3_1_qos, .num_links =3D 1, - .links =3D { SAR2130P_SLAVE_ANOC_PCIE_GEM_NOC }, + .link_nodes =3D { &qns_pcie_mem_noc }, }; =20 static const struct qcom_icc_qosbox qhm_gic_qos =3D { @@ -668,12 +633,11 @@ static const struct qcom_icc_qosbox qhm_gic_qos =3D { =20 static struct qcom_icc_node qhm_gic =3D { .name =3D "qhm_gic", - .id =3D SAR2130P_MASTER_GIC_AHB, .channels =3D 1, .buswidth =3D 4, .qosbox =3D &qhm_gic_qos, .num_links =3D 1, - .links =3D { SAR2130P_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes =3D { &qns_gemnoc_sf }, }; =20 static const struct qcom_icc_qosbox qhm_qdss_bam_qos =3D { @@ -686,12 +650,11 @@ static const struct qcom_icc_qosbox qhm_qdss_bam_qos = =3D { =20 static struct qcom_icc_node qhm_qdss_bam =3D { .name =3D "qhm_qdss_bam", - .id =3D SAR2130P_MASTER_QDSS_BAM, .channels =3D 1, .buswidth =3D 4, .qosbox =3D &qhm_qdss_bam_qos, .num_links =3D 1, - .links =3D { SAR2130P_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static const struct qcom_icc_qosbox qhm_qspi_qos =3D { @@ -704,12 +667,11 @@ static const struct qcom_icc_qosbox qhm_qspi_qos =3D { =20 static struct qcom_icc_node qhm_qspi =3D { .name =3D "qhm_qspi", - .id =3D SAR2130P_MASTER_QSPI_0, .channels =3D 1, .buswidth =3D 4, .qosbox =3D &qhm_qspi_qos, .num_links =3D 1, - .links =3D { SAR2130P_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static const struct qcom_icc_qosbox qhm_qup0_qos =3D { @@ -722,12 +684,11 @@ static const struct qcom_icc_qosbox qhm_qup0_qos =3D { =20 static struct qcom_icc_node qhm_qup0 =3D { .name =3D "qhm_qup0", - .id =3D SAR2130P_MASTER_QUP_0, .channels =3D 1, .buswidth =3D 4, .qosbox =3D &qhm_qup0_qos, .num_links =3D 1, - .links =3D { SAR2130P_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static const struct qcom_icc_qosbox qhm_qup1_qos =3D { @@ -740,21 +701,19 @@ static const struct qcom_icc_qosbox qhm_qup1_qos =3D { =20 static struct qcom_icc_node qhm_qup1 =3D { .name =3D "qhm_qup1", - .id =3D SAR2130P_MASTER_QUP_1, .channels =3D 1, .buswidth =3D 4, .qosbox =3D &qhm_qup1_qos, .num_links =3D 1, - .links =3D { SAR2130P_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qnm_aggre2_noc =3D { .name =3D "qnm_aggre2_noc", - .id =3D SAR2130P_MASTER_A2NOC_SNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SAR2130P_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes =3D { &qns_gemnoc_sf }, }; =20 static const struct qcom_icc_qosbox qnm_cnoc_datapath_qos =3D { @@ -767,12 +726,11 @@ static const struct qcom_icc_qosbox qnm_cnoc_datapath= _qos =3D { =20 static struct qcom_icc_node qnm_cnoc_datapath =3D { .name =3D "qnm_cnoc_datapath", - .id =3D SAR2130P_MASTER_CNOC_DATAPATH, .channels =3D 1, .buswidth =3D 8, .qosbox =3D &qnm_cnoc_datapath_qos, .num_links =3D 1, - .links =3D { SAR2130P_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static const struct qcom_icc_qosbox qnm_lpass_noc_qos =3D { @@ -785,21 +743,19 @@ static const struct qcom_icc_qosbox qnm_lpass_noc_qos= =3D { =20 static struct qcom_icc_node qnm_lpass_noc =3D { .name =3D "qnm_lpass_noc", - .id =3D SAR2130P_MASTER_LPASS_ANOC, .channels =3D 1, .buswidth =3D 16, .qosbox =3D &qnm_lpass_noc_qos, .num_links =3D 1, - .links =3D { SAR2130P_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes =3D { &qns_gemnoc_sf }, }; =20 static struct qcom_icc_node qnm_snoc_cfg =3D { .name =3D "qnm_snoc_cfg", - .id =3D SAR2130P_MASTER_SNOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SAR2130P_SLAVE_SERVICE_SNOC }, + .link_nodes =3D { &srvc_snoc }, }; =20 static const struct qcom_icc_qosbox qxm_crypto_qos =3D { @@ -812,12 +768,11 @@ static const struct qcom_icc_qosbox qxm_crypto_qos = =3D { =20 static struct qcom_icc_node qxm_crypto =3D { .name =3D "qxm_crypto", - .id =3D SAR2130P_MASTER_CRYPTO, .channels =3D 1, .buswidth =3D 8, .qosbox =3D &qxm_crypto_qos, .num_links =3D 1, - .links =3D { SAR2130P_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static const struct qcom_icc_qosbox qxm_pimem_qos =3D { @@ -830,12 +785,11 @@ static const struct qcom_icc_qosbox qxm_pimem_qos =3D= { =20 static struct qcom_icc_node qxm_pimem =3D { .name =3D "qxm_pimem", - .id =3D SAR2130P_MASTER_PIMEM, .channels =3D 1, .buswidth =3D 8, .qosbox =3D &qxm_pimem_qos, .num_links =3D 1, - .links =3D { SAR2130P_SLAVE_SNOC_GEM_NOC_GC }, + .link_nodes =3D { &qns_gemnoc_gc }, }; =20 static const struct qcom_icc_qosbox xm_gic_qos =3D { @@ -848,12 +802,11 @@ static const struct qcom_icc_qosbox xm_gic_qos =3D { =20 static struct qcom_icc_node xm_gic =3D { .name =3D "xm_gic", - .id =3D SAR2130P_MASTER_GIC, .channels =3D 1, .buswidth =3D 8, .qosbox =3D &xm_gic_qos, .num_links =3D 1, - .links =3D { SAR2130P_SLAVE_SNOC_GEM_NOC_GC }, + .link_nodes =3D { &qns_gemnoc_gc }, }; =20 static const struct qcom_icc_qosbox xm_qdss_etr_0_qos =3D { @@ -866,12 +819,11 @@ static const struct qcom_icc_qosbox xm_qdss_etr_0_qos= =3D { =20 static struct qcom_icc_node xm_qdss_etr_0 =3D { .name =3D "xm_qdss_etr_0", - .id =3D SAR2130P_MASTER_QDSS_ETR, .channels =3D 1, .buswidth =3D 8, .qosbox =3D &xm_qdss_etr_0_qos, .num_links =3D 1, - .links =3D { SAR2130P_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static const struct qcom_icc_qosbox xm_qdss_etr_1_qos =3D { @@ -884,12 +836,11 @@ static const struct qcom_icc_qosbox xm_qdss_etr_1_qos= =3D { =20 static struct qcom_icc_node xm_qdss_etr_1 =3D { .name =3D "xm_qdss_etr_1", - .id =3D SAR2130P_MASTER_QDSS_ETR_1, .channels =3D 1, .buswidth =3D 8, .qosbox =3D &xm_qdss_etr_1_qos, .num_links =3D 1, - .links =3D { SAR2130P_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static const struct qcom_icc_qosbox xm_sdc1_qos =3D { @@ -902,12 +853,11 @@ static const struct qcom_icc_qosbox xm_sdc1_qos =3D { =20 static struct qcom_icc_node xm_sdc1 =3D { .name =3D "xm_sdc1", - .id =3D SAR2130P_MASTER_SDCC_1, .channels =3D 1, .buswidth =3D 8, .qosbox =3D &xm_sdc1_qos, .num_links =3D 1, - .links =3D { SAR2130P_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static const struct qcom_icc_qosbox xm_usb3_0_qos =3D { @@ -920,571 +870,449 @@ static const struct qcom_icc_qosbox xm_usb3_0_qos = =3D { =20 static struct qcom_icc_node xm_usb3_0 =3D { .name =3D "xm_usb3_0", - .id =3D SAR2130P_MASTER_USB3_0, .channels =3D 1, .buswidth =3D 8, .qosbox =3D &xm_usb3_0_qos, .num_links =3D 1, - .links =3D { SAR2130P_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qup0_core_slave =3D { .name =3D "qup0_core_slave", - .id =3D SAR2130P_SLAVE_QUP_CORE_0, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qup1_core_slave =3D { .name =3D "qup1_core_slave", - .id =3D SAR2130P_SLAVE_QUP_CORE_1, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_ahb2phy0 =3D { .name =3D "qhs_ahb2phy0", - .id =3D SAR2130P_SLAVE_AHB2PHY_SOUTH, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_aoss =3D { .name =3D "qhs_aoss", - .id =3D SAR2130P_SLAVE_AOSS, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_camera_cfg =3D { .name =3D "qhs_camera_cfg", - .id =3D SAR2130P_SLAVE_CAMERA_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_clk_ctl =3D { .name =3D "qhs_clk_ctl", - .id =3D SAR2130P_SLAVE_CLK_CTL, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_compute_cfg =3D { .name =3D "qhs_compute_cfg", - .id =3D SAR2130P_SLAVE_CDSP_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SAR2130P_MASTER_CDSP_NOC_CFG }, + .link_nodes =3D { &qhm_nsp_noc_config }, }; =20 static struct qcom_icc_node qhs_cpr_cx =3D { .name =3D "qhs_cpr_cx", - .id =3D SAR2130P_SLAVE_RBCPR_CX_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_cpr_mmcx =3D { .name =3D "qhs_cpr_mmcx", - .id =3D SAR2130P_SLAVE_RBCPR_MMCX_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_cpr_mxa =3D { .name =3D "qhs_cpr_mxa", - .id =3D SAR2130P_SLAVE_RBCPR_MXA_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_cpr_mxc =3D { .name =3D "qhs_cpr_mxc", - .id =3D SAR2130P_SLAVE_RBCPR_MXC_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_cpr_nspcx =3D { .name =3D "qhs_cpr_nspcx", - .id =3D SAR2130P_SLAVE_CPR_NSPCX, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_crypto0_cfg =3D { .name =3D "qhs_crypto0_cfg", - .id =3D SAR2130P_SLAVE_CRYPTO_0_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_cx_rdpm =3D { .name =3D "qhs_cx_rdpm", - .id =3D SAR2130P_SLAVE_CX_RDPM, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_display_cfg =3D { .name =3D "qhs_display_cfg", - .id =3D SAR2130P_SLAVE_DISPLAY_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_gpuss_cfg =3D { .name =3D "qhs_gpuss_cfg", - .id =3D SAR2130P_SLAVE_GFX3D_CFG, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_imem_cfg =3D { .name =3D "qhs_imem_cfg", - .id =3D SAR2130P_SLAVE_IMEM_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_ipc_router =3D { .name =3D "qhs_ipc_router", - .id =3D SAR2130P_SLAVE_IPC_ROUTER_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_lpass_cfg =3D { .name =3D "qhs_lpass_cfg", - .id =3D SAR2130P_SLAVE_LPASS, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SAR2130P_MASTER_CNOC_LPASS_AG_NOC }, + .link_nodes =3D { &qhm_config_noc }, }; =20 static struct qcom_icc_node qhs_mx_rdpm =3D { .name =3D "qhs_mx_rdpm", - .id =3D SAR2130P_SLAVE_MX_RDPM, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_pcie0_cfg =3D { .name =3D "qhs_pcie0_cfg", - .id =3D SAR2130P_SLAVE_PCIE_0_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_pcie1_cfg =3D { .name =3D "qhs_pcie1_cfg", - .id =3D SAR2130P_SLAVE_PCIE_1_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_pdm =3D { .name =3D "qhs_pdm", - .id =3D SAR2130P_SLAVE_PDM, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_pimem_cfg =3D { .name =3D "qhs_pimem_cfg", - .id =3D SAR2130P_SLAVE_PIMEM_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_prng =3D { .name =3D "qhs_prng", - .id =3D SAR2130P_SLAVE_PRNG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_qdss_cfg =3D { .name =3D "qhs_qdss_cfg", - .id =3D SAR2130P_SLAVE_QDSS_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_qspi =3D { .name =3D "qhs_qspi", - .id =3D SAR2130P_SLAVE_QSPI_0, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_qup0 =3D { .name =3D "qhs_qup0", - .id =3D SAR2130P_SLAVE_QUP_0, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_qup1 =3D { .name =3D "qhs_qup1", - .id =3D SAR2130P_SLAVE_QUP_1, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_sdc1 =3D { .name =3D "qhs_sdc1", - .id =3D SAR2130P_SLAVE_SDCC_1, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_tcsr =3D { .name =3D "qhs_tcsr", - .id =3D SAR2130P_SLAVE_TCSR, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_tlmm =3D { .name =3D "qhs_tlmm", - .id =3D SAR2130P_SLAVE_TLMM, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_tme_cfg =3D { .name =3D "qhs_tme_cfg", - .id =3D SAR2130P_SLAVE_TME_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_usb3_0 =3D { .name =3D "qhs_usb3_0", - .id =3D SAR2130P_SLAVE_USB3_0, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_venus_cfg =3D { .name =3D "qhs_venus_cfg", - .id =3D SAR2130P_SLAVE_VENUS_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_vsense_ctrl_cfg =3D { .name =3D "qhs_vsense_ctrl_cfg", - .id =3D SAR2130P_SLAVE_VSENSE_CTRL_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_wlan_q6 =3D { .name =3D "qhs_wlan_q6", - .id =3D SAR2130P_SLAVE_WLAN_Q6_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qns_ddrss_cfg =3D { .name =3D "qns_ddrss_cfg", - .id =3D SAR2130P_SLAVE_DDRSS_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qns_mnoc_cfg =3D { .name =3D "qns_mnoc_cfg", - .id =3D SAR2130P_SLAVE_CNOC_MNOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SAR2130P_MASTER_CNOC_MNOC_CFG }, + .link_nodes =3D { &qnm_mnoc_cfg }, }; =20 static struct qcom_icc_node qns_snoc_cfg =3D { .name =3D "qns_snoc_cfg", - .id =3D SAR2130P_SLAVE_SNOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SAR2130P_MASTER_SNOC_CFG }, + .link_nodes =3D { &qnm_snoc_cfg }, }; =20 static struct qcom_icc_node qxs_imem =3D { .name =3D "qxs_imem", - .id =3D SAR2130P_SLAVE_IMEM, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 0, }; =20 static struct qcom_icc_node qxs_pimem =3D { .name =3D "qxs_pimem", - .id =3D SAR2130P_SLAVE_PIMEM, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 0, }; =20 static struct qcom_icc_node srvc_cnoc =3D { .name =3D "srvc_cnoc", - .id =3D SAR2130P_SLAVE_SERVICE_CNOC, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node xs_pcie_0 =3D { .name =3D "xs_pcie_0", - .id =3D SAR2130P_SLAVE_PCIE_0, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 0, }; =20 static struct qcom_icc_node xs_pcie_1 =3D { .name =3D "xs_pcie_1", - .id =3D SAR2130P_SLAVE_PCIE_1, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 0, }; =20 static struct qcom_icc_node xs_qdss_stm =3D { .name =3D "xs_qdss_stm", - .id =3D SAR2130P_SLAVE_QDSS_STM, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node xs_sys_tcu_cfg =3D { .name =3D "xs_sys_tcu_cfg", - .id =3D SAR2130P_SLAVE_TCU, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 0, }; =20 static struct qcom_icc_node qns_gem_noc_cnoc =3D { .name =3D "qns_gem_noc_cnoc", - .id =3D SAR2130P_SLAVE_GEM_NOC_CNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SAR2130P_MASTER_GEM_NOC_CNOC }, + .link_nodes =3D { &qnm_gemnoc_cnoc }, }; =20 static struct qcom_icc_node qns_llcc =3D { .name =3D "qns_llcc", - .id =3D SAR2130P_SLAVE_LLCC, .channels =3D 2, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SAR2130P_MASTER_LLCC }, + .link_nodes =3D { &llcc_mc }, }; =20 static struct qcom_icc_node qns_pcie =3D { .name =3D "qns_pcie", - .id =3D SAR2130P_SLAVE_MEM_NOC_PCIE_SNOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SAR2130P_MASTER_GEM_NOC_PCIE_SNOC }, + .link_nodes =3D { &qnm_gemnoc_pcie }, }; =20 static struct qcom_icc_node qhs_lpass_core =3D { .name =3D "qhs_lpass_core", - .id =3D SAR2130P_SLAVE_LPASS_CORE_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_lpass_lpi =3D { .name =3D "qhs_lpass_lpi", - .id =3D SAR2130P_SLAVE_LPASS_LPI_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_lpass_mpu =3D { .name =3D "qhs_lpass_mpu", - .id =3D SAR2130P_SLAVE_LPASS_MPU_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_lpass_top =3D { .name =3D "qhs_lpass_top", - .id =3D SAR2130P_SLAVE_LPASS_TOP_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qns_sysnoc =3D { .name =3D "qns_sysnoc", - .id =3D SAR2130P_SLAVE_LPASS_SNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SAR2130P_MASTER_LPASS_ANOC }, + .link_nodes =3D { &qnm_lpass_noc }, }; =20 static struct qcom_icc_node srvc_niu_aml_noc =3D { .name =3D "srvc_niu_aml_noc", - .id =3D SAR2130P_SLAVE_SERVICES_LPASS_AML_NOC, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node srvc_niu_lpass_agnoc =3D { .name =3D "srvc_niu_lpass_agnoc", - .id =3D SAR2130P_SLAVE_SERVICE_LPASS_AG_NOC, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node ebi =3D { .name =3D "ebi", - .id =3D SAR2130P_SLAVE_EBI1, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qns_mem_noc_hf =3D { .name =3D "qns_mem_noc_hf", - .id =3D SAR2130P_SLAVE_MNOC_HF_MEM_NOC, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SAR2130P_MASTER_MNOC_HF_MEM_NOC }, + .link_nodes =3D { &qnm_mnoc_hf }, }; =20 static struct qcom_icc_node qns_mem_noc_sf =3D { .name =3D "qns_mem_noc_sf", - .id =3D SAR2130P_SLAVE_MNOC_SF_MEM_NOC, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SAR2130P_MASTER_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qnm_mnoc_sf }, }; =20 static struct qcom_icc_node srvc_mnoc =3D { .name =3D "srvc_mnoc", - .id =3D SAR2130P_SLAVE_SERVICE_MNOC, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qns_nsp_gemnoc =3D { .name =3D "qns_nsp_gemnoc", - .id =3D SAR2130P_SLAVE_CDSP_MEM_NOC, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SAR2130P_MASTER_COMPUTE_NOC }, + .link_nodes =3D { &qnm_nsp_gemnoc }, }; =20 static struct qcom_icc_node service_nsp_noc =3D { .name =3D "service_nsp_noc", - .id =3D SAR2130P_SLAVE_SERVICE_NSP_NOC, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qns_pcie_mem_noc =3D { .name =3D "qns_pcie_mem_noc", - .id =3D SAR2130P_SLAVE_ANOC_PCIE_GEM_NOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SAR2130P_MASTER_ANOC_PCIE_GEM_NOC }, + .link_nodes =3D { &qnm_pcie }, }; =20 static struct qcom_icc_node qns_a2noc_snoc =3D { .name =3D "qns_a2noc_snoc", - .id =3D SAR2130P_SLAVE_A2NOC_SNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SAR2130P_MASTER_A2NOC_SNOC }, + .link_nodes =3D { &qnm_aggre2_noc }, }; =20 static struct qcom_icc_node qns_gemnoc_gc =3D { .name =3D "qns_gemnoc_gc", - .id =3D SAR2130P_SLAVE_SNOC_GEM_NOC_GC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SAR2130P_MASTER_SNOC_GC_MEM_NOC }, + .link_nodes =3D { &qnm_snoc_gc }, }; =20 static struct qcom_icc_node qns_gemnoc_sf =3D { .name =3D "qns_gemnoc_sf", - .id =3D SAR2130P_SLAVE_SNOC_GEM_NOC_SF, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SAR2130P_MASTER_SNOC_SF_MEM_NOC }, + .link_nodes =3D { &qnm_snoc_sf }, }; =20 static struct qcom_icc_node srvc_snoc =3D { .name =3D "srvc_snoc", - .id =3D SAR2130P_SLAVE_SERVICE_SNOC, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_bcm bcm_acv =3D { @@ -1646,6 +1474,7 @@ static struct qcom_icc_node * const clk_virt_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sar2130p_clk_virt =3D { + .alloc_dyn_id =3D true, .nodes =3D clk_virt_nodes, .num_nodes =3D ARRAY_SIZE(clk_virt_nodes), .bcms =3D clk_virt_bcms, @@ -1708,6 +1537,7 @@ static struct qcom_icc_node * const config_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sar2130p_config_noc =3D { + .alloc_dyn_id =3D true, .config =3D &icc_regmap_config, .nodes =3D config_noc_nodes, .num_nodes =3D ARRAY_SIZE(config_noc_nodes), @@ -1738,6 +1568,7 @@ static struct qcom_icc_node * const gem_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sar2130p_gem_noc =3D { + .alloc_dyn_id =3D true, .config =3D &icc_regmap_config, .nodes =3D gem_noc_nodes, .num_nodes =3D ARRAY_SIZE(gem_noc_nodes), @@ -1761,6 +1592,7 @@ static struct qcom_icc_node * const lpass_ag_noc_node= s[] =3D { }; =20 static const struct qcom_icc_desc sar2130p_lpass_ag_noc =3D { + .alloc_dyn_id =3D true, .config =3D &icc_regmap_config, .nodes =3D lpass_ag_noc_nodes, .num_nodes =3D ARRAY_SIZE(lpass_ag_noc_nodes), @@ -1779,6 +1611,7 @@ static struct qcom_icc_node * const mc_virt_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sar2130p_mc_virt =3D { + .alloc_dyn_id =3D true, .nodes =3D mc_virt_nodes, .num_nodes =3D ARRAY_SIZE(mc_virt_nodes), .bcms =3D mc_virt_bcms, @@ -1807,6 +1640,7 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sar2130p_mmss_noc =3D { + .alloc_dyn_id =3D true, .config =3D &icc_regmap_config, .nodes =3D mmss_noc_nodes, .num_nodes =3D ARRAY_SIZE(mmss_noc_nodes), @@ -1826,6 +1660,7 @@ static struct qcom_icc_node * const nsp_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sar2130p_nsp_noc =3D { + .alloc_dyn_id =3D true, .config =3D &icc_regmap_config, .nodes =3D nsp_noc_nodes, .num_nodes =3D ARRAY_SIZE(nsp_noc_nodes), @@ -1844,6 +1679,7 @@ static struct qcom_icc_node * const pcie_anoc_nodes[]= =3D { }; =20 static const struct qcom_icc_desc sar2130p_pcie_anoc =3D { + .alloc_dyn_id =3D true, .config =3D &icc_regmap_config, .nodes =3D pcie_anoc_nodes, .num_nodes =3D ARRAY_SIZE(pcie_anoc_nodes), @@ -1883,6 +1719,7 @@ static struct qcom_icc_node * const system_noc_nodes[= ] =3D { }; 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This gives more flexibility and also allows us to drop the .num_links member, saving from possible errors related to it being not set or set incorrectly. Signed-off-by: Dmitry Baryshkov --- drivers/interconnect/qcom/sc7180.c | 690 ++++++++++++++++++---------------= ---- drivers/interconnect/qcom/sc7180.h | 149 -------- 2 files changed, 344 insertions(+), 495 deletions(-) diff --git a/drivers/interconnect/qcom/sc7180.c b/drivers/interconnect/qcom= /sc7180.c index af2be15438403e4b46fca464b84abd1e0ebebe76..9f94b987c4448a04dc984ad09b0= 733c33c9bb76a 100644 --- a/drivers/interconnect/qcom/sc7180.c +++ b/drivers/interconnect/qcom/sc7180.c @@ -14,1224 +14,1210 @@ =20 #include "bcm-voter.h" #include "icc-rpmh.h" -#include "sc7180.h" + +static struct qcom_icc_node qhm_a1noc_cfg; +static struct qcom_icc_node qhm_qspi; +static struct qcom_icc_node qhm_qup_0; +static struct qcom_icc_node xm_sdc2; +static struct qcom_icc_node xm_emmc; +static struct qcom_icc_node xm_ufs_mem; +static struct qcom_icc_node qhm_a2noc_cfg; +static struct qcom_icc_node qhm_qdss_bam; +static struct qcom_icc_node qhm_qup_1; +static struct qcom_icc_node qxm_crypto; +static struct qcom_icc_node qxm_ipa; +static struct qcom_icc_node xm_qdss_etr; +static struct qcom_icc_node qhm_usb3; +static struct qcom_icc_node qxm_camnoc_hf0_uncomp; +static struct qcom_icc_node qxm_camnoc_hf1_uncomp; +static struct qcom_icc_node qxm_camnoc_sf_uncomp; +static struct qcom_icc_node qnm_npu; +static struct qcom_icc_node qxm_npu_dsp; +static struct qcom_icc_node qnm_snoc; +static struct qcom_icc_node xm_qdss_dap; +static struct qcom_icc_node qhm_cnoc_dc_noc; +static struct qcom_icc_node acm_apps0; +static struct qcom_icc_node acm_sys_tcu; +static struct qcom_icc_node qhm_gemnoc_cfg; +static struct qcom_icc_node qnm_cmpnoc; +static struct qcom_icc_node qnm_mnoc_hf; +static struct qcom_icc_node qnm_mnoc_sf; +static struct qcom_icc_node qnm_snoc_gc; +static struct qcom_icc_node qnm_snoc_sf; +static struct qcom_icc_node qxm_gpu; +static struct qcom_icc_node llcc_mc; +static struct qcom_icc_node qhm_mnoc_cfg; +static struct qcom_icc_node qxm_camnoc_hf0; +static struct qcom_icc_node qxm_camnoc_hf1; +static struct qcom_icc_node qxm_camnoc_sf; +static struct qcom_icc_node qxm_mdp0; +static struct qcom_icc_node qxm_rot; +static struct qcom_icc_node qxm_venus0; +static struct qcom_icc_node qxm_venus_arm9; +static struct qcom_icc_node amm_npu_sys; +static struct qcom_icc_node qhm_npu_cfg; +static struct qcom_icc_node qup_core_master_1; +static struct qcom_icc_node qup_core_master_2; +static struct qcom_icc_node qhm_snoc_cfg; +static struct qcom_icc_node qnm_aggre1_noc; +static struct qcom_icc_node qnm_aggre2_noc; +static struct qcom_icc_node qnm_gemnoc; +static struct qcom_icc_node qxm_pimem; +static struct qcom_icc_node qns_a1noc_snoc; +static struct qcom_icc_node srvc_aggre1_noc; +static struct qcom_icc_node qns_a2noc_snoc; +static struct qcom_icc_node srvc_aggre2_noc; +static struct qcom_icc_node qns_camnoc_uncomp; +static struct qcom_icc_node qns_cdsp_gemnoc; +static struct qcom_icc_node qhs_a1_noc_cfg; +static struct qcom_icc_node qhs_a2_noc_cfg; +static struct qcom_icc_node qhs_ahb2phy0; +static struct qcom_icc_node qhs_ahb2phy2; +static struct qcom_icc_node qhs_aop; +static struct qcom_icc_node qhs_aoss; +static struct qcom_icc_node qhs_boot_rom; +static struct qcom_icc_node qhs_camera_cfg; +static struct qcom_icc_node qhs_camera_nrt_throttle_cfg; +static struct qcom_icc_node qhs_camera_rt_throttle_cfg; +static struct qcom_icc_node qhs_clk_ctl; +static struct qcom_icc_node qhs_cpr_cx; +static struct qcom_icc_node qhs_cpr_mx; +static struct qcom_icc_node qhs_crypto0_cfg; +static struct qcom_icc_node qhs_dcc_cfg; +static struct qcom_icc_node qhs_ddrss_cfg; +static struct qcom_icc_node qhs_display_cfg; +static struct qcom_icc_node qhs_display_rt_throttle_cfg; +static struct qcom_icc_node qhs_display_throttle_cfg; +static struct qcom_icc_node qhs_emmc_cfg; +static struct qcom_icc_node qhs_glm; +static struct qcom_icc_node qhs_gpuss_cfg; +static struct qcom_icc_node qhs_imem_cfg; +static struct qcom_icc_node qhs_ipa; +static struct qcom_icc_node qhs_mnoc_cfg; +static struct qcom_icc_node qhs_mss_cfg; +static struct qcom_icc_node qhs_npu_cfg; +static struct qcom_icc_node qhs_npu_dma_throttle_cfg; +static struct qcom_icc_node qhs_npu_dsp_throttle_cfg; +static struct qcom_icc_node qhs_pdm; +static struct qcom_icc_node qhs_pimem_cfg; +static struct qcom_icc_node qhs_prng; +static struct qcom_icc_node qhs_qdss_cfg; +static struct qcom_icc_node qhs_qm_cfg; +static struct qcom_icc_node qhs_qm_mpu_cfg; +static struct qcom_icc_node qhs_qspi; +static struct qcom_icc_node qhs_qup0; +static struct qcom_icc_node qhs_qup1; +static struct qcom_icc_node qhs_sdc2; +static struct qcom_icc_node qhs_security; +static struct qcom_icc_node qhs_snoc_cfg; +static struct qcom_icc_node qhs_tcsr; +static struct qcom_icc_node qhs_tlmm_1; +static struct qcom_icc_node qhs_tlmm_2; +static struct qcom_icc_node qhs_tlmm_3; +static struct qcom_icc_node qhs_ufs_mem_cfg; +static struct qcom_icc_node qhs_usb3; +static struct qcom_icc_node qhs_venus_cfg; +static struct qcom_icc_node qhs_venus_throttle_cfg; +static struct qcom_icc_node qhs_vsense_ctrl_cfg; +static struct qcom_icc_node srvc_cnoc; +static struct qcom_icc_node qhs_gemnoc; +static struct qcom_icc_node qhs_llcc; +static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg; +static struct qcom_icc_node qns_gem_noc_snoc; +static struct qcom_icc_node qns_llcc; +static struct qcom_icc_node srvc_gemnoc; +static struct qcom_icc_node ebi; +static struct qcom_icc_node qns_mem_noc_hf; +static struct qcom_icc_node qns_mem_noc_sf; +static struct qcom_icc_node srvc_mnoc; +static struct qcom_icc_node qhs_cal_dp0; +static struct qcom_icc_node qhs_cp; +static struct qcom_icc_node qhs_dma_bwmon; +static struct qcom_icc_node qhs_dpm; +static struct qcom_icc_node qhs_isense; +static struct qcom_icc_node qhs_llm; +static struct qcom_icc_node qhs_tcm; +static struct qcom_icc_node qns_npu_sys; +static struct qcom_icc_node srvc_noc; +static struct qcom_icc_node qup_core_slave_1; +static struct qcom_icc_node qup_core_slave_2; +static struct qcom_icc_node qhs_apss; +static struct qcom_icc_node qns_cnoc; +static struct qcom_icc_node qns_gemnoc_gc; +static struct qcom_icc_node qns_gemnoc_sf; +static struct qcom_icc_node qxs_imem; +static struct qcom_icc_node qxs_pimem; +static struct qcom_icc_node srvc_snoc; +static struct qcom_icc_node xs_qdss_stm; +static struct qcom_icc_node xs_sys_tcu_cfg; =20 static struct qcom_icc_node qhm_a1noc_cfg =3D { .name =3D "qhm_a1noc_cfg", - .id =3D SC7180_MASTER_A1NOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SC7180_SLAVE_SERVICE_A1NOC }, + .link_nodes =3D { &srvc_aggre1_noc }, }; =20 static struct qcom_icc_node qhm_qspi =3D { .name =3D "qhm_qspi", - .id =3D SC7180_MASTER_QSPI, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SC7180_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node qhm_qup_0 =3D { .name =3D "qhm_qup_0", - .id =3D SC7180_MASTER_QUP_0, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SC7180_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node xm_sdc2 =3D { .name =3D "xm_sdc2", - .id =3D SC7180_MASTER_SDCC_2, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SC7180_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node xm_emmc =3D { .name =3D "xm_emmc", - .id =3D SC7180_MASTER_EMMC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SC7180_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node xm_ufs_mem =3D { .name =3D "xm_ufs_mem", - .id =3D SC7180_MASTER_UFS_MEM, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SC7180_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node qhm_a2noc_cfg =3D { .name =3D "qhm_a2noc_cfg", - .id =3D SC7180_MASTER_A2NOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SC7180_SLAVE_SERVICE_A2NOC }, + .link_nodes =3D { &srvc_aggre2_noc }, }; =20 static struct qcom_icc_node qhm_qdss_bam =3D { .name =3D "qhm_qdss_bam", - .id =3D SC7180_MASTER_QDSS_BAM, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SC7180_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qhm_qup_1 =3D { .name =3D "qhm_qup_1", - .id =3D SC7180_MASTER_QUP_1, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SC7180_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qxm_crypto =3D { .name =3D "qxm_crypto", - .id =3D SC7180_MASTER_CRYPTO, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SC7180_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qxm_ipa =3D { .name =3D "qxm_ipa", - .id =3D SC7180_MASTER_IPA, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SC7180_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node xm_qdss_etr =3D { .name =3D "xm_qdss_etr", - .id =3D SC7180_MASTER_QDSS_ETR, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SC7180_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qhm_usb3 =3D { .name =3D "qhm_usb3", - .id =3D SC7180_MASTER_USB3, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SC7180_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qxm_camnoc_hf0_uncomp =3D { .name =3D "qxm_camnoc_hf0_uncomp", - .id =3D SC7180_MASTER_CAMNOC_HF0_UNCOMP, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SC7180_SLAVE_CAMNOC_UNCOMP }, + .link_nodes =3D { &qns_camnoc_uncomp }, }; =20 static struct qcom_icc_node qxm_camnoc_hf1_uncomp =3D { .name =3D "qxm_camnoc_hf1_uncomp", - .id =3D SC7180_MASTER_CAMNOC_HF1_UNCOMP, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SC7180_SLAVE_CAMNOC_UNCOMP }, + .link_nodes =3D { &qns_camnoc_uncomp }, }; =20 static struct qcom_icc_node qxm_camnoc_sf_uncomp =3D { .name =3D "qxm_camnoc_sf_uncomp", - .id =3D SC7180_MASTER_CAMNOC_SF_UNCOMP, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SC7180_SLAVE_CAMNOC_UNCOMP }, + .link_nodes =3D { &qns_camnoc_uncomp }, }; =20 static struct qcom_icc_node qnm_npu =3D { .name =3D "qnm_npu", - .id =3D SC7180_MASTER_NPU, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SC7180_SLAVE_CDSP_GEM_NOC }, + .link_nodes =3D { &qns_cdsp_gemnoc }, }; =20 static struct qcom_icc_node qxm_npu_dsp =3D { .name =3D "qxm_npu_dsp", - .id =3D SC7180_MASTER_NPU_PROC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SC7180_SLAVE_CDSP_GEM_NOC }, + .link_nodes =3D { &qns_cdsp_gemnoc }, }; =20 static struct qcom_icc_node qnm_snoc =3D { .name =3D "qnm_snoc", - .id =3D SC7180_MASTER_SNOC_CNOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 51, - .links =3D { SC7180_SLAVE_A1NOC_CFG, - SC7180_SLAVE_A2NOC_CFG, - SC7180_SLAVE_AHB2PHY_SOUTH, - SC7180_SLAVE_AHB2PHY_CENTER, - SC7180_SLAVE_AOP, - SC7180_SLAVE_AOSS, - SC7180_SLAVE_BOOT_ROM, - SC7180_SLAVE_CAMERA_CFG, - SC7180_SLAVE_CAMERA_NRT_THROTTLE_CFG, - SC7180_SLAVE_CAMERA_RT_THROTTLE_CFG, - SC7180_SLAVE_CLK_CTL, - SC7180_SLAVE_RBCPR_CX_CFG, - SC7180_SLAVE_RBCPR_MX_CFG, - SC7180_SLAVE_CRYPTO_0_CFG, - SC7180_SLAVE_DCC_CFG, - SC7180_SLAVE_CNOC_DDRSS, - SC7180_SLAVE_DISPLAY_CFG, - SC7180_SLAVE_DISPLAY_RT_THROTTLE_CFG, - SC7180_SLAVE_DISPLAY_THROTTLE_CFG, - SC7180_SLAVE_EMMC_CFG, - SC7180_SLAVE_GLM, - SC7180_SLAVE_GFX3D_CFG, - SC7180_SLAVE_IMEM_CFG, - SC7180_SLAVE_IPA_CFG, - SC7180_SLAVE_CNOC_MNOC_CFG, - SC7180_SLAVE_CNOC_MSS, - SC7180_SLAVE_NPU_CFG, - SC7180_SLAVE_NPU_DMA_BWMON_CFG, - SC7180_SLAVE_NPU_PROC_BWMON_CFG, - SC7180_SLAVE_PDM, - SC7180_SLAVE_PIMEM_CFG, - SC7180_SLAVE_PRNG, - SC7180_SLAVE_QDSS_CFG, - SC7180_SLAVE_QM_CFG, - SC7180_SLAVE_QM_MPU_CFG, - SC7180_SLAVE_QSPI_0, - SC7180_SLAVE_QUP_0, - SC7180_SLAVE_QUP_1, - SC7180_SLAVE_SDCC_2, - SC7180_SLAVE_SECURITY, - SC7180_SLAVE_SNOC_CFG, - SC7180_SLAVE_TCSR, - SC7180_SLAVE_TLMM_WEST, - SC7180_SLAVE_TLMM_NORTH, - SC7180_SLAVE_TLMM_SOUTH, - SC7180_SLAVE_UFS_MEM_CFG, - SC7180_SLAVE_USB3, - SC7180_SLAVE_VENUS_CFG, - SC7180_SLAVE_VENUS_THROTTLE_CFG, - SC7180_SLAVE_VSENSE_CTRL_CFG, - SC7180_SLAVE_SERVICE_CNOC - }, + .link_nodes =3D { &qhs_a1_noc_cfg, + &qhs_a2_noc_cfg, + &qhs_ahb2phy0, + &qhs_ahb2phy2, + &qhs_aop, + &qhs_aoss, + &qhs_boot_rom, + &qhs_camera_cfg, + &qhs_camera_nrt_throttle_cfg, + &qhs_camera_rt_throttle_cfg, + &qhs_clk_ctl, + &qhs_cpr_cx, + &qhs_cpr_mx, + &qhs_crypto0_cfg, + &qhs_dcc_cfg, + &qhs_ddrss_cfg, + &qhs_display_cfg, + &qhs_display_rt_throttle_cfg, + &qhs_display_throttle_cfg, + &qhs_emmc_cfg, + &qhs_glm, + &qhs_gpuss_cfg, + &qhs_imem_cfg, + &qhs_ipa, + &qhs_mnoc_cfg, + &qhs_mss_cfg, + &qhs_npu_cfg, + &qhs_npu_dma_throttle_cfg, + &qhs_npu_dsp_throttle_cfg, + &qhs_pdm, + &qhs_pimem_cfg, + &qhs_prng, + &qhs_qdss_cfg, + &qhs_qm_cfg, + &qhs_qm_mpu_cfg, + &qhs_qspi, + &qhs_qup0, + &qhs_qup1, + &qhs_sdc2, + &qhs_security, + &qhs_snoc_cfg, + &qhs_tcsr, + &qhs_tlmm_1, + &qhs_tlmm_2, + &qhs_tlmm_3, + &qhs_ufs_mem_cfg, + &qhs_usb3, + &qhs_venus_cfg, + &qhs_venus_throttle_cfg, + &qhs_vsense_ctrl_cfg, + &srvc_cnoc }, }; =20 static struct qcom_icc_node xm_qdss_dap =3D { .name =3D "xm_qdss_dap", - .id =3D SC7180_MASTER_QDSS_DAP, .channels =3D 1, .buswidth =3D 8, .num_links =3D 51, - .links =3D { SC7180_SLAVE_A1NOC_CFG, - SC7180_SLAVE_A2NOC_CFG, - SC7180_SLAVE_AHB2PHY_SOUTH, - SC7180_SLAVE_AHB2PHY_CENTER, - SC7180_SLAVE_AOP, - SC7180_SLAVE_AOSS, - SC7180_SLAVE_BOOT_ROM, - SC7180_SLAVE_CAMERA_CFG, - SC7180_SLAVE_CAMERA_NRT_THROTTLE_CFG, - SC7180_SLAVE_CAMERA_RT_THROTTLE_CFG, - SC7180_SLAVE_CLK_CTL, - SC7180_SLAVE_RBCPR_CX_CFG, - SC7180_SLAVE_RBCPR_MX_CFG, - SC7180_SLAVE_CRYPTO_0_CFG, - SC7180_SLAVE_DCC_CFG, - SC7180_SLAVE_CNOC_DDRSS, - SC7180_SLAVE_DISPLAY_CFG, - SC7180_SLAVE_DISPLAY_RT_THROTTLE_CFG, - SC7180_SLAVE_DISPLAY_THROTTLE_CFG, - SC7180_SLAVE_EMMC_CFG, - SC7180_SLAVE_GLM, - SC7180_SLAVE_GFX3D_CFG, - SC7180_SLAVE_IMEM_CFG, - SC7180_SLAVE_IPA_CFG, - SC7180_SLAVE_CNOC_MNOC_CFG, - SC7180_SLAVE_CNOC_MSS, - SC7180_SLAVE_NPU_CFG, - SC7180_SLAVE_NPU_DMA_BWMON_CFG, - SC7180_SLAVE_NPU_PROC_BWMON_CFG, - SC7180_SLAVE_PDM, - SC7180_SLAVE_PIMEM_CFG, - SC7180_SLAVE_PRNG, - SC7180_SLAVE_QDSS_CFG, - SC7180_SLAVE_QM_CFG, - SC7180_SLAVE_QM_MPU_CFG, - SC7180_SLAVE_QSPI_0, - SC7180_SLAVE_QUP_0, - SC7180_SLAVE_QUP_1, - SC7180_SLAVE_SDCC_2, - SC7180_SLAVE_SECURITY, - SC7180_SLAVE_SNOC_CFG, - SC7180_SLAVE_TCSR, - SC7180_SLAVE_TLMM_WEST, - SC7180_SLAVE_TLMM_NORTH, - SC7180_SLAVE_TLMM_SOUTH, - SC7180_SLAVE_UFS_MEM_CFG, - SC7180_SLAVE_USB3, - SC7180_SLAVE_VENUS_CFG, - SC7180_SLAVE_VENUS_THROTTLE_CFG, - SC7180_SLAVE_VSENSE_CTRL_CFG, - SC7180_SLAVE_SERVICE_CNOC - }, + .link_nodes =3D { &qhs_a1_noc_cfg, + &qhs_a2_noc_cfg, + &qhs_ahb2phy0, + &qhs_ahb2phy2, + &qhs_aop, + &qhs_aoss, + &qhs_boot_rom, + &qhs_camera_cfg, + &qhs_camera_nrt_throttle_cfg, + &qhs_camera_rt_throttle_cfg, + &qhs_clk_ctl, + &qhs_cpr_cx, + &qhs_cpr_mx, + &qhs_crypto0_cfg, + &qhs_dcc_cfg, + &qhs_ddrss_cfg, + &qhs_display_cfg, + &qhs_display_rt_throttle_cfg, + &qhs_display_throttle_cfg, + &qhs_emmc_cfg, + &qhs_glm, + &qhs_gpuss_cfg, + &qhs_imem_cfg, + &qhs_ipa, + &qhs_mnoc_cfg, + &qhs_mss_cfg, + &qhs_npu_cfg, + &qhs_npu_dma_throttle_cfg, + &qhs_npu_dsp_throttle_cfg, + &qhs_pdm, + &qhs_pimem_cfg, + &qhs_prng, + &qhs_qdss_cfg, + &qhs_qm_cfg, + &qhs_qm_mpu_cfg, + &qhs_qspi, + &qhs_qup0, + &qhs_qup1, + &qhs_sdc2, + &qhs_security, + &qhs_snoc_cfg, + &qhs_tcsr, + &qhs_tlmm_1, + &qhs_tlmm_2, + &qhs_tlmm_3, + &qhs_ufs_mem_cfg, + &qhs_usb3, + &qhs_venus_cfg, + &qhs_venus_throttle_cfg, + &qhs_vsense_ctrl_cfg, + &srvc_cnoc }, }; =20 static struct qcom_icc_node qhm_cnoc_dc_noc =3D { .name =3D "qhm_cnoc_dc_noc", - .id =3D SC7180_MASTER_CNOC_DC_NOC, .channels =3D 1, .buswidth =3D 4, .num_links =3D 2, - .links =3D { SC7180_SLAVE_GEM_NOC_CFG, - SC7180_SLAVE_LLCC_CFG - }, + .link_nodes =3D { &qhs_gemnoc, + &qhs_llcc }, }; =20 static struct qcom_icc_node acm_apps0 =3D { .name =3D "acm_apps0", - .id =3D SC7180_MASTER_APPSS_PROC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 2, - .links =3D { SC7180_SLAVE_GEM_NOC_SNOC, - SC7180_SLAVE_LLCC - }, + .link_nodes =3D { &qns_gem_noc_snoc, + &qns_llcc }, }; =20 static struct qcom_icc_node acm_sys_tcu =3D { .name =3D "acm_sys_tcu", - .id =3D SC7180_MASTER_SYS_TCU, .channels =3D 1, .buswidth =3D 8, .num_links =3D 2, - .links =3D { SC7180_SLAVE_GEM_NOC_SNOC, - SC7180_SLAVE_LLCC - }, + .link_nodes =3D { &qns_gem_noc_snoc, + &qns_llcc }, }; =20 static struct qcom_icc_node qhm_gemnoc_cfg =3D { .name =3D "qhm_gemnoc_cfg", - .id =3D SC7180_MASTER_GEM_NOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 2, - .links =3D { SC7180_SLAVE_MSS_PROC_MS_MPU_CFG, - SC7180_SLAVE_SERVICE_GEM_NOC - }, + .link_nodes =3D { &qhs_mdsp_ms_mpu_cfg, + &srvc_gemnoc }, }; =20 static struct qcom_icc_node qnm_cmpnoc =3D { .name =3D "qnm_cmpnoc", - .id =3D SC7180_MASTER_COMPUTE_NOC, .channels =3D 1, .buswidth =3D 32, .num_links =3D 2, - .links =3D { SC7180_SLAVE_GEM_NOC_SNOC, - SC7180_SLAVE_LLCC - }, + .link_nodes =3D { &qns_gem_noc_snoc, + &qns_llcc }, }; =20 static struct qcom_icc_node qnm_mnoc_hf =3D { .name =3D "qnm_mnoc_hf", - .id =3D SC7180_MASTER_MNOC_HF_MEM_NOC, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SC7180_SLAVE_LLCC }, + .link_nodes =3D { &qns_llcc }, }; =20 static struct qcom_icc_node qnm_mnoc_sf =3D { .name =3D "qnm_mnoc_sf", - .id =3D SC7180_MASTER_MNOC_SF_MEM_NOC, .channels =3D 1, .buswidth =3D 32, .num_links =3D 2, - .links =3D { SC7180_SLAVE_GEM_NOC_SNOC, - SC7180_SLAVE_LLCC - }, + .link_nodes =3D { &qns_gem_noc_snoc, + &qns_llcc }, }; =20 static struct qcom_icc_node qnm_snoc_gc =3D { .name =3D "qnm_snoc_gc", - .id =3D SC7180_MASTER_SNOC_GC_MEM_NOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SC7180_SLAVE_LLCC }, + .link_nodes =3D { &qns_llcc }, }; =20 static struct qcom_icc_node qnm_snoc_sf =3D { .name =3D "qnm_snoc_sf", - .id =3D SC7180_MASTER_SNOC_SF_MEM_NOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SC7180_SLAVE_LLCC }, + .link_nodes =3D { &qns_llcc }, }; =20 static struct qcom_icc_node qxm_gpu =3D { .name =3D "qxm_gpu", - .id =3D SC7180_MASTER_GFX3D, .channels =3D 2, .buswidth =3D 32, .num_links =3D 2, - .links =3D { SC7180_SLAVE_GEM_NOC_SNOC, - SC7180_SLAVE_LLCC - }, + .link_nodes =3D { &qns_gem_noc_snoc, + &qns_llcc }, }; =20 static struct qcom_icc_node llcc_mc =3D { .name =3D "llcc_mc", - .id =3D SC7180_MASTER_LLCC, .channels =3D 2, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SC7180_SLAVE_EBI1 }, + .link_nodes =3D { &ebi }, }; =20 static struct qcom_icc_node qhm_mnoc_cfg =3D { .name =3D "qhm_mnoc_cfg", - .id =3D SC7180_MASTER_CNOC_MNOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SC7180_SLAVE_SERVICE_MNOC }, + .link_nodes =3D { &srvc_mnoc }, }; =20 static struct qcom_icc_node qxm_camnoc_hf0 =3D { .name =3D "qxm_camnoc_hf0", - .id =3D SC7180_MASTER_CAMNOC_HF0, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SC7180_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_hf }, }; =20 static struct qcom_icc_node qxm_camnoc_hf1 =3D { .name =3D "qxm_camnoc_hf1", - .id =3D SC7180_MASTER_CAMNOC_HF1, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SC7180_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_hf }, }; =20 static struct qcom_icc_node qxm_camnoc_sf =3D { .name =3D "qxm_camnoc_sf", - .id =3D SC7180_MASTER_CAMNOC_SF, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SC7180_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static struct qcom_icc_node qxm_mdp0 =3D { .name =3D "qxm_mdp0", - .id =3D SC7180_MASTER_MDP0, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SC7180_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_hf }, }; =20 static struct qcom_icc_node qxm_rot =3D { .name =3D "qxm_rot", - .id =3D SC7180_MASTER_ROTATOR, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SC7180_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static struct qcom_icc_node qxm_venus0 =3D { .name =3D "qxm_venus0", - .id =3D SC7180_MASTER_VIDEO_P0, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SC7180_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static struct qcom_icc_node qxm_venus_arm9 =3D { .name =3D "qxm_venus_arm9", - .id =3D SC7180_MASTER_VIDEO_PROC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SC7180_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static struct qcom_icc_node amm_npu_sys =3D { .name =3D "amm_npu_sys", - .id =3D SC7180_MASTER_NPU_SYS, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SC7180_SLAVE_NPU_COMPUTE_NOC }, + .link_nodes =3D { &qns_npu_sys }, }; =20 static struct qcom_icc_node qhm_npu_cfg =3D { .name =3D "qhm_npu_cfg", - .id =3D SC7180_MASTER_NPU_NOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 8, - .links =3D { SC7180_SLAVE_NPU_CAL_DP0, - SC7180_SLAVE_NPU_CP, - SC7180_SLAVE_NPU_INT_DMA_BWMON_CFG, - SC7180_SLAVE_NPU_DPM, - SC7180_SLAVE_ISENSE_CFG, - SC7180_SLAVE_NPU_LLM_CFG, - SC7180_SLAVE_NPU_TCM, - SC7180_SLAVE_SERVICE_NPU_NOC - }, + .link_nodes =3D { &qhs_cal_dp0, + &qhs_cp, + &qhs_dma_bwmon, + &qhs_dpm, + &qhs_isense, + &qhs_llm, + &qhs_tcm, + &srvc_noc }, }; =20 static struct qcom_icc_node qup_core_master_1 =3D { .name =3D "qup_core_master_1", - .id =3D SC7180_MASTER_QUP_CORE_0, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SC7180_SLAVE_QUP_CORE_0 }, + .link_nodes =3D { &qup_core_slave_1 }, }; =20 static struct qcom_icc_node qup_core_master_2 =3D { .name =3D "qup_core_master_2", - .id =3D SC7180_MASTER_QUP_CORE_1, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SC7180_SLAVE_QUP_CORE_1 }, + .link_nodes =3D { &qup_core_slave_2 }, }; =20 static struct qcom_icc_node qhm_snoc_cfg =3D { .name =3D "qhm_snoc_cfg", - .id =3D SC7180_MASTER_SNOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SC7180_SLAVE_SERVICE_SNOC }, + .link_nodes =3D { &srvc_snoc }, }; =20 static struct qcom_icc_node qnm_aggre1_noc =3D { .name =3D "qnm_aggre1_noc", - .id =3D SC7180_MASTER_A1NOC_SNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 6, - .links =3D { SC7180_SLAVE_APPSS, - SC7180_SLAVE_SNOC_CNOC, - SC7180_SLAVE_SNOC_GEM_NOC_SF, - SC7180_SLAVE_IMEM, - SC7180_SLAVE_PIMEM, - SC7180_SLAVE_QDSS_STM - }, + .link_nodes =3D { &qhs_apss, + &qns_cnoc, + &qns_gemnoc_sf, + &qxs_imem, + &qxs_pimem, + &xs_qdss_stm }, }; =20 static struct qcom_icc_node qnm_aggre2_noc =3D { .name =3D "qnm_aggre2_noc", - .id =3D SC7180_MASTER_A2NOC_SNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 7, - .links =3D { SC7180_SLAVE_APPSS, - SC7180_SLAVE_SNOC_CNOC, - SC7180_SLAVE_SNOC_GEM_NOC_SF, - SC7180_SLAVE_IMEM, - SC7180_SLAVE_PIMEM, - SC7180_SLAVE_QDSS_STM, - SC7180_SLAVE_TCU - }, + .link_nodes =3D { &qhs_apss, + &qns_cnoc, + &qns_gemnoc_sf, + &qxs_imem, + &qxs_pimem, + &xs_qdss_stm, + &xs_sys_tcu_cfg }, }; =20 static struct qcom_icc_node qnm_gemnoc =3D { .name =3D "qnm_gemnoc", - .id =3D SC7180_MASTER_GEM_NOC_SNOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 6, - .links =3D { SC7180_SLAVE_APPSS, - SC7180_SLAVE_SNOC_CNOC, - SC7180_SLAVE_IMEM, - SC7180_SLAVE_PIMEM, - SC7180_SLAVE_QDSS_STM, - SC7180_SLAVE_TCU - }, + .link_nodes =3D { &qhs_apss, + &qns_cnoc, + &qxs_imem, + &qxs_pimem, + &xs_qdss_stm, + &xs_sys_tcu_cfg }, }; =20 static struct qcom_icc_node qxm_pimem =3D { .name =3D "qxm_pimem", - .id =3D SC7180_MASTER_PIMEM, .channels =3D 1, .buswidth =3D 8, .num_links =3D 2, - .links =3D { SC7180_SLAVE_SNOC_GEM_NOC_GC, - SC7180_SLAVE_IMEM - }, + .link_nodes =3D { &qns_gemnoc_gc, + &qxs_imem }, }; =20 static struct qcom_icc_node qns_a1noc_snoc =3D { .name =3D "qns_a1noc_snoc", - .id =3D SC7180_SLAVE_A1NOC_SNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SC7180_MASTER_A1NOC_SNOC }, + .link_nodes =3D { &qnm_aggre1_noc }, }; =20 static struct qcom_icc_node srvc_aggre1_noc =3D { .name =3D "srvc_aggre1_noc", - .id =3D SC7180_SLAVE_SERVICE_A1NOC, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qns_a2noc_snoc =3D { .name =3D "qns_a2noc_snoc", - .id =3D SC7180_SLAVE_A2NOC_SNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SC7180_MASTER_A2NOC_SNOC }, + .link_nodes =3D { &qnm_aggre2_noc }, }; =20 static struct qcom_icc_node srvc_aggre2_noc =3D { .name =3D "srvc_aggre2_noc", - .id =3D SC7180_SLAVE_SERVICE_A2NOC, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qns_camnoc_uncomp =3D { .name =3D "qns_camnoc_uncomp", - .id =3D SC7180_SLAVE_CAMNOC_UNCOMP, .channels =3D 1, .buswidth =3D 32, }; =20 static struct qcom_icc_node qns_cdsp_gemnoc =3D { .name =3D "qns_cdsp_gemnoc", - .id =3D SC7180_SLAVE_CDSP_GEM_NOC, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SC7180_MASTER_COMPUTE_NOC }, + .link_nodes =3D { &qnm_cmpnoc }, }; =20 static struct qcom_icc_node qhs_a1_noc_cfg =3D { .name =3D "qhs_a1_noc_cfg", - .id =3D SC7180_SLAVE_A1NOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SC7180_MASTER_A1NOC_CFG }, + .link_nodes =3D { &qhm_a1noc_cfg }, }; =20 static struct qcom_icc_node qhs_a2_noc_cfg =3D { .name =3D "qhs_a2_noc_cfg", - .id =3D SC7180_SLAVE_A2NOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SC7180_MASTER_A2NOC_CFG }, + .link_nodes =3D { &qhm_a2noc_cfg }, }; =20 static struct qcom_icc_node qhs_ahb2phy0 =3D { .name =3D "qhs_ahb2phy0", - .id =3D SC7180_SLAVE_AHB2PHY_SOUTH, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_ahb2phy2 =3D { .name =3D "qhs_ahb2phy2", - .id =3D SC7180_SLAVE_AHB2PHY_CENTER, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_aop =3D { .name =3D "qhs_aop", - .id =3D SC7180_SLAVE_AOP, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_aoss =3D { .name =3D "qhs_aoss", - .id =3D SC7180_SLAVE_AOSS, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_boot_rom =3D { .name =3D "qhs_boot_rom", - .id =3D SC7180_SLAVE_BOOT_ROM, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_camera_cfg =3D { .name =3D "qhs_camera_cfg", - .id =3D SC7180_SLAVE_CAMERA_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_camera_nrt_throttle_cfg =3D { .name =3D "qhs_camera_nrt_throttle_cfg", - .id =3D SC7180_SLAVE_CAMERA_NRT_THROTTLE_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_camera_rt_throttle_cfg =3D { .name =3D "qhs_camera_rt_throttle_cfg", - .id =3D SC7180_SLAVE_CAMERA_RT_THROTTLE_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_clk_ctl =3D { .name =3D "qhs_clk_ctl", - .id =3D SC7180_SLAVE_CLK_CTL, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_cpr_cx =3D { .name =3D "qhs_cpr_cx", - .id =3D SC7180_SLAVE_RBCPR_CX_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_cpr_mx =3D { .name =3D "qhs_cpr_mx", - .id =3D SC7180_SLAVE_RBCPR_MX_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_crypto0_cfg =3D { .name =3D "qhs_crypto0_cfg", - .id =3D SC7180_SLAVE_CRYPTO_0_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_dcc_cfg =3D { .name =3D "qhs_dcc_cfg", - .id =3D SC7180_SLAVE_DCC_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_ddrss_cfg =3D { .name =3D "qhs_ddrss_cfg", - .id =3D SC7180_SLAVE_CNOC_DDRSS, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SC7180_MASTER_CNOC_DC_NOC }, + .link_nodes =3D { &qhm_cnoc_dc_noc }, }; =20 static struct qcom_icc_node qhs_display_cfg =3D { .name =3D "qhs_display_cfg", - .id =3D SC7180_SLAVE_DISPLAY_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_display_rt_throttle_cfg =3D { .name =3D "qhs_display_rt_throttle_cfg", - .id =3D SC7180_SLAVE_DISPLAY_RT_THROTTLE_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_display_throttle_cfg =3D { .name =3D "qhs_display_throttle_cfg", - .id =3D SC7180_SLAVE_DISPLAY_THROTTLE_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_emmc_cfg =3D { .name =3D "qhs_emmc_cfg", - .id =3D SC7180_SLAVE_EMMC_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_glm =3D { .name =3D "qhs_glm", - .id =3D SC7180_SLAVE_GLM, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_gpuss_cfg =3D { .name =3D "qhs_gpuss_cfg", - .id =3D SC7180_SLAVE_GFX3D_CFG, .channels =3D 1, .buswidth =3D 8, }; =20 static struct qcom_icc_node qhs_imem_cfg =3D { .name =3D "qhs_imem_cfg", - .id =3D SC7180_SLAVE_IMEM_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_ipa =3D { .name =3D "qhs_ipa", - .id =3D SC7180_SLAVE_IPA_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_mnoc_cfg =3D { .name =3D "qhs_mnoc_cfg", - .id =3D SC7180_SLAVE_CNOC_MNOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SC7180_MASTER_CNOC_MNOC_CFG }, + .link_nodes =3D { &qhm_mnoc_cfg }, }; =20 static struct qcom_icc_node qhs_mss_cfg =3D { .name =3D "qhs_mss_cfg", - .id =3D SC7180_SLAVE_CNOC_MSS, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_npu_cfg =3D { .name =3D "qhs_npu_cfg", - .id =3D SC7180_SLAVE_NPU_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SC7180_MASTER_NPU_NOC_CFG }, + .link_nodes =3D { &qhm_npu_cfg }, }; =20 static struct qcom_icc_node qhs_npu_dma_throttle_cfg =3D { .name =3D "qhs_npu_dma_throttle_cfg", - .id =3D SC7180_SLAVE_NPU_DMA_BWMON_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_npu_dsp_throttle_cfg =3D { .name =3D "qhs_npu_dsp_throttle_cfg", - .id =3D SC7180_SLAVE_NPU_PROC_BWMON_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_pdm =3D { .name =3D "qhs_pdm", - .id =3D SC7180_SLAVE_PDM, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_pimem_cfg =3D { .name =3D "qhs_pimem_cfg", - .id =3D SC7180_SLAVE_PIMEM_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_prng =3D { .name =3D "qhs_prng", - .id =3D SC7180_SLAVE_PRNG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_qdss_cfg =3D { .name =3D "qhs_qdss_cfg", - .id =3D SC7180_SLAVE_QDSS_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_qm_cfg =3D { .name =3D "qhs_qm_cfg", - .id =3D SC7180_SLAVE_QM_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_qm_mpu_cfg =3D { .name =3D "qhs_qm_mpu_cfg", - .id =3D SC7180_SLAVE_QM_MPU_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_qspi =3D { .name =3D "qhs_qspi", - .id =3D SC7180_SLAVE_QSPI_0, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_qup0 =3D { .name =3D "qhs_qup0", - .id =3D SC7180_SLAVE_QUP_0, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_qup1 =3D { .name =3D "qhs_qup1", - .id =3D SC7180_SLAVE_QUP_1, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_sdc2 =3D { .name =3D "qhs_sdc2", - .id =3D SC7180_SLAVE_SDCC_2, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_security =3D { .name =3D "qhs_security", - .id =3D SC7180_SLAVE_SECURITY, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_snoc_cfg =3D { .name =3D "qhs_snoc_cfg", - .id =3D SC7180_SLAVE_SNOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SC7180_MASTER_SNOC_CFG }, + .link_nodes =3D { &qhm_snoc_cfg }, }; =20 static struct qcom_icc_node qhs_tcsr =3D { .name =3D "qhs_tcsr", - .id =3D SC7180_SLAVE_TCSR, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_tlmm_1 =3D { .name =3D "qhs_tlmm_1", - .id =3D SC7180_SLAVE_TLMM_WEST, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_tlmm_2 =3D { .name =3D "qhs_tlmm_2", - .id =3D SC7180_SLAVE_TLMM_NORTH, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_tlmm_3 =3D { .name =3D "qhs_tlmm_3", - .id =3D SC7180_SLAVE_TLMM_SOUTH, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_ufs_mem_cfg =3D { .name =3D "qhs_ufs_mem_cfg", - .id =3D SC7180_SLAVE_UFS_MEM_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_usb3 =3D { .name =3D "qhs_usb3", - .id =3D SC7180_SLAVE_USB3, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_venus_cfg =3D { .name =3D "qhs_venus_cfg", - .id =3D SC7180_SLAVE_VENUS_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_venus_throttle_cfg =3D { .name =3D "qhs_venus_throttle_cfg", - .id =3D SC7180_SLAVE_VENUS_THROTTLE_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_vsense_ctrl_cfg =3D { .name =3D "qhs_vsense_ctrl_cfg", - .id =3D SC7180_SLAVE_VSENSE_CTRL_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node srvc_cnoc =3D { .name =3D "srvc_cnoc", - .id =3D SC7180_SLAVE_SERVICE_CNOC, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_gemnoc =3D { .name =3D "qhs_gemnoc", - .id =3D SC7180_SLAVE_GEM_NOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SC7180_MASTER_GEM_NOC_CFG }, + .link_nodes =3D { &qhm_gemnoc_cfg }, }; =20 static struct qcom_icc_node qhs_llcc =3D { .name =3D "qhs_llcc", - .id =3D SC7180_SLAVE_LLCC_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg =3D { .name =3D "qhs_mdsp_ms_mpu_cfg", - .id =3D SC7180_SLAVE_MSS_PROC_MS_MPU_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qns_gem_noc_snoc =3D { .name =3D "qns_gem_noc_snoc", - .id =3D SC7180_SLAVE_GEM_NOC_SNOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SC7180_MASTER_GEM_NOC_SNOC }, + .link_nodes =3D { &qnm_gemnoc }, }; =20 static struct qcom_icc_node qns_llcc =3D { .name =3D "qns_llcc", - .id =3D SC7180_SLAVE_LLCC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SC7180_MASTER_LLCC }, + .link_nodes =3D { &llcc_mc }, }; =20 static struct qcom_icc_node srvc_gemnoc =3D { .name =3D "srvc_gemnoc", - .id =3D SC7180_SLAVE_SERVICE_GEM_NOC, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node ebi =3D { .name =3D "ebi", - .id =3D SC7180_SLAVE_EBI1, .channels =3D 2, .buswidth =3D 4, }; =20 static struct qcom_icc_node qns_mem_noc_hf =3D { .name =3D "qns_mem_noc_hf", - .id =3D SC7180_SLAVE_MNOC_HF_MEM_NOC, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SC7180_MASTER_MNOC_HF_MEM_NOC }, + .link_nodes =3D { &qnm_mnoc_hf }, }; =20 static struct qcom_icc_node qns_mem_noc_sf =3D { .name =3D "qns_mem_noc_sf", - .id =3D SC7180_SLAVE_MNOC_SF_MEM_NOC, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SC7180_MASTER_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qnm_mnoc_sf }, }; =20 static struct qcom_icc_node srvc_mnoc =3D { .name =3D "srvc_mnoc", - .id =3D SC7180_SLAVE_SERVICE_MNOC, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_cal_dp0 =3D { .name =3D "qhs_cal_dp0", - .id =3D SC7180_SLAVE_NPU_CAL_DP0, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_cp =3D { .name =3D "qhs_cp", - .id =3D SC7180_SLAVE_NPU_CP, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_dma_bwmon =3D { .name =3D "qhs_dma_bwmon", - .id =3D SC7180_SLAVE_NPU_INT_DMA_BWMON_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_dpm =3D { .name =3D "qhs_dpm", - .id =3D SC7180_SLAVE_NPU_DPM, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_isense =3D { .name =3D "qhs_isense", - .id =3D SC7180_SLAVE_ISENSE_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_llm =3D { .name =3D "qhs_llm", - .id =3D SC7180_SLAVE_NPU_LLM_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_tcm =3D { .name =3D "qhs_tcm", - .id =3D SC7180_SLAVE_NPU_TCM, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qns_npu_sys =3D { .name =3D "qns_npu_sys", - .id =3D SC7180_SLAVE_NPU_COMPUTE_NOC, .channels =3D 2, .buswidth =3D 32, }; =20 static struct qcom_icc_node srvc_noc =3D { .name =3D "srvc_noc", - .id =3D SC7180_SLAVE_SERVICE_NPU_NOC, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qup_core_slave_1 =3D { .name =3D "qup_core_slave_1", - .id =3D SC7180_SLAVE_QUP_CORE_0, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qup_core_slave_2 =3D { .name =3D "qup_core_slave_2", - .id =3D SC7180_SLAVE_QUP_CORE_1, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_apss =3D { .name =3D "qhs_apss", - .id =3D SC7180_SLAVE_APPSS, .channels =3D 1, .buswidth =3D 8, }; =20 static struct qcom_icc_node qns_cnoc =3D { .name =3D "qns_cnoc", - .id =3D SC7180_SLAVE_SNOC_CNOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SC7180_MASTER_SNOC_CNOC }, + .link_nodes =3D { &qnm_snoc }, }; =20 static struct qcom_icc_node qns_gemnoc_gc =3D { .name =3D "qns_gemnoc_gc", - .id =3D SC7180_SLAVE_SNOC_GEM_NOC_GC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SC7180_MASTER_SNOC_GC_MEM_NOC }, + .link_nodes =3D { &qnm_snoc_gc }, }; =20 static struct qcom_icc_node qns_gemnoc_sf =3D { .name =3D "qns_gemnoc_sf", - .id =3D SC7180_SLAVE_SNOC_GEM_NOC_SF, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SC7180_MASTER_SNOC_SF_MEM_NOC }, + .link_nodes =3D { &qnm_snoc_sf }, }; =20 static struct qcom_icc_node qxs_imem =3D { .name =3D "qxs_imem", - .id =3D SC7180_SLAVE_IMEM, .channels =3D 1, .buswidth =3D 8, }; =20 static struct qcom_icc_node qxs_pimem =3D { .name =3D "qxs_pimem", - .id =3D SC7180_SLAVE_PIMEM, .channels =3D 1, .buswidth =3D 8, }; =20 static struct qcom_icc_node srvc_snoc =3D { .name =3D "srvc_snoc", - .id =3D SC7180_SLAVE_SERVICE_SNOC, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node xs_qdss_stm =3D { .name =3D "xs_qdss_stm", - .id =3D SC7180_SLAVE_QDSS_STM, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node xs_sys_tcu_cfg =3D { .name =3D "xs_sys_tcu_cfg", - .id =3D SC7180_SLAVE_TCU, .channels =3D 1, .buswidth =3D 8, }; @@ -1485,6 +1471,7 @@ static struct qcom_icc_node * const aggre1_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sc7180_aggre1_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D aggre1_noc_nodes, .num_nodes =3D ARRAY_SIZE(aggre1_noc_nodes), .bcms =3D aggre1_noc_bcms, @@ -1508,6 +1495,7 @@ static struct qcom_icc_node * const aggre2_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sc7180_aggre2_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D aggre2_noc_nodes, .num_nodes =3D ARRAY_SIZE(aggre2_noc_nodes), .bcms =3D aggre2_noc_bcms, @@ -1526,6 +1514,7 @@ static struct qcom_icc_node * const camnoc_virt_nodes= [] =3D { }; =20 static const struct qcom_icc_desc sc7180_camnoc_virt =3D { + .alloc_dyn_id =3D true, .nodes =3D camnoc_virt_nodes, .num_nodes =3D ARRAY_SIZE(camnoc_virt_nodes), .bcms =3D camnoc_virt_bcms, @@ -1545,6 +1534,7 @@ static struct qcom_icc_node * const compute_noc_nodes= [] =3D { }; =20 static const struct qcom_icc_desc sc7180_compute_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D compute_noc_nodes, .num_nodes =3D ARRAY_SIZE(compute_noc_nodes), .bcms =3D compute_noc_bcms, @@ -1613,6 +1603,7 @@ static struct qcom_icc_node * const config_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sc7180_config_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D config_noc_nodes, .num_nodes =3D ARRAY_SIZE(config_noc_nodes), .bcms =3D config_noc_bcms, @@ -1626,6 +1617,7 @@ static struct qcom_icc_node * const dc_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sc7180_dc_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D dc_noc_nodes, .num_nodes =3D ARRAY_SIZE(dc_noc_nodes), }; @@ -1654,6 +1646,7 @@ static struct qcom_icc_node * const gem_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sc7180_gem_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D gem_noc_nodes, .num_nodes =3D ARRAY_SIZE(gem_noc_nodes), .bcms =3D gem_noc_bcms, @@ -1671,6 +1664,7 @@ static struct qcom_icc_node * const mc_virt_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sc7180_mc_virt =3D { + .alloc_dyn_id =3D true, .nodes =3D mc_virt_nodes, .num_nodes =3D ARRAY_SIZE(mc_virt_nodes), .bcms =3D mc_virt_bcms, @@ -1698,6 +1692,7 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sc7180_mmss_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D mmss_noc_nodes, .num_nodes =3D ARRAY_SIZE(mmss_noc_nodes), .bcms =3D mmss_noc_bcms, @@ -1719,6 +1714,7 @@ static struct qcom_icc_node * const npu_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sc7180_npu_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D npu_noc_nodes, .num_nodes =3D ARRAY_SIZE(npu_noc_nodes), }; @@ -1735,6 +1731,7 @@ static struct qcom_icc_node * const qup_virt_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sc7180_qup_virt =3D { + .alloc_dyn_id =3D true, .nodes =3D qup_virt_nodes, .num_nodes =3D ARRAY_SIZE(qup_virt_nodes), .bcms =3D qup_virt_bcms, @@ -1770,6 +1767,7 @@ static struct qcom_icc_node * const system_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sc7180_system_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D system_noc_nodes, .num_nodes =3D ARRAY_SIZE(system_noc_nodes), .bcms =3D system_noc_bcms, diff --git a/drivers/interconnect/qcom/sc7180.h b/drivers/interconnect/qcom= /sc7180.h deleted file mode 100644 index 2b718922c10903fbb4f127e9b1d15f99f385c5c5..000000000000000000000000000= 0000000000000 --- a/drivers/interconnect/qcom/sc7180.h +++ /dev/null @@ -1,149 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Qualcomm #define SC7180 interconnect IDs - * - * Copyright (c) 2020, The Linux Foundation. All rights reserved. - */ - -#ifndef __DRIVERS_INTERCONNECT_QCOM_SC7180_H -#define __DRIVERS_INTERCONNECT_QCOM_SC7180_H - -#define SC7180_MASTER_APPSS_PROC 0 -#define SC7180_MASTER_SYS_TCU 1 -#define SC7180_MASTER_NPU_SYS 2 -/* 3 was used by MASTER_IPA_CORE, now represented as RPMh clock */ -#define SC7180_MASTER_LLCC 4 -#define SC7180_MASTER_A1NOC_CFG 5 -#define SC7180_MASTER_A2NOC_CFG 6 -#define SC7180_MASTER_CNOC_DC_NOC 7 -#define SC7180_MASTER_GEM_NOC_CFG 8 -#define SC7180_MASTER_CNOC_MNOC_CFG 9 -#define SC7180_MASTER_NPU_NOC_CFG 10 -#define SC7180_MASTER_QDSS_BAM 11 -#define SC7180_MASTER_QSPI 12 -#define SC7180_MASTER_QUP_0 13 -#define SC7180_MASTER_QUP_1 14 -#define SC7180_MASTER_SNOC_CFG 15 -#define SC7180_MASTER_A1NOC_SNOC 16 -#define SC7180_MASTER_A2NOC_SNOC 17 -#define SC7180_MASTER_COMPUTE_NOC 18 -#define SC7180_MASTER_GEM_NOC_SNOC 19 -#define SC7180_MASTER_MNOC_HF_MEM_NOC 20 -#define SC7180_MASTER_MNOC_SF_MEM_NOC 21 -#define SC7180_MASTER_NPU 22 -#define SC7180_MASTER_SNOC_CNOC 23 -#define SC7180_MASTER_SNOC_GC_MEM_NOC 24 -#define SC7180_MASTER_SNOC_SF_MEM_NOC 25 -#define SC7180_MASTER_QUP_CORE_0 26 -#define SC7180_MASTER_QUP_CORE_1 27 -#define SC7180_MASTER_CAMNOC_HF0 28 -#define SC7180_MASTER_CAMNOC_HF1 29 -#define SC7180_MASTER_CAMNOC_HF0_UNCOMP 30 -#define SC7180_MASTER_CAMNOC_HF1_UNCOMP 31 -#define SC7180_MASTER_CAMNOC_SF 32 -#define SC7180_MASTER_CAMNOC_SF_UNCOMP 33 -#define SC7180_MASTER_CRYPTO 34 -#define SC7180_MASTER_GFX3D 35 -#define SC7180_MASTER_IPA 36 -#define SC7180_MASTER_MDP0 37 -#define SC7180_MASTER_NPU_PROC 38 -#define SC7180_MASTER_PIMEM 39 -#define SC7180_MASTER_ROTATOR 40 -#define SC7180_MASTER_VIDEO_P0 41 -#define SC7180_MASTER_VIDEO_PROC 42 -#define SC7180_MASTER_QDSS_DAP 43 -#define SC7180_MASTER_QDSS_ETR 44 -#define SC7180_MASTER_SDCC_2 45 -#define SC7180_MASTER_UFS_MEM 46 -#define SC7180_MASTER_USB3 47 -#define SC7180_MASTER_EMMC 48 -#define SC7180_SLAVE_EBI1 49 -/* 50 was used by SLAVE_IPA_CORE, now represented as RPMh clock */ -#define SC7180_SLAVE_A1NOC_CFG 51 -#define SC7180_SLAVE_A2NOC_CFG 52 -#define SC7180_SLAVE_AHB2PHY_SOUTH 53 -#define SC7180_SLAVE_AHB2PHY_CENTER 54 -#define SC7180_SLAVE_AOP 55 -#define SC7180_SLAVE_AOSS 56 -#define SC7180_SLAVE_APPSS 57 -#define SC7180_SLAVE_BOOT_ROM 58 -#define SC7180_SLAVE_NPU_CAL_DP0 59 -#define SC7180_SLAVE_CAMERA_CFG 60 -#define SC7180_SLAVE_CAMERA_NRT_THROTTLE_CFG 61 -#define SC7180_SLAVE_CAMERA_RT_THROTTLE_CFG 62 -#define SC7180_SLAVE_CLK_CTL 63 -#define SC7180_SLAVE_NPU_CP 64 -#define SC7180_SLAVE_RBCPR_CX_CFG 65 -#define SC7180_SLAVE_RBCPR_MX_CFG 66 -#define SC7180_SLAVE_CRYPTO_0_CFG 67 -#define SC7180_SLAVE_DCC_CFG 68 -#define SC7180_SLAVE_CNOC_DDRSS 69 -#define SC7180_SLAVE_DISPLAY_CFG 70 -#define SC7180_SLAVE_DISPLAY_RT_THROTTLE_CFG 71 -#define SC7180_SLAVE_DISPLAY_THROTTLE_CFG 72 -#define SC7180_SLAVE_NPU_INT_DMA_BWMON_CFG 73 -#define SC7180_SLAVE_NPU_DPM 74 -#define SC7180_SLAVE_EMMC_CFG 75 -#define SC7180_SLAVE_GEM_NOC_CFG 76 -#define SC7180_SLAVE_GLM 77 -#define SC7180_SLAVE_GFX3D_CFG 78 -#define SC7180_SLAVE_IMEM_CFG 79 -#define SC7180_SLAVE_IPA_CFG 80 -#define SC7180_SLAVE_ISENSE_CFG 81 -#define SC7180_SLAVE_LLCC_CFG 82 -#define SC7180_SLAVE_NPU_LLM_CFG 83 -#define SC7180_SLAVE_MSS_PROC_MS_MPU_CFG 84 -#define SC7180_SLAVE_CNOC_MNOC_CFG 85 -#define SC7180_SLAVE_CNOC_MSS 86 -#define SC7180_SLAVE_NPU_CFG 87 -#define SC7180_SLAVE_NPU_DMA_BWMON_CFG 88 -#define SC7180_SLAVE_NPU_PROC_BWMON_CFG 89 -#define SC7180_SLAVE_PDM 90 -#define SC7180_SLAVE_PIMEM_CFG 91 -#define SC7180_SLAVE_PRNG 92 -#define SC7180_SLAVE_QDSS_CFG 93 -#define SC7180_SLAVE_QM_CFG 94 -#define SC7180_SLAVE_QM_MPU_CFG 95 -#define SC7180_SLAVE_QSPI_0 96 -#define SC7180_SLAVE_QUP_0 97 -#define SC7180_SLAVE_QUP_1 98 -#define SC7180_SLAVE_SDCC_2 99 -#define SC7180_SLAVE_SECURITY 100 -#define SC7180_SLAVE_SNOC_CFG 101 -#define SC7180_SLAVE_NPU_TCM 102 -#define SC7180_SLAVE_TCSR 103 -#define SC7180_SLAVE_TLMM_WEST 104 -#define SC7180_SLAVE_TLMM_NORTH 105 -#define SC7180_SLAVE_TLMM_SOUTH 106 -#define SC7180_SLAVE_UFS_MEM_CFG 107 -#define SC7180_SLAVE_USB3 108 -#define SC7180_SLAVE_VENUS_CFG 109 -#define SC7180_SLAVE_VENUS_THROTTLE_CFG 110 -#define SC7180_SLAVE_VSENSE_CTRL_CFG 111 -#define SC7180_SLAVE_A1NOC_SNOC 112 -#define SC7180_SLAVE_A2NOC_SNOC 113 -#define SC7180_SLAVE_CAMNOC_UNCOMP 114 -#define SC7180_SLAVE_CDSP_GEM_NOC 115 -#define SC7180_SLAVE_SNOC_CNOC 116 -#define SC7180_SLAVE_GEM_NOC_SNOC 117 -#define SC7180_SLAVE_SNOC_GEM_NOC_GC 118 -#define SC7180_SLAVE_SNOC_GEM_NOC_SF 119 -#define SC7180_SLAVE_LLCC 120 -#define SC7180_SLAVE_MNOC_HF_MEM_NOC 121 -#define SC7180_SLAVE_MNOC_SF_MEM_NOC 122 -#define SC7180_SLAVE_NPU_COMPUTE_NOC 123 -#define SC7180_SLAVE_QUP_CORE_0 124 -#define SC7180_SLAVE_QUP_CORE_1 125 -#define SC7180_SLAVE_IMEM 126 -#define SC7180_SLAVE_PIMEM 127 -#define SC7180_SLAVE_SERVICE_A1NOC 128 -#define SC7180_SLAVE_SERVICE_A2NOC 129 -#define SC7180_SLAVE_SERVICE_CNOC 130 -#define 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This gives more flexibility and also allows us to drop the .num_links member, saving from possible errors related to it being not set or set incorrectly. Signed-off-by: Dmitry Baryshkov --- drivers/interconnect/qcom/sdm670.c | 530 ++++++++++++++++++---------------= ---- drivers/interconnect/qcom/sdm670.h | 128 --------- 2 files changed, 262 insertions(+), 396 deletions(-) diff --git a/drivers/interconnect/qcom/sdm670.c b/drivers/interconnect/qcom= /sdm670.c index 907e1ff4ff81796ec9459ccc72a3f8c5d110ec57..5e6a5c54f485ebef7be619d76e4= d901811956ee4 100644 --- a/drivers/interconnect/qcom/sdm670.c +++ b/drivers/interconnect/qcom/sdm670.c @@ -13,1034 +13,1020 @@ =20 #include "bcm-voter.h" #include "icc-rpmh.h" -#include "sdm670.h" + +static struct qcom_icc_node qhm_a1noc_cfg; +static struct qcom_icc_node qhm_qup1; +static struct qcom_icc_node qhm_tsif; +static struct qcom_icc_node xm_emmc; +static struct qcom_icc_node xm_sdc2; +static struct qcom_icc_node xm_sdc4; +static struct qcom_icc_node xm_ufs_mem; +static struct qcom_icc_node qhm_a2noc_cfg; +static struct qcom_icc_node qhm_qdss_bam; +static struct qcom_icc_node qhm_qup2; +static struct qcom_icc_node qnm_cnoc; +static struct qcom_icc_node qxm_crypto; +static struct qcom_icc_node qxm_ipa; +static struct qcom_icc_node xm_qdss_etr; +static struct qcom_icc_node xm_usb3_0; +static struct qcom_icc_node qxm_camnoc_hf0_uncomp; +static struct qcom_icc_node qxm_camnoc_hf1_uncomp; +static struct qcom_icc_node qxm_camnoc_sf_uncomp; +static struct qcom_icc_node qhm_spdm; +static struct qcom_icc_node qnm_snoc; +static struct qcom_icc_node qhm_cnoc; +static struct qcom_icc_node acm_l3; +static struct qcom_icc_node pm_gnoc_cfg; +static struct qcom_icc_node llcc_mc; +static struct qcom_icc_node acm_tcu; +static struct qcom_icc_node qhm_memnoc_cfg; +static struct qcom_icc_node qnm_apps; +static struct qcom_icc_node qnm_mnoc_hf; +static struct qcom_icc_node qnm_mnoc_sf; +static struct qcom_icc_node qnm_snoc_gc; +static struct qcom_icc_node qnm_snoc_sf; +static struct qcom_icc_node qxm_gpu; +static struct qcom_icc_node qhm_mnoc_cfg; +static struct qcom_icc_node qxm_camnoc_hf0; +static struct qcom_icc_node qxm_camnoc_hf1; +static struct qcom_icc_node qxm_camnoc_sf; +static struct qcom_icc_node qxm_mdp0; +static struct qcom_icc_node qxm_mdp1; +static struct qcom_icc_node qxm_rot; +static struct qcom_icc_node qxm_venus0; +static struct qcom_icc_node qxm_venus1; +static struct qcom_icc_node qxm_venus_arm9; +static struct qcom_icc_node qhm_snoc_cfg; +static struct qcom_icc_node qnm_aggre1_noc; +static struct qcom_icc_node qnm_aggre2_noc; +static struct qcom_icc_node qnm_gladiator_sodv; +static struct qcom_icc_node qnm_memnoc; +static struct qcom_icc_node qxm_pimem; +static struct qcom_icc_node xm_gic; +static struct qcom_icc_node qns_a1noc_snoc; +static struct qcom_icc_node srvc_aggre1_noc; +static struct qcom_icc_node qns_a2noc_snoc; +static struct qcom_icc_node srvc_aggre2_noc; +static struct qcom_icc_node qns_camnoc_uncomp; +static struct qcom_icc_node qhs_a1_noc_cfg; +static struct qcom_icc_node qhs_a2_noc_cfg; +static struct qcom_icc_node qhs_aop; +static struct qcom_icc_node qhs_aoss; +static struct qcom_icc_node qhs_camera_cfg; +static struct qcom_icc_node qhs_clk_ctl; +static struct qcom_icc_node qhs_compute_dsp_cfg; +static struct qcom_icc_node qhs_cpr_cx; +static struct qcom_icc_node qhs_crypto0_cfg; +static struct qcom_icc_node qhs_dcc_cfg; +static struct qcom_icc_node qhs_ddrss_cfg; +static struct qcom_icc_node qhs_display_cfg; +static struct qcom_icc_node qhs_emmc_cfg; +static struct qcom_icc_node qhs_glm; +static struct qcom_icc_node qhs_gpuss_cfg; +static struct qcom_icc_node qhs_imem_cfg; +static struct qcom_icc_node qhs_ipa; +static struct qcom_icc_node qhs_mnoc_cfg; +static struct qcom_icc_node qhs_pdm; +static struct qcom_icc_node qhs_phy_refgen_south; +static struct qcom_icc_node qhs_pimem_cfg; +static struct qcom_icc_node qhs_prng; +static struct qcom_icc_node qhs_qdss_cfg; +static struct qcom_icc_node qhs_qupv3_north; +static struct qcom_icc_node qhs_qupv3_south; +static struct qcom_icc_node qhs_sdc2; +static struct qcom_icc_node qhs_sdc4; +static struct qcom_icc_node qhs_snoc_cfg; +static struct qcom_icc_node qhs_spdm; +static struct qcom_icc_node qhs_tcsr; +static struct qcom_icc_node qhs_tlmm_north; +static struct qcom_icc_node qhs_tlmm_south; +static struct qcom_icc_node qhs_tsif; +static struct qcom_icc_node qhs_ufs_mem_cfg; +static struct qcom_icc_node qhs_usb3_0; +static struct qcom_icc_node qhs_venus_cfg; +static struct qcom_icc_node qhs_vsense_ctrl_cfg; +static struct qcom_icc_node qns_cnoc_a2noc; +static struct qcom_icc_node srvc_cnoc; +static struct qcom_icc_node qhs_llcc; +static struct qcom_icc_node qhs_memnoc; +static struct qcom_icc_node qns_gladiator_sodv; +static struct qcom_icc_node qns_gnoc_memnoc; +static struct qcom_icc_node srvc_gnoc; +static struct qcom_icc_node ebi; +static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg; +static struct qcom_icc_node qns_apps_io; +static struct qcom_icc_node qns_llcc; +static struct qcom_icc_node qns_memnoc_snoc; +static struct qcom_icc_node srvc_memnoc; +static struct qcom_icc_node qns2_mem_noc; +static struct qcom_icc_node qns_mem_noc_hf; +static struct qcom_icc_node srvc_mnoc; +static struct qcom_icc_node qhs_apss; +static struct qcom_icc_node qns_cnoc; +static struct qcom_icc_node qns_memnoc_gc; +static struct qcom_icc_node qns_memnoc_sf; +static struct qcom_icc_node qxs_imem; +static struct qcom_icc_node qxs_pimem; +static struct qcom_icc_node srvc_snoc; +static struct qcom_icc_node xs_qdss_stm; +static struct qcom_icc_node xs_sys_tcu_cfg; =20 static struct qcom_icc_node qhm_a1noc_cfg =3D { .name =3D "qhm_a1noc_cfg", - .id =3D SDM670_MASTER_A1NOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SDM670_SLAVE_SERVICE_A1NOC }, + .link_nodes =3D { &srvc_aggre1_noc }, }; =20 static struct qcom_icc_node qhm_qup1 =3D { .name =3D "qhm_qup1", - .id =3D SDM670_MASTER_BLSP_1, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SDM670_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node qhm_tsif =3D { .name =3D "qhm_tsif", - .id =3D SDM670_MASTER_TSIF, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SDM670_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node xm_emmc =3D { .name =3D "xm_emmc", - .id =3D SDM670_MASTER_EMMC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SDM670_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node xm_sdc2 =3D { .name =3D "xm_sdc2", - .id =3D SDM670_MASTER_SDCC_2, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SDM670_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node xm_sdc4 =3D { .name =3D "xm_sdc4", - .id =3D SDM670_MASTER_SDCC_4, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SDM670_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node xm_ufs_mem =3D { .name =3D "xm_ufs_mem", - .id =3D SDM670_MASTER_UFS_MEM, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SDM670_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node qhm_a2noc_cfg =3D { .name =3D "qhm_a2noc_cfg", - .id =3D SDM670_MASTER_A2NOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SDM670_SLAVE_SERVICE_A2NOC }, + .link_nodes =3D { &srvc_aggre2_noc }, }; =20 static struct qcom_icc_node qhm_qdss_bam =3D { .name =3D "qhm_qdss_bam", - .id =3D SDM670_MASTER_QDSS_BAM, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SDM670_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qhm_qup2 =3D { .name =3D "qhm_qup2", - .id =3D SDM670_MASTER_BLSP_2, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SDM670_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qnm_cnoc =3D { .name =3D "qnm_cnoc", - .id =3D SDM670_MASTER_CNOC_A2NOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SDM670_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qxm_crypto =3D { .name =3D "qxm_crypto", - .id =3D SDM670_MASTER_CRYPTO_CORE_0, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SDM670_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qxm_ipa =3D { .name =3D "qxm_ipa", - .id =3D SDM670_MASTER_IPA, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SDM670_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node xm_qdss_etr =3D { .name =3D "xm_qdss_etr", - .id =3D SDM670_MASTER_QDSS_ETR, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SDM670_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node xm_usb3_0 =3D { .name =3D "xm_usb3_0", - .id =3D SDM670_MASTER_USB3, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SDM670_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qxm_camnoc_hf0_uncomp =3D { .name =3D "qxm_camnoc_hf0_uncomp", - .id =3D SDM670_MASTER_CAMNOC_HF0_UNCOMP, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SDM670_SLAVE_CAMNOC_UNCOMP }, + .link_nodes =3D { &qns_camnoc_uncomp }, }; =20 static struct qcom_icc_node qxm_camnoc_hf1_uncomp =3D { .name =3D "qxm_camnoc_hf1_uncomp", - .id =3D SDM670_MASTER_CAMNOC_HF1_UNCOMP, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SDM670_SLAVE_CAMNOC_UNCOMP }, + .link_nodes =3D { &qns_camnoc_uncomp }, }; =20 static struct qcom_icc_node qxm_camnoc_sf_uncomp =3D { .name =3D "qxm_camnoc_sf_uncomp", - .id =3D SDM670_MASTER_CAMNOC_SF_UNCOMP, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SDM670_SLAVE_CAMNOC_UNCOMP }, + .link_nodes =3D { &qns_camnoc_uncomp }, }; =20 static struct qcom_icc_node qhm_spdm =3D { .name =3D "qhm_spdm", - .id =3D SDM670_MASTER_SPDM, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SDM670_SLAVE_CNOC_A2NOC }, + .link_nodes =3D { &qns_cnoc_a2noc }, }; =20 static struct qcom_icc_node qnm_snoc =3D { .name =3D "qnm_snoc", - .id =3D SDM670_MASTER_SNOC_CNOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 38, - .links =3D { SDM670_SLAVE_TLMM_SOUTH, - SDM670_SLAVE_CAMERA_CFG, - SDM670_SLAVE_SDCC_4, - SDM670_SLAVE_SDCC_2, - SDM670_SLAVE_CNOC_MNOC_CFG, - SDM670_SLAVE_UFS_MEM_CFG, - SDM670_SLAVE_GLM, - SDM670_SLAVE_PDM, - SDM670_SLAVE_A2NOC_CFG, - SDM670_SLAVE_QDSS_CFG, - SDM670_SLAVE_DISPLAY_CFG, - SDM670_SLAVE_TCSR, - SDM670_SLAVE_DCC_CFG, - SDM670_SLAVE_CNOC_DDRSS, - SDM670_SLAVE_SNOC_CFG, - SDM670_SLAVE_SOUTH_PHY_CFG, - SDM670_SLAVE_GRAPHICS_3D_CFG, - SDM670_SLAVE_VENUS_CFG, - SDM670_SLAVE_TSIF, - SDM670_SLAVE_CDSP_CFG, - SDM670_SLAVE_AOP, - SDM670_SLAVE_BLSP_2, - SDM670_SLAVE_SERVICE_CNOC, - SDM670_SLAVE_USB3, - SDM670_SLAVE_IPA_CFG, - SDM670_SLAVE_RBCPR_CX_CFG, - SDM670_SLAVE_A1NOC_CFG, - SDM670_SLAVE_AOSS, - SDM670_SLAVE_PRNG, - SDM670_SLAVE_VSENSE_CTRL_CFG, - SDM670_SLAVE_EMMC_CFG, - SDM670_SLAVE_BLSP_1, - SDM670_SLAVE_SPDM_WRAPPER, - SDM670_SLAVE_CRYPTO_0_CFG, - SDM670_SLAVE_PIMEM_CFG, - SDM670_SLAVE_TLMM_NORTH, - SDM670_SLAVE_CLK_CTL, - SDM670_SLAVE_IMEM_CFG - }, + .link_nodes =3D { &qhs_tlmm_south, + &qhs_camera_cfg, + &qhs_sdc4, + &qhs_sdc2, + &qhs_mnoc_cfg, + &qhs_ufs_mem_cfg, + &qhs_glm, + &qhs_pdm, + &qhs_a2_noc_cfg, + &qhs_qdss_cfg, + &qhs_display_cfg, + &qhs_tcsr, + &qhs_dcc_cfg, + &qhs_ddrss_cfg, + &qhs_snoc_cfg, + &qhs_phy_refgen_south, + &qhs_gpuss_cfg, + &qhs_venus_cfg, + &qhs_tsif, + &qhs_compute_dsp_cfg, + &qhs_aop, + &qhs_qupv3_north, + &srvc_cnoc, + &qhs_usb3_0, + &qhs_ipa, + &qhs_cpr_cx, + &qhs_a1_noc_cfg, + &qhs_aoss, + &qhs_prng, + &qhs_vsense_ctrl_cfg, + &qhs_emmc_cfg, + &qhs_qupv3_south, + &qhs_spdm, + &qhs_crypto0_cfg, + &qhs_pimem_cfg, + &qhs_tlmm_north, + &qhs_clk_ctl, + &qhs_imem_cfg }, }; =20 static struct qcom_icc_node qhm_cnoc =3D { .name =3D "qhm_cnoc", - .id =3D SDM670_MASTER_CNOC_DC_NOC, .channels =3D 1, .buswidth =3D 4, .num_links =3D 2, - .links =3D { SDM670_SLAVE_MEM_NOC_CFG, - SDM670_SLAVE_LLCC_CFG - }, + .link_nodes =3D { &qhs_memnoc, + &qhs_llcc }, }; =20 static struct qcom_icc_node acm_l3 =3D { .name =3D "acm_l3", - .id =3D SDM670_MASTER_AMPSS_M0, .channels =3D 1, .buswidth =3D 16, .num_links =3D 3, - .links =3D { SDM670_SLAVE_SERVICE_GNOC, - SDM670_SLAVE_GNOC_SNOC, - SDM670_SLAVE_GNOC_MEM_NOC - }, + .link_nodes =3D { &srvc_gnoc, + &qns_gladiator_sodv, + &qns_gnoc_memnoc }, }; =20 static struct qcom_icc_node pm_gnoc_cfg =3D { .name =3D "pm_gnoc_cfg", - .id =3D SDM670_MASTER_GNOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SDM670_SLAVE_SERVICE_GNOC }, + .link_nodes =3D { &srvc_gnoc }, }; =20 static struct qcom_icc_node llcc_mc =3D { .name =3D "llcc_mc", - .id =3D SDM670_MASTER_LLCC, .channels =3D 2, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SDM670_SLAVE_EBI_CH0 }, + .link_nodes =3D { &ebi }, }; =20 static struct qcom_icc_node acm_tcu =3D { .name =3D "acm_tcu", - .id =3D SDM670_MASTER_TCU_0, .channels =3D 1, .buswidth =3D 8, .num_links =3D 3, - .links =3D { SDM670_SLAVE_MEM_NOC_GNOC, - SDM670_SLAVE_LLCC, - SDM670_SLAVE_MEM_NOC_SNOC - }, + .link_nodes =3D { &qns_apps_io, + &qns_llcc, + &qns_memnoc_snoc }, }; =20 static struct qcom_icc_node qhm_memnoc_cfg =3D { .name =3D "qhm_memnoc_cfg", - .id =3D SDM670_MASTER_MEM_NOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 2, - .links =3D { SDM670_SLAVE_SERVICE_MEM_NOC, - SDM670_SLAVE_MSS_PROC_MS_MPU_CFG - }, + .link_nodes =3D { &srvc_memnoc, + &qhs_mdsp_ms_mpu_cfg }, }; =20 static struct qcom_icc_node qnm_apps =3D { .name =3D "qnm_apps", - .id =3D SDM670_MASTER_GNOC_MEM_NOC, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SDM670_SLAVE_LLCC }, + .link_nodes =3D { &qns_llcc }, }; =20 static struct qcom_icc_node qnm_mnoc_hf =3D { .name =3D "qnm_mnoc_hf", - .id =3D SDM670_MASTER_MNOC_HF_MEM_NOC, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SDM670_SLAVE_LLCC }, + .link_nodes =3D { &qns_llcc }, }; =20 static struct qcom_icc_node qnm_mnoc_sf =3D { .name =3D "qnm_mnoc_sf", - .id =3D SDM670_MASTER_MNOC_SF_MEM_NOC, .channels =3D 1, .buswidth =3D 32, .num_links =3D 3, - .links =3D { SDM670_SLAVE_MEM_NOC_GNOC, - SDM670_SLAVE_LLCC, - SDM670_SLAVE_MEM_NOC_SNOC - }, + .link_nodes =3D { &qns_apps_io, + &qns_llcc, + &qns_memnoc_snoc }, }; =20 static struct qcom_icc_node qnm_snoc_gc =3D { .name =3D "qnm_snoc_gc", - .id =3D SDM670_MASTER_SNOC_GC_MEM_NOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SDM670_SLAVE_LLCC }, + .link_nodes =3D { &qns_llcc }, }; =20 static struct qcom_icc_node qnm_snoc_sf =3D { .name =3D "qnm_snoc_sf", - .id =3D SDM670_MASTER_SNOC_SF_MEM_NOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 2, - .links =3D { SDM670_SLAVE_MEM_NOC_GNOC, - SDM670_SLAVE_LLCC - }, + .link_nodes =3D { &qns_apps_io, + &qns_llcc }, }; =20 static struct qcom_icc_node qxm_gpu =3D { .name =3D "qxm_gpu", - .id =3D SDM670_MASTER_GRAPHICS_3D, .channels =3D 2, .buswidth =3D 32, .num_links =3D 3, - .links =3D { SDM670_SLAVE_MEM_NOC_GNOC, - SDM670_SLAVE_LLCC, - SDM670_SLAVE_MEM_NOC_SNOC - }, + .link_nodes =3D { &qns_apps_io, + &qns_llcc, + &qns_memnoc_snoc }, }; =20 static struct qcom_icc_node qhm_mnoc_cfg =3D { .name =3D "qhm_mnoc_cfg", - .id =3D SDM670_MASTER_CNOC_MNOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SDM670_SLAVE_SERVICE_MNOC }, + .link_nodes =3D { &srvc_mnoc }, }; =20 static struct qcom_icc_node qxm_camnoc_hf0 =3D { .name =3D "qxm_camnoc_hf0", - .id =3D SDM670_MASTER_CAMNOC_HF0, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SDM670_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_hf }, }; =20 static struct qcom_icc_node qxm_camnoc_hf1 =3D { .name =3D "qxm_camnoc_hf1", - .id =3D SDM670_MASTER_CAMNOC_HF1, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SDM670_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_hf }, }; =20 static struct qcom_icc_node qxm_camnoc_sf =3D { .name =3D "qxm_camnoc_sf", - .id =3D SDM670_MASTER_CAMNOC_SF, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SDM670_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns2_mem_noc }, }; =20 static struct qcom_icc_node qxm_mdp0 =3D { .name =3D "qxm_mdp0", - .id =3D SDM670_MASTER_MDP_PORT0, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SDM670_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_hf }, }; =20 static struct qcom_icc_node qxm_mdp1 =3D { .name =3D "qxm_mdp1", - .id =3D SDM670_MASTER_MDP_PORT1, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SDM670_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_hf }, }; =20 static struct qcom_icc_node qxm_rot =3D { .name =3D "qxm_rot", - .id =3D SDM670_MASTER_ROTATOR, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SDM670_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns2_mem_noc }, }; =20 static struct qcom_icc_node qxm_venus0 =3D { .name =3D "qxm_venus0", - .id =3D SDM670_MASTER_VIDEO_P0, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SDM670_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns2_mem_noc }, }; =20 static struct qcom_icc_node qxm_venus1 =3D { .name =3D "qxm_venus1", - .id =3D SDM670_MASTER_VIDEO_P1, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SDM670_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns2_mem_noc }, }; =20 static struct qcom_icc_node qxm_venus_arm9 =3D { .name =3D "qxm_venus_arm9", - .id =3D SDM670_MASTER_VIDEO_PROC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SDM670_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns2_mem_noc }, }; =20 static struct qcom_icc_node qhm_snoc_cfg =3D { .name =3D "qhm_snoc_cfg", - .id =3D SDM670_MASTER_SNOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SDM670_SLAVE_SERVICE_SNOC }, + .link_nodes =3D { &srvc_snoc }, }; =20 static struct qcom_icc_node qnm_aggre1_noc =3D { .name =3D "qnm_aggre1_noc", - .id =3D SDM670_MASTER_A1NOC_SNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 6, - .links =3D { SDM670_SLAVE_PIMEM, - SDM670_SLAVE_SNOC_MEM_NOC_SF, - SDM670_SLAVE_OCIMEM, - SDM670_SLAVE_APPSS, - SDM670_SLAVE_SNOC_CNOC, - SDM670_SLAVE_QDSS_STM - }, + .link_nodes =3D { &qxs_pimem, + &qns_memnoc_sf, + &qxs_imem, + &qhs_apss, + &qns_cnoc, + &xs_qdss_stm }, }; =20 static struct qcom_icc_node qnm_aggre2_noc =3D { .name =3D "qnm_aggre2_noc", - .id =3D SDM670_MASTER_A2NOC_SNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 7, - .links =3D { SDM670_SLAVE_PIMEM, - SDM670_SLAVE_SNOC_MEM_NOC_SF, - SDM670_SLAVE_OCIMEM, - SDM670_SLAVE_APPSS, - SDM670_SLAVE_SNOC_CNOC, - SDM670_SLAVE_TCU, - SDM670_SLAVE_QDSS_STM - }, + .link_nodes =3D { &qxs_pimem, + &qns_memnoc_sf, + &qxs_imem, + &qhs_apss, + &qns_cnoc, + &xs_sys_tcu_cfg, + &xs_qdss_stm }, }; =20 static struct qcom_icc_node qnm_gladiator_sodv =3D { .name =3D "qnm_gladiator_sodv", - .id =3D SDM670_MASTER_GNOC_SNOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 6, - .links =3D { SDM670_SLAVE_PIMEM, - SDM670_SLAVE_OCIMEM, - SDM670_SLAVE_APPSS, - SDM670_SLAVE_SNOC_CNOC, - SDM670_SLAVE_TCU, - SDM670_SLAVE_QDSS_STM - }, + .link_nodes =3D { &qxs_pimem, + &qxs_imem, + &qhs_apss, + &qns_cnoc, + &xs_sys_tcu_cfg, + &xs_qdss_stm }, }; =20 static struct qcom_icc_node qnm_memnoc =3D { .name =3D "qnm_memnoc", - .id =3D SDM670_MASTER_MEM_NOC_SNOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 5, - .links =3D { SDM670_SLAVE_OCIMEM, - SDM670_SLAVE_APPSS, - SDM670_SLAVE_PIMEM, - SDM670_SLAVE_SNOC_CNOC, - SDM670_SLAVE_QDSS_STM - }, + .link_nodes =3D { &qxs_imem, + &qhs_apss, + &qxs_pimem, + &qns_cnoc, + &xs_qdss_stm }, }; =20 static struct qcom_icc_node qxm_pimem =3D { .name =3D "qxm_pimem", - .id =3D SDM670_MASTER_PIMEM, .channels =3D 1, .buswidth =3D 8, .num_links =3D 2, - .links =3D { SDM670_SLAVE_OCIMEM, - SDM670_SLAVE_SNOC_MEM_NOC_GC - }, + .link_nodes =3D { &qxs_imem, + &qns_memnoc_gc }, }; =20 static struct qcom_icc_node xm_gic =3D { .name =3D "xm_gic", - .id =3D SDM670_MASTER_GIC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 2, - .links =3D { SDM670_SLAVE_OCIMEM, - SDM670_SLAVE_SNOC_MEM_NOC_GC - }, + .link_nodes =3D { &qxs_imem, + &qns_memnoc_gc }, }; =20 static struct qcom_icc_node qns_a1noc_snoc =3D { .name =3D "qns_a1noc_snoc", - .id =3D SDM670_SLAVE_A1NOC_SNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SDM670_MASTER_A1NOC_SNOC }, + .link_nodes =3D { &qnm_aggre1_noc }, }; =20 static struct qcom_icc_node srvc_aggre1_noc =3D { .name =3D "srvc_aggre1_noc", - .id =3D SDM670_SLAVE_SERVICE_A1NOC, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qns_a2noc_snoc =3D { .name =3D "qns_a2noc_snoc", - .id =3D SDM670_SLAVE_A2NOC_SNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SDM670_MASTER_A2NOC_SNOC }, + .link_nodes =3D { &qnm_aggre2_noc }, }; =20 static struct qcom_icc_node srvc_aggre2_noc =3D { .name =3D "srvc_aggre2_noc", - .id =3D SDM670_SLAVE_SERVICE_A2NOC, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qns_camnoc_uncomp =3D { .name =3D "qns_camnoc_uncomp", - .id =3D SDM670_SLAVE_CAMNOC_UNCOMP, .channels =3D 1, .buswidth =3D 32, }; =20 static struct qcom_icc_node qhs_a1_noc_cfg =3D { .name =3D "qhs_a1_noc_cfg", - .id =3D SDM670_SLAVE_A1NOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SDM670_MASTER_A1NOC_CFG }, + .link_nodes =3D { &qhm_a1noc_cfg }, }; =20 static struct qcom_icc_node qhs_a2_noc_cfg =3D { .name =3D "qhs_a2_noc_cfg", - .id =3D SDM670_SLAVE_A2NOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SDM670_MASTER_A2NOC_CFG }, + .link_nodes =3D { &qhm_a2noc_cfg }, }; =20 static struct qcom_icc_node qhs_aop =3D { .name =3D "qhs_aop", - .id =3D SDM670_SLAVE_AOP, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_aoss =3D { .name =3D "qhs_aoss", - .id =3D SDM670_SLAVE_AOSS, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_camera_cfg =3D { .name =3D "qhs_camera_cfg", - .id =3D SDM670_SLAVE_CAMERA_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_clk_ctl =3D { .name =3D "qhs_clk_ctl", - .id =3D SDM670_SLAVE_CLK_CTL, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_compute_dsp_cfg =3D { .name =3D "qhs_compute_dsp_cfg", - .id =3D SDM670_SLAVE_CDSP_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_cpr_cx =3D { .name =3D "qhs_cpr_cx", - .id =3D SDM670_SLAVE_RBCPR_CX_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_crypto0_cfg =3D { .name =3D "qhs_crypto0_cfg", - .id =3D SDM670_SLAVE_CRYPTO_0_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_dcc_cfg =3D { .name =3D "qhs_dcc_cfg", - .id =3D SDM670_SLAVE_DCC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SDM670_MASTER_CNOC_DC_NOC }, + .link_nodes =3D { &qhm_cnoc }, }; =20 static struct qcom_icc_node qhs_ddrss_cfg =3D { .name =3D "qhs_ddrss_cfg", - .id =3D SDM670_SLAVE_CNOC_DDRSS, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_display_cfg =3D { .name =3D "qhs_display_cfg", - .id =3D SDM670_SLAVE_DISPLAY_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_emmc_cfg =3D { .name =3D "qhs_emmc_cfg", - .id =3D SDM670_SLAVE_EMMC_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_glm =3D { .name =3D "qhs_glm", - .id =3D SDM670_SLAVE_GLM, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_gpuss_cfg =3D { .name =3D "qhs_gpuss_cfg", - .id =3D SDM670_SLAVE_GRAPHICS_3D_CFG, .channels =3D 1, .buswidth =3D 8, }; =20 static struct qcom_icc_node qhs_imem_cfg =3D { .name =3D "qhs_imem_cfg", - .id =3D SDM670_SLAVE_IMEM_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_ipa =3D { .name =3D "qhs_ipa", - .id =3D SDM670_SLAVE_IPA_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_mnoc_cfg =3D { .name =3D "qhs_mnoc_cfg", - .id =3D SDM670_SLAVE_CNOC_MNOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SDM670_MASTER_CNOC_MNOC_CFG }, + .link_nodes =3D { &qhm_mnoc_cfg }, }; =20 static struct qcom_icc_node qhs_pdm =3D { .name =3D "qhs_pdm", - .id =3D SDM670_SLAVE_PDM, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_phy_refgen_south =3D { .name =3D "qhs_phy_refgen_south", - .id =3D SDM670_SLAVE_SOUTH_PHY_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_pimem_cfg =3D { .name =3D "qhs_pimem_cfg", - .id =3D SDM670_SLAVE_PIMEM_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_prng =3D { .name =3D "qhs_prng", - .id =3D SDM670_SLAVE_PRNG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_qdss_cfg =3D { .name =3D "qhs_qdss_cfg", - .id =3D SDM670_SLAVE_QDSS_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_qupv3_north =3D { .name =3D "qhs_qupv3_north", - .id =3D SDM670_SLAVE_BLSP_2, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_qupv3_south =3D { .name =3D "qhs_qupv3_south", - .id =3D SDM670_SLAVE_BLSP_1, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_sdc2 =3D { .name =3D "qhs_sdc2", - .id =3D SDM670_SLAVE_SDCC_2, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_sdc4 =3D { .name =3D "qhs_sdc4", - .id =3D SDM670_SLAVE_SDCC_4, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_snoc_cfg =3D { .name =3D "qhs_snoc_cfg", - .id =3D SDM670_SLAVE_SNOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SDM670_MASTER_SNOC_CFG }, + .link_nodes =3D { &qhm_snoc_cfg }, }; =20 static struct qcom_icc_node qhs_spdm =3D { .name =3D "qhs_spdm", - .id =3D SDM670_SLAVE_SPDM_WRAPPER, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_tcsr =3D { .name =3D "qhs_tcsr", - .id =3D SDM670_SLAVE_TCSR, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_tlmm_north =3D { .name =3D "qhs_tlmm_north", - .id =3D SDM670_SLAVE_TLMM_NORTH, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_tlmm_south =3D { .name =3D "qhs_tlmm_south", - .id =3D SDM670_SLAVE_TLMM_SOUTH, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_tsif =3D { .name =3D "qhs_tsif", - .id =3D SDM670_SLAVE_TSIF, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_ufs_mem_cfg =3D { .name =3D "qhs_ufs_mem_cfg", - .id =3D SDM670_SLAVE_UFS_MEM_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_usb3_0 =3D { .name =3D "qhs_usb3_0", - .id =3D SDM670_SLAVE_USB3, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_venus_cfg =3D { .name =3D "qhs_venus_cfg", - .id =3D SDM670_SLAVE_VENUS_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_vsense_ctrl_cfg =3D { .name =3D "qhs_vsense_ctrl_cfg", - .id =3D SDM670_SLAVE_VSENSE_CTRL_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qns_cnoc_a2noc =3D { .name =3D "qns_cnoc_a2noc", - .id =3D SDM670_SLAVE_CNOC_A2NOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SDM670_MASTER_CNOC_A2NOC }, + .link_nodes =3D { &qnm_cnoc }, }; =20 static struct qcom_icc_node srvc_cnoc =3D { .name =3D "srvc_cnoc", - .id =3D SDM670_SLAVE_SERVICE_CNOC, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_llcc =3D { .name =3D "qhs_llcc", - .id =3D SDM670_SLAVE_LLCC_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_memnoc =3D { .name =3D "qhs_memnoc", - .id =3D SDM670_SLAVE_MEM_NOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SDM670_MASTER_MEM_NOC_CFG }, + .link_nodes =3D { &qhm_memnoc_cfg }, }; =20 static struct qcom_icc_node qns_gladiator_sodv =3D { .name =3D "qns_gladiator_sodv", - .id =3D SDM670_SLAVE_GNOC_SNOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SDM670_MASTER_GNOC_SNOC }, + .link_nodes =3D { &qnm_gladiator_sodv }, }; =20 static struct qcom_icc_node qns_gnoc_memnoc =3D { .name =3D "qns_gnoc_memnoc", - .id =3D SDM670_SLAVE_GNOC_MEM_NOC, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SDM670_MASTER_GNOC_MEM_NOC }, + .link_nodes =3D { &qnm_apps }, }; =20 static struct qcom_icc_node srvc_gnoc =3D { .name =3D "srvc_gnoc", - .id =3D SDM670_SLAVE_SERVICE_GNOC, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node ebi =3D { .name =3D "ebi", - .id =3D SDM670_SLAVE_EBI_CH0, .channels =3D 2, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg =3D { .name =3D "qhs_mdsp_ms_mpu_cfg", - .id =3D SDM670_SLAVE_MSS_PROC_MS_MPU_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qns_apps_io =3D { .name =3D "qns_apps_io", - .id =3D SDM670_SLAVE_MEM_NOC_GNOC, .channels =3D 1, .buswidth =3D 32, }; =20 static struct qcom_icc_node qns_llcc =3D { .name =3D "qns_llcc", - .id =3D SDM670_SLAVE_LLCC, .channels =3D 2, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SDM670_MASTER_LLCC }, + .link_nodes =3D { &llcc_mc }, }; =20 static struct qcom_icc_node qns_memnoc_snoc =3D { .name =3D "qns_memnoc_snoc", - .id =3D SDM670_SLAVE_MEM_NOC_SNOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SDM670_MASTER_MEM_NOC_SNOC }, + .link_nodes =3D { &qnm_memnoc }, }; =20 static struct qcom_icc_node srvc_memnoc =3D { .name =3D "srvc_memnoc", - .id =3D SDM670_SLAVE_SERVICE_MEM_NOC, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qns2_mem_noc =3D { .name =3D "qns2_mem_noc", - .id =3D SDM670_SLAVE_MNOC_SF_MEM_NOC, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SDM670_MASTER_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qnm_mnoc_sf }, }; =20 static struct qcom_icc_node qns_mem_noc_hf =3D { .name =3D "qns_mem_noc_hf", - .id =3D SDM670_SLAVE_MNOC_HF_MEM_NOC, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SDM670_MASTER_MNOC_HF_MEM_NOC }, + .link_nodes =3D { &qnm_mnoc_hf }, }; =20 static struct qcom_icc_node srvc_mnoc =3D { .name =3D "srvc_mnoc", - .id =3D SDM670_SLAVE_SERVICE_MNOC, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_apss =3D { .name =3D "qhs_apss", - .id =3D SDM670_SLAVE_APPSS, .channels =3D 1, .buswidth =3D 8, }; =20 static struct qcom_icc_node qns_cnoc =3D { .name =3D "qns_cnoc", - .id =3D SDM670_SLAVE_SNOC_CNOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SDM670_MASTER_SNOC_CNOC }, + .link_nodes =3D { &qnm_snoc }, }; =20 static struct qcom_icc_node qns_memnoc_gc =3D { .name =3D "qns_memnoc_gc", - .id =3D SDM670_SLAVE_SNOC_MEM_NOC_GC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SDM670_MASTER_SNOC_GC_MEM_NOC }, + .link_nodes =3D { &qnm_snoc_gc }, }; =20 static struct qcom_icc_node qns_memnoc_sf =3D { .name =3D "qns_memnoc_sf", - .id =3D SDM670_SLAVE_SNOC_MEM_NOC_SF, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SDM670_MASTER_SNOC_SF_MEM_NOC }, + .link_nodes =3D { &qnm_snoc_sf }, }; =20 static struct qcom_icc_node qxs_imem =3D { .name =3D "qxs_imem", - .id =3D SDM670_SLAVE_OCIMEM, .channels =3D 1, .buswidth =3D 8, }; =20 static struct qcom_icc_node qxs_pimem =3D { .name =3D "qxs_pimem", - .id =3D SDM670_SLAVE_PIMEM, .channels =3D 1, .buswidth =3D 8, }; =20 static struct qcom_icc_node srvc_snoc =3D { .name =3D "srvc_snoc", - .id =3D SDM670_SLAVE_SERVICE_SNOC, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node xs_qdss_stm =3D { .name =3D "xs_qdss_stm", - .id =3D SDM670_SLAVE_QDSS_STM, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node xs_sys_tcu_cfg =3D { .name =3D "xs_sys_tcu_cfg", - .id =3D SDM670_SLAVE_TCU, .channels =3D 1, .buswidth =3D 8, }; @@ -1280,6 +1266,7 @@ static struct qcom_icc_node * const aggre1_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sdm670_aggre1_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D aggre1_noc_nodes, .num_nodes =3D ARRAY_SIZE(aggre1_noc_nodes), .bcms =3D aggre1_noc_bcms, @@ -1306,6 +1293,7 @@ static struct qcom_icc_node * const aggre2_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sdm670_aggre2_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D aggre2_noc_nodes, .num_nodes =3D ARRAY_SIZE(aggre2_noc_nodes), .bcms =3D aggre2_noc_bcms, @@ -1361,6 +1349,7 @@ static struct qcom_icc_node * const config_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sdm670_config_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D config_noc_nodes, .num_nodes =3D ARRAY_SIZE(config_noc_nodes), .bcms =3D config_noc_bcms, @@ -1377,6 +1366,7 @@ static struct qcom_icc_node * const dc_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sdm670_dc_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D dc_noc_nodes, .num_nodes =3D ARRAY_SIZE(dc_noc_nodes), .bcms =3D dc_noc_bcms, @@ -1395,6 +1385,7 @@ static struct qcom_icc_node * const gladiator_noc_nod= es[] =3D { }; =20 static const struct qcom_icc_desc sdm670_gladiator_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D gladiator_noc_nodes, .num_nodes =3D ARRAY_SIZE(gladiator_noc_nodes), .bcms =3D gladiator_noc_bcms, @@ -1430,6 +1421,7 @@ static struct qcom_icc_node * const mem_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sdm670_mem_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D mem_noc_nodes, .num_nodes =3D ARRAY_SIZE(mem_noc_nodes), .bcms =3D mem_noc_bcms, @@ -1460,6 +1452,7 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sdm670_mmss_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D mmss_noc_nodes, .num_nodes =3D ARRAY_SIZE(mmss_noc_nodes), .bcms =3D mmss_noc_bcms, @@ -1504,6 +1497,7 @@ static struct qcom_icc_node * const system_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sdm670_system_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D system_noc_nodes, .num_nodes =3D ARRAY_SIZE(system_noc_nodes), .bcms =3D system_noc_bcms, diff --git a/drivers/interconnect/qcom/sdm670.h b/drivers/interconnect/qcom= /sdm670.h deleted file mode 100644 index 14155f244c43e87c98037f35f895913666f66a41..000000000000000000000000000= 0000000000000 --- a/drivers/interconnect/qcom/sdm670.h +++ /dev/null @@ -1,128 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Qualcomm #define SDM670 interconnect IDs - * - * Copyright (c) 2020, The Linux Foundation. All rights reserved. - */ - -#ifndef __DRIVERS_INTERCONNECT_QCOM_SDM670_H -#define __DRIVERS_INTERCONNECT_QCOM_SDM670_H - -#define SDM670_MASTER_A1NOC_CFG 0 -#define SDM670_MASTER_A1NOC_SNOC 1 -#define SDM670_MASTER_A2NOC_CFG 2 -#define SDM670_MASTER_A2NOC_SNOC 3 -#define SDM670_MASTER_AMPSS_M0 4 -#define SDM670_MASTER_BLSP_1 5 -#define SDM670_MASTER_BLSP_2 6 -#define SDM670_MASTER_CAMNOC_HF0 7 -#define SDM670_MASTER_CAMNOC_HF0_UNCOMP 8 -#define SDM670_MASTER_CAMNOC_HF1 9 -#define SDM670_MASTER_CAMNOC_HF1_UNCOMP 10 -#define SDM670_MASTER_CAMNOC_SF 11 -#define SDM670_MASTER_CAMNOC_SF_UNCOMP 12 -#define SDM670_MASTER_CNOC_A2NOC 13 -#define SDM670_MASTER_CNOC_DC_NOC 14 -#define SDM670_MASTER_CNOC_MNOC_CFG 15 -#define SDM670_MASTER_CRYPTO_CORE_0 16 -#define SDM670_MASTER_EMMC 17 -#define SDM670_MASTER_GIC 18 -#define SDM670_MASTER_GNOC_CFG 19 -#define SDM670_MASTER_GNOC_MEM_NOC 20 -#define SDM670_MASTER_GNOC_SNOC 21 -#define SDM670_MASTER_GRAPHICS_3D 22 -#define SDM670_MASTER_IPA 23 -#define SDM670_MASTER_LLCC 24 -#define SDM670_MASTER_MDP_PORT0 25 -#define SDM670_MASTER_MDP_PORT1 26 -#define SDM670_MASTER_MEM_NOC_CFG 27 -#define SDM670_MASTER_MEM_NOC_SNOC 28 -#define SDM670_MASTER_MNOC_HF_MEM_NOC 29 -#define SDM670_MASTER_MNOC_SF_MEM_NOC 30 -#define SDM670_MASTER_PIMEM 31 -#define SDM670_MASTER_QDSS_BAM 32 -#define SDM670_MASTER_QDSS_ETR 33 -#define SDM670_MASTER_ROTATOR 34 -#define SDM670_MASTER_SDCC_2 35 -#define SDM670_MASTER_SDCC_4 36 -#define SDM670_MASTER_SNOC_CFG 37 -#define SDM670_MASTER_SNOC_CNOC 38 -#define SDM670_MASTER_SNOC_GC_MEM_NOC 39 -#define SDM670_MASTER_SNOC_SF_MEM_NOC 40 -#define SDM670_MASTER_SPDM 41 -#define SDM670_MASTER_TCU_0 42 -#define SDM670_MASTER_TSIF 43 -#define SDM670_MASTER_UFS_MEM 44 -#define SDM670_MASTER_USB3 45 -#define SDM670_MASTER_VIDEO_P0 46 -#define SDM670_MASTER_VIDEO_P1 47 -#define SDM670_MASTER_VIDEO_PROC 48 -#define SDM670_SLAVE_A1NOC_CFG 49 -#define SDM670_SLAVE_A1NOC_SNOC 50 -#define SDM670_SLAVE_A2NOC_CFG 51 -#define SDM670_SLAVE_A2NOC_SNOC 52 -#define SDM670_SLAVE_AOP 53 -#define SDM670_SLAVE_AOSS 54 -#define SDM670_SLAVE_APPSS 55 -#define SDM670_SLAVE_BLSP_1 56 -#define SDM670_SLAVE_BLSP_2 57 -#define SDM670_SLAVE_CAMERA_CFG 58 -#define SDM670_SLAVE_CAMNOC_UNCOMP 59 -#define SDM670_SLAVE_CDSP_CFG 60 -#define SDM670_SLAVE_CLK_CTL 61 -#define SDM670_SLAVE_CNOC_A2NOC 62 -#define SDM670_SLAVE_CNOC_DDRSS 63 -#define SDM670_SLAVE_CNOC_MNOC_CFG 64 -#define SDM670_SLAVE_CRYPTO_0_CFG 65 -#define SDM670_SLAVE_DCC_CFG 66 -#define SDM670_SLAVE_DISPLAY_CFG 67 -#define SDM670_SLAVE_EBI_CH0 68 -#define SDM670_SLAVE_EMMC_CFG 69 -#define SDM670_SLAVE_GLM 70 -#define SDM670_SLAVE_GNOC_MEM_NOC 71 -#define SDM670_SLAVE_GNOC_SNOC 72 -#define SDM670_SLAVE_GRAPHICS_3D_CFG 73 -#define SDM670_SLAVE_IMEM_CFG 74 -#define SDM670_SLAVE_IPA_CFG 75 -#define SDM670_SLAVE_LLCC 76 -#define SDM670_SLAVE_LLCC_CFG 77 -#define SDM670_SLAVE_MEM_NOC_CFG 78 -#define SDM670_SLAVE_MEM_NOC_GNOC 79 -#define SDM670_SLAVE_MEM_NOC_SNOC 80 -#define SDM670_SLAVE_MNOC_HF_MEM_NOC 81 -#define SDM670_SLAVE_MNOC_SF_MEM_NOC 82 -#define SDM670_SLAVE_MSS_PROC_MS_MPU_CFG 83 -#define SDM670_SLAVE_OCIMEM 84 -#define SDM670_SLAVE_PDM 85 -#define SDM670_SLAVE_PIMEM 86 -#define SDM670_SLAVE_PIMEM_CFG 87 -#define SDM670_SLAVE_PRNG 88 -#define SDM670_SLAVE_QDSS_CFG 89 -#define SDM670_SLAVE_QDSS_STM 90 -#define SDM670_SLAVE_RBCPR_CX_CFG 91 -#define SDM670_SLAVE_SDCC_2 92 -#define SDM670_SLAVE_SDCC_4 93 -#define SDM670_SLAVE_SERVICE_A1NOC 94 -#define SDM670_SLAVE_SERVICE_A2NOC 95 -#define SDM670_SLAVE_SERVICE_CNOC 96 -#define SDM670_SLAVE_SERVICE_GNOC 97 -#define SDM670_SLAVE_SERVICE_MEM_NOC 98 -#define SDM670_SLAVE_SERVICE_MNOC 99 -#define SDM670_SLAVE_SERVICE_SNOC 100 -#define SDM670_SLAVE_SNOC_CFG 101 -#define SDM670_SLAVE_SNOC_CNOC 102 -#define SDM670_SLAVE_SNOC_MEM_NOC_GC 103 -#define SDM670_SLAVE_SNOC_MEM_NOC_SF 104 -#define SDM670_SLAVE_SOUTH_PHY_CFG 105 -#define SDM670_SLAVE_SPDM_WRAPPER 106 -#define SDM670_SLAVE_TCSR 107 -#define SDM670_SLAVE_TCU 108 -#define SDM670_SLAVE_TLMM_NORTH 109 -#define SDM670_SLAVE_TLMM_SOUTH 110 -#define SDM670_SLAVE_TSIF 111 -#define SDM670_SLAVE_UFS_MEM_CFG 112 -#define SDM670_SLAVE_USB3 113 -#define SDM670_SLAVE_VENUS_CFG 114 -#define SDM670_SLAVE_VSENSE_CTRL_CFG 115 - -#endif --=20 2.47.3 From nobody Mon Feb 9 06:05:00 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C15F228C5B8 for ; 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This gives more flexibility and also allows us to drop the .num_links member, saving from possible errors related to it being not set or set incorrectly. Signed-off-by: Dmitry Baryshkov --- drivers/interconnect/qcom/sdx55.c | 492 +++++++++++++++++++---------------= ---- drivers/interconnect/qcom/sdx55.h | 70 ------ 2 files changed, 242 insertions(+), 320 deletions(-) diff --git a/drivers/interconnect/qcom/sdx55.c b/drivers/interconnect/qcom/= sdx55.c index 4117db046fa00c634a43d9287711589315f60210..b1a69e430ef444784fdc31edbe1= f80877fc63cec 100644 --- a/drivers/interconnect/qcom/sdx55.c +++ b/drivers/interconnect/qcom/sdx55.c @@ -17,628 +17,617 @@ =20 #include "bcm-voter.h" #include "icc-rpmh.h" -#include "sdx55.h" + +static struct qcom_icc_node llcc_mc; +static struct qcom_icc_node acm_tcu; +static struct qcom_icc_node qnm_snoc_gc; +static struct qcom_icc_node xm_apps_rdwr; +static struct qcom_icc_node qhm_audio; +static struct qcom_icc_node qhm_blsp1; +static struct qcom_icc_node qhm_qdss_bam; +static struct qcom_icc_node qhm_qpic; +static struct qcom_icc_node qhm_snoc_cfg; +static struct qcom_icc_node qhm_spmi_fetcher1; +static struct qcom_icc_node qnm_aggre_noc; +static struct qcom_icc_node qnm_ipa; +static struct qcom_icc_node qnm_memnoc; +static struct qcom_icc_node qnm_memnoc_pcie; +static struct qcom_icc_node qxm_crypto; +static struct qcom_icc_node xm_emac; +static struct qcom_icc_node xm_ipa2pcie_slv; +static struct qcom_icc_node xm_pcie; +static struct qcom_icc_node xm_qdss_etr; +static struct qcom_icc_node xm_sdc1; +static struct qcom_icc_node xm_usb3; +static struct qcom_icc_node ebi; +static struct qcom_icc_node qns_llcc; +static struct qcom_icc_node qns_memnoc_snoc; +static struct qcom_icc_node qns_sys_pcie; +static struct qcom_icc_node qhs_aop; +static struct qcom_icc_node qhs_aoss; +static struct qcom_icc_node qhs_apss; +static struct qcom_icc_node qhs_audio; +static struct qcom_icc_node qhs_blsp1; +static struct qcom_icc_node qhs_clk_ctl; +static struct qcom_icc_node qhs_crypto0_cfg; +static struct qcom_icc_node qhs_ddrss_cfg; +static struct qcom_icc_node qhs_ecc_cfg; +static struct qcom_icc_node qhs_emac_cfg; +static struct qcom_icc_node qhs_imem_cfg; +static struct qcom_icc_node qhs_ipa; +static struct qcom_icc_node qhs_mss_cfg; +static struct qcom_icc_node qhs_pcie_parf; +static struct qcom_icc_node qhs_pdm; +static struct qcom_icc_node qhs_prng; +static struct qcom_icc_node qhs_qdss_cfg; +static struct qcom_icc_node qhs_qpic; +static struct qcom_icc_node qhs_sdc1; +static struct qcom_icc_node qhs_snoc_cfg; +static struct qcom_icc_node qhs_spmi_fetcher; +static struct qcom_icc_node qhs_spmi_vgi_coex; +static struct qcom_icc_node qhs_tcsr; +static struct qcom_icc_node qhs_tlmm; +static struct qcom_icc_node qhs_usb3; +static struct qcom_icc_node qhs_usb3_phy; +static struct qcom_icc_node qns_aggre_noc; +static struct qcom_icc_node qns_snoc_memnoc; +static struct qcom_icc_node qxs_imem; +static struct qcom_icc_node srvc_snoc; +static struct qcom_icc_node xs_pcie; +static struct qcom_icc_node xs_qdss_stm; +static struct qcom_icc_node xs_sys_tcu_cfg; =20 static struct qcom_icc_node llcc_mc =3D { .name =3D "llcc_mc", - .id =3D SDX55_MASTER_LLCC, .channels =3D 4, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SDX55_SLAVE_EBI_CH0 }, + .link_nodes =3D { &ebi }, }; =20 static struct qcom_icc_node acm_tcu =3D { .name =3D "acm_tcu", - .id =3D SDX55_MASTER_TCU_0, .channels =3D 1, .buswidth =3D 8, .num_links =3D 3, - .links =3D { SDX55_SLAVE_LLCC, - SDX55_SLAVE_MEM_NOC_SNOC, - SDX55_SLAVE_MEM_NOC_PCIE_SNOC - }, + .link_nodes =3D { &qns_llcc, + &qns_memnoc_snoc, + &qns_sys_pcie }, }; =20 static struct qcom_icc_node qnm_snoc_gc =3D { .name =3D "qnm_snoc_gc", - .id =3D SDX55_MASTER_SNOC_GC_MEM_NOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SDX55_SLAVE_LLCC }, + .link_nodes =3D { &qns_llcc }, }; =20 static struct qcom_icc_node xm_apps_rdwr =3D { .name =3D "xm_apps_rdwr", - .id =3D SDX55_MASTER_AMPSS_M0, .channels =3D 1, .buswidth =3D 16, .num_links =3D 3, - .links =3D { SDX55_SLAVE_LLCC, - SDX55_SLAVE_MEM_NOC_SNOC, - SDX55_SLAVE_MEM_NOC_PCIE_SNOC - }, + .link_nodes =3D { &qns_llcc, + &qns_memnoc_snoc, + &qns_sys_pcie }, }; =20 static struct qcom_icc_node qhm_audio =3D { .name =3D "qhm_audio", - .id =3D SDX55_MASTER_AUDIO, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SDX55_SLAVE_ANOC_SNOC }, + .link_nodes =3D { &qns_aggre_noc }, }; =20 static struct qcom_icc_node qhm_blsp1 =3D { .name =3D "qhm_blsp1", - .id =3D SDX55_MASTER_BLSP_1, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SDX55_SLAVE_ANOC_SNOC }, + .link_nodes =3D { &qns_aggre_noc }, }; =20 static struct qcom_icc_node qhm_qdss_bam =3D { .name =3D "qhm_qdss_bam", - .id =3D SDX55_MASTER_QDSS_BAM, .channels =3D 1, .buswidth =3D 4, .num_links =3D 28, - .links =3D { SDX55_SLAVE_SNOC_CFG, - SDX55_SLAVE_EMAC_CFG, - SDX55_SLAVE_USB3, - SDX55_SLAVE_TLMM, - SDX55_SLAVE_SPMI_FETCHER, - SDX55_SLAVE_QDSS_CFG, - SDX55_SLAVE_PDM, - SDX55_SLAVE_SNOC_MEM_NOC_GC, - SDX55_SLAVE_TCSR, - SDX55_SLAVE_CNOC_DDRSS, - SDX55_SLAVE_SPMI_VGI_COEX, - SDX55_SLAVE_QPIC, - SDX55_SLAVE_OCIMEM, - SDX55_SLAVE_IPA_CFG, - SDX55_SLAVE_USB3_PHY_CFG, - SDX55_SLAVE_AOP, - SDX55_SLAVE_BLSP_1, - SDX55_SLAVE_SDCC_1, - SDX55_SLAVE_CNOC_MSS, - SDX55_SLAVE_PCIE_PARF, - SDX55_SLAVE_ECC_CFG, - SDX55_SLAVE_AUDIO, - SDX55_SLAVE_AOSS, - SDX55_SLAVE_PRNG, - SDX55_SLAVE_CRYPTO_0_CFG, - SDX55_SLAVE_TCU, - SDX55_SLAVE_CLK_CTL, - SDX55_SLAVE_IMEM_CFG - }, + .link_nodes =3D { &qhs_snoc_cfg, + &qhs_emac_cfg, + &qhs_usb3, + &qhs_tlmm, + &qhs_spmi_fetcher, + &qhs_qdss_cfg, + &qhs_pdm, + &qns_snoc_memnoc, + &qhs_tcsr, + &qhs_ddrss_cfg, + &qhs_spmi_vgi_coex, + &qhs_qpic, + &qxs_imem, + &qhs_ipa, + &qhs_usb3_phy, + &qhs_aop, + &qhs_blsp1, + &qhs_sdc1, + &qhs_mss_cfg, + &qhs_pcie_parf, + &qhs_ecc_cfg, + &qhs_audio, + &qhs_aoss, + &qhs_prng, + &qhs_crypto0_cfg, + &xs_sys_tcu_cfg, + &qhs_clk_ctl, + &qhs_imem_cfg }, }; =20 static struct qcom_icc_node qhm_qpic =3D { .name =3D "qhm_qpic", - .id =3D SDX55_MASTER_QPIC, .channels =3D 1, .buswidth =3D 4, .num_links =3D 5, - .links =3D { SDX55_SLAVE_AOSS, - SDX55_SLAVE_IPA_CFG, - SDX55_SLAVE_ANOC_SNOC, - SDX55_SLAVE_AOP, - SDX55_SLAVE_AUDIO - }, + .link_nodes =3D { &qhs_aoss, + &qhs_ipa, + &qns_aggre_noc, + &qhs_aop, + &qhs_audio }, }; =20 static struct qcom_icc_node qhm_snoc_cfg =3D { .name =3D "qhm_snoc_cfg", - .id =3D SDX55_MASTER_SNOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SDX55_SLAVE_SERVICE_SNOC }, + .link_nodes =3D { &srvc_snoc }, }; =20 static struct qcom_icc_node qhm_spmi_fetcher1 =3D { .name =3D "qhm_spmi_fetcher1", - .id =3D SDX55_MASTER_SPMI_FETCHER, .channels =3D 1, .buswidth =3D 4, .num_links =3D 3, - .links =3D { SDX55_SLAVE_AOSS, - SDX55_SLAVE_ANOC_SNOC, - SDX55_SLAVE_AOP - }, + .link_nodes =3D { &qhs_aoss, + &qns_aggre_noc, + &qhs_aop }, }; =20 static struct qcom_icc_node qnm_aggre_noc =3D { .name =3D "qnm_aggre_noc", - .id =3D SDX55_MASTER_ANOC_SNOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 30, - .links =3D { SDX55_SLAVE_PCIE_0, - SDX55_SLAVE_SNOC_CFG, - SDX55_SLAVE_SDCC_1, - SDX55_SLAVE_TLMM, - SDX55_SLAVE_SPMI_FETCHER, - SDX55_SLAVE_QDSS_CFG, - SDX55_SLAVE_PDM, - SDX55_SLAVE_SNOC_MEM_NOC_GC, - SDX55_SLAVE_TCSR, - SDX55_SLAVE_CNOC_DDRSS, - SDX55_SLAVE_SPMI_VGI_COEX, - SDX55_SLAVE_QDSS_STM, - SDX55_SLAVE_QPIC, - SDX55_SLAVE_OCIMEM, - SDX55_SLAVE_IPA_CFG, - SDX55_SLAVE_USB3_PHY_CFG, - SDX55_SLAVE_AOP, - SDX55_SLAVE_BLSP_1, - SDX55_SLAVE_USB3, - SDX55_SLAVE_CNOC_MSS, - SDX55_SLAVE_PCIE_PARF, - SDX55_SLAVE_ECC_CFG, - SDX55_SLAVE_APPSS, - SDX55_SLAVE_AUDIO, - SDX55_SLAVE_AOSS, - SDX55_SLAVE_PRNG, - SDX55_SLAVE_CRYPTO_0_CFG, - SDX55_SLAVE_TCU, - SDX55_SLAVE_CLK_CTL, - SDX55_SLAVE_IMEM_CFG - }, + .link_nodes =3D { &xs_pcie, + &qhs_snoc_cfg, + &qhs_sdc1, + &qhs_tlmm, + &qhs_spmi_fetcher, + &qhs_qdss_cfg, + &qhs_pdm, + &qns_snoc_memnoc, + &qhs_tcsr, + &qhs_ddrss_cfg, + &qhs_spmi_vgi_coex, + &xs_qdss_stm, + &qhs_qpic, + &qxs_imem, + &qhs_ipa, + &qhs_usb3_phy, + &qhs_aop, + &qhs_blsp1, + &qhs_usb3, + &qhs_mss_cfg, + &qhs_pcie_parf, + &qhs_ecc_cfg, + &qhs_apss, + &qhs_audio, + &qhs_aoss, + &qhs_prng, + &qhs_crypto0_cfg, + &xs_sys_tcu_cfg, + &qhs_clk_ctl, + &qhs_imem_cfg }, }; =20 static struct qcom_icc_node qnm_ipa =3D { .name =3D "qnm_ipa", - .id =3D SDX55_MASTER_IPA, .channels =3D 1, .buswidth =3D 8, .num_links =3D 27, - .links =3D { SDX55_SLAVE_SNOC_CFG, - SDX55_SLAVE_EMAC_CFG, - SDX55_SLAVE_USB3, - SDX55_SLAVE_AOSS, - SDX55_SLAVE_SPMI_FETCHER, - SDX55_SLAVE_QDSS_CFG, - SDX55_SLAVE_PDM, - SDX55_SLAVE_SNOC_MEM_NOC_GC, - SDX55_SLAVE_TCSR, - SDX55_SLAVE_CNOC_DDRSS, - SDX55_SLAVE_QDSS_STM, - SDX55_SLAVE_QPIC, - SDX55_SLAVE_OCIMEM, - SDX55_SLAVE_IPA_CFG, - SDX55_SLAVE_USB3_PHY_CFG, - SDX55_SLAVE_AOP, - SDX55_SLAVE_BLSP_1, - SDX55_SLAVE_SDCC_1, - SDX55_SLAVE_CNOC_MSS, - SDX55_SLAVE_PCIE_PARF, - SDX55_SLAVE_ECC_CFG, - SDX55_SLAVE_AUDIO, - SDX55_SLAVE_TLMM, - SDX55_SLAVE_PRNG, - SDX55_SLAVE_CRYPTO_0_CFG, - SDX55_SLAVE_CLK_CTL, - SDX55_SLAVE_IMEM_CFG - }, + .link_nodes =3D { &qhs_snoc_cfg, + &qhs_emac_cfg, + &qhs_usb3, + &qhs_aoss, + &qhs_spmi_fetcher, + &qhs_qdss_cfg, + &qhs_pdm, + &qns_snoc_memnoc, + &qhs_tcsr, + &qhs_ddrss_cfg, + &xs_qdss_stm, + &qhs_qpic, + &qxs_imem, + &qhs_ipa, + &qhs_usb3_phy, + &qhs_aop, + &qhs_blsp1, + &qhs_sdc1, + &qhs_mss_cfg, + &qhs_pcie_parf, + &qhs_ecc_cfg, + &qhs_audio, + &qhs_tlmm, + &qhs_prng, + &qhs_crypto0_cfg, + &qhs_clk_ctl, + &qhs_imem_cfg }, }; =20 static struct qcom_icc_node qnm_memnoc =3D { .name =3D "qnm_memnoc", - .id =3D SDX55_MASTER_MEM_NOC_SNOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 29, - .links =3D { SDX55_SLAVE_SNOC_CFG, - SDX55_SLAVE_EMAC_CFG, - SDX55_SLAVE_USB3, - SDX55_SLAVE_TLMM, - SDX55_SLAVE_SPMI_FETCHER, - SDX55_SLAVE_QDSS_CFG, - SDX55_SLAVE_PDM, - SDX55_SLAVE_TCSR, - SDX55_SLAVE_CNOC_DDRSS, - SDX55_SLAVE_SPMI_VGI_COEX, - SDX55_SLAVE_QDSS_STM, - SDX55_SLAVE_QPIC, - SDX55_SLAVE_OCIMEM, - SDX55_SLAVE_IPA_CFG, - SDX55_SLAVE_USB3_PHY_CFG, - SDX55_SLAVE_AOP, - SDX55_SLAVE_BLSP_1, - SDX55_SLAVE_SDCC_1, - SDX55_SLAVE_CNOC_MSS, - SDX55_SLAVE_PCIE_PARF, - SDX55_SLAVE_ECC_CFG, - SDX55_SLAVE_APPSS, - SDX55_SLAVE_AUDIO, - SDX55_SLAVE_AOSS, - SDX55_SLAVE_PRNG, - SDX55_SLAVE_CRYPTO_0_CFG, - SDX55_SLAVE_TCU, - SDX55_SLAVE_CLK_CTL, - SDX55_SLAVE_IMEM_CFG - }, + .link_nodes =3D { &qhs_snoc_cfg, + &qhs_emac_cfg, + &qhs_usb3, + &qhs_tlmm, + &qhs_spmi_fetcher, + &qhs_qdss_cfg, + &qhs_pdm, + &qhs_tcsr, + &qhs_ddrss_cfg, + &qhs_spmi_vgi_coex, + &xs_qdss_stm, + &qhs_qpic, + &qxs_imem, + &qhs_ipa, + &qhs_usb3_phy, + &qhs_aop, + &qhs_blsp1, + &qhs_sdc1, + &qhs_mss_cfg, + &qhs_pcie_parf, + &qhs_ecc_cfg, + &qhs_apss, + &qhs_audio, + &qhs_aoss, + &qhs_prng, + &qhs_crypto0_cfg, + &xs_sys_tcu_cfg, + &qhs_clk_ctl, + &qhs_imem_cfg }, }; =20 static struct qcom_icc_node qnm_memnoc_pcie =3D { .name =3D "qnm_memnoc_pcie", - .id =3D SDX55_MASTER_MEM_NOC_PCIE_SNOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SDX55_SLAVE_PCIE_0 }, + .link_nodes =3D { &xs_pcie }, }; =20 static struct qcom_icc_node qxm_crypto =3D { .name =3D "qxm_crypto", - .id =3D SDX55_MASTER_CRYPTO_CORE_0, .channels =3D 1, .buswidth =3D 8, .num_links =3D 3, - .links =3D { SDX55_SLAVE_AOSS, - SDX55_SLAVE_ANOC_SNOC, - SDX55_SLAVE_AOP - }, + .link_nodes =3D { &qhs_aoss, + &qns_aggre_noc, + &qhs_aop }, }; =20 static struct qcom_icc_node xm_emac =3D { .name =3D "xm_emac", - .id =3D SDX55_MASTER_EMAC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SDX55_SLAVE_ANOC_SNOC }, + .link_nodes =3D { &qns_aggre_noc }, }; =20 static struct qcom_icc_node xm_ipa2pcie_slv =3D { .name =3D "xm_ipa2pcie_slv", - .id =3D SDX55_MASTER_IPA_PCIE, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SDX55_SLAVE_PCIE_0 }, + .link_nodes =3D { &xs_pcie }, }; =20 static struct qcom_icc_node xm_pcie =3D { .name =3D "xm_pcie", - .id =3D SDX55_MASTER_PCIE, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SDX55_SLAVE_ANOC_SNOC }, + .link_nodes =3D { &qns_aggre_noc }, }; =20 static struct qcom_icc_node xm_qdss_etr =3D { .name =3D "xm_qdss_etr", - .id =3D SDX55_MASTER_QDSS_ETR, .channels =3D 1, .buswidth =3D 8, .num_links =3D 28, - .links =3D { SDX55_SLAVE_SNOC_CFG, - SDX55_SLAVE_EMAC_CFG, - SDX55_SLAVE_USB3, - SDX55_SLAVE_AOSS, - SDX55_SLAVE_SPMI_FETCHER, - SDX55_SLAVE_QDSS_CFG, - SDX55_SLAVE_PDM, - SDX55_SLAVE_SNOC_MEM_NOC_GC, - SDX55_SLAVE_TCSR, - SDX55_SLAVE_CNOC_DDRSS, - SDX55_SLAVE_SPMI_VGI_COEX, - SDX55_SLAVE_QPIC, - SDX55_SLAVE_OCIMEM, - SDX55_SLAVE_IPA_CFG, - SDX55_SLAVE_USB3_PHY_CFG, - SDX55_SLAVE_AOP, - SDX55_SLAVE_BLSP_1, - SDX55_SLAVE_SDCC_1, - SDX55_SLAVE_CNOC_MSS, - SDX55_SLAVE_PCIE_PARF, - SDX55_SLAVE_ECC_CFG, - SDX55_SLAVE_AUDIO, - SDX55_SLAVE_AOSS, - SDX55_SLAVE_PRNG, - SDX55_SLAVE_CRYPTO_0_CFG, - SDX55_SLAVE_TCU, - SDX55_SLAVE_CLK_CTL, - SDX55_SLAVE_IMEM_CFG - }, + .link_nodes =3D { &qhs_snoc_cfg, + &qhs_emac_cfg, + &qhs_usb3, + &qhs_aoss, + &qhs_spmi_fetcher, + &qhs_qdss_cfg, + &qhs_pdm, + &qns_snoc_memnoc, + &qhs_tcsr, + &qhs_ddrss_cfg, + &qhs_spmi_vgi_coex, + &qhs_qpic, + &qxs_imem, + &qhs_ipa, + &qhs_usb3_phy, + &qhs_aop, + &qhs_blsp1, + &qhs_sdc1, + &qhs_mss_cfg, + &qhs_pcie_parf, + &qhs_ecc_cfg, + &qhs_audio, + &qhs_aoss, + &qhs_prng, + &qhs_crypto0_cfg, + &xs_sys_tcu_cfg, + &qhs_clk_ctl, + &qhs_imem_cfg }, }; =20 static struct qcom_icc_node xm_sdc1 =3D { .name =3D "xm_sdc1", - .id =3D SDX55_MASTER_SDCC_1, .channels =3D 1, .buswidth =3D 8, .num_links =3D 5, - .links =3D { SDX55_SLAVE_AOSS, - SDX55_SLAVE_IPA_CFG, - SDX55_SLAVE_ANOC_SNOC, - SDX55_SLAVE_AOP, - SDX55_SLAVE_AUDIO - }, + .link_nodes =3D { &qhs_aoss, + &qhs_ipa, + &qns_aggre_noc, + &qhs_aop, + &qhs_audio }, }; =20 static struct qcom_icc_node xm_usb3 =3D { .name =3D "xm_usb3", - .id =3D SDX55_MASTER_USB3, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SDX55_SLAVE_ANOC_SNOC }, + .link_nodes =3D { &qns_aggre_noc }, }; =20 static struct qcom_icc_node ebi =3D { .name =3D "ebi", - .id =3D SDX55_SLAVE_EBI_CH0, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qns_llcc =3D { .name =3D "qns_llcc", - .id =3D SDX55_SLAVE_LLCC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SDX55_SLAVE_EBI_CH0 }, + .link_nodes =3D { &ebi }, }; =20 static struct qcom_icc_node qns_memnoc_snoc =3D { .name =3D "qns_memnoc_snoc", - .id =3D SDX55_SLAVE_MEM_NOC_SNOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SDX55_MASTER_MEM_NOC_SNOC }, + .link_nodes =3D { &qnm_memnoc }, }; =20 static struct qcom_icc_node qns_sys_pcie =3D { .name =3D "qns_sys_pcie", - .id =3D SDX55_SLAVE_MEM_NOC_PCIE_SNOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SDX55_MASTER_MEM_NOC_PCIE_SNOC }, + .link_nodes =3D { &qnm_memnoc_pcie }, }; =20 static struct qcom_icc_node qhs_aop =3D { .name =3D "qhs_aop", - .id =3D SDX55_SLAVE_AOP, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_aoss =3D { .name =3D "qhs_aoss", - .id =3D SDX55_SLAVE_AOSS, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_apss =3D { .name =3D "qhs_apss", - .id =3D SDX55_SLAVE_APPSS, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_audio =3D { .name =3D "qhs_audio", - .id =3D SDX55_SLAVE_AUDIO, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_blsp1 =3D { .name =3D "qhs_blsp1", - .id =3D SDX55_SLAVE_BLSP_1, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_clk_ctl =3D { .name =3D "qhs_clk_ctl", - .id =3D SDX55_SLAVE_CLK_CTL, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_crypto0_cfg =3D { .name =3D "qhs_crypto0_cfg", - .id =3D SDX55_SLAVE_CRYPTO_0_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_ddrss_cfg =3D { .name =3D "qhs_ddrss_cfg", - .id =3D SDX55_SLAVE_CNOC_DDRSS, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_ecc_cfg =3D { .name =3D "qhs_ecc_cfg", - .id =3D SDX55_SLAVE_ECC_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_emac_cfg =3D { .name =3D "qhs_emac_cfg", - .id =3D SDX55_SLAVE_EMAC_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_imem_cfg =3D { .name =3D "qhs_imem_cfg", - .id =3D SDX55_SLAVE_IMEM_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_ipa =3D { .name =3D "qhs_ipa", - .id =3D SDX55_SLAVE_IPA_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_mss_cfg =3D { .name =3D "qhs_mss_cfg", - .id =3D SDX55_SLAVE_CNOC_MSS, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_pcie_parf =3D { .name =3D "qhs_pcie_parf", - .id =3D SDX55_SLAVE_PCIE_PARF, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_pdm =3D { .name =3D "qhs_pdm", - .id =3D SDX55_SLAVE_PDM, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_prng =3D { .name =3D "qhs_prng", - .id =3D SDX55_SLAVE_PRNG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_qdss_cfg =3D { .name =3D "qhs_qdss_cfg", - .id =3D SDX55_SLAVE_QDSS_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_qpic =3D { .name =3D "qhs_qpic", - .id =3D SDX55_SLAVE_QPIC, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_sdc1 =3D { .name =3D "qhs_sdc1", - .id =3D SDX55_SLAVE_SDCC_1, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_snoc_cfg =3D { .name =3D "qhs_snoc_cfg", - .id =3D SDX55_SLAVE_SNOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SDX55_MASTER_SNOC_CFG }, + .link_nodes =3D { &qhm_snoc_cfg }, }; =20 static struct qcom_icc_node qhs_spmi_fetcher =3D { .name =3D "qhs_spmi_fetcher", - .id =3D SDX55_SLAVE_SPMI_FETCHER, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_spmi_vgi_coex =3D { .name =3D "qhs_spmi_vgi_coex", - .id =3D SDX55_SLAVE_SPMI_VGI_COEX, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_tcsr =3D { .name =3D "qhs_tcsr", - .id =3D SDX55_SLAVE_TCSR, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_tlmm =3D { .name =3D "qhs_tlmm", - .id =3D SDX55_SLAVE_TLMM, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_usb3 =3D { .name =3D "qhs_usb3", - .id =3D SDX55_SLAVE_USB3, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_usb3_phy =3D { .name =3D "qhs_usb3_phy", - .id =3D SDX55_SLAVE_USB3_PHY_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qns_aggre_noc =3D { .name =3D "qns_aggre_noc", - .id =3D SDX55_SLAVE_ANOC_SNOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SDX55_MASTER_ANOC_SNOC }, + .link_nodes =3D { &qnm_aggre_noc }, }; =20 static struct qcom_icc_node qns_snoc_memnoc =3D { .name =3D "qns_snoc_memnoc", - .id =3D SDX55_SLAVE_SNOC_MEM_NOC_GC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SDX55_MASTER_SNOC_GC_MEM_NOC }, + .link_nodes =3D { &qnm_snoc_gc }, }; =20 static struct qcom_icc_node qxs_imem =3D { .name =3D "qxs_imem", - .id =3D SDX55_SLAVE_OCIMEM, .channels =3D 1, .buswidth =3D 8, }; =20 static struct qcom_icc_node srvc_snoc =3D { .name =3D "srvc_snoc", - .id =3D SDX55_SLAVE_SERVICE_SNOC, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node xs_pcie =3D { .name =3D "xs_pcie", - .id =3D SDX55_SLAVE_PCIE_0, .channels =3D 1, .buswidth =3D 8, }; =20 static struct qcom_icc_node xs_qdss_stm =3D { .name =3D "xs_qdss_stm", - .id =3D SDX55_SLAVE_QDSS_STM, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node xs_sys_tcu_cfg =3D { .name =3D "xs_sys_tcu_cfg", - .id =3D SDX55_SLAVE_TCU, .channels =3D 1, .buswidth =3D 8, }; @@ -793,6 +782,7 @@ static struct qcom_icc_node * const mc_virt_nodes[] =3D= { }; =20 static const struct qcom_icc_desc sdx55_mc_virt =3D { + .alloc_dyn_id =3D true, .nodes =3D mc_virt_nodes, .num_nodes =3D ARRAY_SIZE(mc_virt_nodes), .bcms =3D mc_virt_bcms, @@ -815,6 +805,7 @@ static struct qcom_icc_node * const mem_noc_nodes[] =3D= { }; =20 static const struct qcom_icc_desc sdx55_mem_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D mem_noc_nodes, .num_nodes =3D ARRAY_SIZE(mem_noc_nodes), .bcms =3D mem_noc_bcms, @@ -894,6 +885,7 @@ static struct qcom_icc_node * const system_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sdx55_system_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D system_noc_nodes, .num_nodes =3D ARRAY_SIZE(system_noc_nodes), .bcms =3D system_noc_bcms, diff --git a/drivers/interconnect/qcom/sdx55.h b/drivers/interconnect/qcom/= sdx55.h deleted file mode 100644 index 46cbabec8aa1f95be840e50618efd04bcbf89f10..000000000000000000000000000= 0000000000000 --- a/drivers/interconnect/qcom/sdx55.h +++ /dev/null @@ -1,70 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2021, Linaro Ltd. - */ - -#ifndef __DRIVERS_INTERCONNECT_QCOM_SDX55_H -#define __DRIVERS_INTERCONNECT_QCOM_SDX55_H - -/* 0 was used by MASTER_IPA_CORE, now represented as RPMh clock */ -#define SDX55_MASTER_LLCC 1 -#define SDX55_MASTER_TCU_0 2 -#define SDX55_MASTER_SNOC_GC_MEM_NOC 3 -#define SDX55_MASTER_AMPSS_M0 4 -#define SDX55_MASTER_AUDIO 5 -#define SDX55_MASTER_BLSP_1 6 -#define SDX55_MASTER_QDSS_BAM 7 -#define SDX55_MASTER_QPIC 8 -#define SDX55_MASTER_SNOC_CFG 9 -#define SDX55_MASTER_SPMI_FETCHER 10 -#define SDX55_MASTER_ANOC_SNOC 11 -#define SDX55_MASTER_IPA 12 -#define SDX55_MASTER_MEM_NOC_SNOC 13 -#define SDX55_MASTER_MEM_NOC_PCIE_SNOC 14 -#define SDX55_MASTER_CRYPTO_CORE_0 15 -#define SDX55_MASTER_EMAC 16 -#define SDX55_MASTER_IPA_PCIE 17 -#define SDX55_MASTER_PCIE 18 -#define SDX55_MASTER_QDSS_ETR 19 -#define SDX55_MASTER_SDCC_1 20 -#define SDX55_MASTER_USB3 21 -/* 22 was used by SLAVE_IPA_CORE, now represented as RPMh clock */ -#define SDX55_SLAVE_EBI_CH0 23 -#define SDX55_SLAVE_LLCC 24 -#define SDX55_SLAVE_MEM_NOC_SNOC 25 -#define SDX55_SLAVE_MEM_NOC_PCIE_SNOC 26 -#define SDX55_SLAVE_ANOC_SNOC 27 -#define SDX55_SLAVE_SNOC_CFG 28 -#define SDX55_SLAVE_EMAC_CFG 29 -#define SDX55_SLAVE_USB3 30 -#define SDX55_SLAVE_TLMM 31 -#define SDX55_SLAVE_SPMI_FETCHER 32 -#define SDX55_SLAVE_QDSS_CFG 33 -#define SDX55_SLAVE_PDM 34 -#define SDX55_SLAVE_SNOC_MEM_NOC_GC 35 -#define SDX55_SLAVE_TCSR 36 -#define SDX55_SLAVE_CNOC_DDRSS 37 -#define SDX55_SLAVE_SPMI_VGI_COEX 38 -#define SDX55_SLAVE_QPIC 39 -#define SDX55_SLAVE_OCIMEM 40 -#define SDX55_SLAVE_IPA_CFG 41 -#define SDX55_SLAVE_USB3_PHY_CFG 42 -#define SDX55_SLAVE_AOP 43 -#define SDX55_SLAVE_BLSP_1 44 -#define SDX55_SLAVE_SDCC_1 45 -#define SDX55_SLAVE_CNOC_MSS 46 -#define SDX55_SLAVE_PCIE_PARF 47 -#define SDX55_SLAVE_ECC_CFG 48 -#define SDX55_SLAVE_AUDIO 49 -#define SDX55_SLAVE_AOSS 51 -#define SDX55_SLAVE_PRNG 52 -#define SDX55_SLAVE_CRYPTO_0_CFG 53 -#define SDX55_SLAVE_TCU 54 -#define SDX55_SLAVE_CLK_CTL 55 -#define SDX55_SLAVE_IMEM_CFG 56 -#define SDX55_SLAVE_SERVICE_SNOC 57 -#define SDX55_SLAVE_PCIE_0 58 -#define SDX55_SLAVE_QDSS_STM 59 -#define SDX55_SLAVE_APPSS 60 - -#endif --=20 2.47.3 From nobody Mon Feb 9 06:05:00 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8E33E269AEE for ; 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This gives more flexibility and also allows us to drop the .num_links member, saving from possible errors related to it being not set or set incorrectly. Signed-off-by: Dmitry Baryshkov --- drivers/interconnect/qcom/sdx65.c | 460 +++++++++++++++++++---------------= ---- drivers/interconnect/qcom/sdx65.h | 65 ------ 2 files changed, 226 insertions(+), 299 deletions(-) diff --git a/drivers/interconnect/qcom/sdx65.c b/drivers/interconnect/qcom/= sdx65.c index d3a6c6c148e5dedc95dbac3ad9b20538ce56a16d..7c8798174e026c9d1fa06b60a75= bf15e01a34049 100644 --- a/drivers/interconnect/qcom/sdx65.c +++ b/drivers/interconnect/qcom/sdx65.c @@ -13,593 +13,582 @@ =20 #include "bcm-voter.h" #include "icc-rpmh.h" -#include "sdx65.h" + +static struct qcom_icc_node llcc_mc; +static struct qcom_icc_node acm_tcu; +static struct qcom_icc_node qnm_snoc_gc; +static struct qcom_icc_node xm_apps_rdwr; +static struct qcom_icc_node qhm_audio; +static struct qcom_icc_node qhm_blsp1; +static struct qcom_icc_node qhm_qdss_bam; +static struct qcom_icc_node qhm_qpic; +static struct qcom_icc_node qhm_snoc_cfg; +static struct qcom_icc_node qhm_spmi_fetcher1; +static struct qcom_icc_node qnm_aggre_noc; +static struct qcom_icc_node qnm_ipa; +static struct qcom_icc_node qnm_memnoc; +static struct qcom_icc_node qnm_memnoc_pcie; +static struct qcom_icc_node qxm_crypto; +static struct qcom_icc_node xm_ipa2pcie_slv; +static struct qcom_icc_node xm_pcie; +static struct qcom_icc_node xm_qdss_etr; +static struct qcom_icc_node xm_sdc1; +static struct qcom_icc_node xm_usb3; +static struct qcom_icc_node ebi; +static struct qcom_icc_node qns_llcc; +static struct qcom_icc_node qns_memnoc_snoc; +static struct qcom_icc_node qns_sys_pcie; +static struct qcom_icc_node qhs_aoss; +static struct qcom_icc_node qhs_apss; +static struct qcom_icc_node qhs_audio; +static struct qcom_icc_node qhs_blsp1; +static struct qcom_icc_node qhs_clk_ctl; +static struct qcom_icc_node qhs_crypto0_cfg; +static struct qcom_icc_node qhs_ddrss_cfg; +static struct qcom_icc_node qhs_ecc_cfg; +static struct qcom_icc_node qhs_imem_cfg; +static struct qcom_icc_node qhs_ipa; +static struct qcom_icc_node qhs_mss_cfg; +static struct qcom_icc_node qhs_pcie_parf; +static struct qcom_icc_node qhs_pdm; +static struct qcom_icc_node qhs_prng; +static struct qcom_icc_node qhs_qdss_cfg; +static struct qcom_icc_node qhs_qpic; +static struct qcom_icc_node qhs_sdc1; +static struct qcom_icc_node qhs_snoc_cfg; +static struct qcom_icc_node qhs_spmi_fetcher; +static struct qcom_icc_node qhs_spmi_vgi_coex; +static struct qcom_icc_node qhs_tcsr; +static struct qcom_icc_node qhs_tlmm; +static struct qcom_icc_node qhs_usb3; +static struct qcom_icc_node qhs_usb3_phy; +static struct qcom_icc_node qns_aggre_noc; +static struct qcom_icc_node qns_snoc_memnoc; +static struct qcom_icc_node qxs_imem; +static struct qcom_icc_node srvc_snoc; +static struct qcom_icc_node xs_pcie; +static struct qcom_icc_node xs_qdss_stm; +static struct qcom_icc_node xs_sys_tcu_cfg; =20 static struct qcom_icc_node llcc_mc =3D { .name =3D "llcc_mc", - .id =3D SDX65_MASTER_LLCC, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SDX65_SLAVE_EBI1 }, + .link_nodes =3D { &ebi }, }; =20 static struct qcom_icc_node acm_tcu =3D { .name =3D "acm_tcu", - .id =3D SDX65_MASTER_TCU_0, .channels =3D 1, .buswidth =3D 8, .num_links =3D 3, - .links =3D { SDX65_SLAVE_LLCC, - SDX65_SLAVE_MEM_NOC_SNOC, - SDX65_SLAVE_MEM_NOC_PCIE_SNOC - }, + .link_nodes =3D { &qns_llcc, + &qns_memnoc_snoc, + &qns_sys_pcie }, }; =20 static struct qcom_icc_node qnm_snoc_gc =3D { .name =3D "qnm_snoc_gc", - .id =3D SDX65_MASTER_SNOC_GC_MEM_NOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SDX65_SLAVE_LLCC }, + .link_nodes =3D { &qns_llcc }, }; =20 static struct qcom_icc_node xm_apps_rdwr =3D { .name =3D "xm_apps_rdwr", - .id =3D SDX65_MASTER_APPSS_PROC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 3, - .links =3D { SDX65_SLAVE_LLCC, - SDX65_SLAVE_MEM_NOC_SNOC, - SDX65_SLAVE_MEM_NOC_PCIE_SNOC - }, + .link_nodes =3D { &qns_llcc, + &qns_memnoc_snoc, + &qns_sys_pcie }, }; =20 static struct qcom_icc_node qhm_audio =3D { .name =3D "qhm_audio", - .id =3D SDX65_MASTER_AUDIO, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SDX65_SLAVE_ANOC_SNOC }, + .link_nodes =3D { &qns_aggre_noc }, }; =20 static struct qcom_icc_node qhm_blsp1 =3D { .name =3D "qhm_blsp1", - .id =3D SDX65_MASTER_BLSP_1, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SDX65_SLAVE_ANOC_SNOC }, + .link_nodes =3D { &qns_aggre_noc }, }; =20 static struct qcom_icc_node qhm_qdss_bam =3D { .name =3D "qhm_qdss_bam", - .id =3D SDX65_MASTER_QDSS_BAM, .channels =3D 1, .buswidth =3D 4, .num_links =3D 26, - .links =3D { SDX65_SLAVE_AOSS, - SDX65_SLAVE_AUDIO, - SDX65_SLAVE_BLSP_1, - SDX65_SLAVE_CLK_CTL, - SDX65_SLAVE_CRYPTO_0_CFG, - SDX65_SLAVE_CNOC_DDRSS, - SDX65_SLAVE_ECC_CFG, - SDX65_SLAVE_IMEM_CFG, - SDX65_SLAVE_IPA_CFG, - SDX65_SLAVE_CNOC_MSS, - SDX65_SLAVE_PCIE_PARF, - SDX65_SLAVE_PDM, - SDX65_SLAVE_PRNG, - SDX65_SLAVE_QDSS_CFG, - SDX65_SLAVE_QPIC, - SDX65_SLAVE_SDCC_1, - SDX65_SLAVE_SNOC_CFG, - SDX65_SLAVE_SPMI_FETCHER, - SDX65_SLAVE_SPMI_VGI_COEX, - SDX65_SLAVE_TCSR, - SDX65_SLAVE_TLMM, - SDX65_SLAVE_USB3, - SDX65_SLAVE_USB3_PHY_CFG, - SDX65_SLAVE_SNOC_MEM_NOC_GC, - SDX65_SLAVE_IMEM, - SDX65_SLAVE_TCU - }, + .link_nodes =3D { &qhs_aoss, + &qhs_audio, + &qhs_blsp1, + &qhs_clk_ctl, + &qhs_crypto0_cfg, + &qhs_ddrss_cfg, + &qhs_ecc_cfg, + &qhs_imem_cfg, + &qhs_ipa, + &qhs_mss_cfg, + &qhs_pcie_parf, + &qhs_pdm, + &qhs_prng, + &qhs_qdss_cfg, + &qhs_qpic, + &qhs_sdc1, + &qhs_snoc_cfg, + &qhs_spmi_fetcher, + &qhs_spmi_vgi_coex, + &qhs_tcsr, + &qhs_tlmm, + &qhs_usb3, + &qhs_usb3_phy, + &qns_snoc_memnoc, + &qxs_imem, + &xs_sys_tcu_cfg }, }; =20 static struct qcom_icc_node qhm_qpic =3D { .name =3D "qhm_qpic", - .id =3D SDX65_MASTER_QPIC, .channels =3D 1, .buswidth =3D 4, .num_links =3D 4, - .links =3D { SDX65_SLAVE_AOSS, - SDX65_SLAVE_AUDIO, - SDX65_SLAVE_IPA_CFG, - SDX65_SLAVE_ANOC_SNOC - }, + .link_nodes =3D { &qhs_aoss, + &qhs_audio, + &qhs_ipa, + &qns_aggre_noc }, }; =20 static struct qcom_icc_node qhm_snoc_cfg =3D { .name =3D "qhm_snoc_cfg", - .id =3D SDX65_MASTER_SNOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SDX65_SLAVE_SERVICE_SNOC }, + .link_nodes =3D { &srvc_snoc }, }; =20 static struct qcom_icc_node qhm_spmi_fetcher1 =3D { .name =3D "qhm_spmi_fetcher1", - .id =3D SDX65_MASTER_SPMI_FETCHER, .channels =3D 1, .buswidth =3D 4, .num_links =3D 2, - .links =3D { SDX65_SLAVE_AOSS, - SDX65_SLAVE_ANOC_SNOC - }, + .link_nodes =3D { &qhs_aoss, + &qns_aggre_noc }, }; =20 static struct qcom_icc_node qnm_aggre_noc =3D { .name =3D "qnm_aggre_noc", - .id =3D SDX65_MASTER_ANOC_SNOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 29, - .links =3D { SDX65_SLAVE_AOSS, - SDX65_SLAVE_APPSS, - SDX65_SLAVE_AUDIO, - SDX65_SLAVE_BLSP_1, - SDX65_SLAVE_CLK_CTL, - SDX65_SLAVE_CRYPTO_0_CFG, - SDX65_SLAVE_CNOC_DDRSS, - SDX65_SLAVE_ECC_CFG, - SDX65_SLAVE_IMEM_CFG, - SDX65_SLAVE_IPA_CFG, - SDX65_SLAVE_CNOC_MSS, - SDX65_SLAVE_PCIE_PARF, - SDX65_SLAVE_PDM, - SDX65_SLAVE_PRNG, - SDX65_SLAVE_QDSS_CFG, - SDX65_SLAVE_QPIC, - SDX65_SLAVE_SDCC_1, - SDX65_SLAVE_SNOC_CFG, - SDX65_SLAVE_SPMI_FETCHER, - SDX65_SLAVE_SPMI_VGI_COEX, - SDX65_SLAVE_TCSR, - SDX65_SLAVE_TLMM, - SDX65_SLAVE_USB3, - SDX65_SLAVE_USB3_PHY_CFG, - SDX65_SLAVE_SNOC_MEM_NOC_GC, - SDX65_SLAVE_IMEM, - SDX65_SLAVE_PCIE_0, - SDX65_SLAVE_QDSS_STM, - SDX65_SLAVE_TCU - }, + .link_nodes =3D { &qhs_aoss, + &qhs_apss, + &qhs_audio, + &qhs_blsp1, + &qhs_clk_ctl, + &qhs_crypto0_cfg, + &qhs_ddrss_cfg, + &qhs_ecc_cfg, + &qhs_imem_cfg, + &qhs_ipa, + &qhs_mss_cfg, + &qhs_pcie_parf, + &qhs_pdm, + &qhs_prng, + &qhs_qdss_cfg, + &qhs_qpic, + &qhs_sdc1, + &qhs_snoc_cfg, + &qhs_spmi_fetcher, + &qhs_spmi_vgi_coex, + &qhs_tcsr, + &qhs_tlmm, + &qhs_usb3, + &qhs_usb3_phy, + &qns_snoc_memnoc, + &qxs_imem, + &xs_pcie, + &xs_qdss_stm, + &xs_sys_tcu_cfg }, }; =20 static struct qcom_icc_node qnm_ipa =3D { .name =3D "qnm_ipa", - .id =3D SDX65_MASTER_IPA, .channels =3D 1, .buswidth =3D 8, .num_links =3D 26, - .links =3D { SDX65_SLAVE_AOSS, - SDX65_SLAVE_AUDIO, - SDX65_SLAVE_BLSP_1, - SDX65_SLAVE_CLK_CTL, - SDX65_SLAVE_CRYPTO_0_CFG, - SDX65_SLAVE_CNOC_DDRSS, - SDX65_SLAVE_ECC_CFG, - SDX65_SLAVE_IMEM_CFG, - SDX65_SLAVE_IPA_CFG, - SDX65_SLAVE_CNOC_MSS, - SDX65_SLAVE_PCIE_PARF, - SDX65_SLAVE_PDM, - SDX65_SLAVE_PRNG, - SDX65_SLAVE_QDSS_CFG, - SDX65_SLAVE_QPIC, - SDX65_SLAVE_SDCC_1, - SDX65_SLAVE_SNOC_CFG, - SDX65_SLAVE_SPMI_FETCHER, - SDX65_SLAVE_TCSR, - SDX65_SLAVE_TLMM, - SDX65_SLAVE_USB3, - SDX65_SLAVE_USB3_PHY_CFG, - SDX65_SLAVE_SNOC_MEM_NOC_GC, - SDX65_SLAVE_IMEM, - SDX65_SLAVE_PCIE_0, - SDX65_SLAVE_QDSS_STM - }, + .link_nodes =3D { &qhs_aoss, + &qhs_audio, + &qhs_blsp1, + &qhs_clk_ctl, + &qhs_crypto0_cfg, + &qhs_ddrss_cfg, + &qhs_ecc_cfg, + &qhs_imem_cfg, + &qhs_ipa, + &qhs_mss_cfg, + &qhs_pcie_parf, + &qhs_pdm, + &qhs_prng, + &qhs_qdss_cfg, + &qhs_qpic, + &qhs_sdc1, + &qhs_snoc_cfg, + &qhs_spmi_fetcher, + &qhs_tcsr, + &qhs_tlmm, + &qhs_usb3, + &qhs_usb3_phy, + &qns_snoc_memnoc, + &qxs_imem, + &xs_pcie, + &xs_qdss_stm }, }; =20 static struct qcom_icc_node qnm_memnoc =3D { .name =3D "qnm_memnoc", - .id =3D SDX65_MASTER_MEM_NOC_SNOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 27, - .links =3D { SDX65_SLAVE_AOSS, - SDX65_SLAVE_APPSS, - SDX65_SLAVE_AUDIO, - SDX65_SLAVE_BLSP_1, - SDX65_SLAVE_CLK_CTL, - SDX65_SLAVE_CRYPTO_0_CFG, - SDX65_SLAVE_CNOC_DDRSS, - SDX65_SLAVE_ECC_CFG, - SDX65_SLAVE_IMEM_CFG, - SDX65_SLAVE_IPA_CFG, - SDX65_SLAVE_CNOC_MSS, - SDX65_SLAVE_PCIE_PARF, - SDX65_SLAVE_PDM, - SDX65_SLAVE_PRNG, - SDX65_SLAVE_QDSS_CFG, - SDX65_SLAVE_QPIC, - SDX65_SLAVE_SDCC_1, - SDX65_SLAVE_SNOC_CFG, - SDX65_SLAVE_SPMI_FETCHER, - SDX65_SLAVE_SPMI_VGI_COEX, - SDX65_SLAVE_TCSR, - SDX65_SLAVE_TLMM, - SDX65_SLAVE_USB3, - SDX65_SLAVE_USB3_PHY_CFG, - SDX65_SLAVE_IMEM, - SDX65_SLAVE_QDSS_STM, - SDX65_SLAVE_TCU - }, + .link_nodes =3D { &qhs_aoss, + &qhs_apss, + &qhs_audio, + &qhs_blsp1, + &qhs_clk_ctl, + &qhs_crypto0_cfg, + &qhs_ddrss_cfg, + &qhs_ecc_cfg, + &qhs_imem_cfg, + &qhs_ipa, + &qhs_mss_cfg, + &qhs_pcie_parf, + &qhs_pdm, + &qhs_prng, + &qhs_qdss_cfg, + &qhs_qpic, + &qhs_sdc1, + &qhs_snoc_cfg, + &qhs_spmi_fetcher, + &qhs_spmi_vgi_coex, + &qhs_tcsr, + &qhs_tlmm, + &qhs_usb3, + &qhs_usb3_phy, + &qxs_imem, + &xs_qdss_stm, + &xs_sys_tcu_cfg }, }; =20 static struct qcom_icc_node qnm_memnoc_pcie =3D { .name =3D "qnm_memnoc_pcie", - .id =3D SDX65_MASTER_MEM_NOC_PCIE_SNOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SDX65_SLAVE_PCIE_0 }, + .link_nodes =3D { &xs_pcie }, }; =20 static struct qcom_icc_node qxm_crypto =3D { .name =3D "qxm_crypto", - .id =3D SDX65_MASTER_CRYPTO, .channels =3D 1, .buswidth =3D 8, .num_links =3D 2, - .links =3D { SDX65_SLAVE_AOSS, - SDX65_SLAVE_ANOC_SNOC - }, + .link_nodes =3D { &qhs_aoss, + &qns_aggre_noc }, }; =20 static struct qcom_icc_node xm_ipa2pcie_slv =3D { .name =3D "xm_ipa2pcie_slv", - .id =3D SDX65_MASTER_IPA_PCIE, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SDX65_SLAVE_PCIE_0 }, + .link_nodes =3D { &xs_pcie }, }; =20 static struct qcom_icc_node xm_pcie =3D { .name =3D "xm_pcie", - .id =3D SDX65_MASTER_PCIE_0, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SDX65_SLAVE_ANOC_SNOC }, + .link_nodes =3D { &qns_aggre_noc }, }; =20 static struct qcom_icc_node xm_qdss_etr =3D { .name =3D "xm_qdss_etr", - .id =3D SDX65_MASTER_QDSS_ETR, .channels =3D 1, .buswidth =3D 8, .num_links =3D 26, - .links =3D { SDX65_SLAVE_AOSS, - SDX65_SLAVE_AUDIO, - SDX65_SLAVE_BLSP_1, - SDX65_SLAVE_CLK_CTL, - SDX65_SLAVE_CRYPTO_0_CFG, - SDX65_SLAVE_CNOC_DDRSS, - SDX65_SLAVE_ECC_CFG, - SDX65_SLAVE_IMEM_CFG, - SDX65_SLAVE_IPA_CFG, - SDX65_SLAVE_CNOC_MSS, - SDX65_SLAVE_PCIE_PARF, - SDX65_SLAVE_PDM, - SDX65_SLAVE_PRNG, - SDX65_SLAVE_QDSS_CFG, - SDX65_SLAVE_QPIC, - SDX65_SLAVE_SDCC_1, - SDX65_SLAVE_SNOC_CFG, - SDX65_SLAVE_SPMI_FETCHER, - SDX65_SLAVE_SPMI_VGI_COEX, - SDX65_SLAVE_TCSR, - SDX65_SLAVE_TLMM, - SDX65_SLAVE_USB3, - SDX65_SLAVE_USB3_PHY_CFG, - SDX65_SLAVE_SNOC_MEM_NOC_GC, - SDX65_SLAVE_IMEM, - SDX65_SLAVE_TCU - }, + .link_nodes =3D { &qhs_aoss, + &qhs_audio, + &qhs_blsp1, + &qhs_clk_ctl, + &qhs_crypto0_cfg, + &qhs_ddrss_cfg, + &qhs_ecc_cfg, + &qhs_imem_cfg, + &qhs_ipa, + &qhs_mss_cfg, + &qhs_pcie_parf, + &qhs_pdm, + &qhs_prng, + &qhs_qdss_cfg, + &qhs_qpic, + &qhs_sdc1, + &qhs_snoc_cfg, + &qhs_spmi_fetcher, + &qhs_spmi_vgi_coex, + &qhs_tcsr, + &qhs_tlmm, + &qhs_usb3, + &qhs_usb3_phy, + &qns_snoc_memnoc, + &qxs_imem, + &xs_sys_tcu_cfg }, }; =20 static struct qcom_icc_node xm_sdc1 =3D { .name =3D "xm_sdc1", - .id =3D SDX65_MASTER_SDCC_1, .channels =3D 1, .buswidth =3D 8, .num_links =3D 4, - .links =3D { SDX65_SLAVE_AOSS, - SDX65_SLAVE_AUDIO, - SDX65_SLAVE_IPA_CFG, - SDX65_SLAVE_ANOC_SNOC - }, + .link_nodes =3D { &qhs_aoss, + &qhs_audio, + &qhs_ipa, + &qns_aggre_noc }, }; =20 static struct qcom_icc_node xm_usb3 =3D { .name =3D "xm_usb3", - .id =3D SDX65_MASTER_USB3, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SDX65_SLAVE_ANOC_SNOC }, + .link_nodes =3D { &qns_aggre_noc }, }; =20 static struct qcom_icc_node ebi =3D { .name =3D "ebi", - .id =3D SDX65_SLAVE_EBI1, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qns_llcc =3D { .name =3D "qns_llcc", - .id =3D SDX65_SLAVE_LLCC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SDX65_MASTER_LLCC }, + .link_nodes =3D { &llcc_mc }, }; =20 static struct qcom_icc_node qns_memnoc_snoc =3D { .name =3D "qns_memnoc_snoc", - .id =3D SDX65_SLAVE_MEM_NOC_SNOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SDX65_MASTER_MEM_NOC_SNOC }, + .link_nodes =3D { &qnm_memnoc }, }; =20 static struct qcom_icc_node qns_sys_pcie =3D { .name =3D "qns_sys_pcie", - .id =3D SDX65_SLAVE_MEM_NOC_PCIE_SNOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SDX65_MASTER_MEM_NOC_PCIE_SNOC }, + .link_nodes =3D { &qnm_memnoc_pcie }, }; =20 static struct qcom_icc_node qhs_aoss =3D { .name =3D "qhs_aoss", - .id =3D SDX65_SLAVE_AOSS, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_apss =3D { .name =3D "qhs_apss", - .id =3D SDX65_SLAVE_APPSS, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_audio =3D { .name =3D "qhs_audio", - .id =3D SDX65_SLAVE_AUDIO, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_blsp1 =3D { .name =3D "qhs_blsp1", - .id =3D SDX65_SLAVE_BLSP_1, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_clk_ctl =3D { .name =3D "qhs_clk_ctl", - .id =3D SDX65_SLAVE_CLK_CTL, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_crypto0_cfg =3D { .name =3D "qhs_crypto0_cfg", - .id =3D SDX65_SLAVE_CRYPTO_0_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_ddrss_cfg =3D { .name =3D "qhs_ddrss_cfg", - .id =3D SDX65_SLAVE_CNOC_DDRSS, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_ecc_cfg =3D { .name =3D "qhs_ecc_cfg", - .id =3D SDX65_SLAVE_ECC_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_imem_cfg =3D { .name =3D "qhs_imem_cfg", - .id =3D SDX65_SLAVE_IMEM_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_ipa =3D { .name =3D "qhs_ipa", - .id =3D SDX65_SLAVE_IPA_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_mss_cfg =3D { .name =3D "qhs_mss_cfg", - .id =3D SDX65_SLAVE_CNOC_MSS, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_pcie_parf =3D { .name =3D "qhs_pcie_parf", - .id =3D SDX65_SLAVE_PCIE_PARF, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_pdm =3D { .name =3D "qhs_pdm", - .id =3D SDX65_SLAVE_PDM, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_prng =3D { .name =3D "qhs_prng", - .id =3D SDX65_SLAVE_PRNG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_qdss_cfg =3D { .name =3D "qhs_qdss_cfg", - .id =3D SDX65_SLAVE_QDSS_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_qpic =3D { .name =3D "qhs_qpic", - .id =3D SDX65_SLAVE_QPIC, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_sdc1 =3D { .name =3D "qhs_sdc1", - .id =3D SDX65_SLAVE_SDCC_1, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_snoc_cfg =3D { .name =3D "qhs_snoc_cfg", - .id =3D SDX65_SLAVE_SNOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SDX65_MASTER_SNOC_CFG }, + .link_nodes =3D { &qhm_snoc_cfg }, }; =20 static struct qcom_icc_node qhs_spmi_fetcher =3D { .name =3D "qhs_spmi_fetcher", - .id =3D SDX65_SLAVE_SPMI_FETCHER, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_spmi_vgi_coex =3D { .name =3D "qhs_spmi_vgi_coex", - .id =3D SDX65_SLAVE_SPMI_VGI_COEX, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_tcsr =3D { .name =3D "qhs_tcsr", - .id =3D SDX65_SLAVE_TCSR, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_tlmm =3D { .name =3D "qhs_tlmm", - .id =3D SDX65_SLAVE_TLMM, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_usb3 =3D { .name =3D "qhs_usb3", - .id =3D SDX65_SLAVE_USB3, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_usb3_phy =3D { .name =3D "qhs_usb3_phy", - .id =3D SDX65_SLAVE_USB3_PHY_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qns_aggre_noc =3D { .name =3D "qns_aggre_noc", - .id =3D SDX65_SLAVE_ANOC_SNOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SDX65_MASTER_ANOC_SNOC }, + .link_nodes =3D { &qnm_aggre_noc }, }; =20 static struct qcom_icc_node qns_snoc_memnoc =3D { .name =3D "qns_snoc_memnoc", - .id =3D SDX65_SLAVE_SNOC_MEM_NOC_GC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SDX65_MASTER_SNOC_GC_MEM_NOC }, + .link_nodes =3D { &qnm_snoc_gc }, }; =20 static struct qcom_icc_node qxs_imem =3D { .name =3D "qxs_imem", - .id =3D SDX65_SLAVE_IMEM, .channels =3D 1, .buswidth =3D 8, }; =20 static struct qcom_icc_node srvc_snoc =3D { .name =3D "srvc_snoc", - .id =3D SDX65_SLAVE_SERVICE_SNOC, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node xs_pcie =3D { .name =3D "xs_pcie", - .id =3D SDX65_SLAVE_PCIE_0, .channels =3D 1, .buswidth =3D 8, }; =20 static struct qcom_icc_node xs_qdss_stm =3D { .name =3D "xs_qdss_stm", - .id =3D SDX65_SLAVE_QDSS_STM, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node xs_sys_tcu_cfg =3D { .name =3D "xs_sys_tcu_cfg", - .id =3D SDX65_SLAVE_TCU, .channels =3D 1, .buswidth =3D 8, }; @@ -780,6 +769,7 @@ static struct qcom_icc_node * const mc_virt_nodes[] =3D= { }; =20 static const struct qcom_icc_desc sdx65_mc_virt =3D { + .alloc_dyn_id =3D true, .nodes =3D mc_virt_nodes, .num_nodes =3D ARRAY_SIZE(mc_virt_nodes), .bcms =3D mc_virt_bcms, @@ -802,6 +792,7 @@ static struct qcom_icc_node * const mem_noc_nodes[] =3D= { }; =20 static const struct qcom_icc_desc sdx65_mem_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D mem_noc_nodes, .num_nodes =3D ARRAY_SIZE(mem_noc_nodes), .bcms =3D mem_noc_bcms, @@ -878,6 +869,7 @@ static struct qcom_icc_node * const system_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sdx65_system_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D system_noc_nodes, .num_nodes =3D ARRAY_SIZE(system_noc_nodes), .bcms =3D system_noc_bcms, diff --git a/drivers/interconnect/qcom/sdx65.h b/drivers/interconnect/qcom/= sdx65.h deleted file mode 100644 index 5dca6e8b32c99942e4a4f474999bc72ea2fb4fb6..000000000000000000000000000= 0000000000000 --- a/drivers/interconnect/qcom/sdx65.h +++ /dev/null @@ -1,65 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserve= d. - */ - -#ifndef __DRIVERS_INTERCONNECT_QCOM_SDX65_H -#define __DRIVERS_INTERCONNECT_QCOM_SDX65_H - -#define SDX65_MASTER_TCU_0 0 -#define SDX65_MASTER_LLCC 1 -#define SDX65_MASTER_AUDIO 2 -#define SDX65_MASTER_BLSP_1 3 -#define SDX65_MASTER_QDSS_BAM 4 -#define SDX65_MASTER_QPIC 5 -#define SDX65_MASTER_SNOC_CFG 6 -#define SDX65_MASTER_SPMI_FETCHER 7 -#define SDX65_MASTER_ANOC_SNOC 8 -#define SDX65_MASTER_IPA 9 -#define SDX65_MASTER_MEM_NOC_SNOC 10 -#define SDX65_MASTER_MEM_NOC_PCIE_SNOC 11 -#define SDX65_MASTER_SNOC_GC_MEM_NOC 12 -#define SDX65_MASTER_CRYPTO 13 -#define SDX65_MASTER_APPSS_PROC 14 -#define SDX65_MASTER_IPA_PCIE 15 -#define SDX65_MASTER_PCIE_0 16 -#define SDX65_MASTER_QDSS_ETR 17 -#define SDX65_MASTER_SDCC_1 18 -#define SDX65_MASTER_USB3 19 -#define SDX65_SLAVE_EBI1 512 -#define SDX65_SLAVE_AOSS 513 -#define SDX65_SLAVE_APPSS 514 -#define SDX65_SLAVE_AUDIO 515 -#define SDX65_SLAVE_BLSP_1 516 -#define SDX65_SLAVE_CLK_CTL 517 -#define SDX65_SLAVE_CRYPTO_0_CFG 518 -#define SDX65_SLAVE_CNOC_DDRSS 519 -#define SDX65_SLAVE_ECC_CFG 520 -#define SDX65_SLAVE_IMEM_CFG 521 -#define SDX65_SLAVE_IPA_CFG 522 -#define SDX65_SLAVE_CNOC_MSS 523 -#define SDX65_SLAVE_PCIE_PARF 524 -#define SDX65_SLAVE_PDM 525 -#define SDX65_SLAVE_PRNG 526 -#define SDX65_SLAVE_QDSS_CFG 527 -#define SDX65_SLAVE_QPIC 528 -#define SDX65_SLAVE_SDCC_1 529 -#define SDX65_SLAVE_SNOC_CFG 530 -#define SDX65_SLAVE_SPMI_FETCHER 531 -#define SDX65_SLAVE_SPMI_VGI_COEX 532 -#define SDX65_SLAVE_TCSR 533 -#define SDX65_SLAVE_TLMM 534 -#define SDX65_SLAVE_USB3 535 -#define SDX65_SLAVE_USB3_PHY_CFG 536 -#define SDX65_SLAVE_ANOC_SNOC 537 -#define SDX65_SLAVE_LLCC 538 -#define SDX65_SLAVE_MEM_NOC_SNOC 539 -#define SDX65_SLAVE_SNOC_MEM_NOC_GC 540 -#define SDX65_SLAVE_MEM_NOC_PCIE_SNOC 541 -#define SDX65_SLAVE_IMEM 542 -#define SDX65_SLAVE_SERVICE_SNOC 543 -#define SDX65_SLAVE_PCIE_0 544 -#define SDX65_SLAVE_QDSS_STM 545 -#define SDX65_SLAVE_TCU 546 - -#endif --=20 2.47.3 From nobody Mon Feb 9 06:05:00 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CAD03296BD8 for ; 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This gives more flexibility and also allows us to drop the .num_links member, saving from possible errors related to it being not set or set incorrectly. Signed-off-by: Dmitry Baryshkov --- drivers/interconnect/qcom/sdx75.c | 384 +++++++++++++++++-----------------= ---- drivers/interconnect/qcom/sdx75.h | 97 ---------- 2 files changed, 174 insertions(+), 307 deletions(-) diff --git a/drivers/interconnect/qcom/sdx75.c b/drivers/interconnect/qcom/= sdx75.c index 7ef1f17f3292e15959cb06e3d8d8c5f3c6ecd060..3721d8f503a022e4c5fde62b0aa= 9eed9989c1554 100644 --- a/drivers/interconnect/qcom/sdx75.c +++ b/drivers/interconnect/qcom/sdx75.c @@ -14,782 +14,740 @@ #include "bcm-voter.h" #include "icc-common.h" #include "icc-rpmh.h" -#include "sdx75.h" + +static struct qcom_icc_node qpic_core_master; +static struct qcom_icc_node qup0_core_master; +static struct qcom_icc_node qnm_cnoc; +static struct qcom_icc_node alm_sys_tcu; +static struct qcom_icc_node chm_apps; +static struct qcom_icc_node qnm_gemnoc_cfg; +static struct qcom_icc_node qnm_mdsp; +static struct qcom_icc_node qnm_pcie; +static struct qcom_icc_node qnm_snoc_sf; +static struct qcom_icc_node xm_gic; +static struct qcom_icc_node xm_ipa2pcie; +static struct qcom_icc_node llcc_mc; +static struct qcom_icc_node xm_pcie3_0; +static struct qcom_icc_node xm_pcie3_1; +static struct qcom_icc_node xm_pcie3_2; +static struct qcom_icc_node qhm_audio; +static struct qcom_icc_node qhm_gic; +static struct qcom_icc_node qhm_pcie_rscc; +static struct qcom_icc_node qhm_qdss_bam; +static struct qcom_icc_node qhm_qpic; +static struct qcom_icc_node qhm_qup0; +static struct qcom_icc_node qnm_aggre_noc; +static struct qcom_icc_node qnm_gemnoc_cnoc; +static struct qcom_icc_node qnm_gemnoc_pcie; +static struct qcom_icc_node qnm_system_noc_cfg; +static struct qcom_icc_node qnm_system_noc_pcie_cfg; +static struct qcom_icc_node qxm_crypto; +static struct qcom_icc_node qxm_ipa; +static struct qcom_icc_node qxm_mvmss; +static struct qcom_icc_node xm_emac_0; +static struct qcom_icc_node xm_emac_1; +static struct qcom_icc_node xm_qdss_etr0; +static struct qcom_icc_node xm_qdss_etr1; +static struct qcom_icc_node xm_sdc1; +static struct qcom_icc_node xm_sdc4; +static struct qcom_icc_node xm_usb3; +static struct qcom_icc_node qpic_core_slave; +static struct qcom_icc_node qup0_core_slave; +static struct qcom_icc_node qhs_lagg; +static struct qcom_icc_node qhs_mccc_master; +static struct qcom_icc_node qns_gemnoc; +static struct qcom_icc_node qss_snoop_bwmon; +static struct qcom_icc_node qns_gemnoc_cnoc; +static struct qcom_icc_node qns_llcc; +static struct qcom_icc_node qns_pcie; +static struct qcom_icc_node srvc_gemnoc; +static struct qcom_icc_node ebi; +static struct qcom_icc_node qns_pcie_gemnoc; +static struct qcom_icc_node ps_eth0_cfg; +static struct qcom_icc_node ps_eth1_cfg; +static struct qcom_icc_node qhs_audio; +static struct qcom_icc_node qhs_clk_ctl; +static struct qcom_icc_node qhs_crypto_cfg; +static struct qcom_icc_node qhs_imem_cfg; +static struct qcom_icc_node qhs_ipa; +static struct qcom_icc_node qhs_ipc_router; +static struct qcom_icc_node qhs_mss_cfg; +static struct qcom_icc_node qhs_mvmss_cfg; +static struct qcom_icc_node qhs_pcie0_cfg; +static struct qcom_icc_node qhs_pcie1_cfg; +static struct qcom_icc_node qhs_pcie2_cfg; +static struct qcom_icc_node qhs_pcie_rscc; +static struct qcom_icc_node qhs_pdm; +static struct qcom_icc_node qhs_prng; +static struct qcom_icc_node qhs_qdss_cfg; +static struct qcom_icc_node qhs_qpic; +static struct qcom_icc_node qhs_qup0; +static struct qcom_icc_node qhs_sdc1; +static struct qcom_icc_node qhs_sdc4; +static struct qcom_icc_node qhs_spmi_vgi_coex; +static struct qcom_icc_node qhs_tcsr; +static struct qcom_icc_node qhs_tlmm; +static struct qcom_icc_node qhs_usb3; +static struct qcom_icc_node qhs_usb3_phy; +static struct qcom_icc_node qns_a1noc; +static struct qcom_icc_node qns_ddrss_cfg; +static struct qcom_icc_node qns_gemnoc_sf; +static struct qcom_icc_node qns_system_noc_cfg; +static struct qcom_icc_node qns_system_noc_pcie_cfg; +static struct qcom_icc_node qxs_imem; +static struct qcom_icc_node srvc_pcie_system_noc; +static struct qcom_icc_node srvc_system_noc; +static struct qcom_icc_node xs_pcie_0; +static struct qcom_icc_node xs_pcie_1; +static struct qcom_icc_node xs_pcie_2; +static struct qcom_icc_node xs_qdss_stm; +static struct qcom_icc_node xs_sys_tcu_cfg; =20 static struct qcom_icc_node qpic_core_master =3D { .name =3D "qpic_core_master", - .id =3D SDX75_MASTER_QPIC_CORE, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SDX75_SLAVE_QPIC_CORE }, + .link_nodes =3D { &qpic_core_slave }, }; =20 static struct qcom_icc_node qup0_core_master =3D { .name =3D "qup0_core_master", - .id =3D SDX75_MASTER_QUP_CORE_0, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SDX75_SLAVE_QUP_CORE_0 }, + .link_nodes =3D { &qup0_core_slave }, }; =20 static struct qcom_icc_node qnm_cnoc =3D { .name =3D "qnm_cnoc", - .id =3D SDX75_MASTER_CNOC_DC_NOC, .channels =3D 1, .buswidth =3D 4, .num_links =3D 4, - .links =3D { SDX75_SLAVE_LAGG_CFG, SDX75_SLAVE_MCCC_MASTER, - SDX75_SLAVE_GEM_NOC_CFG, SDX75_SLAVE_SNOOP_BWMON }, + .link_nodes =3D { &qhs_lagg, &qhs_mccc_master, + &qns_gemnoc, &qss_snoop_bwmon }, }; =20 static struct qcom_icc_node alm_sys_tcu =3D { .name =3D "alm_sys_tcu", - .id =3D SDX75_MASTER_SYS_TCU, .channels =3D 1, .buswidth =3D 8, .num_links =3D 2, - .links =3D { SDX75_SLAVE_GEM_NOC_CNOC, SDX75_SLAVE_LLCC }, + .link_nodes =3D { &qns_gemnoc_cnoc, &qns_llcc }, }; =20 static struct qcom_icc_node chm_apps =3D { .name =3D "chm_apps", - .id =3D SDX75_MASTER_APPSS_PROC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 3, - .links =3D { SDX75_SLAVE_GEM_NOC_CNOC, SDX75_SLAVE_LLCC, - SDX75_SLAVE_MEM_NOC_PCIE_SNOC }, + .link_nodes =3D { &qns_gemnoc_cnoc, &qns_llcc, + &qns_pcie }, }; =20 static struct qcom_icc_node qnm_gemnoc_cfg =3D { .name =3D "qnm_gemnoc_cfg", - .id =3D SDX75_MASTER_GEM_NOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SDX75_SLAVE_SERVICE_GEM_NOC }, + .link_nodes =3D { &srvc_gemnoc }, }; =20 static struct qcom_icc_node qnm_mdsp =3D { .name =3D "qnm_mdsp", - .id =3D SDX75_MASTER_MSS_PROC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 3, - .links =3D { SDX75_SLAVE_GEM_NOC_CNOC, SDX75_SLAVE_LLCC, - SDX75_SLAVE_MEM_NOC_PCIE_SNOC }, + .link_nodes =3D { &qns_gemnoc_cnoc, &qns_llcc, + &qns_pcie }, }; =20 static struct qcom_icc_node qnm_pcie =3D { .name =3D "qnm_pcie", - .id =3D SDX75_MASTER_ANOC_PCIE_GEM_NOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 2, - .links =3D { SDX75_SLAVE_GEM_NOC_CNOC, SDX75_SLAVE_LLCC }, + .link_nodes =3D { &qns_gemnoc_cnoc, &qns_llcc }, }; =20 static struct qcom_icc_node qnm_snoc_sf =3D { .name =3D "qnm_snoc_sf", - .id =3D SDX75_MASTER_SNOC_SF_MEM_NOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 3, - .links =3D { SDX75_SLAVE_GEM_NOC_CNOC, SDX75_SLAVE_LLCC, - SDX75_SLAVE_MEM_NOC_PCIE_SNOC }, + .link_nodes =3D { &qns_gemnoc_cnoc, &qns_llcc, + &qns_pcie }, }; =20 static struct qcom_icc_node xm_gic =3D { .name =3D "xm_gic", - .id =3D SDX75_MASTER_GIC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SDX75_SLAVE_LLCC }, + .link_nodes =3D { &qns_llcc }, }; =20 static struct qcom_icc_node xm_ipa2pcie =3D { .name =3D "xm_ipa2pcie", - .id =3D SDX75_MASTER_IPA_PCIE, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SDX75_SLAVE_MEM_NOC_PCIE_SNOC }, + .link_nodes =3D { &qns_pcie }, }; =20 static struct qcom_icc_node llcc_mc =3D { .name =3D "llcc_mc", - .id =3D SDX75_MASTER_LLCC, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SDX75_SLAVE_EBI1 }, + .link_nodes =3D { &ebi }, }; =20 static struct qcom_icc_node xm_pcie3_0 =3D { .name =3D "xm_pcie3_0", - .id =3D SDX75_MASTER_PCIE_0, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SDX75_SLAVE_ANOC_PCIE_GEM_NOC }, + .link_nodes =3D { &qns_pcie_gemnoc }, }; =20 static struct qcom_icc_node xm_pcie3_1 =3D { .name =3D "xm_pcie3_1", - .id =3D SDX75_MASTER_PCIE_1, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SDX75_SLAVE_ANOC_PCIE_GEM_NOC }, + .link_nodes =3D { &qns_pcie_gemnoc }, }; =20 static struct qcom_icc_node xm_pcie3_2 =3D { .name =3D "xm_pcie3_2", - .id =3D SDX75_MASTER_PCIE_2, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SDX75_SLAVE_ANOC_PCIE_GEM_NOC }, + .link_nodes =3D { &qns_pcie_gemnoc }, }; =20 static struct qcom_icc_node qhm_audio =3D { .name =3D "qhm_audio", - .id =3D SDX75_MASTER_AUDIO, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SDX75_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes =3D { &qns_gemnoc_sf }, }; =20 static struct qcom_icc_node qhm_gic =3D { .name =3D "qhm_gic", - .id =3D SDX75_MASTER_GIC_AHB, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SDX75_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes =3D { &qns_gemnoc_sf }, }; =20 static struct qcom_icc_node qhm_pcie_rscc =3D { .name =3D "qhm_pcie_rscc", - .id =3D SDX75_MASTER_PCIE_RSCC, .channels =3D 1, .buswidth =3D 4, .num_links =3D 31, - .links =3D { SDX75_SLAVE_ETH0_CFG, SDX75_SLAVE_ETH1_CFG, - SDX75_SLAVE_AUDIO, SDX75_SLAVE_CLK_CTL, - SDX75_SLAVE_CRYPTO_0_CFG, SDX75_SLAVE_IMEM_CFG, - SDX75_SLAVE_IPA_CFG, SDX75_SLAVE_IPC_ROUTER_CFG, - SDX75_SLAVE_CNOC_MSS, SDX75_SLAVE_ICBDI_MVMSS_CFG, - SDX75_SLAVE_PCIE_0_CFG, SDX75_SLAVE_PCIE_1_CFG, - SDX75_SLAVE_PCIE_2_CFG, SDX75_SLAVE_PDM, - SDX75_SLAVE_PRNG, SDX75_SLAVE_QDSS_CFG, - SDX75_SLAVE_QPIC, SDX75_SLAVE_QUP_0, - SDX75_SLAVE_SDCC_1, SDX75_SLAVE_SDCC_4, - SDX75_SLAVE_SPMI_VGI_COEX, SDX75_SLAVE_TCSR, - SDX75_SLAVE_TLMM, SDX75_SLAVE_USB3, - SDX75_SLAVE_USB3_PHY_CFG, SDX75_SLAVE_DDRSS_CFG, - SDX75_SLAVE_SNOC_CFG, SDX75_SLAVE_PCIE_ANOC_CFG, - SDX75_SLAVE_IMEM, SDX75_SLAVE_QDSS_STM, - SDX75_SLAVE_TCU }, + .link_nodes =3D { &ps_eth0_cfg, &ps_eth1_cfg, + &qhs_audio, &qhs_clk_ctl, + &qhs_crypto_cfg, &qhs_imem_cfg, + &qhs_ipa, &qhs_ipc_router, + &qhs_mss_cfg, &qhs_mvmss_cfg, + &qhs_pcie0_cfg, &qhs_pcie1_cfg, + &qhs_pcie2_cfg, &qhs_pdm, + &qhs_prng, &qhs_qdss_cfg, + &qhs_qpic, &qhs_qup0, + &qhs_sdc1, &qhs_sdc4, + &qhs_spmi_vgi_coex, &qhs_tcsr, + &qhs_tlmm, &qhs_usb3, + &qhs_usb3_phy, &qns_ddrss_cfg, + &qns_system_noc_cfg, &qns_system_noc_pcie_cfg, + &qxs_imem, &xs_qdss_stm, + &xs_sys_tcu_cfg }, }; =20 static struct qcom_icc_node qhm_qdss_bam =3D { .name =3D "qhm_qdss_bam", - .id =3D SDX75_MASTER_QDSS_BAM, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SDX75_SLAVE_A1NOC_CFG }, + .link_nodes =3D { &qns_a1noc }, }; =20 static struct qcom_icc_node qhm_qpic =3D { .name =3D "qhm_qpic", - .id =3D SDX75_MASTER_QPIC, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SDX75_SLAVE_A1NOC_CFG }, + .link_nodes =3D { &qns_a1noc }, }; =20 static struct qcom_icc_node qhm_qup0 =3D { .name =3D "qhm_qup0", - .id =3D SDX75_MASTER_QUP_0, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SDX75_SLAVE_A1NOC_CFG }, + .link_nodes =3D { &qns_a1noc }, }; =20 static struct qcom_icc_node qnm_aggre_noc =3D { .name =3D "qnm_aggre_noc", - .id =3D SDX75_MASTER_ANOC_SNOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SDX75_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes =3D { &qns_gemnoc_sf }, }; =20 static struct qcom_icc_node qnm_gemnoc_cnoc =3D { .name =3D "qnm_gemnoc_cnoc", - .id =3D SDX75_MASTER_GEM_NOC_CNOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 32, - .links =3D { SDX75_SLAVE_ETH0_CFG, SDX75_SLAVE_ETH1_CFG, - SDX75_SLAVE_AUDIO, SDX75_SLAVE_CLK_CTL, - SDX75_SLAVE_CRYPTO_0_CFG, SDX75_SLAVE_IMEM_CFG, - SDX75_SLAVE_IPA_CFG, SDX75_SLAVE_IPC_ROUTER_CFG, - SDX75_SLAVE_CNOC_MSS, SDX75_SLAVE_ICBDI_MVMSS_CFG, - SDX75_SLAVE_PCIE_0_CFG, SDX75_SLAVE_PCIE_1_CFG, - SDX75_SLAVE_PCIE_2_CFG, SDX75_SLAVE_PCIE_RSC_CFG, - SDX75_SLAVE_PDM, SDX75_SLAVE_PRNG, - SDX75_SLAVE_QDSS_CFG, SDX75_SLAVE_QPIC, - SDX75_SLAVE_QUP_0, SDX75_SLAVE_SDCC_1, - SDX75_SLAVE_SDCC_4, SDX75_SLAVE_SPMI_VGI_COEX, - SDX75_SLAVE_TCSR, SDX75_SLAVE_TLMM, - SDX75_SLAVE_USB3, SDX75_SLAVE_USB3_PHY_CFG, - SDX75_SLAVE_DDRSS_CFG, SDX75_SLAVE_SNOC_CFG, - SDX75_SLAVE_PCIE_ANOC_CFG, SDX75_SLAVE_IMEM, - SDX75_SLAVE_QDSS_STM, SDX75_SLAVE_TCU }, + .link_nodes =3D { &ps_eth0_cfg, &ps_eth1_cfg, + &qhs_audio, &qhs_clk_ctl, + &qhs_crypto_cfg, &qhs_imem_cfg, + &qhs_ipa, &qhs_ipc_router, + &qhs_mss_cfg, &qhs_mvmss_cfg, + &qhs_pcie0_cfg, &qhs_pcie1_cfg, + &qhs_pcie2_cfg, &qhs_pcie_rscc, + &qhs_pdm, &qhs_prng, + &qhs_qdss_cfg, &qhs_qpic, + &qhs_qup0, &qhs_sdc1, + &qhs_sdc4, &qhs_spmi_vgi_coex, + &qhs_tcsr, &qhs_tlmm, + &qhs_usb3, &qhs_usb3_phy, + &qns_ddrss_cfg, &qns_system_noc_cfg, + &qns_system_noc_pcie_cfg, &qxs_imem, + &xs_qdss_stm, &xs_sys_tcu_cfg }, }; =20 static struct qcom_icc_node qnm_gemnoc_pcie =3D { .name =3D "qnm_gemnoc_pcie", - .id =3D SDX75_MASTER_GEM_NOC_PCIE_SNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 3, - .links =3D { SDX75_SLAVE_PCIE_0, SDX75_SLAVE_PCIE_1, - SDX75_SLAVE_PCIE_2 }, + .link_nodes =3D { &xs_pcie_0, &xs_pcie_1, + &xs_pcie_2 }, }; =20 static struct qcom_icc_node qnm_system_noc_cfg =3D { .name =3D "qnm_system_noc_cfg", - .id =3D SDX75_MASTER_SNOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SDX75_SLAVE_SERVICE_SNOC }, + .link_nodes =3D { &srvc_system_noc }, }; =20 static struct qcom_icc_node qnm_system_noc_pcie_cfg =3D { .name =3D "qnm_system_noc_pcie_cfg", - .id =3D SDX75_MASTER_PCIE_ANOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SDX75_SLAVE_SERVICE_PCIE_ANOC }, + .link_nodes =3D { &srvc_pcie_system_noc }, }; =20 static struct qcom_icc_node qxm_crypto =3D { .name =3D "qxm_crypto", - .id =3D SDX75_MASTER_CRYPTO, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SDX75_SLAVE_A1NOC_CFG }, + .link_nodes =3D { &qns_a1noc }, }; =20 static struct qcom_icc_node qxm_ipa =3D { .name =3D "qxm_ipa", - .id =3D SDX75_MASTER_IPA, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SDX75_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes =3D { &qns_gemnoc_sf }, }; =20 static struct qcom_icc_node qxm_mvmss =3D { .name =3D "qxm_mvmss", - .id =3D SDX75_MASTER_MVMSS, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SDX75_SLAVE_A1NOC_CFG }, + .link_nodes =3D { &qns_a1noc }, }; =20 static struct qcom_icc_node xm_emac_0 =3D { .name =3D "xm_emac_0", - .id =3D SDX75_MASTER_EMAC_0, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SDX75_SLAVE_A1NOC_CFG }, + .link_nodes =3D { &qns_a1noc }, }; =20 static struct qcom_icc_node xm_emac_1 =3D { .name =3D "xm_emac_1", - .id =3D SDX75_MASTER_EMAC_1, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SDX75_SLAVE_A1NOC_CFG }, + .link_nodes =3D { &qns_a1noc }, }; =20 static struct qcom_icc_node xm_qdss_etr0 =3D { .name =3D "xm_qdss_etr0", - .id =3D SDX75_MASTER_QDSS_ETR, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SDX75_SLAVE_A1NOC_CFG }, + .link_nodes =3D { &qns_a1noc }, }; =20 static struct qcom_icc_node xm_qdss_etr1 =3D { .name =3D "xm_qdss_etr1", - .id =3D SDX75_MASTER_QDSS_ETR_1, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SDX75_SLAVE_A1NOC_CFG }, + .link_nodes =3D { &qns_a1noc }, }; =20 static struct qcom_icc_node xm_sdc1 =3D { .name =3D "xm_sdc1", - .id =3D SDX75_MASTER_SDCC_1, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SDX75_SLAVE_A1NOC_CFG }, + .link_nodes =3D { &qns_a1noc }, }; =20 static struct qcom_icc_node xm_sdc4 =3D { .name =3D "xm_sdc4", - .id =3D SDX75_MASTER_SDCC_4, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SDX75_SLAVE_A1NOC_CFG }, + .link_nodes =3D { &qns_a1noc }, }; =20 static struct qcom_icc_node xm_usb3 =3D { .name =3D "xm_usb3", - .id =3D SDX75_MASTER_USB3_0, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SDX75_SLAVE_A1NOC_CFG }, + .link_nodes =3D { &qns_a1noc }, }; =20 static struct qcom_icc_node qpic_core_slave =3D { .name =3D "qpic_core_slave", - .id =3D SDX75_SLAVE_QPIC_CORE, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qup0_core_slave =3D { .name =3D "qup0_core_slave", - .id =3D SDX75_SLAVE_QUP_CORE_0, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_lagg =3D { .name =3D "qhs_lagg", - .id =3D SDX75_SLAVE_LAGG_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_mccc_master =3D { .name =3D "qhs_mccc_master", - .id =3D SDX75_SLAVE_MCCC_MASTER, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qns_gemnoc =3D { .name =3D "qns_gemnoc", - .id =3D SDX75_SLAVE_GEM_NOC_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qss_snoop_bwmon =3D { .name =3D "qss_snoop_bwmon", - .id =3D SDX75_SLAVE_SNOOP_BWMON, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qns_gemnoc_cnoc =3D { .name =3D "qns_gemnoc_cnoc", - .id =3D SDX75_SLAVE_GEM_NOC_CNOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SDX75_MASTER_GEM_NOC_CNOC }, + .link_nodes =3D { &qnm_gemnoc_cnoc }, }; =20 static struct qcom_icc_node qns_llcc =3D { .name =3D "qns_llcc", - .id =3D SDX75_SLAVE_LLCC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SDX75_MASTER_LLCC }, + .link_nodes =3D { &llcc_mc }, }; =20 static struct qcom_icc_node qns_pcie =3D { .name =3D "qns_pcie", - .id =3D SDX75_SLAVE_MEM_NOC_PCIE_SNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SDX75_MASTER_GEM_NOC_PCIE_SNOC }, + .link_nodes =3D { &qnm_gemnoc_pcie }, }; =20 static struct qcom_icc_node srvc_gemnoc =3D { .name =3D "srvc_gemnoc", - .id =3D SDX75_SLAVE_SERVICE_GEM_NOC, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node ebi =3D { .name =3D "ebi", - .id =3D SDX75_SLAVE_EBI1, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qns_pcie_gemnoc =3D { .name =3D "qns_pcie_gemnoc", - .id =3D SDX75_SLAVE_ANOC_PCIE_GEM_NOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SDX75_MASTER_ANOC_PCIE_GEM_NOC }, + .link_nodes =3D { &qnm_pcie }, }; =20 static struct qcom_icc_node ps_eth0_cfg =3D { .name =3D "ps_eth0_cfg", - .id =3D SDX75_SLAVE_ETH0_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node ps_eth1_cfg =3D { .name =3D "ps_eth1_cfg", - .id =3D SDX75_SLAVE_ETH1_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_audio =3D { .name =3D "qhs_audio", - .id =3D SDX75_SLAVE_AUDIO, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_clk_ctl =3D { .name =3D "qhs_clk_ctl", - .id =3D SDX75_SLAVE_CLK_CTL, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_crypto_cfg =3D { .name =3D "qhs_crypto_cfg", - .id =3D SDX75_SLAVE_CRYPTO_0_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_imem_cfg =3D { .name =3D "qhs_imem_cfg", - .id =3D SDX75_SLAVE_IMEM_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_ipa =3D { .name =3D "qhs_ipa", - .id =3D SDX75_SLAVE_IPA_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_ipc_router =3D { .name =3D "qhs_ipc_router", - .id =3D SDX75_SLAVE_IPC_ROUTER_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_mss_cfg =3D { .name =3D "qhs_mss_cfg", - .id =3D SDX75_SLAVE_CNOC_MSS, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_mvmss_cfg =3D { .name =3D "qhs_mvmss_cfg", - .id =3D SDX75_SLAVE_ICBDI_MVMSS_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_pcie0_cfg =3D { .name =3D "qhs_pcie0_cfg", - .id =3D SDX75_SLAVE_PCIE_0_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_pcie1_cfg =3D { .name =3D "qhs_pcie1_cfg", - .id =3D SDX75_SLAVE_PCIE_1_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_pcie2_cfg =3D { .name =3D "qhs_pcie2_cfg", - .id =3D SDX75_SLAVE_PCIE_2_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_pcie_rscc =3D { .name =3D "qhs_pcie_rscc", - .id =3D SDX75_SLAVE_PCIE_RSC_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_pdm =3D { .name =3D "qhs_pdm", - .id =3D SDX75_SLAVE_PDM, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_prng =3D { .name =3D "qhs_prng", - .id =3D SDX75_SLAVE_PRNG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_qdss_cfg =3D { .name =3D "qhs_qdss_cfg", - .id =3D SDX75_SLAVE_QDSS_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_qpic =3D { .name =3D "qhs_qpic", - .id =3D SDX75_SLAVE_QPIC, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_qup0 =3D { .name =3D "qhs_qup0", - .id =3D SDX75_SLAVE_QUP_0, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_sdc1 =3D { .name =3D "qhs_sdc1", - .id =3D SDX75_SLAVE_SDCC_1, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_sdc4 =3D { .name =3D "qhs_sdc4", - .id =3D SDX75_SLAVE_SDCC_4, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_spmi_vgi_coex =3D { .name =3D "qhs_spmi_vgi_coex", - .id =3D SDX75_SLAVE_SPMI_VGI_COEX, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_tcsr =3D { .name =3D "qhs_tcsr", - .id =3D SDX75_SLAVE_TCSR, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_tlmm =3D { .name =3D "qhs_tlmm", - .id =3D SDX75_SLAVE_TLMM, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_usb3 =3D { .name =3D "qhs_usb3", - .id =3D SDX75_SLAVE_USB3, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_usb3_phy =3D { .name =3D "qhs_usb3_phy", - .id =3D SDX75_SLAVE_USB3_PHY_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qns_a1noc =3D { .name =3D "qns_a1noc", - .id =3D SDX75_SLAVE_A1NOC_CFG, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SDX75_MASTER_ANOC_SNOC }, + .link_nodes =3D { &qnm_aggre_noc }, }; =20 static struct qcom_icc_node qns_ddrss_cfg =3D { .name =3D "qns_ddrss_cfg", - .id =3D SDX75_SLAVE_DDRSS_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SDX75_MASTER_CNOC_DC_NOC }, + .link_nodes =3D { &qnm_cnoc }, }; =20 static struct qcom_icc_node qns_gemnoc_sf =3D { .name =3D "qns_gemnoc_sf", - .id =3D SDX75_SLAVE_SNOC_GEM_NOC_SF, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SDX75_MASTER_SNOC_SF_MEM_NOC }, + .link_nodes =3D { &qnm_snoc_sf }, }; =20 static struct qcom_icc_node qns_system_noc_cfg =3D { .name =3D "qns_system_noc_cfg", - .id =3D SDX75_SLAVE_SNOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SDX75_MASTER_SNOC_CFG }, + .link_nodes =3D { &qnm_system_noc_cfg }, }; =20 static struct qcom_icc_node qns_system_noc_pcie_cfg =3D { .name =3D "qns_system_noc_pcie_cfg", - .id =3D SDX75_SLAVE_PCIE_ANOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SDX75_MASTER_PCIE_ANOC_CFG }, + .link_nodes =3D { &qnm_system_noc_pcie_cfg }, }; =20 static struct qcom_icc_node qxs_imem =3D { .name =3D "qxs_imem", - .id =3D SDX75_SLAVE_IMEM, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 0, }; =20 static struct qcom_icc_node srvc_pcie_system_noc =3D { .name =3D "srvc_pcie_system_noc", - .id =3D SDX75_SLAVE_SERVICE_PCIE_ANOC, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node srvc_system_noc =3D { .name =3D "srvc_system_noc", - .id =3D SDX75_SLAVE_SERVICE_SNOC, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node xs_pcie_0 =3D { .name =3D "xs_pcie_0", - .id =3D SDX75_SLAVE_PCIE_0, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 0, }; =20 static struct qcom_icc_node xs_pcie_1 =3D { .name =3D "xs_pcie_1", - .id =3D SDX75_SLAVE_PCIE_1, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 0, }; =20 static struct qcom_icc_node xs_pcie_2 =3D { .name =3D "xs_pcie_2", - .id =3D SDX75_SLAVE_PCIE_2, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 0, }; =20 static struct qcom_icc_node xs_qdss_stm =3D { .name =3D "xs_qdss_stm", - .id =3D SDX75_SLAVE_QDSS_STM, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node xs_sys_tcu_cfg =3D { .name =3D "xs_sys_tcu_cfg", - .id =3D SDX75_SLAVE_TCU, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 0, }; =20 static struct qcom_icc_bcm bcm_ce0 =3D { @@ -910,6 +868,7 @@ static struct qcom_icc_node * const clk_virt_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sdx75_clk_virt =3D { + .alloc_dyn_id =3D true, .nodes =3D clk_virt_nodes, .num_nodes =3D ARRAY_SIZE(clk_virt_nodes), .bcms =3D clk_virt_bcms, @@ -925,6 +884,7 @@ static struct qcom_icc_node * const dc_noc_nodes[] =3D { }; =20 static const struct qcom_icc_desc sdx75_dc_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D dc_noc_nodes, .num_nodes =3D ARRAY_SIZE(dc_noc_nodes), }; @@ -951,6 +911,7 @@ static struct qcom_icc_node * const gem_noc_nodes[] =3D= { }; =20 static const struct qcom_icc_desc sdx75_gem_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D gem_noc_nodes, .num_nodes =3D ARRAY_SIZE(gem_noc_nodes), .bcms =3D gem_noc_bcms, @@ -967,6 +928,7 @@ static struct qcom_icc_node * const mc_virt_nodes[] =3D= { }; =20 static const struct qcom_icc_desc sdx75_mc_virt =3D { + .alloc_dyn_id =3D true, .nodes =3D mc_virt_nodes, .num_nodes =3D ARRAY_SIZE(mc_virt_nodes), .bcms =3D mc_virt_bcms, @@ -986,6 +948,7 @@ static struct qcom_icc_node * const pcie_anoc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sdx75_pcie_anoc =3D { + .alloc_dyn_id =3D true, .nodes =3D pcie_anoc_nodes, .num_nodes =3D ARRAY_SIZE(pcie_anoc_nodes), .bcms =3D pcie_anoc_bcms, @@ -1064,6 +1027,7 @@ static struct qcom_icc_node * const system_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sdx75_system_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D system_noc_nodes, .num_nodes =3D ARRAY_SIZE(system_noc_nodes), .bcms =3D system_noc_bcms, diff --git a/drivers/interconnect/qcom/sdx75.h b/drivers/interconnect/qcom/= sdx75.h deleted file mode 100644 index 24e88715992010d934a1a630979f864af3a8426c..000000000000000000000000000= 0000000000000 --- a/drivers/interconnect/qcom/sdx75.h +++ /dev/null @@ -1,97 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserve= d. - */ - -#ifndef __DRIVERS_INTERCONNECT_QCOM_SDX75_H -#define __DRIVERS_INTERCONNECT_QCOM_SDX75_H - -#define SDX75_MASTER_ANOC_PCIE_GEM_NOC 0 -#define SDX75_MASTER_ANOC_SNOC 1 -#define SDX75_MASTER_APPSS_PROC 2 -#define SDX75_MASTER_AUDIO 3 -#define SDX75_MASTER_CNOC_DC_NOC 4 -#define SDX75_MASTER_CRYPTO 5 -#define SDX75_MASTER_EMAC_0 6 -#define SDX75_MASTER_EMAC_1 7 -#define SDX75_MASTER_GEM_NOC_CFG 8 -#define SDX75_MASTER_GEM_NOC_CNOC 9 -#define SDX75_MASTER_GEM_NOC_PCIE_SNOC 10 -#define SDX75_MASTER_GIC 11 -#define SDX75_MASTER_GIC_AHB 12 -#define SDX75_MASTER_IPA 13 -#define SDX75_MASTER_IPA_PCIE 14 -#define SDX75_MASTER_LLCC 15 -#define SDX75_MASTER_MSS_PROC 16 -#define SDX75_MASTER_MVMSS 17 -#define SDX75_MASTER_PCIE_0 18 -#define SDX75_MASTER_PCIE_1 19 -#define SDX75_MASTER_PCIE_2 20 -#define SDX75_MASTER_PCIE_ANOC_CFG 21 -#define SDX75_MASTER_PCIE_RSCC 22 -#define SDX75_MASTER_QDSS_BAM 23 -#define SDX75_MASTER_QDSS_ETR 24 -#define SDX75_MASTER_QDSS_ETR_1 25 -#define SDX75_MASTER_QPIC 26 -#define SDX75_MASTER_QPIC_CORE 27 -#define SDX75_MASTER_QUP_0 28 -#define SDX75_MASTER_QUP_CORE_0 29 -#define SDX75_MASTER_SDCC_1 30 -#define SDX75_MASTER_SDCC_4 31 -#define SDX75_MASTER_SNOC_CFG 32 -#define SDX75_MASTER_SNOC_SF_MEM_NOC 33 -#define SDX75_MASTER_SYS_TCU 34 -#define SDX75_MASTER_USB3_0 35 -#define SDX75_SLAVE_A1NOC_CFG 36 -#define SDX75_SLAVE_ANOC_PCIE_GEM_NOC 37 -#define SDX75_SLAVE_AUDIO 38 -#define SDX75_SLAVE_CLK_CTL 39 -#define SDX75_SLAVE_CRYPTO_0_CFG 40 -#define SDX75_SLAVE_CNOC_MSS 41 -#define SDX75_SLAVE_DDRSS_CFG 42 -#define SDX75_SLAVE_EBI1 43 -#define SDX75_SLAVE_ETH0_CFG 44 -#define SDX75_SLAVE_ETH1_CFG 45 -#define SDX75_SLAVE_GEM_NOC_CFG 46 -#define SDX75_SLAVE_GEM_NOC_CNOC 47 -#define SDX75_SLAVE_ICBDI_MVMSS_CFG 48 -#define SDX75_SLAVE_IMEM 49 -#define SDX75_SLAVE_IMEM_CFG 50 -#define SDX75_SLAVE_IPA_CFG 51 -#define SDX75_SLAVE_IPC_ROUTER_CFG 52 -#define SDX75_SLAVE_LAGG_CFG 53 -#define SDX75_SLAVE_LLCC 54 -#define SDX75_SLAVE_MCCC_MASTER 55 -#define SDX75_SLAVE_MEM_NOC_PCIE_SNOC 56 -#define SDX75_SLAVE_PCIE_0 57 -#define SDX75_SLAVE_PCIE_1 58 -#define SDX75_SLAVE_PCIE_2 59 -#define SDX75_SLAVE_PCIE_0_CFG 60 -#define SDX75_SLAVE_PCIE_1_CFG 61 -#define SDX75_SLAVE_PCIE_2_CFG 62 -#define SDX75_SLAVE_PCIE_ANOC_CFG 63 -#define SDX75_SLAVE_PCIE_RSC_CFG 64 -#define SDX75_SLAVE_PDM 65 -#define SDX75_SLAVE_PRNG 66 -#define SDX75_SLAVE_QDSS_CFG 67 -#define SDX75_SLAVE_QDSS_STM 68 -#define SDX75_SLAVE_QPIC 69 -#define SDX75_SLAVE_QPIC_CORE 70 -#define SDX75_SLAVE_QUP_0 71 -#define SDX75_SLAVE_QUP_CORE_0 72 -#define SDX75_SLAVE_SDCC_1 73 -#define SDX75_SLAVE_SDCC_4 74 -#define SDX75_SLAVE_SERVICE_GEM_NOC 75 -#define SDX75_SLAVE_SERVICE_PCIE_ANOC 76 -#define SDX75_SLAVE_SERVICE_SNOC 77 -#define SDX75_SLAVE_SNOC_CFG 78 -#define SDX75_SLAVE_SNOC_GEM_NOC_SF 79 -#define SDX75_SLAVE_SNOOP_BWMON 80 -#define SDX75_SLAVE_SPMI_VGI_COEX 81 -#define SDX75_SLAVE_TCSR 82 -#define SDX75_SLAVE_TCU 83 -#define SDX75_SLAVE_TLMM 84 -#define SDX75_SLAVE_USB3 85 -#define SDX75_SLAVE_USB3_PHY_CFG 86 - -#endif --=20 2.47.3 From nobody Mon Feb 9 06:05:00 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3D0BF29C347 for ; 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This gives more flexibility and also allows us to drop the .num_links member, saving from possible errors related to it being not set or set incorrectly. Signed-off-by: Dmitry Baryshkov --- drivers/interconnect/qcom/sm6350.c | 639 ++++++++++++++++++---------------= ---- drivers/interconnect/qcom/sm6350.h | 139 -------- 2 files changed, 317 insertions(+), 461 deletions(-) diff --git a/drivers/interconnect/qcom/sm6350.c b/drivers/interconnect/qcom= /sm6350.c index f41d7e19ba269cba7cc07b0136a6d1fcccd8af4d..df2511dbfa96ba7454612ea0fcd= f4a8f5fc39540 100644 --- a/drivers/interconnect/qcom/sm6350.c +++ b/drivers/interconnect/qcom/sm6350.c @@ -13,1151 +13,1136 @@ =20 #include "bcm-voter.h" #include "icc-rpmh.h" -#include "sm6350.h" + +static struct qcom_icc_node qhm_a1noc_cfg; +static struct qcom_icc_node qhm_qup_0; +static struct qcom_icc_node xm_emmc; +static struct qcom_icc_node xm_ufs_mem; +static struct qcom_icc_node qhm_a2noc_cfg; +static struct qcom_icc_node qhm_qdss_bam; +static struct qcom_icc_node qhm_qup_1; +static struct qcom_icc_node qxm_crypto; +static struct qcom_icc_node qxm_ipa; +static struct qcom_icc_node xm_qdss_etr; +static struct qcom_icc_node xm_sdc2; +static struct qcom_icc_node xm_usb3_0; +static struct qcom_icc_node qxm_camnoc_hf0_uncomp; +static struct qcom_icc_node qxm_camnoc_icp_uncomp; +static struct qcom_icc_node qxm_camnoc_sf_uncomp; +static struct qcom_icc_node qup0_core_master; +static struct qcom_icc_node qup1_core_master; +static struct qcom_icc_node qnm_npu; +static struct qcom_icc_node qxm_npu_dsp; +static struct qcom_icc_node qnm_snoc; +static struct qcom_icc_node xm_qdss_dap; +static struct qcom_icc_node qhm_cnoc_dc_noc; +static struct qcom_icc_node acm_apps; +static struct qcom_icc_node acm_sys_tcu; +static struct qcom_icc_node qhm_gemnoc_cfg; +static struct qcom_icc_node qnm_cmpnoc; +static struct qcom_icc_node qnm_mnoc_hf; +static struct qcom_icc_node qnm_mnoc_sf; +static struct qcom_icc_node qnm_snoc_gc; +static struct qcom_icc_node qnm_snoc_sf; +static struct qcom_icc_node qxm_gpu; +static struct qcom_icc_node llcc_mc; +static struct qcom_icc_node qhm_mnoc_cfg; +static struct qcom_icc_node qnm_video0; +static struct qcom_icc_node qnm_video_cvp; +static struct qcom_icc_node qxm_camnoc_hf; +static struct qcom_icc_node qxm_camnoc_icp; +static struct qcom_icc_node qxm_camnoc_sf; +static struct qcom_icc_node qxm_mdp0; +static struct qcom_icc_node amm_npu_sys; +static struct qcom_icc_node qhm_npu_cfg; +static struct qcom_icc_node qhm_snoc_cfg; +static struct qcom_icc_node qnm_aggre1_noc; +static struct qcom_icc_node qnm_aggre2_noc; +static struct qcom_icc_node qnm_gemnoc; +static struct qcom_icc_node qxm_pimem; +static struct qcom_icc_node xm_gic; +static struct qcom_icc_node qns_a1noc_snoc; +static struct qcom_icc_node srvc_aggre1_noc; +static struct qcom_icc_node qns_a2noc_snoc; +static struct qcom_icc_node srvc_aggre2_noc; +static struct qcom_icc_node qns_camnoc_uncomp; +static struct qcom_icc_node qup0_core_slave; +static struct qcom_icc_node qup1_core_slave; +static struct qcom_icc_node qns_cdsp_gemnoc; +static struct qcom_icc_node qhs_a1_noc_cfg; +static struct qcom_icc_node qhs_a2_noc_cfg; +static struct qcom_icc_node qhs_ahb2phy0; +static struct qcom_icc_node qhs_ahb2phy2; +static struct qcom_icc_node qhs_aoss; +static struct qcom_icc_node qhs_boot_rom; +static struct qcom_icc_node qhs_camera_cfg; +static struct qcom_icc_node qhs_camera_nrt_thrott_cfg; +static struct qcom_icc_node qhs_camera_rt_throttle_cfg; +static struct qcom_icc_node qhs_clk_ctl; +static struct qcom_icc_node qhs_cpr_cx; +static struct qcom_icc_node qhs_cpr_mx; +static struct qcom_icc_node qhs_crypto0_cfg; +static struct qcom_icc_node qhs_dcc_cfg; +static struct qcom_icc_node qhs_ddrss_cfg; +static struct qcom_icc_node qhs_display_cfg; +static struct qcom_icc_node qhs_display_throttle_cfg; +static struct qcom_icc_node qhs_emmc_cfg; +static struct qcom_icc_node qhs_glm; +static struct qcom_icc_node qhs_gpuss_cfg; +static struct qcom_icc_node qhs_imem_cfg; +static struct qcom_icc_node qhs_ipa; +static struct qcom_icc_node qhs_mnoc_cfg; +static struct qcom_icc_node qhs_mss_cfg; +static struct qcom_icc_node qhs_npu_cfg; +static struct qcom_icc_node qhs_pdm; +static struct qcom_icc_node qhs_pimem_cfg; +static struct qcom_icc_node qhs_prng; +static struct qcom_icc_node qhs_qdss_cfg; +static struct qcom_icc_node qhs_qm_cfg; +static struct qcom_icc_node qhs_qm_mpu_cfg; +static struct qcom_icc_node qhs_qup0; +static struct qcom_icc_node qhs_qup1; +static struct qcom_icc_node qhs_sdc2; +static struct qcom_icc_node qhs_security; +static struct qcom_icc_node qhs_snoc_cfg; +static struct qcom_icc_node qhs_tcsr; +static struct qcom_icc_node qhs_ufs_mem_cfg; +static struct qcom_icc_node qhs_usb3_0; +static struct qcom_icc_node qhs_venus_cfg; +static struct qcom_icc_node qhs_venus_throttle_cfg; +static struct qcom_icc_node qhs_vsense_ctrl_cfg; +static struct qcom_icc_node srvc_cnoc; +static struct qcom_icc_node qhs_gemnoc; +static struct qcom_icc_node qhs_llcc; +static struct qcom_icc_node qhs_mcdma_ms_mpu_cfg; +static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg; +static struct qcom_icc_node qns_gem_noc_snoc; +static struct qcom_icc_node qns_llcc; +static struct qcom_icc_node srvc_gemnoc; +static struct qcom_icc_node ebi; +static struct qcom_icc_node qns_mem_noc_hf; +static struct qcom_icc_node qns_mem_noc_sf; +static struct qcom_icc_node srvc_mnoc; +static struct qcom_icc_node qhs_cal_dp0; +static struct qcom_icc_node qhs_cp; +static struct qcom_icc_node qhs_dma_bwmon; +static struct qcom_icc_node qhs_dpm; +static struct qcom_icc_node qhs_isense; +static struct qcom_icc_node qhs_llm; +static struct qcom_icc_node qhs_tcm; +static struct qcom_icc_node qns_npu_sys; +static struct qcom_icc_node srvc_noc; +static struct qcom_icc_node qhs_apss; +static struct qcom_icc_node qns_cnoc; +static struct qcom_icc_node qns_gemnoc_gc; +static struct qcom_icc_node qns_gemnoc_sf; +static struct qcom_icc_node qxs_imem; +static struct qcom_icc_node qxs_pimem; +static struct qcom_icc_node srvc_snoc; +static struct qcom_icc_node xs_qdss_stm; +static struct qcom_icc_node xs_sys_tcu_cfg; =20 static struct qcom_icc_node qhm_a1noc_cfg =3D { .name =3D "qhm_a1noc_cfg", - .id =3D SM6350_MASTER_A1NOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM6350_SLAVE_SERVICE_A1NOC }, + .link_nodes =3D { &srvc_aggre1_noc }, }; =20 static struct qcom_icc_node qhm_qup_0 =3D { .name =3D "qhm_qup_0", - .id =3D SM6350_MASTER_QUP_0, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM6350_A1NOC_SNOC_SLV }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node xm_emmc =3D { .name =3D "xm_emmc", - .id =3D SM6350_MASTER_EMMC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM6350_A1NOC_SNOC_SLV }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node xm_ufs_mem =3D { .name =3D "xm_ufs_mem", - .id =3D SM6350_MASTER_UFS_MEM, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM6350_A1NOC_SNOC_SLV }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node qhm_a2noc_cfg =3D { .name =3D "qhm_a2noc_cfg", - .id =3D SM6350_MASTER_A2NOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM6350_SLAVE_SERVICE_A2NOC }, + .link_nodes =3D { &srvc_aggre2_noc }, }; =20 static struct qcom_icc_node qhm_qdss_bam =3D { .name =3D "qhm_qdss_bam", - .id =3D SM6350_MASTER_QDSS_BAM, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM6350_A2NOC_SNOC_SLV }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qhm_qup_1 =3D { .name =3D "qhm_qup_1", - .id =3D SM6350_MASTER_QUP_1, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM6350_A2NOC_SNOC_SLV }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qxm_crypto =3D { .name =3D "qxm_crypto", - .id =3D SM6350_MASTER_CRYPTO_CORE_0, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM6350_A2NOC_SNOC_SLV }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qxm_ipa =3D { .name =3D "qxm_ipa", - .id =3D SM6350_MASTER_IPA, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM6350_A2NOC_SNOC_SLV }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node xm_qdss_etr =3D { .name =3D "xm_qdss_etr", - .id =3D SM6350_MASTER_QDSS_ETR, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM6350_A2NOC_SNOC_SLV }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node xm_sdc2 =3D { .name =3D "xm_sdc2", - .id =3D SM6350_MASTER_SDCC_2, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM6350_A2NOC_SNOC_SLV }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node xm_usb3_0 =3D { .name =3D "xm_usb3_0", - .id =3D SM6350_MASTER_USB3, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM6350_A2NOC_SNOC_SLV }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qxm_camnoc_hf0_uncomp =3D { .name =3D "qxm_camnoc_hf0_uncomp", - .id =3D SM6350_MASTER_CAMNOC_HF0_UNCOMP, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM6350_SLAVE_CAMNOC_UNCOMP }, + .link_nodes =3D { &qns_camnoc_uncomp }, }; =20 static struct qcom_icc_node qxm_camnoc_icp_uncomp =3D { .name =3D "qxm_camnoc_icp_uncomp", - .id =3D SM6350_MASTER_CAMNOC_ICP_UNCOMP, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM6350_SLAVE_CAMNOC_UNCOMP }, + .link_nodes =3D { &qns_camnoc_uncomp }, }; =20 static struct qcom_icc_node qxm_camnoc_sf_uncomp =3D { .name =3D "qxm_camnoc_sf_uncomp", - .id =3D SM6350_MASTER_CAMNOC_SF_UNCOMP, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM6350_SLAVE_CAMNOC_UNCOMP }, + .link_nodes =3D { &qns_camnoc_uncomp }, }; =20 static struct qcom_icc_node qup0_core_master =3D { .name =3D "qup0_core_master", - .id =3D SM6350_MASTER_QUP_CORE_0, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM6350_SLAVE_QUP_CORE_0 }, + .link_nodes =3D { &qup0_core_slave }, }; =20 static struct qcom_icc_node qup1_core_master =3D { .name =3D "qup1_core_master", - .id =3D SM6350_MASTER_QUP_CORE_1, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM6350_SLAVE_QUP_CORE_1 }, + .link_nodes =3D { &qup1_core_slave }, }; =20 static struct qcom_icc_node qnm_npu =3D { .name =3D "qnm_npu", - .id =3D SM6350_MASTER_NPU, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM6350_SLAVE_CDSP_GEM_NOC }, + .link_nodes =3D { &qns_cdsp_gemnoc }, }; =20 static struct qcom_icc_node qxm_npu_dsp =3D { .name =3D "qxm_npu_dsp", - .id =3D SM6350_MASTER_NPU_PROC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM6350_SLAVE_CDSP_GEM_NOC }, + .link_nodes =3D { &qns_cdsp_gemnoc }, }; =20 static struct qcom_icc_node qnm_snoc =3D { .name =3D "qnm_snoc", - .id =3D SM6350_SNOC_CNOC_MAS, .channels =3D 1, .buswidth =3D 8, .num_links =3D 42, - .links =3D { SM6350_SLAVE_CAMERA_CFG, - SM6350_SLAVE_SDCC_2, - SM6350_SLAVE_CNOC_MNOC_CFG, - SM6350_SLAVE_UFS_MEM_CFG, - SM6350_SLAVE_QM_CFG, - SM6350_SLAVE_SNOC_CFG, - SM6350_SLAVE_QM_MPU_CFG, - SM6350_SLAVE_GLM, - SM6350_SLAVE_PDM, - SM6350_SLAVE_CAMERA_NRT_THROTTLE_CFG, - SM6350_SLAVE_A2NOC_CFG, - SM6350_SLAVE_QDSS_CFG, - SM6350_SLAVE_VSENSE_CTRL_CFG, - SM6350_SLAVE_CAMERA_RT_THROTTLE_CFG, - SM6350_SLAVE_DISPLAY_CFG, - SM6350_SLAVE_TCSR, - SM6350_SLAVE_DCC_CFG, - SM6350_SLAVE_CNOC_DDRSS, - SM6350_SLAVE_DISPLAY_THROTTLE_CFG, - SM6350_SLAVE_NPU_CFG, - SM6350_SLAVE_AHB2PHY, - SM6350_SLAVE_GRAPHICS_3D_CFG, - SM6350_SLAVE_BOOT_ROM, - SM6350_SLAVE_VENUS_CFG, - SM6350_SLAVE_IPA_CFG, - SM6350_SLAVE_SECURITY, - SM6350_SLAVE_IMEM_CFG, - SM6350_SLAVE_CNOC_MSS, - SM6350_SLAVE_SERVICE_CNOC, - SM6350_SLAVE_USB3, - SM6350_SLAVE_VENUS_THROTTLE_CFG, - SM6350_SLAVE_RBCPR_CX_CFG, - SM6350_SLAVE_A1NOC_CFG, - SM6350_SLAVE_AOSS, - SM6350_SLAVE_PRNG, - SM6350_SLAVE_EMMC_CFG, - SM6350_SLAVE_CRYPTO_0_CFG, - SM6350_SLAVE_PIMEM_CFG, - SM6350_SLAVE_RBCPR_MX_CFG, - SM6350_SLAVE_QUP_0, - SM6350_SLAVE_QUP_1, - SM6350_SLAVE_CLK_CTL - }, + .link_nodes =3D { &qhs_camera_cfg, + &qhs_sdc2, + &qhs_mnoc_cfg, + &qhs_ufs_mem_cfg, + &qhs_qm_cfg, + &qhs_snoc_cfg, + &qhs_qm_mpu_cfg, + &qhs_glm, + &qhs_pdm, + &qhs_camera_nrt_thrott_cfg, + &qhs_a2_noc_cfg, + &qhs_qdss_cfg, + &qhs_vsense_ctrl_cfg, + &qhs_camera_rt_throttle_cfg, + &qhs_display_cfg, + &qhs_tcsr, + &qhs_dcc_cfg, + &qhs_ddrss_cfg, + &qhs_display_throttle_cfg, + &qhs_npu_cfg, + &qhs_ahb2phy0, + &qhs_gpuss_cfg, + &qhs_boot_rom, + &qhs_venus_cfg, + &qhs_ipa, + &qhs_security, + &qhs_imem_cfg, + &qhs_mss_cfg, + &srvc_cnoc, + &qhs_usb3_0, + &qhs_venus_throttle_cfg, + &qhs_cpr_cx, + &qhs_a1_noc_cfg, + &qhs_aoss, + &qhs_prng, + &qhs_emmc_cfg, + &qhs_crypto0_cfg, + &qhs_pimem_cfg, + &qhs_cpr_mx, + &qhs_qup0, + &qhs_qup1, + &qhs_clk_ctl }, }; =20 static struct qcom_icc_node xm_qdss_dap =3D { .name =3D "xm_qdss_dap", - .id =3D SM6350_MASTER_QDSS_DAP, .channels =3D 1, .buswidth =3D 8, .num_links =3D 42, - .links =3D { SM6350_SLAVE_CAMERA_CFG, - SM6350_SLAVE_SDCC_2, - SM6350_SLAVE_CNOC_MNOC_CFG, - SM6350_SLAVE_UFS_MEM_CFG, - SM6350_SLAVE_QM_CFG, - SM6350_SLAVE_SNOC_CFG, - SM6350_SLAVE_QM_MPU_CFG, - SM6350_SLAVE_GLM, - SM6350_SLAVE_PDM, - SM6350_SLAVE_CAMERA_NRT_THROTTLE_CFG, - SM6350_SLAVE_A2NOC_CFG, - SM6350_SLAVE_QDSS_CFG, - SM6350_SLAVE_VSENSE_CTRL_CFG, - SM6350_SLAVE_CAMERA_RT_THROTTLE_CFG, - SM6350_SLAVE_DISPLAY_CFG, - SM6350_SLAVE_TCSR, - SM6350_SLAVE_DCC_CFG, - SM6350_SLAVE_CNOC_DDRSS, - SM6350_SLAVE_DISPLAY_THROTTLE_CFG, - SM6350_SLAVE_NPU_CFG, - SM6350_SLAVE_AHB2PHY, - SM6350_SLAVE_GRAPHICS_3D_CFG, - SM6350_SLAVE_BOOT_ROM, - SM6350_SLAVE_VENUS_CFG, - SM6350_SLAVE_IPA_CFG, - SM6350_SLAVE_SECURITY, - SM6350_SLAVE_IMEM_CFG, - SM6350_SLAVE_CNOC_MSS, - SM6350_SLAVE_SERVICE_CNOC, - SM6350_SLAVE_USB3, - SM6350_SLAVE_VENUS_THROTTLE_CFG, - SM6350_SLAVE_RBCPR_CX_CFG, - SM6350_SLAVE_A1NOC_CFG, - SM6350_SLAVE_AOSS, - SM6350_SLAVE_PRNG, - SM6350_SLAVE_EMMC_CFG, - SM6350_SLAVE_CRYPTO_0_CFG, - SM6350_SLAVE_PIMEM_CFG, - SM6350_SLAVE_RBCPR_MX_CFG, - SM6350_SLAVE_QUP_0, - SM6350_SLAVE_QUP_1, - SM6350_SLAVE_CLK_CTL - }, + .link_nodes =3D { &qhs_camera_cfg, + &qhs_sdc2, + &qhs_mnoc_cfg, + &qhs_ufs_mem_cfg, + &qhs_qm_cfg, + &qhs_snoc_cfg, + &qhs_qm_mpu_cfg, + &qhs_glm, + &qhs_pdm, + &qhs_camera_nrt_thrott_cfg, + &qhs_a2_noc_cfg, + &qhs_qdss_cfg, + &qhs_vsense_ctrl_cfg, + &qhs_camera_rt_throttle_cfg, + &qhs_display_cfg, + &qhs_tcsr, + &qhs_dcc_cfg, + &qhs_ddrss_cfg, + &qhs_display_throttle_cfg, + &qhs_npu_cfg, + &qhs_ahb2phy0, + &qhs_gpuss_cfg, + &qhs_boot_rom, + &qhs_venus_cfg, + &qhs_ipa, + &qhs_security, + &qhs_imem_cfg, + &qhs_mss_cfg, + &srvc_cnoc, + &qhs_usb3_0, + &qhs_venus_throttle_cfg, + &qhs_cpr_cx, + &qhs_a1_noc_cfg, + &qhs_aoss, + &qhs_prng, + &qhs_emmc_cfg, + &qhs_crypto0_cfg, + &qhs_pimem_cfg, + &qhs_cpr_mx, + &qhs_qup0, + &qhs_qup1, + &qhs_clk_ctl }, }; =20 static struct qcom_icc_node qhm_cnoc_dc_noc =3D { .name =3D "qhm_cnoc_dc_noc", - .id =3D SM6350_MASTER_CNOC_DC_NOC, .channels =3D 1, .buswidth =3D 4, .num_links =3D 2, - .links =3D { SM6350_SLAVE_LLCC_CFG, - SM6350_SLAVE_GEM_NOC_CFG - }, + .link_nodes =3D { &qhs_llcc, + &qhs_gemnoc }, }; =20 static struct qcom_icc_node acm_apps =3D { .name =3D "acm_apps", - .id =3D SM6350_MASTER_AMPSS_M0, .channels =3D 1, .buswidth =3D 16, .num_links =3D 2, - .links =3D { SM6350_SLAVE_LLCC, - SM6350_SLAVE_GEM_NOC_SNOC - }, + .link_nodes =3D { &qns_llcc, + &qns_gem_noc_snoc }, }; =20 static struct qcom_icc_node acm_sys_tcu =3D { .name =3D "acm_sys_tcu", - .id =3D SM6350_MASTER_SYS_TCU, .channels =3D 1, .buswidth =3D 8, .num_links =3D 2, - .links =3D { SM6350_SLAVE_LLCC, - SM6350_SLAVE_GEM_NOC_SNOC - }, + .link_nodes =3D { &qns_llcc, + &qns_gem_noc_snoc }, }; =20 static struct qcom_icc_node qhm_gemnoc_cfg =3D { .name =3D "qhm_gemnoc_cfg", - .id =3D SM6350_MASTER_GEM_NOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 3, - .links =3D { SM6350_SLAVE_MCDMA_MS_MPU_CFG, - SM6350_SLAVE_SERVICE_GEM_NOC, - SM6350_SLAVE_MSS_PROC_MS_MPU_CFG - }, + .link_nodes =3D { &qhs_mcdma_ms_mpu_cfg, + &srvc_gemnoc, + &qhs_mdsp_ms_mpu_cfg }, }; =20 static struct qcom_icc_node qnm_cmpnoc =3D { .name =3D "qnm_cmpnoc", - .id =3D SM6350_MASTER_COMPUTE_NOC, .channels =3D 1, .buswidth =3D 32, .num_links =3D 2, - .links =3D { SM6350_SLAVE_LLCC, - SM6350_SLAVE_GEM_NOC_SNOC - }, + .link_nodes =3D { &qns_llcc, + &qns_gem_noc_snoc }, }; =20 static struct qcom_icc_node qnm_mnoc_hf =3D { .name =3D "qnm_mnoc_hf", - .id =3D SM6350_MASTER_MNOC_HF_MEM_NOC, .channels =3D 1, .buswidth =3D 32, .num_links =3D 2, - .links =3D { SM6350_SLAVE_LLCC, - SM6350_SLAVE_GEM_NOC_SNOC - }, + .link_nodes =3D { &qns_llcc, + &qns_gem_noc_snoc }, }; =20 static struct qcom_icc_node qnm_mnoc_sf =3D { .name =3D "qnm_mnoc_sf", - .id =3D SM6350_MASTER_MNOC_SF_MEM_NOC, .channels =3D 1, .buswidth =3D 32, .num_links =3D 2, - .links =3D { SM6350_SLAVE_LLCC, - SM6350_SLAVE_GEM_NOC_SNOC - }, + .link_nodes =3D { &qns_llcc, + &qns_gem_noc_snoc }, }; =20 static struct qcom_icc_node qnm_snoc_gc =3D { .name =3D "qnm_snoc_gc", - .id =3D SM6350_MASTER_SNOC_GC_MEM_NOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM6350_SLAVE_LLCC }, + .link_nodes =3D { &qns_llcc }, }; =20 static struct qcom_icc_node qnm_snoc_sf =3D { .name =3D "qnm_snoc_sf", - .id =3D SM6350_MASTER_SNOC_SF_MEM_NOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM6350_SLAVE_LLCC }, + .link_nodes =3D { &qns_llcc }, }; =20 static struct qcom_icc_node qxm_gpu =3D { .name =3D "qxm_gpu", - .id =3D SM6350_MASTER_GRAPHICS_3D, .channels =3D 2, .buswidth =3D 32, .num_links =3D 2, - .links =3D { SM6350_SLAVE_LLCC, - SM6350_SLAVE_GEM_NOC_SNOC - }, + .link_nodes =3D { &qns_llcc, + &qns_gem_noc_snoc }, }; =20 static struct qcom_icc_node llcc_mc =3D { .name =3D "llcc_mc", - .id =3D SM6350_MASTER_LLCC, .channels =3D 2, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM6350_SLAVE_EBI_CH0 }, + .link_nodes =3D { &ebi }, }; =20 static struct qcom_icc_node qhm_mnoc_cfg =3D { .name =3D "qhm_mnoc_cfg", - .id =3D SM6350_MASTER_CNOC_MNOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM6350_SLAVE_SERVICE_MNOC }, + .link_nodes =3D { &srvc_mnoc }, }; =20 static struct qcom_icc_node qnm_video0 =3D { .name =3D "qnm_video0", - .id =3D SM6350_MASTER_VIDEO_P0, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM6350_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static struct qcom_icc_node qnm_video_cvp =3D { .name =3D "qnm_video_cvp", - .id =3D SM6350_MASTER_VIDEO_PROC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM6350_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static struct qcom_icc_node qxm_camnoc_hf =3D { .name =3D "qxm_camnoc_hf", - .id =3D SM6350_MASTER_CAMNOC_HF, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM6350_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_hf }, }; =20 static struct qcom_icc_node qxm_camnoc_icp =3D { .name =3D "qxm_camnoc_icp", - .id =3D SM6350_MASTER_CAMNOC_ICP, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM6350_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static struct qcom_icc_node qxm_camnoc_sf =3D { .name =3D "qxm_camnoc_sf", - .id =3D SM6350_MASTER_CAMNOC_SF, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM6350_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static struct qcom_icc_node qxm_mdp0 =3D { .name =3D "qxm_mdp0", - .id =3D SM6350_MASTER_MDP_PORT0, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM6350_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_hf }, }; =20 static struct qcom_icc_node amm_npu_sys =3D { .name =3D "amm_npu_sys", - .id =3D SM6350_MASTER_NPU_SYS, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM6350_SLAVE_NPU_COMPUTE_NOC }, + .link_nodes =3D { &qns_npu_sys }, }; =20 static struct qcom_icc_node qhm_npu_cfg =3D { .name =3D "qhm_npu_cfg", - .id =3D SM6350_MASTER_NPU_NOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 8, - .links =3D { SM6350_SLAVE_SERVICE_NPU_NOC, - SM6350_SLAVE_ISENSE_CFG, - SM6350_SLAVE_NPU_LLM_CFG, - SM6350_SLAVE_NPU_INT_DMA_BWMON_CFG, - SM6350_SLAVE_NPU_CP, - SM6350_SLAVE_NPU_TCM, - SM6350_SLAVE_NPU_CAL_DP0, - SM6350_SLAVE_NPU_DPM - }, + .link_nodes =3D { &srvc_noc, + &qhs_isense, + &qhs_llm, + &qhs_dma_bwmon, + &qhs_cp, + &qhs_tcm, + &qhs_cal_dp0, + &qhs_dpm }, }; =20 static struct qcom_icc_node qhm_snoc_cfg =3D { .name =3D "qhm_snoc_cfg", - .id =3D SM6350_MASTER_SNOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM6350_SLAVE_SERVICE_SNOC }, + .link_nodes =3D { &srvc_snoc }, }; =20 static struct qcom_icc_node qnm_aggre1_noc =3D { .name =3D "qnm_aggre1_noc", - .id =3D SM6350_A1NOC_SNOC_MAS, .channels =3D 1, .buswidth =3D 16, .num_links =3D 6, - .links =3D { SM6350_SLAVE_SNOC_GEM_NOC_SF, - SM6350_SLAVE_PIMEM, - SM6350_SLAVE_OCIMEM, - SM6350_SLAVE_APPSS, - SM6350_SNOC_CNOC_SLV, - SM6350_SLAVE_QDSS_STM - }, + .link_nodes =3D { &qns_gemnoc_sf, + &qxs_pimem, + &qxs_imem, + &qhs_apss, + &qns_cnoc, + &xs_qdss_stm }, }; =20 static struct qcom_icc_node qnm_aggre2_noc =3D { .name =3D "qnm_aggre2_noc", - .id =3D SM6350_A2NOC_SNOC_MAS, .channels =3D 1, .buswidth =3D 16, .num_links =3D 7, - .links =3D { SM6350_SLAVE_SNOC_GEM_NOC_SF, - SM6350_SLAVE_PIMEM, - SM6350_SLAVE_OCIMEM, - SM6350_SLAVE_APPSS, - SM6350_SNOC_CNOC_SLV, - SM6350_SLAVE_TCU, - SM6350_SLAVE_QDSS_STM - }, + .link_nodes =3D { &qns_gemnoc_sf, + &qxs_pimem, + &qxs_imem, + &qhs_apss, + &qns_cnoc, + &xs_sys_tcu_cfg, + &xs_qdss_stm }, }; =20 static struct qcom_icc_node qnm_gemnoc =3D { .name =3D "qnm_gemnoc", - .id =3D SM6350_MASTER_GEM_NOC_SNOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 6, - .links =3D { SM6350_SLAVE_PIMEM, - SM6350_SLAVE_OCIMEM, - SM6350_SLAVE_APPSS, - SM6350_SNOC_CNOC_SLV, - SM6350_SLAVE_TCU, - SM6350_SLAVE_QDSS_STM - }, + .link_nodes =3D { &qxs_pimem, + &qxs_imem, + &qhs_apss, + &qns_cnoc, + &xs_sys_tcu_cfg, + &xs_qdss_stm }, }; =20 static struct qcom_icc_node qxm_pimem =3D { .name =3D "qxm_pimem", - .id =3D SM6350_MASTER_PIMEM, .channels =3D 1, .buswidth =3D 8, .num_links =3D 2, - .links =3D { SM6350_SLAVE_SNOC_GEM_NOC_GC, - SM6350_SLAVE_OCIMEM - }, + .link_nodes =3D { &qns_gemnoc_gc, + &qxs_imem }, }; =20 static struct qcom_icc_node xm_gic =3D { .name =3D "xm_gic", - .id =3D SM6350_MASTER_GIC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM6350_SLAVE_SNOC_GEM_NOC_GC }, + .link_nodes =3D { &qns_gemnoc_gc }, }; =20 static struct qcom_icc_node qns_a1noc_snoc =3D { .name =3D "qns_a1noc_snoc", - .id =3D SM6350_A1NOC_SNOC_SLV, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM6350_A1NOC_SNOC_MAS }, + .link_nodes =3D { &qnm_aggre1_noc }, }; =20 static struct qcom_icc_node srvc_aggre1_noc =3D { .name =3D "srvc_aggre1_noc", - .id =3D SM6350_SLAVE_SERVICE_A1NOC, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qns_a2noc_snoc =3D { .name =3D "qns_a2noc_snoc", - .id =3D SM6350_A2NOC_SNOC_SLV, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM6350_A2NOC_SNOC_MAS }, + .link_nodes =3D { &qnm_aggre2_noc }, }; =20 static struct qcom_icc_node srvc_aggre2_noc =3D { .name =3D "srvc_aggre2_noc", - .id =3D SM6350_SLAVE_SERVICE_A2NOC, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qns_camnoc_uncomp =3D { .name =3D "qns_camnoc_uncomp", - .id =3D SM6350_SLAVE_CAMNOC_UNCOMP, .channels =3D 1, .buswidth =3D 32, }; =20 static struct qcom_icc_node qup0_core_slave =3D { .name =3D "qup0_core_slave", - .id =3D SM6350_SLAVE_QUP_CORE_0, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qup1_core_slave =3D { .name =3D "qup1_core_slave", - .id =3D SM6350_SLAVE_QUP_CORE_1, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qns_cdsp_gemnoc =3D { .name =3D "qns_cdsp_gemnoc", - .id =3D SM6350_SLAVE_CDSP_GEM_NOC, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM6350_MASTER_COMPUTE_NOC }, + .link_nodes =3D { &qnm_cmpnoc }, }; =20 static struct qcom_icc_node qhs_a1_noc_cfg =3D { .name =3D "qhs_a1_noc_cfg", - .id =3D SM6350_SLAVE_A1NOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM6350_MASTER_A1NOC_CFG }, + .link_nodes =3D { &qhm_a1noc_cfg }, }; =20 static struct qcom_icc_node qhs_a2_noc_cfg =3D { .name =3D "qhs_a2_noc_cfg", - .id =3D SM6350_SLAVE_A2NOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM6350_MASTER_A2NOC_CFG }, + .link_nodes =3D { &qhm_a2noc_cfg }, }; =20 static struct qcom_icc_node qhs_ahb2phy0 =3D { .name =3D "qhs_ahb2phy0", - .id =3D SM6350_SLAVE_AHB2PHY, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_ahb2phy2 =3D { .name =3D "qhs_ahb2phy2", - .id =3D SM6350_SLAVE_AHB2PHY_2, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_aoss =3D { .name =3D "qhs_aoss", - .id =3D SM6350_SLAVE_AOSS, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_boot_rom =3D { .name =3D "qhs_boot_rom", - .id =3D SM6350_SLAVE_BOOT_ROM, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_camera_cfg =3D { .name =3D "qhs_camera_cfg", - .id =3D SM6350_SLAVE_CAMERA_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_camera_nrt_thrott_cfg =3D { .name =3D "qhs_camera_nrt_thrott_cfg", - .id =3D SM6350_SLAVE_CAMERA_NRT_THROTTLE_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_camera_rt_throttle_cfg =3D { .name =3D "qhs_camera_rt_throttle_cfg", - .id =3D SM6350_SLAVE_CAMERA_RT_THROTTLE_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_clk_ctl =3D { .name =3D "qhs_clk_ctl", - .id =3D SM6350_SLAVE_CLK_CTL, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_cpr_cx =3D { .name =3D "qhs_cpr_cx", - .id =3D SM6350_SLAVE_RBCPR_CX_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_cpr_mx =3D { .name =3D "qhs_cpr_mx", - .id =3D SM6350_SLAVE_RBCPR_MX_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_crypto0_cfg =3D { .name =3D "qhs_crypto0_cfg", - .id =3D SM6350_SLAVE_CRYPTO_0_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_dcc_cfg =3D { .name =3D "qhs_dcc_cfg", - .id =3D SM6350_SLAVE_DCC_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_ddrss_cfg =3D { .name =3D "qhs_ddrss_cfg", - .id =3D SM6350_SLAVE_CNOC_DDRSS, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM6350_MASTER_CNOC_DC_NOC }, + .link_nodes =3D { &qhm_cnoc_dc_noc }, }; =20 static struct qcom_icc_node qhs_display_cfg =3D { .name =3D "qhs_display_cfg", - .id =3D SM6350_SLAVE_DISPLAY_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_display_throttle_cfg =3D { .name =3D "qhs_display_throttle_cfg", - .id =3D SM6350_SLAVE_DISPLAY_THROTTLE_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_emmc_cfg =3D { .name =3D "qhs_emmc_cfg", - .id =3D SM6350_SLAVE_EMMC_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_glm =3D { .name =3D "qhs_glm", - .id =3D SM6350_SLAVE_GLM, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_gpuss_cfg =3D { .name =3D "qhs_gpuss_cfg", - .id =3D SM6350_SLAVE_GRAPHICS_3D_CFG, .channels =3D 1, .buswidth =3D 8, }; =20 static struct qcom_icc_node qhs_imem_cfg =3D { .name =3D "qhs_imem_cfg", - .id =3D SM6350_SLAVE_IMEM_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_ipa =3D { .name =3D "qhs_ipa", - .id =3D SM6350_SLAVE_IPA_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_mnoc_cfg =3D { .name =3D "qhs_mnoc_cfg", - .id =3D SM6350_SLAVE_CNOC_MNOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM6350_MASTER_CNOC_MNOC_CFG }, + .link_nodes =3D { &qhm_mnoc_cfg }, }; =20 static struct qcom_icc_node qhs_mss_cfg =3D { .name =3D "qhs_mss_cfg", - .id =3D SM6350_SLAVE_CNOC_MSS, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_npu_cfg =3D { .name =3D "qhs_npu_cfg", - .id =3D SM6350_SLAVE_NPU_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM6350_MASTER_NPU_NOC_CFG }, + .link_nodes =3D { &qhm_npu_cfg }, }; =20 static struct qcom_icc_node qhs_pdm =3D { .name =3D "qhs_pdm", - .id =3D SM6350_SLAVE_PDM, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_pimem_cfg =3D { .name =3D "qhs_pimem_cfg", - .id =3D SM6350_SLAVE_PIMEM_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_prng =3D { .name =3D "qhs_prng", - .id =3D SM6350_SLAVE_PRNG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_qdss_cfg =3D { .name =3D "qhs_qdss_cfg", - .id =3D SM6350_SLAVE_QDSS_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_qm_cfg =3D { .name =3D "qhs_qm_cfg", - .id =3D SM6350_SLAVE_QM_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_qm_mpu_cfg =3D { .name =3D "qhs_qm_mpu_cfg", - .id =3D SM6350_SLAVE_QM_MPU_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_qup0 =3D { .name =3D "qhs_qup0", - .id =3D SM6350_SLAVE_QUP_0, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_qup1 =3D { .name =3D "qhs_qup1", - .id =3D SM6350_SLAVE_QUP_1, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_sdc2 =3D { .name =3D "qhs_sdc2", - .id =3D SM6350_SLAVE_SDCC_2, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_security =3D { .name =3D "qhs_security", - .id =3D SM6350_SLAVE_SECURITY, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_snoc_cfg =3D { .name =3D "qhs_snoc_cfg", - .id =3D SM6350_SLAVE_SNOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM6350_MASTER_SNOC_CFG }, + .link_nodes =3D { &qhm_snoc_cfg }, }; =20 static struct qcom_icc_node qhs_tcsr =3D { .name =3D "qhs_tcsr", - .id =3D SM6350_SLAVE_TCSR, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_ufs_mem_cfg =3D { .name =3D "qhs_ufs_mem_cfg", - .id =3D SM6350_SLAVE_UFS_MEM_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_usb3_0 =3D { .name =3D "qhs_usb3_0", - .id =3D SM6350_SLAVE_USB3, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_venus_cfg =3D { .name =3D "qhs_venus_cfg", - .id =3D SM6350_SLAVE_VENUS_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_venus_throttle_cfg =3D { .name =3D "qhs_venus_throttle_cfg", - .id =3D SM6350_SLAVE_VENUS_THROTTLE_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_vsense_ctrl_cfg =3D { .name =3D "qhs_vsense_ctrl_cfg", - .id =3D SM6350_SLAVE_VSENSE_CTRL_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node srvc_cnoc =3D { .name =3D "srvc_cnoc", - .id =3D SM6350_SLAVE_SERVICE_CNOC, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_gemnoc =3D { .name =3D "qhs_gemnoc", - .id =3D SM6350_SLAVE_GEM_NOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM6350_MASTER_GEM_NOC_CFG }, + .link_nodes =3D { &qhm_gemnoc_cfg }, }; =20 static struct qcom_icc_node qhs_llcc =3D { .name =3D "qhs_llcc", - .id =3D SM6350_SLAVE_LLCC_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_mcdma_ms_mpu_cfg =3D { .name =3D "qhs_mcdma_ms_mpu_cfg", - .id =3D SM6350_SLAVE_MCDMA_MS_MPU_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg =3D { .name =3D "qhs_mdsp_ms_mpu_cfg", - .id =3D SM6350_SLAVE_MSS_PROC_MS_MPU_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qns_gem_noc_snoc =3D { .name =3D "qns_gem_noc_snoc", - .id =3D SM6350_SLAVE_GEM_NOC_SNOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM6350_MASTER_GEM_NOC_SNOC }, + .link_nodes =3D { &qnm_gemnoc }, }; =20 static struct qcom_icc_node qns_llcc =3D { .name =3D "qns_llcc", - .id =3D SM6350_SLAVE_LLCC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM6350_MASTER_LLCC }, + .link_nodes =3D { &llcc_mc }, }; =20 static struct qcom_icc_node srvc_gemnoc =3D { .name =3D "srvc_gemnoc", - .id =3D SM6350_SLAVE_SERVICE_GEM_NOC, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node ebi =3D { .name =3D "ebi", - .id =3D SM6350_SLAVE_EBI_CH0, .channels =3D 2, .buswidth =3D 4, }; =20 static struct qcom_icc_node qns_mem_noc_hf =3D { .name =3D "qns_mem_noc_hf", - .id =3D SM6350_SLAVE_MNOC_HF_MEM_NOC, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM6350_MASTER_MNOC_HF_MEM_NOC }, + .link_nodes =3D { &qnm_mnoc_hf }, }; =20 static struct qcom_icc_node qns_mem_noc_sf =3D { .name =3D "qns_mem_noc_sf", - .id =3D SM6350_SLAVE_MNOC_SF_MEM_NOC, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM6350_MASTER_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qnm_mnoc_sf }, }; =20 static struct qcom_icc_node srvc_mnoc =3D { .name =3D "srvc_mnoc", - .id =3D SM6350_SLAVE_SERVICE_MNOC, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_cal_dp0 =3D { .name =3D "qhs_cal_dp0", - .id =3D SM6350_SLAVE_NPU_CAL_DP0, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_cp =3D { .name =3D "qhs_cp", - .id =3D SM6350_SLAVE_NPU_CP, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_dma_bwmon =3D { .name =3D "qhs_dma_bwmon", - .id =3D SM6350_SLAVE_NPU_INT_DMA_BWMON_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_dpm =3D { .name =3D "qhs_dpm", - .id =3D SM6350_SLAVE_NPU_DPM, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_isense =3D { .name =3D "qhs_isense", - .id =3D SM6350_SLAVE_ISENSE_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_llm =3D { .name =3D "qhs_llm", - .id =3D SM6350_SLAVE_NPU_LLM_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_tcm =3D { .name =3D "qhs_tcm", - .id =3D SM6350_SLAVE_NPU_TCM, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qns_npu_sys =3D { .name =3D "qns_npu_sys", - .id =3D SM6350_SLAVE_NPU_COMPUTE_NOC, .channels =3D 2, .buswidth =3D 32, }; =20 static struct qcom_icc_node srvc_noc =3D { .name =3D "srvc_noc", - .id =3D SM6350_SLAVE_SERVICE_NPU_NOC, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_apss =3D { .name =3D "qhs_apss", - .id =3D SM6350_SLAVE_APPSS, .channels =3D 1, .buswidth =3D 8, }; =20 static struct qcom_icc_node qns_cnoc =3D { .name =3D "qns_cnoc", - .id =3D SM6350_SNOC_CNOC_SLV, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM6350_SNOC_CNOC_MAS }, + .link_nodes =3D { &qnm_snoc }, }; =20 static struct qcom_icc_node qns_gemnoc_gc =3D { .name =3D "qns_gemnoc_gc", - .id =3D SM6350_SLAVE_SNOC_GEM_NOC_GC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM6350_MASTER_SNOC_GC_MEM_NOC }, + .link_nodes =3D { &qnm_snoc_gc }, }; =20 static struct qcom_icc_node qns_gemnoc_sf =3D { .name =3D "qns_gemnoc_sf", - .id =3D SM6350_SLAVE_SNOC_GEM_NOC_SF, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM6350_MASTER_SNOC_SF_MEM_NOC }, + .link_nodes =3D { &qnm_snoc_sf }, }; =20 static struct qcom_icc_node qxs_imem =3D { .name =3D "qxs_imem", - .id =3D SM6350_SLAVE_OCIMEM, .channels =3D 1, .buswidth =3D 8, }; =20 static struct qcom_icc_node qxs_pimem =3D { .name =3D "qxs_pimem", - .id =3D SM6350_SLAVE_PIMEM, .channels =3D 1, .buswidth =3D 8, }; =20 static struct qcom_icc_node srvc_snoc =3D { .name =3D "srvc_snoc", - .id =3D SM6350_SLAVE_SERVICE_SNOC, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node xs_qdss_stm =3D { .name =3D "xs_qdss_stm", - .id =3D SM6350_SLAVE_QDSS_STM, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node xs_sys_tcu_cfg =3D { .name =3D "xs_sys_tcu_cfg", - .id =3D SM6350_SLAVE_TCU, .channels =3D 1, .buswidth =3D 8, }; @@ -1404,6 +1389,7 @@ static struct qcom_icc_node * const aggre1_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sm6350_aggre1_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D aggre1_noc_nodes, .num_nodes =3D ARRAY_SIZE(aggre1_noc_nodes), .bcms =3D aggre1_noc_bcms, @@ -1429,6 +1415,7 @@ static struct qcom_icc_node * const aggre2_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sm6350_aggre2_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D aggre2_noc_nodes, .num_nodes =3D ARRAY_SIZE(aggre2_noc_nodes), .bcms =3D aggre2_noc_bcms, @@ -1456,6 +1443,7 @@ static struct qcom_icc_node * const clk_virt_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sm6350_clk_virt =3D { + .alloc_dyn_id =3D true, .nodes =3D clk_virt_nodes, .num_nodes =3D ARRAY_SIZE(clk_virt_nodes), .bcms =3D clk_virt_bcms, @@ -1475,6 +1463,7 @@ static struct qcom_icc_node * const compute_noc_nodes= [] =3D { }; =20 static const struct qcom_icc_desc sm6350_compute_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D compute_noc_nodes, .num_nodes =3D ARRAY_SIZE(compute_noc_nodes), .bcms =3D compute_noc_bcms, @@ -1535,6 +1524,7 @@ static struct qcom_icc_node * const config_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sm6350_config_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D config_noc_nodes, .num_nodes =3D ARRAY_SIZE(config_noc_nodes), .bcms =3D config_noc_bcms, @@ -1551,6 +1541,7 @@ static struct qcom_icc_node * const dc_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sm6350_dc_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D dc_noc_nodes, .num_nodes =3D ARRAY_SIZE(dc_noc_nodes), .bcms =3D dc_noc_bcms, @@ -1582,6 +1573,7 @@ static struct qcom_icc_node * const gem_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sm6350_gem_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D gem_noc_nodes, .num_nodes =3D ARRAY_SIZE(gem_noc_nodes), .bcms =3D gem_noc_bcms, @@ -1609,6 +1601,7 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sm6350_mmss_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D mmss_noc_nodes, .num_nodes =3D ARRAY_SIZE(mmss_noc_nodes), .bcms =3D mmss_noc_bcms, @@ -1633,6 +1626,7 @@ static struct qcom_icc_node * const npu_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sm6350_npu_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D npu_noc_nodes, .num_nodes =3D ARRAY_SIZE(npu_noc_nodes), .bcms =3D npu_noc_bcms, @@ -1669,6 +1663,7 @@ static struct qcom_icc_node * const system_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sm6350_system_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D system_noc_nodes, .num_nodes =3D ARRAY_SIZE(system_noc_nodes), .bcms =3D system_noc_bcms, diff --git a/drivers/interconnect/qcom/sm6350.h b/drivers/interconnect/qcom= /sm6350.h deleted file mode 100644 index 43cf2930c88a5ae1bc36600ab2b3661a4d11ca71..000000000000000000000000000= 0000000000000 --- a/drivers/interconnect/qcom/sm6350.h +++ /dev/null @@ -1,139 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Qualcomm #define SM6350 interconnect IDs - * - * Copyright (C) 2022 Luca Weiss - */ - -#ifndef __DRIVERS_INTERCONNECT_QCOM_SM6350_H -#define __DRIVERS_INTERCONNECT_QCOM_SM6350_H - -#define SM6350_A1NOC_SNOC_MAS 0 -#define SM6350_A1NOC_SNOC_SLV 1 -#define SM6350_A2NOC_SNOC_MAS 2 -#define SM6350_A2NOC_SNOC_SLV 3 -#define SM6350_MASTER_A1NOC_CFG 4 -#define SM6350_MASTER_A2NOC_CFG 5 -#define SM6350_MASTER_AMPSS_M0 6 -#define SM6350_MASTER_CAMNOC_HF 7 -#define SM6350_MASTER_CAMNOC_HF0_UNCOMP 8 -#define SM6350_MASTER_CAMNOC_ICP 9 -#define SM6350_MASTER_CAMNOC_ICP_UNCOMP 10 -#define SM6350_MASTER_CAMNOC_SF 11 -#define SM6350_MASTER_CAMNOC_SF_UNCOMP 12 -#define SM6350_MASTER_CNOC_DC_NOC 13 -#define SM6350_MASTER_CNOC_MNOC_CFG 14 -#define SM6350_MASTER_COMPUTE_NOC 15 -#define SM6350_MASTER_CRYPTO_CORE_0 16 -#define SM6350_MASTER_EMMC 17 -#define SM6350_MASTER_GEM_NOC_CFG 18 -#define SM6350_MASTER_GEM_NOC_SNOC 19 -#define SM6350_MASTER_GIC 20 -#define SM6350_MASTER_GRAPHICS_3D 21 -#define SM6350_MASTER_IPA 22 -#define SM6350_MASTER_LLCC 23 -#define SM6350_MASTER_MDP_PORT0 24 -#define SM6350_MASTER_MNOC_HF_MEM_NOC 25 -#define SM6350_MASTER_MNOC_SF_MEM_NOC 26 -#define SM6350_MASTER_NPU 27 -#define SM6350_MASTER_NPU_NOC_CFG 28 -#define SM6350_MASTER_NPU_PROC 29 -#define SM6350_MASTER_NPU_SYS 30 -#define SM6350_MASTER_PIMEM 31 -#define SM6350_MASTER_QDSS_BAM 32 -#define SM6350_MASTER_QDSS_DAP 33 -#define SM6350_MASTER_QDSS_ETR 34 -#define SM6350_MASTER_QUP_0 35 -#define SM6350_MASTER_QUP_1 36 -#define SM6350_MASTER_QUP_CORE_0 37 -#define SM6350_MASTER_QUP_CORE_1 38 -#define SM6350_MASTER_SDCC_2 39 -#define SM6350_MASTER_SNOC_CFG 40 -#define SM6350_MASTER_SNOC_GC_MEM_NOC 41 -#define SM6350_MASTER_SNOC_SF_MEM_NOC 42 -#define SM6350_MASTER_SYS_TCU 43 -#define SM6350_MASTER_UFS_MEM 44 -#define SM6350_MASTER_USB3 45 -#define SM6350_MASTER_VIDEO_P0 46 -#define SM6350_MASTER_VIDEO_PROC 47 -#define SM6350_SLAVE_A1NOC_CFG 48 -#define SM6350_SLAVE_A2NOC_CFG 49 -#define SM6350_SLAVE_AHB2PHY 50 -#define SM6350_SLAVE_AHB2PHY_2 51 -#define SM6350_SLAVE_AOSS 52 -#define SM6350_SLAVE_APPSS 53 -#define SM6350_SLAVE_BOOT_ROM 54 -#define SM6350_SLAVE_CAMERA_CFG 55 -#define SM6350_SLAVE_CAMERA_NRT_THROTTLE_CFG 56 -#define SM6350_SLAVE_CAMERA_RT_THROTTLE_CFG 57 -#define SM6350_SLAVE_CAMNOC_UNCOMP 58 -#define SM6350_SLAVE_CDSP_GEM_NOC 59 -#define SM6350_SLAVE_CLK_CTL 60 -#define SM6350_SLAVE_CNOC_DDRSS 61 -#define SM6350_SLAVE_CNOC_MNOC_CFG 62 -#define SM6350_SLAVE_CNOC_MSS 63 -#define SM6350_SLAVE_CRYPTO_0_CFG 64 -#define SM6350_SLAVE_DCC_CFG 65 -#define SM6350_SLAVE_DISPLAY_CFG 66 -#define SM6350_SLAVE_DISPLAY_THROTTLE_CFG 67 -#define SM6350_SLAVE_EBI_CH0 68 -#define SM6350_SLAVE_EMMC_CFG 69 -#define SM6350_SLAVE_GEM_NOC_CFG 70 -#define SM6350_SLAVE_GEM_NOC_SNOC 71 -#define SM6350_SLAVE_GLM 72 -#define SM6350_SLAVE_GRAPHICS_3D_CFG 73 -#define SM6350_SLAVE_IMEM_CFG 74 -#define SM6350_SLAVE_IPA_CFG 75 -#define SM6350_SLAVE_ISENSE_CFG 76 -#define SM6350_SLAVE_LLCC 77 -#define SM6350_SLAVE_LLCC_CFG 78 -#define SM6350_SLAVE_MCDMA_MS_MPU_CFG 79 -#define SM6350_SLAVE_MNOC_HF_MEM_NOC 80 -#define SM6350_SLAVE_MNOC_SF_MEM_NOC 81 -#define SM6350_SLAVE_MSS_PROC_MS_MPU_CFG 82 -#define SM6350_SLAVE_NPU_CAL_DP0 83 -#define SM6350_SLAVE_NPU_CFG 84 -#define SM6350_SLAVE_NPU_COMPUTE_NOC 85 -#define SM6350_SLAVE_NPU_CP 86 -#define SM6350_SLAVE_NPU_DPM 87 -#define SM6350_SLAVE_NPU_INT_DMA_BWMON_CFG 88 -#define SM6350_SLAVE_NPU_LLM_CFG 89 -#define SM6350_SLAVE_NPU_TCM 90 -#define SM6350_SLAVE_OCIMEM 91 -#define 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This gives more flexibility and also allows us to drop the .num_links member, saving from possible errors related to it being not set or set incorrectly. Signed-off-by: Dmitry Baryshkov --- drivers/interconnect/qcom/sm7150.c | 663 ++++++++++++++++++---------------= ---- drivers/interconnect/qcom/sm7150.h | 140 -------- 2 files changed, 329 insertions(+), 474 deletions(-) diff --git a/drivers/interconnect/qcom/sm7150.c b/drivers/interconnect/qcom= /sm7150.c index c8c77407cd508dfede2821b7d52bf9da54283bad..296cf350a08fb521ea12fce69a6= b1ab19b6c97a8 100644 --- a/drivers/interconnect/qcom/sm7150.c +++ b/drivers/interconnect/qcom/sm7150.c @@ -14,1169 +14,1154 @@ =20 #include "bcm-voter.h" #include "icc-rpmh.h" -#include "sm7150.h" + +static struct qcom_icc_node qhm_a1noc_cfg; +static struct qcom_icc_node qhm_qup_center; +static struct qcom_icc_node qhm_tsif; +static struct qcom_icc_node xm_emmc; +static struct qcom_icc_node xm_sdc2; +static struct qcom_icc_node xm_sdc4; +static struct qcom_icc_node xm_ufs_mem; +static struct qcom_icc_node qhm_a2noc_cfg; +static struct qcom_icc_node qhm_qdss_bam; +static struct qcom_icc_node qhm_qup_north; +static struct qcom_icc_node qnm_cnoc; +static struct qcom_icc_node qxm_crypto; +static struct qcom_icc_node qxm_ipa; +static struct qcom_icc_node xm_pcie3_0; +static struct qcom_icc_node xm_qdss_etr; +static struct qcom_icc_node xm_usb3_0; +static struct qcom_icc_node qxm_camnoc_hf0_uncomp; +static struct qcom_icc_node qxm_camnoc_rt_uncomp; +static struct qcom_icc_node qxm_camnoc_sf_uncomp; +static struct qcom_icc_node qxm_camnoc_nrt_uncomp; +static struct qcom_icc_node qnm_npu; +static struct qcom_icc_node qhm_spdm; +static struct qcom_icc_node qnm_snoc; +static struct qcom_icc_node xm_qdss_dap; +static struct qcom_icc_node qhm_cnoc_dc_noc; +static struct qcom_icc_node acm_apps; +static struct qcom_icc_node acm_sys_tcu; +static struct qcom_icc_node qhm_gemnoc_cfg; +static struct qcom_icc_node qnm_cmpnoc; +static struct qcom_icc_node qnm_mnoc_hf; +static struct qcom_icc_node qnm_mnoc_sf; +static struct qcom_icc_node qnm_pcie; +static struct qcom_icc_node qnm_snoc_gc; +static struct qcom_icc_node qnm_snoc_sf; +static struct qcom_icc_node qxm_gpu; +static struct qcom_icc_node llcc_mc; +static struct qcom_icc_node qhm_mnoc_cfg; +static struct qcom_icc_node qxm_camnoc_hf; +static struct qcom_icc_node qxm_camnoc_nrt; +static struct qcom_icc_node qxm_camnoc_rt; +static struct qcom_icc_node qxm_camnoc_sf; +static struct qcom_icc_node qxm_mdp0; +static struct qcom_icc_node qxm_mdp1; +static struct qcom_icc_node qxm_rot; +static struct qcom_icc_node qxm_venus0; +static struct qcom_icc_node qxm_venus1; +static struct qcom_icc_node qxm_venus_arm9; +static struct qcom_icc_node qhm_snoc_cfg; +static struct qcom_icc_node qnm_aggre1_noc; +static struct qcom_icc_node qnm_aggre2_noc; +static struct qcom_icc_node qnm_gemnoc; +static struct qcom_icc_node qxm_pimem; +static struct qcom_icc_node xm_gic; +static struct qcom_icc_node qns_a1noc_snoc; +static struct qcom_icc_node srvc_aggre1_noc; +static struct qcom_icc_node qns_a2noc_snoc; +static struct qcom_icc_node qns_pcie_gemnoc; +static struct qcom_icc_node srvc_aggre2_noc; +static struct qcom_icc_node qns_camnoc_uncomp; +static struct qcom_icc_node qns_cdsp_gemnoc; +static struct qcom_icc_node qhs_a1_noc_cfg; +static struct qcom_icc_node qhs_a2_noc_cfg; +static struct qcom_icc_node qhs_ahb2phy_north; +static struct qcom_icc_node qhs_ahb2phy_south; +static struct qcom_icc_node qhs_ahb2phy_west; +static struct qcom_icc_node qhs_aop; +static struct qcom_icc_node qhs_aoss; +static struct qcom_icc_node qhs_camera_cfg; +static struct qcom_icc_node qhs_camera_nrt_thrott_cfg; +static struct qcom_icc_node qhs_camera_rt_throttle_cfg; +static struct qcom_icc_node qhs_clk_ctl; +static struct qcom_icc_node qhs_compute_dsp_cfg; +static struct qcom_icc_node qhs_cpr_cx; +static struct qcom_icc_node qhs_cpr_mx; +static struct qcom_icc_node qhs_crypto0_cfg; +static struct qcom_icc_node qhs_ddrss_cfg; +static struct qcom_icc_node qhs_display_cfg; +static struct qcom_icc_node qhs_display_throttle_cfg; +static struct qcom_icc_node qhs_emmc_cfg; +static struct qcom_icc_node qhs_glm; +static struct qcom_icc_node qhs_gpuss_cfg; +static struct qcom_icc_node qhs_imem_cfg; +static struct qcom_icc_node qhs_ipa; +static struct qcom_icc_node qhs_mnoc_cfg; +static struct qcom_icc_node qhs_pcie_cfg; +static struct qcom_icc_node qhs_pdm; +static struct qcom_icc_node qhs_pimem_cfg; +static struct qcom_icc_node qhs_prng; +static struct qcom_icc_node qhs_qdss_cfg; +static struct qcom_icc_node qhs_qupv3_center; +static struct qcom_icc_node qhs_qupv3_north; +static struct qcom_icc_node qhs_sdc2; +static struct qcom_icc_node qhs_sdc4; +static struct qcom_icc_node qhs_snoc_cfg; +static struct qcom_icc_node qhs_spdm; +static struct qcom_icc_node qhs_tcsr; +static struct qcom_icc_node qhs_tlmm_north; +static struct qcom_icc_node qhs_tlmm_south; +static struct qcom_icc_node qhs_tlmm_west; +static struct qcom_icc_node qhs_tsif; +static struct qcom_icc_node qhs_ufs_mem_cfg; +static struct qcom_icc_node qhs_usb3_0; +static struct qcom_icc_node qhs_venus_cfg; +static struct qcom_icc_node qhs_venus_cvp_throttle_cfg; +static struct qcom_icc_node qhs_venus_throttle_cfg; +static struct qcom_icc_node qhs_vsense_ctrl_cfg; +static struct qcom_icc_node qns_cnoc_a2noc; +static struct qcom_icc_node srvc_cnoc; +static struct qcom_icc_node qhs_gemnoc; +static struct qcom_icc_node qhs_llcc; +static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg; +static struct qcom_icc_node qns_gem_noc_snoc; +static struct qcom_icc_node qns_llcc; +static struct qcom_icc_node srvc_gemnoc; +static struct qcom_icc_node ebi; +static struct qcom_icc_node qns2_mem_noc; +static struct qcom_icc_node qns_mem_noc_hf; +static struct qcom_icc_node srvc_mnoc; +static struct qcom_icc_node qhs_apss; +static struct qcom_icc_node qns_cnoc; +static struct qcom_icc_node qns_gemnoc_gc; +static struct qcom_icc_node qns_gemnoc_sf; +static struct qcom_icc_node qxs_imem; +static struct qcom_icc_node qxs_pimem; +static struct qcom_icc_node srvc_snoc; +static struct qcom_icc_node xs_qdss_stm; +static struct qcom_icc_node xs_sys_tcu_cfg; =20 static struct qcom_icc_node qhm_a1noc_cfg =3D { - .name =3D "qhm-a1noc-cfg", - .id =3D SM7150_MASTER_A1NOC_CFG, + .name =3D "qhm_a1noc_cfg", .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM7150_SLAVE_SERVICE_A1NOC }, + .link_nodes =3D { &srvc_aggre1_noc }, }; =20 static struct qcom_icc_node qhm_qup_center =3D { .name =3D "qhm_qup_center", - .id =3D SM7150_MASTER_QUP_0, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM7150_A1NOC_SNOC_SLV }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node qhm_tsif =3D { .name =3D "qhm_tsif", - .id =3D SM7150_MASTER_TSIF, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM7150_A1NOC_SNOC_SLV }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node xm_emmc =3D { .name =3D "xm_emmc", - .id =3D SM7150_MASTER_EMMC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM7150_A1NOC_SNOC_SLV }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node xm_sdc2 =3D { .name =3D "xm_sdc2", - .id =3D SM7150_MASTER_SDCC_2, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM7150_A1NOC_SNOC_SLV }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node xm_sdc4 =3D { .name =3D "xm_sdc4", - .id =3D SM7150_MASTER_SDCC_4, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM7150_A1NOC_SNOC_SLV }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node xm_ufs_mem =3D { .name =3D "xm_ufs_mem", - .id =3D SM7150_MASTER_UFS_MEM, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM7150_A1NOC_SNOC_SLV }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node qhm_a2noc_cfg =3D { .name =3D "qhm_a2noc_cfg", - .id =3D SM7150_MASTER_A2NOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM7150_SLAVE_SERVICE_A2NOC }, + .link_nodes =3D { &srvc_aggre2_noc }, }; =20 static struct qcom_icc_node qhm_qdss_bam =3D { .name =3D "qhm_qdss_bam", - .id =3D SM7150_MASTER_QDSS_BAM, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM7150_A2NOC_SNOC_SLV }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qhm_qup_north =3D { .name =3D "qhm_qup_north", - .id =3D SM7150_MASTER_QUP_1, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM7150_A2NOC_SNOC_SLV }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qnm_cnoc =3D { .name =3D "qnm_cnoc", - .id =3D SM7150_MASTER_CNOC_A2NOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM7150_A2NOC_SNOC_SLV }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qxm_crypto =3D { .name =3D "qxm_crypto", - .id =3D SM7150_MASTER_CRYPTO_CORE_0, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM7150_A2NOC_SNOC_SLV }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qxm_ipa =3D { .name =3D "qxm_ipa", - .id =3D SM7150_MASTER_IPA, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM7150_A2NOC_SNOC_SLV }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node xm_pcie3_0 =3D { .name =3D "xm_pcie3_0", - .id =3D SM7150_MASTER_PCIE, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM7150_SLAVE_ANOC_PCIE_GEM_NOC }, + .link_nodes =3D { &qns_pcie_gemnoc }, }; =20 static struct qcom_icc_node xm_qdss_etr =3D { .name =3D "xm_qdss_etr", - .id =3D SM7150_MASTER_QDSS_ETR, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM7150_A2NOC_SNOC_SLV }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node xm_usb3_0 =3D { .name =3D "xm_usb3_0", - .id =3D SM7150_MASTER_USB3, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM7150_A2NOC_SNOC_SLV }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qxm_camnoc_hf0_uncomp =3D { .name =3D "qxm_camnoc_hf0_uncomp", - .id =3D SM7150_MASTER_CAMNOC_HF0_UNCOMP, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM7150_SLAVE_CAMNOC_UNCOMP }, + .link_nodes =3D { &qns_camnoc_uncomp }, }; =20 static struct qcom_icc_node qxm_camnoc_rt_uncomp =3D { .name =3D "qxm_camnoc_rt_uncomp", - .id =3D SM7150_MASTER_CAMNOC_RT_UNCOMP, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM7150_SLAVE_CAMNOC_UNCOMP }, + .link_nodes =3D { &qns_camnoc_uncomp }, }; =20 static struct qcom_icc_node qxm_camnoc_sf_uncomp =3D { .name =3D "qxm_camnoc_sf_uncomp", - .id =3D SM7150_MASTER_CAMNOC_SF_UNCOMP, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM7150_SLAVE_CAMNOC_UNCOMP }, + .link_nodes =3D { &qns_camnoc_uncomp }, }; =20 static struct qcom_icc_node qxm_camnoc_nrt_uncomp =3D { .name =3D "qxm_camnoc_nrt_uncomp", - .id =3D SM7150_MASTER_CAMNOC_NRT_UNCOMP, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM7150_SLAVE_CAMNOC_UNCOMP }, + .link_nodes =3D { &qns_camnoc_uncomp }, }; =20 static struct qcom_icc_node qnm_npu =3D { .name =3D "qnm_npu", - .id =3D SM7150_MASTER_NPU, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM7150_SLAVE_CDSP_GEM_NOC }, + .link_nodes =3D { &qns_cdsp_gemnoc }, }; =20 static struct qcom_icc_node qhm_spdm =3D { .name =3D "qhm_spdm", - .id =3D SM7150_MASTER_SPDM, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM7150_SLAVE_CNOC_A2NOC }, + .link_nodes =3D { &qns_cnoc_a2noc }, }; =20 static struct qcom_icc_node qnm_snoc =3D { .name =3D "qnm_snoc", - .id =3D SM7150_SNOC_CNOC_MAS, .channels =3D 1, .buswidth =3D 8, .num_links =3D 47, - .links =3D { SM7150_SLAVE_TLMM_SOUTH, - SM7150_SLAVE_CAMERA_CFG, - SM7150_SLAVE_SDCC_4, - SM7150_SLAVE_SDCC_2, - SM7150_SLAVE_CNOC_MNOC_CFG, - SM7150_SLAVE_UFS_MEM_CFG, - SM7150_SLAVE_QUP_0, - SM7150_SLAVE_GLM, - SM7150_SLAVE_PDM, - SM7150_SLAVE_CAMERA_NRT_THROTTLE_CFG, - SM7150_SLAVE_A2NOC_CFG, - SM7150_SLAVE_QDSS_CFG, - SM7150_SLAVE_CAMERA_RT_THROTTLE_CFG, - SM7150_SLAVE_DISPLAY_CFG, - SM7150_SLAVE_PCIE_CFG, - SM7150_SLAVE_DISPLAY_THROTTLE_CFG, - SM7150_SLAVE_TCSR, - SM7150_SLAVE_VENUS_CVP_THROTTLE_CFG, - SM7150_SLAVE_CNOC_DDRSS, - SM7150_SLAVE_AHB2PHY_NORTH, - SM7150_SLAVE_SNOC_CFG, - SM7150_SLAVE_GRAPHICS_3D_CFG, - SM7150_SLAVE_VENUS_CFG, - SM7150_SLAVE_TSIF, - SM7150_SLAVE_CDSP_CFG, - SM7150_SLAVE_CLK_CTL, - SM7150_SLAVE_AOP, - SM7150_SLAVE_QUP_1, - SM7150_SLAVE_AHB2PHY_SOUTH, - SM7150_SLAVE_SERVICE_CNOC, - SM7150_SLAVE_AHB2PHY_WEST, - SM7150_SLAVE_USB3, - SM7150_SLAVE_VENUS_THROTTLE_CFG, - SM7150_SLAVE_IPA_CFG, - SM7150_SLAVE_RBCPR_CX_CFG, - SM7150_SLAVE_TLMM_WEST, - SM7150_SLAVE_A1NOC_CFG, - SM7150_SLAVE_AOSS, - SM7150_SLAVE_PRNG, - SM7150_SLAVE_VSENSE_CTRL_CFG, - SM7150_SLAVE_EMMC_CFG, - SM7150_SLAVE_SPDM_WRAPPER, - SM7150_SLAVE_CRYPTO_0_CFG, - SM7150_SLAVE_PIMEM_CFG, - SM7150_SLAVE_TLMM_NORTH, - SM7150_SLAVE_RBCPR_MX_CFG, - SM7150_SLAVE_IMEM_CFG - }, + .link_nodes =3D { &qhs_tlmm_south, + &qhs_camera_cfg, + &qhs_sdc4, + &qhs_sdc2, + &qhs_mnoc_cfg, + &qhs_ufs_mem_cfg, + &qhs_qupv3_center, + &qhs_glm, + &qhs_pdm, + &qhs_camera_nrt_thrott_cfg, + &qhs_a2_noc_cfg, + &qhs_qdss_cfg, + &qhs_camera_rt_throttle_cfg, + &qhs_display_cfg, + &qhs_pcie_cfg, + &qhs_display_throttle_cfg, + &qhs_tcsr, + &qhs_venus_cvp_throttle_cfg, + &qhs_ddrss_cfg, + &qhs_ahb2phy_north, + &qhs_snoc_cfg, + &qhs_gpuss_cfg, + &qhs_venus_cfg, + &qhs_tsif, + &qhs_compute_dsp_cfg, + &qhs_clk_ctl, + &qhs_aop, + &qhs_qupv3_north, + &qhs_ahb2phy_south, + &srvc_cnoc, + &qhs_ahb2phy_west, + &qhs_usb3_0, + &qhs_venus_throttle_cfg, + &qhs_ipa, + &qhs_cpr_cx, + &qhs_tlmm_west, + &qhs_a1_noc_cfg, + &qhs_aoss, + &qhs_prng, + &qhs_vsense_ctrl_cfg, + &qhs_emmc_cfg, + &qhs_spdm, + &qhs_crypto0_cfg, + &qhs_pimem_cfg, + &qhs_tlmm_north, + &qhs_cpr_mx, + &qhs_imem_cfg }, }; =20 static struct qcom_icc_node xm_qdss_dap =3D { .name =3D "xm_qdss_dap", - .id =3D SM7150_MASTER_QDSS_DAP, .channels =3D 1, .buswidth =3D 8, .num_links =3D 48, - .links =3D { SM7150_SLAVE_TLMM_SOUTH, - SM7150_SLAVE_CAMERA_CFG, - SM7150_SLAVE_SDCC_4, - SM7150_SLAVE_SDCC_2, - SM7150_SLAVE_CNOC_MNOC_CFG, - SM7150_SLAVE_UFS_MEM_CFG, - SM7150_SLAVE_QUP_0, - SM7150_SLAVE_GLM, - SM7150_SLAVE_PDM, - SM7150_SLAVE_CAMERA_NRT_THROTTLE_CFG, - SM7150_SLAVE_A2NOC_CFG, - SM7150_SLAVE_QDSS_CFG, - SM7150_SLAVE_CAMERA_RT_THROTTLE_CFG, - SM7150_SLAVE_DISPLAY_CFG, - SM7150_SLAVE_PCIE_CFG, - SM7150_SLAVE_DISPLAY_THROTTLE_CFG, - SM7150_SLAVE_TCSR, - SM7150_SLAVE_VENUS_CVP_THROTTLE_CFG, - SM7150_SLAVE_CNOC_DDRSS, - SM7150_SLAVE_CNOC_A2NOC, - SM7150_SLAVE_AHB2PHY_NORTH, - SM7150_SLAVE_SNOC_CFG, - SM7150_SLAVE_GRAPHICS_3D_CFG, - SM7150_SLAVE_VENUS_CFG, - SM7150_SLAVE_TSIF, - SM7150_SLAVE_CDSP_CFG, - SM7150_SLAVE_CLK_CTL, - SM7150_SLAVE_AOP, - SM7150_SLAVE_QUP_1, - SM7150_SLAVE_AHB2PHY_SOUTH, - SM7150_SLAVE_SERVICE_CNOC, - SM7150_SLAVE_AHB2PHY_WEST, - SM7150_SLAVE_USB3, - SM7150_SLAVE_VENUS_THROTTLE_CFG, - SM7150_SLAVE_IPA_CFG, - SM7150_SLAVE_RBCPR_CX_CFG, - SM7150_SLAVE_TLMM_WEST, - SM7150_SLAVE_A1NOC_CFG, - SM7150_SLAVE_AOSS, - SM7150_SLAVE_PRNG, - SM7150_SLAVE_VSENSE_CTRL_CFG, - SM7150_SLAVE_EMMC_CFG, - SM7150_SLAVE_SPDM_WRAPPER, - SM7150_SLAVE_CRYPTO_0_CFG, - SM7150_SLAVE_PIMEM_CFG, - SM7150_SLAVE_TLMM_NORTH, - SM7150_SLAVE_RBCPR_MX_CFG, - SM7150_SLAVE_IMEM_CFG - }, + .link_nodes =3D { &qhs_tlmm_south, + &qhs_camera_cfg, + &qhs_sdc4, + &qhs_sdc2, + &qhs_mnoc_cfg, + &qhs_ufs_mem_cfg, + &qhs_qupv3_center, + &qhs_glm, + &qhs_pdm, + &qhs_camera_nrt_thrott_cfg, + &qhs_a2_noc_cfg, + &qhs_qdss_cfg, + &qhs_camera_rt_throttle_cfg, + &qhs_display_cfg, + &qhs_pcie_cfg, + &qhs_display_throttle_cfg, + &qhs_tcsr, + &qhs_venus_cvp_throttle_cfg, + &qhs_ddrss_cfg, + &qns_cnoc_a2noc, + &qhs_ahb2phy_north, + &qhs_snoc_cfg, + &qhs_gpuss_cfg, + &qhs_venus_cfg, + &qhs_tsif, + &qhs_compute_dsp_cfg, + &qhs_clk_ctl, + &qhs_aop, + &qhs_qupv3_north, + &qhs_ahb2phy_south, + &srvc_cnoc, + &qhs_ahb2phy_west, + &qhs_usb3_0, + &qhs_venus_throttle_cfg, + &qhs_ipa, + &qhs_cpr_cx, + &qhs_tlmm_west, + &qhs_a1_noc_cfg, + &qhs_aoss, + &qhs_prng, + &qhs_vsense_ctrl_cfg, + &qhs_emmc_cfg, + &qhs_spdm, + &qhs_crypto0_cfg, + &qhs_pimem_cfg, + &qhs_tlmm_north, + &qhs_cpr_mx, + &qhs_imem_cfg }, }; =20 static struct qcom_icc_node qhm_cnoc_dc_noc =3D { .name =3D "qhm_cnoc_dc_noc", - .id =3D SM7150_MASTER_CNOC_DC_NOC, .channels =3D 1, .buswidth =3D 4, .num_links =3D 2, - .links =3D { SM7150_SLAVE_LLCC_CFG, - SM7150_SLAVE_GEM_NOC_CFG - }, + .link_nodes =3D { &qhs_llcc, + &qhs_gemnoc }, }; =20 static struct qcom_icc_node acm_apps =3D { .name =3D "acm_apps", - .id =3D SM7150_MASTER_AMPSS_M0, .channels =3D 1, .buswidth =3D 16, .num_links =3D 2, - .links =3D { SM7150_SLAVE_LLCC, - SM7150_SLAVE_GEM_NOC_SNOC - }, + .link_nodes =3D { &qns_llcc, + &qns_gem_noc_snoc }, }; =20 static struct qcom_icc_node acm_sys_tcu =3D { .name =3D "acm_sys_tcu", - .id =3D SM7150_MASTER_SYS_TCU, .channels =3D 1, .buswidth =3D 8, .num_links =3D 2, - .links =3D { SM7150_SLAVE_LLCC, - SM7150_SLAVE_GEM_NOC_SNOC - }, + .link_nodes =3D { &qns_llcc, + &qns_gem_noc_snoc }, }; =20 static struct qcom_icc_node qhm_gemnoc_cfg =3D { .name =3D "qhm_gemnoc_cfg", - .id =3D SM7150_MASTER_GEM_NOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 2, - .links =3D { SM7150_SLAVE_SERVICE_GEM_NOC, - SM7150_SLAVE_MSS_PROC_MS_MPU_CFG - }, + .link_nodes =3D { &srvc_gemnoc, + &qhs_mdsp_ms_mpu_cfg }, }; =20 static struct qcom_icc_node qnm_cmpnoc =3D { .name =3D "qnm_cmpnoc", - .id =3D SM7150_MASTER_COMPUTE_NOC, .channels =3D 1, .buswidth =3D 32, .num_links =3D 2, - .links =3D { SM7150_SLAVE_LLCC, - SM7150_SLAVE_GEM_NOC_SNOC - }, + .link_nodes =3D { &qns_llcc, + &qns_gem_noc_snoc }, }; =20 static struct qcom_icc_node qnm_mnoc_hf =3D { .name =3D "qnm_mnoc_hf", - .id =3D SM7150_MASTER_MNOC_HF_MEM_NOC, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM7150_SLAVE_LLCC }, + .link_nodes =3D { &qns_llcc }, }; =20 static struct qcom_icc_node qnm_mnoc_sf =3D { .name =3D "qnm_mnoc_sf", - .id =3D SM7150_MASTER_MNOC_SF_MEM_NOC, .channels =3D 1, .buswidth =3D 32, .num_links =3D 2, - .links =3D { SM7150_SLAVE_LLCC, - SM7150_SLAVE_GEM_NOC_SNOC - }, + .link_nodes =3D { &qns_llcc, + &qns_gem_noc_snoc }, }; =20 static struct qcom_icc_node qnm_pcie =3D { .name =3D "qnm_pcie", - .id =3D SM7150_MASTER_GEM_NOC_PCIE_SNOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 2, - .links =3D { SM7150_SLAVE_LLCC, - SM7150_SLAVE_GEM_NOC_SNOC - }, + .link_nodes =3D { &qns_llcc, + &qns_gem_noc_snoc }, }; =20 static struct qcom_icc_node qnm_snoc_gc =3D { .name =3D "qnm_snoc_gc", - .id =3D SM7150_MASTER_SNOC_GC_MEM_NOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM7150_SLAVE_LLCC }, + .link_nodes =3D { &qns_llcc }, }; =20 static struct qcom_icc_node qnm_snoc_sf =3D { .name =3D "qnm_snoc_sf", - .id =3D SM7150_MASTER_SNOC_SF_MEM_NOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM7150_SLAVE_LLCC }, + .link_nodes =3D { &qns_llcc }, }; =20 static struct qcom_icc_node qxm_gpu =3D { .name =3D "qxm_gpu", - .id =3D SM7150_MASTER_GRAPHICS_3D, .channels =3D 2, .buswidth =3D 32, .num_links =3D 2, - .links =3D { SM7150_SLAVE_LLCC, - SM7150_SLAVE_GEM_NOC_SNOC - }, + .link_nodes =3D { &qns_llcc, + &qns_gem_noc_snoc }, }; =20 static struct qcom_icc_node llcc_mc =3D { .name =3D "llcc_mc", - .id =3D SM7150_MASTER_LLCC, .channels =3D 2, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM7150_SLAVE_EBI_CH0 }, + .link_nodes =3D { &ebi }, }; =20 static struct qcom_icc_node qhm_mnoc_cfg =3D { .name =3D "qhm_mnoc_cfg", - .id =3D SM7150_MASTER_CNOC_MNOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM7150_SLAVE_SERVICE_MNOC }, + .link_nodes =3D { &srvc_mnoc }, }; =20 static struct qcom_icc_node qxm_camnoc_hf =3D { .name =3D "qxm_camnoc_hf", - .id =3D SM7150_MASTER_CAMNOC_HF0, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM7150_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_hf }, }; =20 static struct qcom_icc_node qxm_camnoc_nrt =3D { .name =3D "qxm_camnoc_nrt", - .id =3D SM7150_MASTER_CAMNOC_NRT, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM7150_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns2_mem_noc }, }; =20 static struct qcom_icc_node qxm_camnoc_rt =3D { .name =3D "qxm_camnoc_rt", - .id =3D SM7150_MASTER_CAMNOC_RT, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM7150_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_hf }, }; =20 static struct qcom_icc_node qxm_camnoc_sf =3D { .name =3D "qxm_camnoc_sf", - .id =3D SM7150_MASTER_CAMNOC_SF, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM7150_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns2_mem_noc }, }; =20 static struct qcom_icc_node qxm_mdp0 =3D { .name =3D "qxm_mdp0", - .id =3D SM7150_MASTER_MDP_PORT0, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM7150_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_hf }, }; =20 static struct qcom_icc_node qxm_mdp1 =3D { .name =3D "qxm_mdp1", - .id =3D SM7150_MASTER_MDP_PORT1, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM7150_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_hf }, }; =20 static struct qcom_icc_node qxm_rot =3D { .name =3D "qxm_rot", - .id =3D SM7150_MASTER_ROTATOR, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM7150_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns2_mem_noc }, }; =20 static struct qcom_icc_node qxm_venus0 =3D { .name =3D "qxm_venus0", - .id =3D SM7150_MASTER_VIDEO_P0, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM7150_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns2_mem_noc }, }; =20 static struct qcom_icc_node qxm_venus1 =3D { .name =3D "qxm_venus1", - .id =3D SM7150_MASTER_VIDEO_P1, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM7150_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns2_mem_noc }, }; =20 static struct qcom_icc_node qxm_venus_arm9 =3D { .name =3D "qxm_venus_arm9", - .id =3D SM7150_MASTER_VIDEO_PROC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM7150_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns2_mem_noc }, }; =20 static struct qcom_icc_node qhm_snoc_cfg =3D { .name =3D "qhm_snoc_cfg", - .id =3D SM7150_MASTER_SNOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM7150_SLAVE_SERVICE_SNOC }, + .link_nodes =3D { &srvc_snoc }, }; =20 static struct qcom_icc_node qnm_aggre1_noc =3D { .name =3D "qnm_aggre1_noc", - .id =3D SM7150_A1NOC_SNOC_MAS, .channels =3D 1, .buswidth =3D 16, .num_links =3D 6, - .links =3D { SM7150_SLAVE_SNOC_GEM_NOC_SF, - SM7150_SLAVE_PIMEM, - SM7150_SLAVE_OCIMEM, - SM7150_SLAVE_APPSS, - SM7150_SNOC_CNOC_SLV, - SM7150_SLAVE_QDSS_STM - }, + .link_nodes =3D { &qns_gemnoc_sf, + &qxs_pimem, + &qxs_imem, + &qhs_apss, + &qns_cnoc, + &xs_qdss_stm }, }; =20 static struct qcom_icc_node qnm_aggre2_noc =3D { .name =3D "qnm_aggre2_noc", - .id =3D SM7150_A2NOC_SNOC_MAS, .channels =3D 1, .buswidth =3D 16, .num_links =3D 7, - .links =3D { SM7150_SLAVE_SNOC_GEM_NOC_SF, - SM7150_SLAVE_PIMEM, - SM7150_SLAVE_OCIMEM, - SM7150_SLAVE_APPSS, - SM7150_SNOC_CNOC_SLV, - SM7150_SLAVE_TCU, - SM7150_SLAVE_QDSS_STM - }, + .link_nodes =3D { &qns_gemnoc_sf, + &qxs_pimem, + &qxs_imem, + &qhs_apss, + &qns_cnoc, + &xs_sys_tcu_cfg, + &xs_qdss_stm }, }; =20 static struct qcom_icc_node qnm_gemnoc =3D { .name =3D "qnm_gemnoc", - .id =3D SM7150_MASTER_GEM_NOC_SNOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 6, - .links =3D { SM7150_SLAVE_PIMEM, - SM7150_SLAVE_OCIMEM, - SM7150_SLAVE_APPSS, - SM7150_SNOC_CNOC_SLV, - SM7150_SLAVE_TCU, - SM7150_SLAVE_QDSS_STM - }, + .link_nodes =3D { &qxs_pimem, + &qxs_imem, + &qhs_apss, + &qns_cnoc, + &xs_sys_tcu_cfg, + &xs_qdss_stm }, }; =20 static struct qcom_icc_node qxm_pimem =3D { .name =3D "qxm_pimem", - .id =3D SM7150_MASTER_PIMEM, .channels =3D 1, .buswidth =3D 8, .num_links =3D 2, - .links =3D { SM7150_SLAVE_SNOC_GEM_NOC_GC, - SM7150_SLAVE_OCIMEM - }, + .link_nodes =3D { &qns_gemnoc_gc, + &qxs_imem }, }; =20 static struct qcom_icc_node xm_gic =3D { .name =3D "xm_gic", - .id =3D SM7150_MASTER_GIC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 2, - .links =3D { SM7150_SLAVE_SNOC_GEM_NOC_GC, - SM7150_SLAVE_OCIMEM - }, + .link_nodes =3D { &qns_gemnoc_gc, + &qxs_imem }, }; =20 static struct qcom_icc_node qns_a1noc_snoc =3D { .name =3D "qns_a1noc_snoc", - .id =3D SM7150_A1NOC_SNOC_SLV, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM7150_A1NOC_SNOC_MAS }, + .link_nodes =3D { &qnm_aggre1_noc }, }; =20 static struct qcom_icc_node srvc_aggre1_noc =3D { .name =3D "srvc_aggre1_noc", - .id =3D SM7150_SLAVE_SERVICE_A1NOC, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qns_a2noc_snoc =3D { .name =3D "qns_a2noc_snoc", - .id =3D SM7150_A2NOC_SNOC_SLV, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM7150_A2NOC_SNOC_MAS }, + .link_nodes =3D { &qnm_aggre2_noc }, }; =20 static struct qcom_icc_node qns_pcie_gemnoc =3D { .name =3D "qns_pcie_gemnoc", - .id =3D SM7150_SLAVE_ANOC_PCIE_GEM_NOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM7150_MASTER_GEM_NOC_PCIE_SNOC }, + .link_nodes =3D { &qnm_pcie }, }; =20 static struct qcom_icc_node srvc_aggre2_noc =3D { .name =3D "srvc_aggre2_noc", - .id =3D SM7150_SLAVE_SERVICE_A2NOC, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qns_camnoc_uncomp =3D { .name =3D "qns_camnoc_uncomp", - .id =3D SM7150_SLAVE_CAMNOC_UNCOMP, .channels =3D 1, .buswidth =3D 32, }; =20 static struct qcom_icc_node qns_cdsp_gemnoc =3D { .name =3D "qns_cdsp_gemnoc", - .id =3D SM7150_SLAVE_CDSP_GEM_NOC, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM7150_MASTER_COMPUTE_NOC }, + .link_nodes =3D { &qnm_cmpnoc }, }; =20 static struct qcom_icc_node qhs_a1_noc_cfg =3D { .name =3D "qhs_a1_noc_cfg", - .id =3D SM7150_SLAVE_A1NOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM7150_MASTER_A1NOC_CFG }, + .link_nodes =3D { &qhm_a1noc_cfg }, }; =20 static struct qcom_icc_node qhs_a2_noc_cfg =3D { .name =3D "qhs_a2_noc_cfg", - .id =3D SM7150_SLAVE_A2NOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM7150_MASTER_A2NOC_CFG }, + .link_nodes =3D { &qhm_a2noc_cfg }, }; =20 static struct qcom_icc_node qhs_ahb2phy_north =3D { .name =3D "qhs_ahb2phy_north", - .id =3D SM7150_SLAVE_AHB2PHY_NORTH, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_ahb2phy_south =3D { .name =3D "qhs_ahb2phy_south", - .id =3D SM7150_SLAVE_AHB2PHY_SOUTH, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_ahb2phy_west =3D { .name =3D "qhs_ahb2phy_west", - .id =3D SM7150_SLAVE_AHB2PHY_WEST, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_aop =3D { .name =3D "qhs_aop", - .id =3D SM7150_SLAVE_AOP, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_aoss =3D { .name =3D "qhs_aoss", - .id =3D SM7150_SLAVE_AOSS, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_camera_cfg =3D { .name =3D "qhs_camera_cfg", - .id =3D SM7150_SLAVE_CAMERA_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_camera_nrt_thrott_cfg =3D { .name =3D "qhs_camera_nrt_thrott_cfg", - .id =3D SM7150_SLAVE_CAMERA_NRT_THROTTLE_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_camera_rt_throttle_cfg =3D { .name =3D "qhs_camera_rt_throttle_cfg", - .id =3D SM7150_SLAVE_CAMERA_RT_THROTTLE_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_clk_ctl =3D { .name =3D "qhs_clk_ctl", - .id =3D SM7150_SLAVE_CLK_CTL, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_compute_dsp_cfg =3D { .name =3D "qhs_compute_dsp_cfg", - .id =3D SM7150_SLAVE_CDSP_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_cpr_cx =3D { .name =3D "qhs_cpr_cx", - .id =3D SM7150_SLAVE_RBCPR_CX_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_cpr_mx =3D { .name =3D "qhs_cpr_mx", - .id =3D SM7150_SLAVE_RBCPR_MX_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_crypto0_cfg =3D { .name =3D "qhs_crypto0_cfg", - .id =3D SM7150_SLAVE_CRYPTO_0_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_ddrss_cfg =3D { .name =3D "qhs_ddrss_cfg", - .id =3D SM7150_SLAVE_CNOC_DDRSS, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM7150_MASTER_CNOC_DC_NOC }, + .link_nodes =3D { &qhm_cnoc_dc_noc }, }; =20 static struct qcom_icc_node qhs_display_cfg =3D { .name =3D "qhs_display_cfg", - .id =3D SM7150_SLAVE_DISPLAY_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_display_throttle_cfg =3D { .name =3D "qhs_display_throttle_cfg", - .id =3D SM7150_SLAVE_DISPLAY_THROTTLE_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_emmc_cfg =3D { .name =3D "qhs_emmc_cfg", - .id =3D SM7150_SLAVE_EMMC_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_glm =3D { .name =3D "qhs_glm", - .id =3D SM7150_SLAVE_GLM, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_gpuss_cfg =3D { .name =3D "qhs_gpuss_cfg", - .id =3D SM7150_SLAVE_GRAPHICS_3D_CFG, .channels =3D 1, .buswidth =3D 8, }; =20 static struct qcom_icc_node qhs_imem_cfg =3D { .name =3D "qhs_imem_cfg", - .id =3D SM7150_SLAVE_IMEM_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_ipa =3D { .name =3D "qhs_ipa", - .id =3D SM7150_SLAVE_IPA_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_mnoc_cfg =3D { .name =3D "qhs_mnoc_cfg", - .id =3D SM7150_SLAVE_CNOC_MNOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM7150_MASTER_CNOC_MNOC_CFG }, + .link_nodes =3D { &qhm_mnoc_cfg }, }; =20 static struct qcom_icc_node qhs_pcie_cfg =3D { .name =3D "qhs_pcie_cfg", - .id =3D SM7150_SLAVE_PCIE_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_pdm =3D { .name =3D "qhs_pdm", - .id =3D SM7150_SLAVE_PDM, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_pimem_cfg =3D { .name =3D "qhs_pimem_cfg", - .id =3D SM7150_SLAVE_PIMEM_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_prng =3D { .name =3D "qhs_prng", - .id =3D SM7150_SLAVE_PRNG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_qdss_cfg =3D { .name =3D "qhs_qdss_cfg", - .id =3D SM7150_SLAVE_QDSS_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_qupv3_center =3D { .name =3D "qhs_qupv3_center", - .id =3D SM7150_SLAVE_QUP_0, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_qupv3_north =3D { .name =3D "qhs_qupv3_north", - .id =3D SM7150_SLAVE_QUP_1, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_sdc2 =3D { .name =3D "qhs_sdc2", - .id =3D SM7150_SLAVE_SDCC_2, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_sdc4 =3D { .name =3D "qhs_sdc4", - .id =3D SM7150_SLAVE_SDCC_4, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_snoc_cfg =3D { .name =3D "qhs_snoc_cfg", - .id =3D SM7150_SLAVE_SNOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM7150_MASTER_SNOC_CFG }, + .link_nodes =3D { &qhm_snoc_cfg }, }; =20 static struct qcom_icc_node qhs_spdm =3D { .name =3D "qhs_spdm", - .id =3D SM7150_SLAVE_SPDM_WRAPPER, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_tcsr =3D { .name =3D "qhs_tcsr", - .id =3D SM7150_SLAVE_TCSR, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_tlmm_north =3D { .name =3D "qhs_tlmm_north", - .id =3D SM7150_SLAVE_TLMM_NORTH, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_tlmm_south =3D { .name =3D "qhs_tlmm_south", - .id =3D SM7150_SLAVE_TLMM_SOUTH, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_tlmm_west =3D { .name =3D "qhs_tlmm_west", - .id =3D SM7150_SLAVE_TLMM_WEST, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_tsif =3D { .name =3D "qhs_tsif", - .id =3D SM7150_SLAVE_TSIF, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_ufs_mem_cfg =3D { .name =3D "qhs_ufs_mem_cfg", - .id =3D SM7150_SLAVE_UFS_MEM_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_usb3_0 =3D { .name =3D "qhs_usb3_0", - .id =3D SM7150_SLAVE_USB3, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_venus_cfg =3D { .name =3D "qhs_venus_cfg", - .id =3D SM7150_SLAVE_VENUS_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_venus_cvp_throttle_cfg =3D { .name =3D "qhs_venus_cvp_throttle_cfg", - .id =3D SM7150_SLAVE_VENUS_CVP_THROTTLE_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_venus_throttle_cfg =3D { .name =3D "qhs_venus_throttle_cfg", - .id =3D SM7150_SLAVE_VENUS_THROTTLE_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_vsense_ctrl_cfg =3D { .name =3D "qhs_vsense_ctrl_cfg", - .id =3D SM7150_SLAVE_VSENSE_CTRL_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qns_cnoc_a2noc =3D { .name =3D "qns_cnoc_a2noc", - .id =3D SM7150_SLAVE_CNOC_A2NOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM7150_MASTER_CNOC_A2NOC }, + .link_nodes =3D { &qnm_cnoc }, }; =20 static struct qcom_icc_node srvc_cnoc =3D { .name =3D "srvc_cnoc", - .id =3D SM7150_SLAVE_SERVICE_CNOC, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_gemnoc =3D { .name =3D "qhs_gemnoc", - .id =3D SM7150_SLAVE_GEM_NOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM7150_MASTER_GEM_NOC_CFG }, + .link_nodes =3D { &qhm_gemnoc_cfg }, }; =20 static struct qcom_icc_node qhs_llcc =3D { .name =3D "qhs_llcc", - .id =3D SM7150_SLAVE_LLCC_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg =3D { .name =3D "qhs_mdsp_ms_mpu_cfg", - .id =3D SM7150_SLAVE_MSS_PROC_MS_MPU_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qns_gem_noc_snoc =3D { .name =3D "qns_gem_noc_snoc", - .id =3D SM7150_SLAVE_GEM_NOC_SNOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM7150_MASTER_GEM_NOC_SNOC }, + .link_nodes =3D { &qnm_gemnoc }, }; =20 static struct qcom_icc_node qns_llcc =3D { .name =3D "qns_llcc", - .id =3D SM7150_SLAVE_LLCC, .channels =3D 2, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM7150_MASTER_LLCC }, + .link_nodes =3D { &llcc_mc }, }; =20 static struct qcom_icc_node srvc_gemnoc =3D { .name =3D "srvc_gemnoc", - .id =3D SM7150_SLAVE_SERVICE_GEM_NOC, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node ebi =3D { .name =3D "ebi", - .id =3D SM7150_SLAVE_EBI_CH0, .channels =3D 2, .buswidth =3D 4, }; =20 static struct qcom_icc_node qns2_mem_noc =3D { .name =3D "qns2_mem_noc", - .id =3D SM7150_SLAVE_MNOC_SF_MEM_NOC, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM7150_MASTER_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qnm_mnoc_sf }, }; =20 static struct qcom_icc_node qns_mem_noc_hf =3D { .name =3D "qns_mem_noc_hf", - .id =3D SM7150_SLAVE_MNOC_HF_MEM_NOC, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM7150_MASTER_MNOC_HF_MEM_NOC }, + .link_nodes =3D { &qnm_mnoc_hf }, }; =20 static struct qcom_icc_node srvc_mnoc =3D { .name =3D "srvc_mnoc", - .id =3D SM7150_SLAVE_SERVICE_MNOC, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_apss =3D { .name =3D "qhs_apss", - .id =3D SM7150_SLAVE_APPSS, .channels =3D 1, .buswidth =3D 8, }; =20 static struct qcom_icc_node qns_cnoc =3D { .name =3D "qns_cnoc", - .id =3D SM7150_SNOC_CNOC_SLV, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM7150_SNOC_CNOC_MAS }, + .link_nodes =3D { &qnm_snoc }, }; =20 static struct qcom_icc_node qns_gemnoc_gc =3D { .name =3D "qns_gemnoc_gc", - .id =3D SM7150_SLAVE_SNOC_GEM_NOC_GC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM7150_MASTER_SNOC_GC_MEM_NOC }, + .link_nodes =3D { &qnm_snoc_gc }, }; =20 static struct qcom_icc_node qns_gemnoc_sf =3D { .name =3D "qns_gemnoc_sf", - .id =3D SM7150_SLAVE_SNOC_GEM_NOC_SF, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM7150_MASTER_SNOC_SF_MEM_NOC }, + .link_nodes =3D { &qnm_snoc_sf }, }; =20 static struct qcom_icc_node qxs_imem =3D { .name =3D "qxs_imem", - .id =3D SM7150_SLAVE_OCIMEM, .channels =3D 1, .buswidth =3D 8, }; =20 static struct qcom_icc_node qxs_pimem =3D { .name =3D "qxs_pimem", - .id =3D SM7150_SLAVE_PIMEM, .channels =3D 1, .buswidth =3D 8, }; =20 static struct qcom_icc_node srvc_snoc =3D { .name =3D "srvc_snoc", - .id =3D SM7150_SLAVE_SERVICE_SNOC, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node xs_qdss_stm =3D { .name =3D "xs_qdss_stm", - .id =3D SM7150_SLAVE_QDSS_STM, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node xs_sys_tcu_cfg =3D { .name =3D "xs_sys_tcu_cfg", - .id =3D SM7150_SLAVE_TCU, .channels =3D 1, .buswidth =3D 8, }; @@ -1446,6 +1431,7 @@ static struct qcom_icc_node * const aggre1_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sm7150_aggre1_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D aggre1_noc_nodes, .num_nodes =3D ARRAY_SIZE(aggre1_noc_nodes), .bcms =3D aggre1_noc_bcms, @@ -1475,6 +1461,7 @@ static struct qcom_icc_node * const aggre2_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sm7150_aggre2_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D aggre2_noc_nodes, .num_nodes =3D ARRAY_SIZE(aggre2_noc_nodes), .bcms =3D aggre2_noc_bcms, @@ -1494,6 +1481,7 @@ static struct qcom_icc_node * const camnoc_virt_nodes= [] =3D { }; =20 static const struct qcom_icc_desc sm7150_camnoc_virt =3D { + .alloc_dyn_id =3D true, .nodes =3D camnoc_virt_nodes, .num_nodes =3D ARRAY_SIZE(camnoc_virt_nodes), .bcms =3D camnoc_virt_bcms, @@ -1511,6 +1499,7 @@ static struct qcom_icc_node * const compute_noc_nodes= [] =3D { }; =20 static const struct qcom_icc_desc sm7150_compute_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D compute_noc_nodes, .num_nodes =3D ARRAY_SIZE(compute_noc_nodes), .bcms =3D compute_noc_bcms, @@ -1576,6 +1565,7 @@ static struct qcom_icc_node * const config_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sm7150_config_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D config_noc_nodes, .num_nodes =3D ARRAY_SIZE(config_noc_nodes), .bcms =3D config_noc_bcms, @@ -1592,6 +1582,7 @@ static struct qcom_icc_node * const dc_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sm7150_dc_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D dc_noc_nodes, .num_nodes =3D ARRAY_SIZE(dc_noc_nodes), .bcms =3D dc_noc_bcms, @@ -1623,6 +1614,7 @@ static struct qcom_icc_node * const gem_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sm7150_gem_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D gem_noc_nodes, .num_nodes =3D ARRAY_SIZE(gem_noc_nodes), .bcms =3D gem_noc_bcms, @@ -1640,6 +1632,7 @@ static struct qcom_icc_node * const mc_virt_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sm7150_mc_virt =3D { + .alloc_dyn_id =3D true, .nodes =3D mc_virt_nodes, .num_nodes =3D ARRAY_SIZE(mc_virt_nodes), .bcms =3D mc_virt_bcms, @@ -1671,6 +1664,7 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sm7150_mmss_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D mmss_noc_nodes, .num_nodes =3D ARRAY_SIZE(mmss_noc_nodes), .bcms =3D mmss_noc_bcms, @@ -1707,6 +1701,7 @@ static struct qcom_icc_node * const system_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sm7150_system_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D system_noc_nodes, .num_nodes =3D ARRAY_SIZE(system_noc_nodes), .bcms =3D system_noc_bcms, diff --git a/drivers/interconnect/qcom/sm7150.h b/drivers/interconnect/qcom= /sm7150.h deleted file mode 100644 index e00a9b0c1279367890e01e2a4108aef7c5cd7580..000000000000000000000000000= 0000000000000 --- a/drivers/interconnect/qcom/sm7150.h +++ /dev/null @@ -1,140 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Qualcomm #define SM7150 interconnect IDs - * - * Copyright (c) 2020, The Linux Foundation. All rights reserved. - * Copyright (c) 2024, Danila Tikhonov - */ - -#ifndef __DRIVERS_INTERCONNECT_QCOM_SM7150_H -#define __DRIVERS_INTERCONNECT_QCOM_SM7150_H - -#define SM7150_A1NOC_SNOC_MAS 0 -#define SM7150_A1NOC_SNOC_SLV 1 -#define SM7150_A2NOC_SNOC_MAS 2 -#define SM7150_A2NOC_SNOC_SLV 3 -#define SM7150_MASTER_A1NOC_CFG 4 -#define SM7150_MASTER_A2NOC_CFG 5 -#define SM7150_MASTER_AMPSS_M0 6 -#define SM7150_MASTER_CAMNOC_HF0 7 -#define SM7150_MASTER_CAMNOC_HF0_UNCOMP 8 -#define SM7150_MASTER_CAMNOC_NRT 9 -#define SM7150_MASTER_CAMNOC_NRT_UNCOMP 10 -#define SM7150_MASTER_CAMNOC_RT 11 -#define SM7150_MASTER_CAMNOC_RT_UNCOMP 12 -#define SM7150_MASTER_CAMNOC_SF 13 -#define SM7150_MASTER_CAMNOC_SF_UNCOMP 14 -#define SM7150_MASTER_CNOC_A2NOC 15 -#define SM7150_MASTER_CNOC_DC_NOC 16 -#define SM7150_MASTER_CNOC_MNOC_CFG 17 -#define SM7150_MASTER_COMPUTE_NOC 18 -#define SM7150_MASTER_CRYPTO_CORE_0 19 -#define SM7150_MASTER_EMMC 20 -#define SM7150_MASTER_GEM_NOC_CFG 21 -#define SM7150_MASTER_GEM_NOC_PCIE_SNOC 22 -#define SM7150_MASTER_GEM_NOC_SNOC 23 -#define SM7150_MASTER_GIC 24 -#define SM7150_MASTER_GRAPHICS_3D 25 -#define SM7150_MASTER_IPA 26 -#define SM7150_MASTER_LLCC 27 -#define SM7150_MASTER_MDP_PORT0 28 -#define SM7150_MASTER_MDP_PORT1 29 -#define SM7150_MASTER_MNOC_HF_MEM_NOC 30 -#define SM7150_MASTER_MNOC_SF_MEM_NOC 31 -#define SM7150_MASTER_NPU 32 -#define SM7150_MASTER_PCIE 33 -#define SM7150_MASTER_PIMEM 34 -#define SM7150_MASTER_QDSS_BAM 35 -#define SM7150_MASTER_QDSS_DAP 36 -#define SM7150_MASTER_QDSS_ETR 37 -#define SM7150_MASTER_QUP_0 38 -#define SM7150_MASTER_QUP_1 39 -#define SM7150_MASTER_ROTATOR 40 -#define SM7150_MASTER_SDCC_2 41 -#define SM7150_MASTER_SDCC_4 42 -#define SM7150_MASTER_SNOC_CFG 43 -#define SM7150_MASTER_SNOC_GC_MEM_NOC 44 -#define SM7150_MASTER_SNOC_SF_MEM_NOC 45 -#define SM7150_MASTER_SPDM 46 -#define SM7150_MASTER_SYS_TCU 47 -#define SM7150_MASTER_TSIF 48 -#define SM7150_MASTER_UFS_MEM 49 -#define SM7150_MASTER_USB3 50 -#define SM7150_MASTER_VIDEO_P0 51 -#define SM7150_MASTER_VIDEO_P1 52 -#define SM7150_MASTER_VIDEO_PROC 53 -#define SM7150_SLAVE_A1NOC_CFG 54 -#define SM7150_SLAVE_A2NOC_CFG 55 -#define SM7150_SLAVE_AHB2PHY_NORTH 56 -#define SM7150_SLAVE_AHB2PHY_SOUTH 57 -#define SM7150_SLAVE_AHB2PHY_WEST 58 -#define SM7150_SLAVE_ANOC_PCIE_GEM_NOC 59 -#define SM7150_SLAVE_AOP 60 -#define SM7150_SLAVE_AOSS 61 -#define SM7150_SLAVE_APPSS 62 -#define SM7150_SLAVE_CAMERA_CFG 63 -#define SM7150_SLAVE_CAMERA_NRT_THROTTLE_CFG 64 -#define SM7150_SLAVE_CAMERA_RT_THROTTLE_CFG 65 -#define SM7150_SLAVE_CAMNOC_UNCOMP 66 -#define SM7150_SLAVE_CDSP_CFG 67 -#define SM7150_SLAVE_CDSP_GEM_NOC 68 -#define SM7150_SLAVE_CLK_CTL 69 -#define SM7150_SLAVE_CNOC_A2NOC 70 -#define SM7150_SLAVE_CNOC_DDRSS 71 -#define SM7150_SLAVE_CNOC_MNOC_CFG 72 -#define SM7150_SLAVE_CRYPTO_0_CFG 73 -#define SM7150_SLAVE_DISPLAY_CFG 74 -#define SM7150_SLAVE_DISPLAY_THROTTLE_CFG 75 -#define SM7150_SLAVE_EBI_CH0 76 -#define SM7150_SLAVE_EMMC_CFG 77 -#define SM7150_SLAVE_GEM_NOC_CFG 78 -#define SM7150_SLAVE_GEM_NOC_SNOC 79 -#define SM7150_SLAVE_GLM 80 -#define SM7150_SLAVE_GRAPHICS_3D_CFG 81 -#define SM7150_SLAVE_IMEM_CFG 82 -#define SM7150_SLAVE_IPA_CFG 83 -#define SM7150_SLAVE_LLCC 84 -#define SM7150_SLAVE_LLCC_CFG 85 -#define SM7150_SLAVE_MNOC_HF_MEM_NOC 86 -#define SM7150_SLAVE_MNOC_SF_MEM_NOC 87 -#define SM7150_SLAVE_MSS_PROC_MS_MPU_CFG 88 -#define SM7150_SLAVE_OCIMEM 89 -#define SM7150_SLAVE_PCIE_CFG 90 -#define SM7150_SLAVE_PDM 91 -#define SM7150_SLAVE_PIMEM 92 -#define SM7150_SLAVE_PIMEM_CFG 93 -#define SM7150_SLAVE_PRNG 94 -#define SM7150_SLAVE_QDSS_CFG 95 -#define SM7150_SLAVE_QDSS_STM 96 -#define SM7150_SLAVE_QUP_0 97 -#define SM7150_SLAVE_QUP_1 98 -#define SM7150_SLAVE_RBCPR_CX_CFG 99 -#define SM7150_SLAVE_RBCPR_MX_CFG 100 -#define SM7150_SLAVE_SDCC_2 101 -#define SM7150_SLAVE_SDCC_4 102 -#define SM7150_SLAVE_SERVICE_A1NOC 103 -#define SM7150_SLAVE_SERVICE_A2NOC 104 -#define SM7150_SLAVE_SERVICE_CNOC 105 -#define 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This gives more flexibility and also allows us to drop the .num_links member, saving from possible errors related to it being not set or set incorrectly. Signed-off-by: Dmitry Baryshkov --- drivers/interconnect/qcom/sm8150.c | 716 ++++++++++++++++++---------------= ---- drivers/interconnect/qcom/sm8150.h | 152 -------- 2 files changed, 355 insertions(+), 513 deletions(-) diff --git a/drivers/interconnect/qcom/sm8150.c b/drivers/interconnect/qcom= /sm8150.c index edfe824cad3533cfc6263c2031838f96e1986fa5..58a6643921bb4e9c3298352e3fb= 5755b92162a6d 100644 --- a/drivers/interconnect/qcom/sm8150.c +++ b/drivers/interconnect/qcom/sm8150.c @@ -14,1268 +14,1252 @@ =20 #include "bcm-voter.h" #include "icc-rpmh.h" -#include "sm8150.h" + +static struct qcom_icc_node qhm_a1noc_cfg; +static struct qcom_icc_node qhm_qup0; +static struct qcom_icc_node xm_emac; +static struct qcom_icc_node xm_ufs_mem; +static struct qcom_icc_node xm_usb3_0; +static struct qcom_icc_node xm_usb3_1; +static struct qcom_icc_node qhm_a2noc_cfg; +static struct qcom_icc_node qhm_qdss_bam; +static struct qcom_icc_node qhm_qspi; +static struct qcom_icc_node qhm_qup1; +static struct qcom_icc_node qhm_qup2; +static struct qcom_icc_node qhm_sensorss_ahb; +static struct qcom_icc_node qhm_tsif; +static struct qcom_icc_node qnm_cnoc; +static struct qcom_icc_node qxm_crypto; +static struct qcom_icc_node qxm_ipa; +static struct qcom_icc_node xm_pcie3_0; +static struct qcom_icc_node xm_pcie3_1; +static struct qcom_icc_node xm_qdss_etr; +static struct qcom_icc_node xm_sdc2; +static struct qcom_icc_node xm_sdc4; +static struct qcom_icc_node qxm_camnoc_hf0_uncomp; +static struct qcom_icc_node qxm_camnoc_hf1_uncomp; +static struct qcom_icc_node qxm_camnoc_sf_uncomp; +static struct qcom_icc_node qnm_npu; +static struct qcom_icc_node qhm_spdm; +static struct qcom_icc_node qnm_snoc; +static struct qcom_icc_node xm_qdss_dap; +static struct qcom_icc_node qhm_cnoc_dc_noc; +static struct qcom_icc_node acm_apps; +static struct qcom_icc_node acm_gpu_tcu; +static struct qcom_icc_node acm_sys_tcu; +static struct qcom_icc_node qhm_gemnoc_cfg; +static struct qcom_icc_node qnm_cmpnoc; +static struct qcom_icc_node qnm_gpu; +static struct qcom_icc_node qnm_mnoc_hf; +static struct qcom_icc_node qnm_mnoc_sf; +static struct qcom_icc_node qnm_pcie; +static struct qcom_icc_node qnm_snoc_gc; +static struct qcom_icc_node qnm_snoc_sf; +static struct qcom_icc_node qxm_ecc; +static struct qcom_icc_node llcc_mc; +static struct qcom_icc_node qhm_mnoc_cfg; +static struct qcom_icc_node qxm_camnoc_hf0; +static struct qcom_icc_node qxm_camnoc_hf1; +static struct qcom_icc_node qxm_camnoc_sf; +static struct qcom_icc_node qxm_mdp0; +static struct qcom_icc_node qxm_mdp1; +static struct qcom_icc_node qxm_rot; +static struct qcom_icc_node qxm_venus0; +static struct qcom_icc_node qxm_venus1; +static struct qcom_icc_node qxm_venus_arm9; +static struct qcom_icc_node qhm_snoc_cfg; +static struct qcom_icc_node qnm_aggre1_noc; +static struct qcom_icc_node qnm_aggre2_noc; +static struct qcom_icc_node qnm_gemnoc; +static struct qcom_icc_node qxm_pimem; +static struct qcom_icc_node xm_gic; +static struct qcom_icc_node qns_a1noc_snoc; +static struct qcom_icc_node srvc_aggre1_noc; +static struct qcom_icc_node qns_a2noc_snoc; +static struct qcom_icc_node qns_pcie_mem_noc; +static struct qcom_icc_node srvc_aggre2_noc; +static struct qcom_icc_node qns_camnoc_uncomp; +static struct qcom_icc_node qns_cdsp_mem_noc; +static struct qcom_icc_node qhs_a1_noc_cfg; +static struct qcom_icc_node qhs_a2_noc_cfg; +static struct qcom_icc_node qhs_ahb2phy_south; +static struct qcom_icc_node qhs_aop; +static struct qcom_icc_node qhs_aoss; +static struct qcom_icc_node qhs_camera_cfg; +static struct qcom_icc_node qhs_clk_ctl; +static struct qcom_icc_node qhs_compute_dsp; +static struct qcom_icc_node qhs_cpr_cx; +static struct qcom_icc_node qhs_cpr_mmcx; +static struct qcom_icc_node qhs_cpr_mx; +static struct qcom_icc_node qhs_crypto0_cfg; +static struct qcom_icc_node qhs_ddrss_cfg; +static struct qcom_icc_node qhs_display_cfg; +static struct qcom_icc_node qhs_emac_cfg; +static struct qcom_icc_node qhs_glm; +static struct qcom_icc_node qhs_gpuss_cfg; +static struct qcom_icc_node qhs_imem_cfg; +static struct qcom_icc_node qhs_ipa; +static struct qcom_icc_node qhs_mnoc_cfg; +static struct qcom_icc_node qhs_npu_cfg; +static struct qcom_icc_node qhs_pcie0_cfg; +static struct qcom_icc_node qhs_pcie1_cfg; +static struct qcom_icc_node qhs_phy_refgen_north; +static struct qcom_icc_node qhs_pimem_cfg; +static struct qcom_icc_node qhs_prng; +static struct qcom_icc_node qhs_qdss_cfg; +static struct qcom_icc_node qhs_qspi; +static struct qcom_icc_node qhs_qupv3_east; +static struct qcom_icc_node qhs_qupv3_north; +static struct qcom_icc_node qhs_qupv3_south; +static struct qcom_icc_node qhs_sdc2; +static struct qcom_icc_node qhs_sdc4; +static struct qcom_icc_node qhs_snoc_cfg; +static struct qcom_icc_node qhs_spdm; +static struct qcom_icc_node qhs_spss_cfg; +static struct qcom_icc_node qhs_ssc_cfg; +static struct qcom_icc_node qhs_tcsr; +static struct qcom_icc_node qhs_tlmm_east; +static struct qcom_icc_node qhs_tlmm_north; +static struct qcom_icc_node qhs_tlmm_south; +static struct qcom_icc_node qhs_tlmm_west; +static struct qcom_icc_node qhs_tsif; +static struct qcom_icc_node qhs_ufs_card_cfg; +static struct qcom_icc_node qhs_ufs_mem_cfg; +static struct qcom_icc_node qhs_usb3_0; +static struct qcom_icc_node qhs_usb3_1; +static struct qcom_icc_node qhs_venus_cfg; +static struct qcom_icc_node qhs_vsense_ctrl_cfg; +static struct qcom_icc_node qns_cnoc_a2noc; +static struct qcom_icc_node srvc_cnoc; +static struct qcom_icc_node qhs_llcc; +static struct qcom_icc_node qhs_memnoc; +static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg; +static struct qcom_icc_node qns_ecc; +static struct qcom_icc_node qns_gem_noc_snoc; +static struct qcom_icc_node qns_llcc; +static struct qcom_icc_node srvc_gemnoc; +static struct qcom_icc_node ebi; +static struct qcom_icc_node qns2_mem_noc; +static struct qcom_icc_node qns_mem_noc_hf; +static struct qcom_icc_node srvc_mnoc; +static struct qcom_icc_node qhs_apss; +static struct qcom_icc_node qns_cnoc; +static struct qcom_icc_node qns_gemnoc_gc; +static struct qcom_icc_node qns_gemnoc_sf; +static struct qcom_icc_node qxs_imem; +static struct qcom_icc_node qxs_pimem; +static struct qcom_icc_node srvc_snoc; +static struct qcom_icc_node xs_pcie_0; +static struct qcom_icc_node xs_pcie_1; +static struct qcom_icc_node xs_qdss_stm; +static struct qcom_icc_node xs_sys_tcu_cfg; =20 static struct qcom_icc_node qhm_a1noc_cfg =3D { .name =3D "qhm_a1noc_cfg", - .id =3D SM8150_MASTER_A1NOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8150_SLAVE_SERVICE_A1NOC }, + .link_nodes =3D { &srvc_aggre1_noc }, }; =20 static struct qcom_icc_node qhm_qup0 =3D { .name =3D "qhm_qup0", - .id =3D SM8150_MASTER_QUP_0, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8150_A1NOC_SNOC_SLV }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node xm_emac =3D { .name =3D "xm_emac", - .id =3D SM8150_MASTER_EMAC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8150_A1NOC_SNOC_SLV }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node xm_ufs_mem =3D { .name =3D "xm_ufs_mem", - .id =3D SM8150_MASTER_UFS_MEM, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8150_A1NOC_SNOC_SLV }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node xm_usb3_0 =3D { .name =3D "xm_usb3_0", - .id =3D SM8150_MASTER_USB3, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8150_A1NOC_SNOC_SLV }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node xm_usb3_1 =3D { .name =3D "xm_usb3_1", - .id =3D SM8150_MASTER_USB3_1, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8150_A1NOC_SNOC_SLV }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node qhm_a2noc_cfg =3D { .name =3D "qhm_a2noc_cfg", - .id =3D SM8150_MASTER_A2NOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8150_SLAVE_SERVICE_A2NOC }, + .link_nodes =3D { &srvc_aggre2_noc }, }; =20 static struct qcom_icc_node qhm_qdss_bam =3D { .name =3D "qhm_qdss_bam", - .id =3D SM8150_MASTER_QDSS_BAM, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8150_A2NOC_SNOC_SLV }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qhm_qspi =3D { .name =3D "qhm_qspi", - .id =3D SM8150_MASTER_QSPI, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8150_A2NOC_SNOC_SLV }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qhm_qup1 =3D { .name =3D "qhm_qup1", - .id =3D SM8150_MASTER_QUP_1, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8150_A2NOC_SNOC_SLV }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qhm_qup2 =3D { .name =3D "qhm_qup2", - .id =3D SM8150_MASTER_QUP_2, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8150_A2NOC_SNOC_SLV }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qhm_sensorss_ahb =3D { .name =3D "qhm_sensorss_ahb", - .id =3D SM8150_MASTER_SENSORS_AHB, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8150_A2NOC_SNOC_SLV }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qhm_tsif =3D { .name =3D "qhm_tsif", - .id =3D SM8150_MASTER_TSIF, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8150_A2NOC_SNOC_SLV }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qnm_cnoc =3D { .name =3D "qnm_cnoc", - .id =3D SM8150_MASTER_CNOC_A2NOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8150_A2NOC_SNOC_SLV }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qxm_crypto =3D { .name =3D "qxm_crypto", - .id =3D SM8150_MASTER_CRYPTO_CORE_0, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8150_A2NOC_SNOC_SLV }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qxm_ipa =3D { .name =3D "qxm_ipa", - .id =3D SM8150_MASTER_IPA, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8150_A2NOC_SNOC_SLV }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node xm_pcie3_0 =3D { .name =3D "xm_pcie3_0", - .id =3D SM8150_MASTER_PCIE, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8150_SLAVE_ANOC_PCIE_GEM_NOC }, + .link_nodes =3D { &qns_pcie_mem_noc }, }; =20 static struct qcom_icc_node xm_pcie3_1 =3D { .name =3D "xm_pcie3_1", - .id =3D SM8150_MASTER_PCIE_1, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8150_SLAVE_ANOC_PCIE_GEM_NOC }, + .link_nodes =3D { &qns_pcie_mem_noc }, }; =20 static struct qcom_icc_node xm_qdss_etr =3D { .name =3D "xm_qdss_etr", - .id =3D SM8150_MASTER_QDSS_ETR, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8150_A2NOC_SNOC_SLV }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node xm_sdc2 =3D { .name =3D "xm_sdc2", - .id =3D SM8150_MASTER_SDCC_2, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8150_A2NOC_SNOC_SLV }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node xm_sdc4 =3D { .name =3D "xm_sdc4", - .id =3D SM8150_MASTER_SDCC_4, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8150_A2NOC_SNOC_SLV }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qxm_camnoc_hf0_uncomp =3D { .name =3D "qxm_camnoc_hf0_uncomp", - .id =3D SM8150_MASTER_CAMNOC_HF0_UNCOMP, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8150_SLAVE_CAMNOC_UNCOMP }, + .link_nodes =3D { &qns_camnoc_uncomp }, }; =20 static struct qcom_icc_node qxm_camnoc_hf1_uncomp =3D { .name =3D "qxm_camnoc_hf1_uncomp", - .id =3D SM8150_MASTER_CAMNOC_HF1_UNCOMP, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8150_SLAVE_CAMNOC_UNCOMP }, + .link_nodes =3D { &qns_camnoc_uncomp }, }; =20 static struct qcom_icc_node qxm_camnoc_sf_uncomp =3D { .name =3D "qxm_camnoc_sf_uncomp", - .id =3D SM8150_MASTER_CAMNOC_SF_UNCOMP, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8150_SLAVE_CAMNOC_UNCOMP }, + .link_nodes =3D { &qns_camnoc_uncomp }, }; =20 static struct qcom_icc_node qnm_npu =3D { .name =3D "qnm_npu", - .id =3D SM8150_MASTER_NPU, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8150_SLAVE_CDSP_MEM_NOC }, + .link_nodes =3D { &qns_cdsp_mem_noc }, }; =20 static struct qcom_icc_node qhm_spdm =3D { .name =3D "qhm_spdm", - .id =3D SM8150_MASTER_SPDM, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8150_SLAVE_CNOC_A2NOC }, + .link_nodes =3D { &qns_cnoc_a2noc }, }; =20 static struct qcom_icc_node qnm_snoc =3D { .name =3D "qnm_snoc", - .id =3D SM8150_SNOC_CNOC_MAS, .channels =3D 1, .buswidth =3D 8, .num_links =3D 50, - .links =3D { SM8150_SLAVE_TLMM_SOUTH, - SM8150_SLAVE_CDSP_CFG, - SM8150_SLAVE_SPSS_CFG, - SM8150_SLAVE_CAMERA_CFG, - SM8150_SLAVE_SDCC_4, - SM8150_SLAVE_SDCC_2, - SM8150_SLAVE_CNOC_MNOC_CFG, - SM8150_SLAVE_EMAC_CFG, - SM8150_SLAVE_UFS_MEM_CFG, - SM8150_SLAVE_TLMM_EAST, - SM8150_SLAVE_SSC_CFG, - SM8150_SLAVE_SNOC_CFG, - SM8150_SLAVE_NORTH_PHY_CFG, - SM8150_SLAVE_QUP_0, - SM8150_SLAVE_GLM, - SM8150_SLAVE_PCIE_1_CFG, - SM8150_SLAVE_A2NOC_CFG, - SM8150_SLAVE_QDSS_CFG, - SM8150_SLAVE_DISPLAY_CFG, - SM8150_SLAVE_TCSR, - SM8150_SLAVE_CNOC_DDRSS, - SM8150_SLAVE_RBCPR_MMCX_CFG, - SM8150_SLAVE_NPU_CFG, - SM8150_SLAVE_PCIE_0_CFG, - SM8150_SLAVE_GRAPHICS_3D_CFG, - SM8150_SLAVE_VENUS_CFG, - SM8150_SLAVE_TSIF, - SM8150_SLAVE_IPA_CFG, - SM8150_SLAVE_CLK_CTL, - SM8150_SLAVE_AOP, - SM8150_SLAVE_QUP_1, - SM8150_SLAVE_AHB2PHY_SOUTH, - SM8150_SLAVE_USB3_1, - SM8150_SLAVE_SERVICE_CNOC, - SM8150_SLAVE_UFS_CARD_CFG, - SM8150_SLAVE_QUP_2, - SM8150_SLAVE_RBCPR_CX_CFG, - SM8150_SLAVE_TLMM_WEST, - SM8150_SLAVE_A1NOC_CFG, - SM8150_SLAVE_AOSS, - SM8150_SLAVE_PRNG, - SM8150_SLAVE_VSENSE_CTRL_CFG, - SM8150_SLAVE_QSPI, - SM8150_SLAVE_USB3, - SM8150_SLAVE_SPDM_WRAPPER, - SM8150_SLAVE_CRYPTO_0_CFG, - SM8150_SLAVE_PIMEM_CFG, - SM8150_SLAVE_TLMM_NORTH, - SM8150_SLAVE_RBCPR_MX_CFG, - SM8150_SLAVE_IMEM_CFG - }, + .link_nodes =3D { &qhs_tlmm_south, + &qhs_compute_dsp, + &qhs_spss_cfg, + &qhs_camera_cfg, + &qhs_sdc4, + &qhs_sdc2, + &qhs_mnoc_cfg, + &qhs_emac_cfg, + &qhs_ufs_mem_cfg, + &qhs_tlmm_east, + &qhs_ssc_cfg, + &qhs_snoc_cfg, + &qhs_phy_refgen_north, + &qhs_qupv3_south, + &qhs_glm, + &qhs_pcie1_cfg, + &qhs_a2_noc_cfg, + &qhs_qdss_cfg, + &qhs_display_cfg, + &qhs_tcsr, + &qhs_ddrss_cfg, + &qhs_cpr_mmcx, + &qhs_npu_cfg, + &qhs_pcie0_cfg, + &qhs_gpuss_cfg, + &qhs_venus_cfg, + &qhs_tsif, + &qhs_ipa, + &qhs_clk_ctl, + &qhs_aop, + &qhs_qupv3_north, + &qhs_ahb2phy_south, + &qhs_usb3_1, + &srvc_cnoc, + &qhs_ufs_card_cfg, + &qhs_qupv3_east, + &qhs_cpr_cx, + &qhs_tlmm_west, + &qhs_a1_noc_cfg, + &qhs_aoss, + &qhs_prng, + &qhs_vsense_ctrl_cfg, + &qhs_qspi, + &qhs_usb3_0, + &qhs_spdm, + &qhs_crypto0_cfg, + &qhs_pimem_cfg, + &qhs_tlmm_north, + &qhs_cpr_mx, + &qhs_imem_cfg }, }; =20 static struct qcom_icc_node xm_qdss_dap =3D { .name =3D "xm_qdss_dap", - .id =3D SM8150_MASTER_QDSS_DAP, .channels =3D 1, .buswidth =3D 8, .num_links =3D 51, - .links =3D { SM8150_SLAVE_TLMM_SOUTH, - SM8150_SLAVE_CDSP_CFG, - SM8150_SLAVE_SPSS_CFG, - SM8150_SLAVE_CAMERA_CFG, - SM8150_SLAVE_SDCC_4, - SM8150_SLAVE_SDCC_2, - SM8150_SLAVE_CNOC_MNOC_CFG, - SM8150_SLAVE_EMAC_CFG, - SM8150_SLAVE_UFS_MEM_CFG, - SM8150_SLAVE_TLMM_EAST, - SM8150_SLAVE_SSC_CFG, - SM8150_SLAVE_SNOC_CFG, - SM8150_SLAVE_NORTH_PHY_CFG, - SM8150_SLAVE_QUP_0, - SM8150_SLAVE_GLM, - SM8150_SLAVE_PCIE_1_CFG, - SM8150_SLAVE_A2NOC_CFG, - SM8150_SLAVE_QDSS_CFG, - SM8150_SLAVE_DISPLAY_CFG, - SM8150_SLAVE_TCSR, - SM8150_SLAVE_CNOC_DDRSS, - SM8150_SLAVE_CNOC_A2NOC, - SM8150_SLAVE_RBCPR_MMCX_CFG, - SM8150_SLAVE_NPU_CFG, - SM8150_SLAVE_PCIE_0_CFG, - SM8150_SLAVE_GRAPHICS_3D_CFG, - SM8150_SLAVE_VENUS_CFG, - SM8150_SLAVE_TSIF, - SM8150_SLAVE_IPA_CFG, - SM8150_SLAVE_CLK_CTL, - SM8150_SLAVE_AOP, - SM8150_SLAVE_QUP_1, - SM8150_SLAVE_AHB2PHY_SOUTH, - SM8150_SLAVE_USB3_1, - SM8150_SLAVE_SERVICE_CNOC, - SM8150_SLAVE_UFS_CARD_CFG, - SM8150_SLAVE_QUP_2, - SM8150_SLAVE_RBCPR_CX_CFG, - SM8150_SLAVE_TLMM_WEST, - SM8150_SLAVE_A1NOC_CFG, - SM8150_SLAVE_AOSS, - SM8150_SLAVE_PRNG, - SM8150_SLAVE_VSENSE_CTRL_CFG, - SM8150_SLAVE_QSPI, - SM8150_SLAVE_USB3, - SM8150_SLAVE_SPDM_WRAPPER, - SM8150_SLAVE_CRYPTO_0_CFG, - SM8150_SLAVE_PIMEM_CFG, - SM8150_SLAVE_TLMM_NORTH, - SM8150_SLAVE_RBCPR_MX_CFG, - SM8150_SLAVE_IMEM_CFG - }, + .link_nodes =3D { &qhs_tlmm_south, + &qhs_compute_dsp, + &qhs_spss_cfg, + &qhs_camera_cfg, + &qhs_sdc4, + &qhs_sdc2, + &qhs_mnoc_cfg, + &qhs_emac_cfg, + &qhs_ufs_mem_cfg, + &qhs_tlmm_east, + &qhs_ssc_cfg, + &qhs_snoc_cfg, + &qhs_phy_refgen_north, + &qhs_qupv3_south, + &qhs_glm, + &qhs_pcie1_cfg, + &qhs_a2_noc_cfg, + &qhs_qdss_cfg, + &qhs_display_cfg, + &qhs_tcsr, + &qhs_ddrss_cfg, + &qns_cnoc_a2noc, + &qhs_cpr_mmcx, + &qhs_npu_cfg, + &qhs_pcie0_cfg, + &qhs_gpuss_cfg, + &qhs_venus_cfg, + &qhs_tsif, + &qhs_ipa, + &qhs_clk_ctl, + &qhs_aop, + &qhs_qupv3_north, + &qhs_ahb2phy_south, + &qhs_usb3_1, + &srvc_cnoc, + &qhs_ufs_card_cfg, + &qhs_qupv3_east, + &qhs_cpr_cx, + &qhs_tlmm_west, + &qhs_a1_noc_cfg, + &qhs_aoss, + &qhs_prng, + &qhs_vsense_ctrl_cfg, + &qhs_qspi, + &qhs_usb3_0, + &qhs_spdm, + &qhs_crypto0_cfg, + &qhs_pimem_cfg, + &qhs_tlmm_north, + &qhs_cpr_mx, + &qhs_imem_cfg }, }; =20 static struct qcom_icc_node qhm_cnoc_dc_noc =3D { .name =3D "qhm_cnoc_dc_noc", - .id =3D SM8150_MASTER_CNOC_DC_NOC, .channels =3D 1, .buswidth =3D 4, .num_links =3D 2, - .links =3D { SM8150_SLAVE_GEM_NOC_CFG, - SM8150_SLAVE_LLCC_CFG - }, + .link_nodes =3D { &qhs_memnoc, + &qhs_llcc }, }; =20 static struct qcom_icc_node acm_apps =3D { .name =3D "acm_apps", - .id =3D SM8150_MASTER_AMPSS_M0, .channels =3D 2, .buswidth =3D 32, .num_links =3D 3, - .links =3D { SM8150_SLAVE_ECC, - SM8150_SLAVE_LLCC, - SM8150_SLAVE_GEM_NOC_SNOC - }, + .link_nodes =3D { &qns_ecc, + &qns_llcc, + &qns_gem_noc_snoc }, }; =20 static struct qcom_icc_node acm_gpu_tcu =3D { .name =3D "acm_gpu_tcu", - .id =3D SM8150_MASTER_GPU_TCU, .channels =3D 1, .buswidth =3D 8, .num_links =3D 2, - .links =3D { SM8150_SLAVE_LLCC, - SM8150_SLAVE_GEM_NOC_SNOC - }, + .link_nodes =3D { &qns_llcc, + &qns_gem_noc_snoc }, }; =20 static struct qcom_icc_node acm_sys_tcu =3D { .name =3D "acm_sys_tcu", - .id =3D SM8150_MASTER_SYS_TCU, .channels =3D 1, .buswidth =3D 8, .num_links =3D 2, - .links =3D { SM8150_SLAVE_LLCC, - SM8150_SLAVE_GEM_NOC_SNOC - }, + .link_nodes =3D { &qns_llcc, + &qns_gem_noc_snoc }, }; =20 static struct qcom_icc_node qhm_gemnoc_cfg =3D { .name =3D "qhm_gemnoc_cfg", - .id =3D SM8150_MASTER_GEM_NOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 2, - .links =3D { SM8150_SLAVE_SERVICE_GEM_NOC, - SM8150_SLAVE_MSS_PROC_MS_MPU_CFG - }, + .link_nodes =3D { &srvc_gemnoc, + &qhs_mdsp_ms_mpu_cfg }, }; =20 static struct qcom_icc_node qnm_cmpnoc =3D { .name =3D "qnm_cmpnoc", - .id =3D SM8150_MASTER_COMPUTE_NOC, .channels =3D 2, .buswidth =3D 32, .num_links =3D 3, - .links =3D { SM8150_SLAVE_ECC, - SM8150_SLAVE_LLCC, - SM8150_SLAVE_GEM_NOC_SNOC - }, + .link_nodes =3D { &qns_ecc, + &qns_llcc, + &qns_gem_noc_snoc }, }; =20 static struct qcom_icc_node qnm_gpu =3D { .name =3D "qnm_gpu", - .id =3D SM8150_MASTER_GRAPHICS_3D, .channels =3D 2, .buswidth =3D 32, .num_links =3D 2, - .links =3D { SM8150_SLAVE_LLCC, - SM8150_SLAVE_GEM_NOC_SNOC - }, + .link_nodes =3D { &qns_llcc, + &qns_gem_noc_snoc }, }; =20 static struct qcom_icc_node qnm_mnoc_hf =3D { .name =3D "qnm_mnoc_hf", - .id =3D SM8150_MASTER_MNOC_HF_MEM_NOC, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8150_SLAVE_LLCC }, + .link_nodes =3D { &qns_llcc }, }; =20 static struct qcom_icc_node qnm_mnoc_sf =3D { .name =3D "qnm_mnoc_sf", - .id =3D SM8150_MASTER_MNOC_SF_MEM_NOC, .channels =3D 1, .buswidth =3D 32, .num_links =3D 2, - .links =3D { SM8150_SLAVE_LLCC, - SM8150_SLAVE_GEM_NOC_SNOC - }, + .link_nodes =3D { &qns_llcc, + &qns_gem_noc_snoc }, }; =20 static struct qcom_icc_node qnm_pcie =3D { .name =3D "qnm_pcie", - .id =3D SM8150_MASTER_GEM_NOC_PCIE_SNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 2, - .links =3D { SM8150_SLAVE_LLCC, - SM8150_SLAVE_GEM_NOC_SNOC - }, + .link_nodes =3D { &qns_llcc, + &qns_gem_noc_snoc }, }; =20 static struct qcom_icc_node qnm_snoc_gc =3D { .name =3D "qnm_snoc_gc", - .id =3D SM8150_MASTER_SNOC_GC_MEM_NOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8150_SLAVE_LLCC }, + .link_nodes =3D { &qns_llcc }, }; =20 static struct qcom_icc_node qnm_snoc_sf =3D { .name =3D "qnm_snoc_sf", - .id =3D SM8150_MASTER_SNOC_SF_MEM_NOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM8150_SLAVE_LLCC }, + .link_nodes =3D { &qns_llcc }, }; =20 static struct qcom_icc_node qxm_ecc =3D { .name =3D "qxm_ecc", - .id =3D SM8150_MASTER_ECC, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8150_SLAVE_LLCC }, + .link_nodes =3D { &qns_llcc }, }; =20 static struct qcom_icc_node llcc_mc =3D { .name =3D "llcc_mc", - .id =3D SM8150_MASTER_LLCC, .channels =3D 4, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8150_SLAVE_EBI_CH0 }, + .link_nodes =3D { &ebi }, }; =20 static struct qcom_icc_node qhm_mnoc_cfg =3D { .name =3D "qhm_mnoc_cfg", - .id =3D SM8150_MASTER_CNOC_MNOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8150_SLAVE_SERVICE_MNOC }, + .link_nodes =3D { &srvc_mnoc }, }; =20 static struct qcom_icc_node qxm_camnoc_hf0 =3D { .name =3D "qxm_camnoc_hf0", - .id =3D SM8150_MASTER_CAMNOC_HF0, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8150_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_hf }, }; =20 static struct qcom_icc_node qxm_camnoc_hf1 =3D { .name =3D "qxm_camnoc_hf1", - .id =3D SM8150_MASTER_CAMNOC_HF1, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8150_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_hf }, }; =20 static struct qcom_icc_node qxm_camnoc_sf =3D { .name =3D "qxm_camnoc_sf", - .id =3D SM8150_MASTER_CAMNOC_SF, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8150_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns2_mem_noc }, }; =20 static struct qcom_icc_node qxm_mdp0 =3D { .name =3D "qxm_mdp0", - .id =3D SM8150_MASTER_MDP_PORT0, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8150_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_hf }, }; =20 static struct qcom_icc_node qxm_mdp1 =3D { .name =3D "qxm_mdp1", - .id =3D SM8150_MASTER_MDP_PORT1, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8150_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_hf }, }; =20 static struct qcom_icc_node qxm_rot =3D { .name =3D "qxm_rot", - .id =3D SM8150_MASTER_ROTATOR, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8150_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns2_mem_noc }, }; =20 static struct qcom_icc_node qxm_venus0 =3D { .name =3D "qxm_venus0", - .id =3D SM8150_MASTER_VIDEO_P0, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8150_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns2_mem_noc }, }; =20 static struct qcom_icc_node qxm_venus1 =3D { .name =3D "qxm_venus1", - .id =3D SM8150_MASTER_VIDEO_P1, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8150_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns2_mem_noc }, }; =20 static struct qcom_icc_node qxm_venus_arm9 =3D { .name =3D "qxm_venus_arm9", - .id =3D SM8150_MASTER_VIDEO_PROC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8150_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns2_mem_noc }, }; =20 static struct qcom_icc_node qhm_snoc_cfg =3D { .name =3D "qhm_snoc_cfg", - .id =3D SM8150_MASTER_SNOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8150_SLAVE_SERVICE_SNOC }, + .link_nodes =3D { &srvc_snoc }, }; =20 static struct qcom_icc_node qnm_aggre1_noc =3D { .name =3D "qnm_aggre1_noc", - .id =3D SM8150_A1NOC_SNOC_MAS, .channels =3D 1, .buswidth =3D 16, .num_links =3D 6, - .links =3D { SM8150_SLAVE_SNOC_GEM_NOC_SF, - SM8150_SLAVE_PIMEM, - SM8150_SLAVE_OCIMEM, - SM8150_SLAVE_APPSS, - SM8150_SNOC_CNOC_SLV, - SM8150_SLAVE_QDSS_STM - }, + .link_nodes =3D { &qns_gemnoc_sf, + &qxs_pimem, + &qxs_imem, + &qhs_apss, + &qns_cnoc, + &xs_qdss_stm }, }; =20 static struct qcom_icc_node qnm_aggre2_noc =3D { .name =3D "qnm_aggre2_noc", - .id =3D SM8150_A2NOC_SNOC_MAS, .channels =3D 1, .buswidth =3D 16, .num_links =3D 9, - .links =3D { SM8150_SLAVE_SNOC_GEM_NOC_SF, - SM8150_SLAVE_PIMEM, - SM8150_SLAVE_OCIMEM, - SM8150_SLAVE_APPSS, - SM8150_SNOC_CNOC_SLV, - SM8150_SLAVE_PCIE_0, - SM8150_SLAVE_PCIE_1, - SM8150_SLAVE_TCU, - SM8150_SLAVE_QDSS_STM - }, + .link_nodes =3D { &qns_gemnoc_sf, + &qxs_pimem, + &qxs_imem, + &qhs_apss, + &qns_cnoc, + &xs_pcie_0, + &xs_pcie_1, + &xs_sys_tcu_cfg, + &xs_qdss_stm }, }; =20 static struct qcom_icc_node qnm_gemnoc =3D { .name =3D "qnm_gemnoc", - .id =3D SM8150_MASTER_GEM_NOC_SNOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 6, - .links =3D { SM8150_SLAVE_PIMEM, - SM8150_SLAVE_OCIMEM, - SM8150_SLAVE_APPSS, - SM8150_SNOC_CNOC_SLV, - SM8150_SLAVE_TCU, - SM8150_SLAVE_QDSS_STM - }, + .link_nodes =3D { &qxs_pimem, + &qxs_imem, + &qhs_apss, + &qns_cnoc, + &xs_sys_tcu_cfg, + &xs_qdss_stm }, }; =20 static struct qcom_icc_node qxm_pimem =3D { .name =3D "qxm_pimem", - .id =3D SM8150_MASTER_PIMEM, .channels =3D 1, .buswidth =3D 8, .num_links =3D 2, - .links =3D { SM8150_SLAVE_SNOC_GEM_NOC_GC, - SM8150_SLAVE_OCIMEM - }, + .link_nodes =3D { &qns_gemnoc_gc, + &qxs_imem }, }; =20 static struct qcom_icc_node xm_gic =3D { .name =3D "xm_gic", - .id =3D SM8150_MASTER_GIC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 2, - .links =3D { SM8150_SLAVE_SNOC_GEM_NOC_GC, - SM8150_SLAVE_OCIMEM - }, + .link_nodes =3D { &qns_gemnoc_gc, + &qxs_imem }, }; =20 static struct qcom_icc_node qns_a1noc_snoc =3D { .name =3D "qns_a1noc_snoc", - .id =3D SM8150_A1NOC_SNOC_SLV, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM8150_A1NOC_SNOC_MAS }, + .link_nodes =3D { &qnm_aggre1_noc }, }; =20 static struct qcom_icc_node srvc_aggre1_noc =3D { .name =3D "srvc_aggre1_noc", - .id =3D SM8150_SLAVE_SERVICE_A1NOC, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qns_a2noc_snoc =3D { .name =3D "qns_a2noc_snoc", - .id =3D SM8150_A2NOC_SNOC_SLV, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM8150_A2NOC_SNOC_MAS }, + .link_nodes =3D { &qnm_aggre2_noc }, }; =20 static struct qcom_icc_node qns_pcie_mem_noc =3D { .name =3D "qns_pcie_mem_noc", - .id =3D SM8150_SLAVE_ANOC_PCIE_GEM_NOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM8150_MASTER_GEM_NOC_PCIE_SNOC }, + .link_nodes =3D { &qnm_pcie }, }; =20 static struct qcom_icc_node srvc_aggre2_noc =3D { .name =3D "srvc_aggre2_noc", - .id =3D SM8150_SLAVE_SERVICE_A2NOC, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qns_camnoc_uncomp =3D { .name =3D "qns_camnoc_uncomp", - .id =3D SM8150_SLAVE_CAMNOC_UNCOMP, .channels =3D 1, .buswidth =3D 32, }; =20 static struct qcom_icc_node qns_cdsp_mem_noc =3D { .name =3D "qns_cdsp_mem_noc", - .id =3D SM8150_SLAVE_CDSP_MEM_NOC, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8150_MASTER_COMPUTE_NOC }, + .link_nodes =3D { &qnm_cmpnoc }, }; =20 static struct qcom_icc_node qhs_a1_noc_cfg =3D { .name =3D "qhs_a1_noc_cfg", - .id =3D SM8150_SLAVE_A1NOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8150_MASTER_A1NOC_CFG }, + .link_nodes =3D { &qhm_a1noc_cfg }, }; =20 static struct qcom_icc_node qhs_a2_noc_cfg =3D { .name =3D "qhs_a2_noc_cfg", - .id =3D SM8150_SLAVE_A2NOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8150_MASTER_A2NOC_CFG }, + .link_nodes =3D { &qhm_a2noc_cfg }, }; =20 static struct qcom_icc_node qhs_ahb2phy_south =3D { .name =3D "qhs_ahb2phy_south", - .id =3D SM8150_SLAVE_AHB2PHY_SOUTH, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_aop =3D { .name =3D "qhs_aop", - .id =3D SM8150_SLAVE_AOP, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_aoss =3D { .name =3D "qhs_aoss", - .id =3D SM8150_SLAVE_AOSS, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_camera_cfg =3D { .name =3D "qhs_camera_cfg", - .id =3D SM8150_SLAVE_CAMERA_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_clk_ctl =3D { .name =3D "qhs_clk_ctl", - .id =3D SM8150_SLAVE_CLK_CTL, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_compute_dsp =3D { .name =3D "qhs_compute_dsp", - .id =3D SM8150_SLAVE_CDSP_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_cpr_cx =3D { .name =3D "qhs_cpr_cx", - .id =3D SM8150_SLAVE_RBCPR_CX_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_cpr_mmcx =3D { .name =3D "qhs_cpr_mmcx", - .id =3D SM8150_SLAVE_RBCPR_MMCX_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_cpr_mx =3D { .name =3D "qhs_cpr_mx", - .id =3D SM8150_SLAVE_RBCPR_MX_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_crypto0_cfg =3D { .name =3D "qhs_crypto0_cfg", - .id =3D SM8150_SLAVE_CRYPTO_0_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_ddrss_cfg =3D { .name =3D "qhs_ddrss_cfg", - .id =3D SM8150_SLAVE_CNOC_DDRSS, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8150_MASTER_CNOC_DC_NOC }, + .link_nodes =3D { &qhm_cnoc_dc_noc }, }; =20 static struct qcom_icc_node qhs_display_cfg =3D { .name =3D "qhs_display_cfg", - .id =3D SM8150_SLAVE_DISPLAY_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_emac_cfg =3D { .name =3D "qhs_emac_cfg", - .id =3D SM8150_SLAVE_EMAC_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_glm =3D { .name =3D "qhs_glm", - .id =3D SM8150_SLAVE_GLM, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_gpuss_cfg =3D { .name =3D "qhs_gpuss_cfg", - .id =3D SM8150_SLAVE_GRAPHICS_3D_CFG, .channels =3D 1, .buswidth =3D 8, }; =20 static struct qcom_icc_node qhs_imem_cfg =3D { .name =3D "qhs_imem_cfg", - .id =3D SM8150_SLAVE_IMEM_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_ipa =3D { .name =3D "qhs_ipa", - .id =3D SM8150_SLAVE_IPA_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_mnoc_cfg =3D { .name =3D "qhs_mnoc_cfg", - .id =3D SM8150_SLAVE_CNOC_MNOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8150_MASTER_CNOC_MNOC_CFG }, + .link_nodes =3D { &qhm_mnoc_cfg }, }; =20 static struct qcom_icc_node qhs_npu_cfg =3D { .name =3D "qhs_npu_cfg", - .id =3D SM8150_SLAVE_NPU_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_pcie0_cfg =3D { .name =3D "qhs_pcie0_cfg", - .id =3D SM8150_SLAVE_PCIE_0_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_pcie1_cfg =3D { .name =3D "qhs_pcie1_cfg", - .id =3D SM8150_SLAVE_PCIE_1_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_phy_refgen_north =3D { .name =3D "qhs_phy_refgen_north", - .id =3D SM8150_SLAVE_NORTH_PHY_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_pimem_cfg =3D { .name =3D "qhs_pimem_cfg", - .id =3D SM8150_SLAVE_PIMEM_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_prng =3D { .name =3D "qhs_prng", - .id =3D SM8150_SLAVE_PRNG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_qdss_cfg =3D { .name =3D "qhs_qdss_cfg", - .id =3D SM8150_SLAVE_QDSS_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_qspi =3D { .name =3D "qhs_qspi", - .id =3D SM8150_SLAVE_QSPI, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_qupv3_east =3D { .name =3D "qhs_qupv3_east", - .id =3D SM8150_SLAVE_QUP_2, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_qupv3_north =3D { .name =3D "qhs_qupv3_north", - .id =3D SM8150_SLAVE_QUP_1, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_qupv3_south =3D { .name =3D "qhs_qupv3_south", - .id =3D SM8150_SLAVE_QUP_0, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_sdc2 =3D { .name =3D "qhs_sdc2", - .id =3D SM8150_SLAVE_SDCC_2, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_sdc4 =3D { .name =3D "qhs_sdc4", - .id =3D SM8150_SLAVE_SDCC_4, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_snoc_cfg =3D { .name =3D "qhs_snoc_cfg", - .id =3D SM8150_SLAVE_SNOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8150_MASTER_SNOC_CFG }, + .link_nodes =3D { &qhm_snoc_cfg }, }; =20 static struct qcom_icc_node qhs_spdm =3D { .name =3D "qhs_spdm", - .id =3D SM8150_SLAVE_SPDM_WRAPPER, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_spss_cfg =3D { .name =3D "qhs_spss_cfg", - .id =3D SM8150_SLAVE_SPSS_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_ssc_cfg =3D { .name =3D "qhs_ssc_cfg", - .id =3D SM8150_SLAVE_SSC_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_tcsr =3D { .name =3D "qhs_tcsr", - .id =3D SM8150_SLAVE_TCSR, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_tlmm_east =3D { .name =3D "qhs_tlmm_east", - .id =3D SM8150_SLAVE_TLMM_EAST, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_tlmm_north =3D { .name =3D "qhs_tlmm_north", - .id =3D SM8150_SLAVE_TLMM_NORTH, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_tlmm_south =3D { .name =3D "qhs_tlmm_south", - .id =3D SM8150_SLAVE_TLMM_SOUTH, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_tlmm_west =3D { .name =3D "qhs_tlmm_west", - .id =3D SM8150_SLAVE_TLMM_WEST, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_tsif =3D { .name =3D "qhs_tsif", - .id =3D SM8150_SLAVE_TSIF, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_ufs_card_cfg =3D { .name =3D "qhs_ufs_card_cfg", - .id =3D SM8150_SLAVE_UFS_CARD_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_ufs_mem_cfg =3D { .name =3D "qhs_ufs_mem_cfg", - .id =3D SM8150_SLAVE_UFS_MEM_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_usb3_0 =3D { .name =3D "qhs_usb3_0", - .id =3D SM8150_SLAVE_USB3, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_usb3_1 =3D { .name =3D "qhs_usb3_1", - .id =3D SM8150_SLAVE_USB3_1, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_venus_cfg =3D { .name =3D "qhs_venus_cfg", - .id =3D SM8150_SLAVE_VENUS_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_vsense_ctrl_cfg =3D { .name =3D "qhs_vsense_ctrl_cfg", - .id =3D SM8150_SLAVE_VSENSE_CTRL_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qns_cnoc_a2noc =3D { .name =3D "qns_cnoc_a2noc", - .id =3D SM8150_SLAVE_CNOC_A2NOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8150_MASTER_CNOC_A2NOC }, + .link_nodes =3D { &qnm_cnoc }, }; =20 static struct qcom_icc_node srvc_cnoc =3D { .name =3D "srvc_cnoc", - .id =3D SM8150_SLAVE_SERVICE_CNOC, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_llcc =3D { .name =3D "qhs_llcc", - .id =3D SM8150_SLAVE_LLCC_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_memnoc =3D { .name =3D "qhs_memnoc", - .id =3D SM8150_SLAVE_GEM_NOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8150_MASTER_GEM_NOC_CFG }, + .link_nodes =3D { &qhm_gemnoc_cfg }, }; =20 static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg =3D { .name =3D "qhs_mdsp_ms_mpu_cfg", - .id =3D SM8150_SLAVE_MSS_PROC_MS_MPU_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qns_ecc =3D { .name =3D "qns_ecc", - .id =3D SM8150_SLAVE_ECC, .channels =3D 1, .buswidth =3D 32, }; =20 static struct qcom_icc_node qns_gem_noc_snoc =3D { .name =3D "qns_gem_noc_snoc", - .id =3D SM8150_SLAVE_GEM_NOC_SNOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8150_MASTER_GEM_NOC_SNOC }, + .link_nodes =3D { &qnm_gemnoc }, }; =20 static struct qcom_icc_node qns_llcc =3D { .name =3D "qns_llcc", - .id =3D SM8150_SLAVE_LLCC, .channels =3D 4, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM8150_MASTER_LLCC }, + .link_nodes =3D { &llcc_mc }, }; =20 static struct qcom_icc_node srvc_gemnoc =3D { .name =3D "srvc_gemnoc", - .id =3D SM8150_SLAVE_SERVICE_GEM_NOC, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node ebi =3D { .name =3D "ebi", - .id =3D SM8150_SLAVE_EBI_CH0, .channels =3D 4, .buswidth =3D 4, }; =20 static struct qcom_icc_node qns2_mem_noc =3D { .name =3D "qns2_mem_noc", - .id =3D SM8150_SLAVE_MNOC_SF_MEM_NOC, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8150_MASTER_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qnm_mnoc_sf }, }; =20 static struct qcom_icc_node qns_mem_noc_hf =3D { .name =3D "qns_mem_noc_hf", - .id =3D SM8150_SLAVE_MNOC_HF_MEM_NOC, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8150_MASTER_MNOC_HF_MEM_NOC }, + .link_nodes =3D { &qnm_mnoc_hf }, }; =20 static struct qcom_icc_node srvc_mnoc =3D { .name =3D "srvc_mnoc", - .id =3D SM8150_SLAVE_SERVICE_MNOC, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_apss =3D { .name =3D "qhs_apss", - .id =3D SM8150_SLAVE_APPSS, .channels =3D 1, .buswidth =3D 8, }; =20 static struct qcom_icc_node qns_cnoc =3D { .name =3D "qns_cnoc", - .id =3D SM8150_SNOC_CNOC_SLV, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8150_SNOC_CNOC_MAS }, + .link_nodes =3D { &qnm_snoc }, }; =20 static struct qcom_icc_node qns_gemnoc_gc =3D { .name =3D "qns_gemnoc_gc", - .id =3D SM8150_SLAVE_SNOC_GEM_NOC_GC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8150_MASTER_SNOC_GC_MEM_NOC }, + .link_nodes =3D { &qnm_snoc_gc }, }; =20 static struct qcom_icc_node qns_gemnoc_sf =3D { .name =3D "qns_gemnoc_sf", - .id =3D SM8150_SLAVE_SNOC_GEM_NOC_SF, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM8150_MASTER_SNOC_SF_MEM_NOC }, + .link_nodes =3D { &qnm_snoc_sf }, }; =20 static struct qcom_icc_node qxs_imem =3D { .name =3D "qxs_imem", - .id =3D SM8150_SLAVE_OCIMEM, .channels =3D 1, .buswidth =3D 8, }; =20 static struct qcom_icc_node qxs_pimem =3D { .name =3D "qxs_pimem", - .id =3D SM8150_SLAVE_PIMEM, .channels =3D 1, .buswidth =3D 8, }; =20 static struct qcom_icc_node srvc_snoc =3D { .name =3D "srvc_snoc", - .id =3D SM8150_SLAVE_SERVICE_SNOC, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node xs_pcie_0 =3D { .name =3D "xs_pcie_0", - .id =3D SM8150_SLAVE_PCIE_0, .channels =3D 1, .buswidth =3D 8, }; =20 static struct qcom_icc_node xs_pcie_1 =3D { .name =3D "xs_pcie_1", - .id =3D SM8150_SLAVE_PCIE_1, .channels =3D 1, .buswidth =3D 8, }; =20 static struct qcom_icc_node xs_qdss_stm =3D { .name =3D "xs_qdss_stm", - .id =3D SM8150_SLAVE_QDSS_STM, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node xs_sys_tcu_cfg =3D { .name =3D "xs_sys_tcu_cfg", - .id =3D SM8150_SLAVE_TCU, .channels =3D 1, .buswidth =3D 8, }; @@ -1554,6 +1538,7 @@ static struct qcom_icc_node * const aggre1_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sm8150_aggre1_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D aggre1_noc_nodes, .num_nodes =3D ARRAY_SIZE(aggre1_noc_nodes), .bcms =3D aggre1_noc_bcms, @@ -1589,6 +1574,7 @@ static struct qcom_icc_node * const aggre2_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sm8150_aggre2_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D aggre2_noc_nodes, .num_nodes =3D ARRAY_SIZE(aggre2_noc_nodes), .bcms =3D aggre2_noc_bcms, @@ -1607,6 +1593,7 @@ static struct qcom_icc_node * const camnoc_virt_nodes= [] =3D { }; =20 static const struct qcom_icc_desc sm8150_camnoc_virt =3D { + .alloc_dyn_id =3D true, .nodes =3D camnoc_virt_nodes, .num_nodes =3D ARRAY_SIZE(camnoc_virt_nodes), .bcms =3D camnoc_virt_bcms, @@ -1624,6 +1611,7 @@ static struct qcom_icc_node * const compute_noc_nodes= [] =3D { }; =20 static const struct qcom_icc_desc sm8150_compute_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D compute_noc_nodes, .num_nodes =3D ARRAY_SIZE(compute_noc_nodes), .bcms =3D compute_noc_bcms, @@ -1692,6 +1680,7 @@ static struct qcom_icc_node * const config_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sm8150_config_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D config_noc_nodes, .num_nodes =3D ARRAY_SIZE(config_noc_nodes), .bcms =3D config_noc_bcms, @@ -1708,6 +1697,7 @@ static struct qcom_icc_node * const dc_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sm8150_dc_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D dc_noc_nodes, .num_nodes =3D ARRAY_SIZE(dc_noc_nodes), .bcms =3D dc_noc_bcms, @@ -1743,6 +1733,7 @@ static struct qcom_icc_node * const gem_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sm8150_gem_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D gem_noc_nodes, .num_nodes =3D ARRAY_SIZE(gem_noc_nodes), .bcms =3D gem_noc_bcms, @@ -1760,6 +1751,7 @@ static struct qcom_icc_node * const mc_virt_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sm8150_mc_virt =3D { + .alloc_dyn_id =3D true, .nodes =3D mc_virt_nodes, .num_nodes =3D ARRAY_SIZE(mc_virt_nodes), .bcms =3D mc_virt_bcms, @@ -1790,6 +1782,7 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sm8150_mmss_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D mmss_noc_nodes, .num_nodes =3D ARRAY_SIZE(mmss_noc_nodes), .bcms =3D mmss_noc_bcms, @@ -1831,6 +1824,7 @@ static struct qcom_icc_node * const system_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sm8150_system_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D system_noc_nodes, .num_nodes =3D ARRAY_SIZE(system_noc_nodes), .bcms =3D system_noc_bcms, diff --git a/drivers/interconnect/qcom/sm8150.h b/drivers/interconnect/qcom= /sm8150.h deleted file mode 100644 index 1d587c94eb06e1b06b0dcd582807b87aa59af075..000000000000000000000000000= 0000000000000 --- a/drivers/interconnect/qcom/sm8150.h +++ /dev/null @@ -1,152 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Qualcomm #define SM8250 interconnect IDs - * - * Copyright (c) 2020, The Linux Foundation. All rights reserved. - */ - -#ifndef __DRIVERS_INTERCONNECT_QCOM_SM8150_H -#define __DRIVERS_INTERCONNECT_QCOM_SM8150_H - -#define SM8150_A1NOC_SNOC_MAS 0 -#define SM8150_A1NOC_SNOC_SLV 1 -#define SM8150_A2NOC_SNOC_MAS 2 -#define SM8150_A2NOC_SNOC_SLV 3 -#define SM8150_MASTER_A1NOC_CFG 4 -#define SM8150_MASTER_A2NOC_CFG 5 -#define SM8150_MASTER_AMPSS_M0 6 -#define SM8150_MASTER_CAMNOC_HF0 7 -#define SM8150_MASTER_CAMNOC_HF0_UNCOMP 8 -#define SM8150_MASTER_CAMNOC_HF1 9 -#define SM8150_MASTER_CAMNOC_HF1_UNCOMP 10 -#define SM8150_MASTER_CAMNOC_SF 11 -#define SM8150_MASTER_CAMNOC_SF_UNCOMP 12 -#define SM8150_MASTER_CNOC_A2NOC 13 -#define SM8150_MASTER_CNOC_DC_NOC 14 -#define SM8150_MASTER_CNOC_MNOC_CFG 15 -#define SM8150_MASTER_COMPUTE_NOC 16 -#define SM8150_MASTER_CRYPTO_CORE_0 17 -#define SM8150_MASTER_ECC 18 -#define SM8150_MASTER_EMAC 19 -#define SM8150_MASTER_GEM_NOC_CFG 20 -#define SM8150_MASTER_GEM_NOC_PCIE_SNOC 21 -#define SM8150_MASTER_GEM_NOC_SNOC 22 -#define SM8150_MASTER_GIC 23 -#define SM8150_MASTER_GPU_TCU 24 -#define SM8150_MASTER_GRAPHICS_3D 25 -#define SM8150_MASTER_IPA 26 -/* 27 was used by SLAVE_IPA_CORE, now represented as RPMh clock */ -#define SM8150_MASTER_LLCC 28 -#define SM8150_MASTER_MDP_PORT0 29 -#define SM8150_MASTER_MDP_PORT1 30 -#define SM8150_MASTER_MNOC_HF_MEM_NOC 31 -#define SM8150_MASTER_MNOC_SF_MEM_NOC 32 -#define SM8150_MASTER_NPU 33 -#define SM8150_MASTER_PCIE 34 -#define SM8150_MASTER_PCIE_1 35 -#define SM8150_MASTER_PIMEM 36 -#define SM8150_MASTER_QDSS_BAM 37 -#define SM8150_MASTER_QDSS_DAP 38 -#define SM8150_MASTER_QDSS_ETR 39 -#define SM8150_MASTER_QSPI 40 -#define SM8150_MASTER_QUP_0 41 -#define SM8150_MASTER_QUP_1 42 -#define SM8150_MASTER_QUP_2 43 -#define SM8150_MASTER_ROTATOR 44 -#define SM8150_MASTER_SDCC_2 45 -#define SM8150_MASTER_SDCC_4 46 -#define SM8150_MASTER_SENSORS_AHB 47 -#define SM8150_MASTER_SNOC_CFG 48 -#define SM8150_MASTER_SNOC_GC_MEM_NOC 49 -#define SM8150_MASTER_SNOC_SF_MEM_NOC 50 -#define SM8150_MASTER_SPDM 51 -#define SM8150_MASTER_SYS_TCU 52 -#define SM8150_MASTER_TSIF 53 -#define SM8150_MASTER_UFS_MEM 54 -#define SM8150_MASTER_USB3 55 -#define SM8150_MASTER_USB3_1 56 -#define SM8150_MASTER_VIDEO_P0 57 -#define SM8150_MASTER_VIDEO_P1 58 -#define SM8150_MASTER_VIDEO_PROC 59 -#define SM8150_SLAVE_A1NOC_CFG 60 -#define SM8150_SLAVE_A2NOC_CFG 61 -#define SM8150_SLAVE_AHB2PHY_SOUTH 62 -#define SM8150_SLAVE_ANOC_PCIE_GEM_NOC 63 -#define SM8150_SLAVE_AOP 64 -#define SM8150_SLAVE_AOSS 65 -#define SM8150_SLAVE_APPSS 66 -#define SM8150_SLAVE_CAMERA_CFG 67 -#define SM8150_SLAVE_CAMNOC_UNCOMP 68 -#define SM8150_SLAVE_CDSP_CFG 69 -#define SM8150_SLAVE_CDSP_MEM_NOC 70 -#define SM8150_SLAVE_CLK_CTL 71 -#define SM8150_SLAVE_CNOC_A2NOC 72 -#define SM8150_SLAVE_CNOC_DDRSS 73 -#define SM8150_SLAVE_CNOC_MNOC_CFG 74 -#define SM8150_SLAVE_CRYPTO_0_CFG 75 -#define SM8150_SLAVE_DISPLAY_CFG 76 -#define SM8150_SLAVE_EBI_CH0 77 -#define SM8150_SLAVE_ECC 78 -#define SM8150_SLAVE_EMAC_CFG 79 -#define SM8150_SLAVE_GEM_NOC_CFG 80 -#define SM8150_SLAVE_GEM_NOC_SNOC 81 -#define SM8150_SLAVE_GLM 82 -#define SM8150_SLAVE_GRAPHICS_3D_CFG 83 -#define SM8150_SLAVE_IMEM_CFG 84 -#define SM8150_SLAVE_IPA_CFG 85 -/* 86 was used by SLAVE_IPA_CORE, now represented as RPMh clock */ -#define SM8150_SLAVE_LLCC 87 -#define SM8150_SLAVE_LLCC_CFG 88 -#define SM8150_SLAVE_MNOC_HF_MEM_NOC 89 -#define SM8150_SLAVE_MNOC_SF_MEM_NOC 90 -#define SM8150_SLAVE_MSS_PROC_MS_MPU_CFG 91 -#define SM8150_SLAVE_NORTH_PHY_CFG 92 -#define SM8150_SLAVE_NPU_CFG 93 -#define SM8150_SLAVE_OCIMEM 94 -#define SM8150_SLAVE_PCIE_0 95 -#define SM8150_SLAVE_PCIE_0_CFG 96 -#define SM8150_SLAVE_PCIE_1 97 -#define SM8150_SLAVE_PCIE_1_CFG 98 -#define SM8150_SLAVE_PIMEM 99 -#define SM8150_SLAVE_PIMEM_CFG 100 -#define SM8150_SLAVE_PRNG 101 -#define SM8150_SLAVE_QDSS_CFG 102 -#define SM8150_SLAVE_QDSS_STM 103 -#define SM8150_SLAVE_QSPI 104 -#define SM8150_SLAVE_QUP_0 105 -#define SM8150_SLAVE_QUP_1 106 -#define SM8150_SLAVE_QUP_2 107 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This gives more flexibility and also allows us to drop the .num_links member, saving from possible errors related to it being not set or set incorrectly. Signed-off-by: Dmitry Baryshkov --- drivers/interconnect/qcom/sm8350.c | 694 ++++++++++++++++++---------------= ---- drivers/interconnect/qcom/sm8350.h | 158 --------- 2 files changed, 345 insertions(+), 507 deletions(-) diff --git a/drivers/interconnect/qcom/sm8350.c b/drivers/interconnect/qcom= /sm8350.c index 38105ead4f29548ab32c60aeba224fbf3909667c..75a9b0ddb8d5c5a3d990bbe0e50= 67a06d5903a86 100644 --- a/drivers/interconnect/qcom/sm8350.c +++ b/drivers/interconnect/qcom/sm8350.c @@ -13,1255 +13,1241 @@ =20 #include "bcm-voter.h" #include "icc-rpmh.h" -#include "sm8350.h" + +static struct qcom_icc_node qhm_qspi; +static struct qcom_icc_node qhm_qup0; +static struct qcom_icc_node qhm_qup1; +static struct qcom_icc_node qhm_qup2; +static struct qcom_icc_node qnm_a1noc_cfg; +static struct qcom_icc_node xm_sdc4; +static struct qcom_icc_node xm_ufs_mem; +static struct qcom_icc_node xm_usb3_0; +static struct qcom_icc_node xm_usb3_1; +static struct qcom_icc_node qhm_qdss_bam; +static struct qcom_icc_node qnm_a2noc_cfg; +static struct qcom_icc_node qxm_crypto; +static struct qcom_icc_node qxm_ipa; +static struct qcom_icc_node xm_pcie3_0; +static struct qcom_icc_node xm_pcie3_1; +static struct qcom_icc_node xm_qdss_etr; +static struct qcom_icc_node xm_sdc2; +static struct qcom_icc_node xm_ufs_card; +static struct qcom_icc_node qnm_gemnoc_cnoc; +static struct qcom_icc_node qnm_gemnoc_pcie; +static struct qcom_icc_node xm_qdss_dap; +static struct qcom_icc_node qnm_cnoc_dc_noc; +static struct qcom_icc_node alm_gpu_tcu; +static struct qcom_icc_node alm_sys_tcu; +static struct qcom_icc_node chm_apps; +static struct qcom_icc_node qnm_cmpnoc; +static struct qcom_icc_node qnm_gemnoc_cfg; +static struct qcom_icc_node qnm_gpu; +static struct qcom_icc_node qnm_mnoc_hf; +static struct qcom_icc_node qnm_mnoc_sf; +static struct qcom_icc_node qnm_pcie; +static struct qcom_icc_node qnm_snoc_gc; +static struct qcom_icc_node qnm_snoc_sf; +static struct qcom_icc_node qhm_config_noc; +static struct qcom_icc_node llcc_mc; +static struct qcom_icc_node qnm_camnoc_hf; +static struct qcom_icc_node qnm_camnoc_icp; +static struct qcom_icc_node qnm_camnoc_sf; +static struct qcom_icc_node qnm_mnoc_cfg; +static struct qcom_icc_node qnm_video0; +static struct qcom_icc_node qnm_video1; +static struct qcom_icc_node qnm_video_cvp; +static struct qcom_icc_node qxm_mdp0; +static struct qcom_icc_node qxm_mdp1; +static struct qcom_icc_node qxm_rot; +static struct qcom_icc_node qhm_nsp_noc_config; +static struct qcom_icc_node qxm_nsp; +static struct qcom_icc_node qnm_aggre1_noc; +static struct qcom_icc_node qnm_aggre2_noc; +static struct qcom_icc_node qnm_snoc_cfg; +static struct qcom_icc_node qxm_pimem; +static struct qcom_icc_node xm_gic; +static struct qcom_icc_node qns_a1noc_snoc; +static struct qcom_icc_node srvc_aggre1_noc; +static struct qcom_icc_node qns_a2noc_snoc; +static struct qcom_icc_node qns_pcie_mem_noc; +static struct qcom_icc_node srvc_aggre2_noc; +static struct qcom_icc_node qhs_ahb2phy0; +static struct qcom_icc_node qhs_ahb2phy1; +static struct qcom_icc_node qhs_aoss; +static struct qcom_icc_node qhs_apss; +static struct qcom_icc_node qhs_camera_cfg; +static struct qcom_icc_node qhs_clk_ctl; +static struct qcom_icc_node qhs_compute_cfg; +static struct qcom_icc_node qhs_cpr_cx; +static struct qcom_icc_node qhs_cpr_mmcx; +static struct qcom_icc_node qhs_cpr_mx; +static struct qcom_icc_node qhs_crypto0_cfg; +static struct qcom_icc_node qhs_cx_rdpm; +static struct qcom_icc_node qhs_dcc_cfg; +static struct qcom_icc_node qhs_display_cfg; +static struct qcom_icc_node qhs_gpuss_cfg; +static struct qcom_icc_node qhs_hwkm; +static struct qcom_icc_node qhs_imem_cfg; +static struct qcom_icc_node qhs_ipa; +static struct qcom_icc_node qhs_ipc_router; +static struct qcom_icc_node qhs_lpass_cfg; +static struct qcom_icc_node qhs_mss_cfg; +static struct qcom_icc_node qhs_mx_rdpm; +static struct qcom_icc_node qhs_pcie0_cfg; +static struct qcom_icc_node qhs_pcie1_cfg; +static struct qcom_icc_node qhs_pdm; +static struct qcom_icc_node qhs_pimem_cfg; +static struct qcom_icc_node qhs_pka_wrapper_cfg; +static struct qcom_icc_node qhs_pmu_wrapper_cfg; +static struct qcom_icc_node qhs_qdss_cfg; +static struct qcom_icc_node qhs_qspi; +static struct qcom_icc_node qhs_qup0; +static struct qcom_icc_node qhs_qup1; +static struct qcom_icc_node qhs_qup2; +static struct qcom_icc_node qhs_sdc2; +static struct qcom_icc_node qhs_sdc4; +static struct qcom_icc_node qhs_security; +static struct qcom_icc_node qhs_spss_cfg; +static struct qcom_icc_node qhs_tcsr; +static struct qcom_icc_node qhs_tlmm; +static struct qcom_icc_node qhs_ufs_card_cfg; +static struct qcom_icc_node qhs_ufs_mem_cfg; +static struct qcom_icc_node qhs_usb3_0; +static struct qcom_icc_node qhs_usb3_1; +static struct qcom_icc_node qhs_venus_cfg; +static struct qcom_icc_node qhs_vsense_ctrl_cfg; +static struct qcom_icc_node qns_a1_noc_cfg; +static struct qcom_icc_node qns_a2_noc_cfg; +static struct qcom_icc_node qns_ddrss_cfg; +static struct qcom_icc_node qns_mnoc_cfg; +static struct qcom_icc_node qns_snoc_cfg; +static struct qcom_icc_node qxs_boot_imem; +static struct qcom_icc_node qxs_imem; +static struct qcom_icc_node qxs_pimem; +static struct qcom_icc_node srvc_cnoc; +static struct qcom_icc_node xs_pcie_0; +static struct qcom_icc_node xs_pcie_1; +static struct qcom_icc_node xs_qdss_stm; +static struct qcom_icc_node xs_sys_tcu_cfg; +static struct qcom_icc_node qhs_llcc; +static struct qcom_icc_node qns_gemnoc; +static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg; +static struct qcom_icc_node qhs_modem_ms_mpu_cfg; +static struct qcom_icc_node qns_gem_noc_cnoc; +static struct qcom_icc_node qns_llcc; +static struct qcom_icc_node qns_pcie; +static struct qcom_icc_node srvc_even_gemnoc; +static struct qcom_icc_node srvc_odd_gemnoc; +static struct qcom_icc_node srvc_sys_gemnoc; +static struct qcom_icc_node qhs_lpass_core; +static struct qcom_icc_node qhs_lpass_lpi; +static struct qcom_icc_node qhs_lpass_mpu; +static struct qcom_icc_node qhs_lpass_top; +static struct qcom_icc_node srvc_niu_aml_noc; +static struct qcom_icc_node srvc_niu_lpass_agnoc; +static struct qcom_icc_node ebi; +static struct qcom_icc_node qns_mem_noc_hf; +static struct qcom_icc_node qns_mem_noc_sf; +static struct qcom_icc_node srvc_mnoc; +static struct qcom_icc_node qns_nsp_gemnoc; +static struct qcom_icc_node service_nsp_noc; +static struct qcom_icc_node qns_gemnoc_gc; +static struct qcom_icc_node qns_gemnoc_sf; +static struct qcom_icc_node srvc_snoc; =20 static struct qcom_icc_node qhm_qspi =3D { .name =3D "qhm_qspi", - .id =3D SM8350_MASTER_QSPI_0, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8350_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node qhm_qup0 =3D { .name =3D "qhm_qup0", - .id =3D SM8350_MASTER_QUP_0, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8350_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qhm_qup1 =3D { .name =3D "qhm_qup1", - .id =3D SM8350_MASTER_QUP_1, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8350_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node qhm_qup2 =3D { .name =3D "qhm_qup2", - .id =3D SM8350_MASTER_QUP_2, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8350_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qnm_a1noc_cfg =3D { .name =3D "qnm_a1noc_cfg", - .id =3D SM8350_MASTER_A1NOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8350_SLAVE_SERVICE_A1NOC }, + .link_nodes =3D { &srvc_aggre1_noc }, }; =20 static struct qcom_icc_node xm_sdc4 =3D { .name =3D "xm_sdc4", - .id =3D SM8350_MASTER_SDCC_4, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8350_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node xm_ufs_mem =3D { .name =3D "xm_ufs_mem", - .id =3D SM8350_MASTER_UFS_MEM, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8350_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node xm_usb3_0 =3D { .name =3D "xm_usb3_0", - .id =3D SM8350_MASTER_USB3_0, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8350_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node xm_usb3_1 =3D { .name =3D "xm_usb3_1", - .id =3D SM8350_MASTER_USB3_1, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8350_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node qhm_qdss_bam =3D { .name =3D "qhm_qdss_bam", - .id =3D SM8350_MASTER_QDSS_BAM, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8350_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qnm_a2noc_cfg =3D { .name =3D "qnm_a2noc_cfg", - .id =3D SM8350_MASTER_A2NOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8350_SLAVE_SERVICE_A2NOC }, + .link_nodes =3D { &srvc_aggre2_noc }, }; =20 static struct qcom_icc_node qxm_crypto =3D { .name =3D "qxm_crypto", - .id =3D SM8350_MASTER_CRYPTO, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8350_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qxm_ipa =3D { .name =3D "qxm_ipa", - .id =3D SM8350_MASTER_IPA, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8350_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node xm_pcie3_0 =3D { .name =3D "xm_pcie3_0", - .id =3D SM8350_MASTER_PCIE_0, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8350_SLAVE_ANOC_PCIE_GEM_NOC }, + .link_nodes =3D { &qns_pcie_mem_noc }, }; =20 static struct qcom_icc_node xm_pcie3_1 =3D { .name =3D "xm_pcie3_1", - .id =3D SM8350_MASTER_PCIE_1, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8350_SLAVE_ANOC_PCIE_GEM_NOC }, + .link_nodes =3D { &qns_pcie_mem_noc }, }; =20 static struct qcom_icc_node xm_qdss_etr =3D { .name =3D "xm_qdss_etr", - .id =3D SM8350_MASTER_QDSS_ETR, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8350_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node xm_sdc2 =3D { .name =3D "xm_sdc2", - .id =3D SM8350_MASTER_SDCC_2, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8350_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node xm_ufs_card =3D { .name =3D "xm_ufs_card", - .id =3D SM8350_MASTER_UFS_CARD, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8350_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qnm_gemnoc_cnoc =3D { .name =3D "qnm_gemnoc_cnoc", - .id =3D SM8350_MASTER_GEM_NOC_CNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 56, - .links =3D { SM8350_SLAVE_AHB2PHY_SOUTH, - SM8350_SLAVE_AHB2PHY_NORTH, - SM8350_SLAVE_AOSS, - SM8350_SLAVE_APPSS, - SM8350_SLAVE_CAMERA_CFG, - SM8350_SLAVE_CLK_CTL, - SM8350_SLAVE_CDSP_CFG, - SM8350_SLAVE_RBCPR_CX_CFG, - SM8350_SLAVE_RBCPR_MMCX_CFG, - SM8350_SLAVE_RBCPR_MX_CFG, - SM8350_SLAVE_CRYPTO_0_CFG, - SM8350_SLAVE_CX_RDPM, - SM8350_SLAVE_DCC_CFG, - SM8350_SLAVE_DISPLAY_CFG, - SM8350_SLAVE_GFX3D_CFG, - SM8350_SLAVE_HWKM, - SM8350_SLAVE_IMEM_CFG, - SM8350_SLAVE_IPA_CFG, - SM8350_SLAVE_IPC_ROUTER_CFG, - SM8350_SLAVE_LPASS, - SM8350_SLAVE_CNOC_MSS, - SM8350_SLAVE_MX_RDPM, - SM8350_SLAVE_PCIE_0_CFG, - SM8350_SLAVE_PCIE_1_CFG, - SM8350_SLAVE_PDM, - SM8350_SLAVE_PIMEM_CFG, - SM8350_SLAVE_PKA_WRAPPER_CFG, - SM8350_SLAVE_PMU_WRAPPER_CFG, - SM8350_SLAVE_QDSS_CFG, - SM8350_SLAVE_QSPI_0, - SM8350_SLAVE_QUP_0, - SM8350_SLAVE_QUP_1, - SM8350_SLAVE_QUP_2, - SM8350_SLAVE_SDCC_2, - SM8350_SLAVE_SDCC_4, - SM8350_SLAVE_SECURITY, - SM8350_SLAVE_SPSS_CFG, - SM8350_SLAVE_TCSR, - SM8350_SLAVE_TLMM, - SM8350_SLAVE_UFS_CARD_CFG, - SM8350_SLAVE_UFS_MEM_CFG, - SM8350_SLAVE_USB3_0, - SM8350_SLAVE_USB3_1, - SM8350_SLAVE_VENUS_CFG, - SM8350_SLAVE_VSENSE_CTRL_CFG, - SM8350_SLAVE_A1NOC_CFG, - SM8350_SLAVE_A2NOC_CFG, - SM8350_SLAVE_DDRSS_CFG, - SM8350_SLAVE_CNOC_MNOC_CFG, - SM8350_SLAVE_SNOC_CFG, - SM8350_SLAVE_BOOT_IMEM, - SM8350_SLAVE_IMEM, - SM8350_SLAVE_PIMEM, - SM8350_SLAVE_SERVICE_CNOC, - SM8350_SLAVE_QDSS_STM, - SM8350_SLAVE_TCU - }, + .link_nodes =3D { &qhs_ahb2phy0, + &qhs_ahb2phy1, + &qhs_aoss, + &qhs_apss, + &qhs_camera_cfg, + &qhs_clk_ctl, + &qhs_compute_cfg, + &qhs_cpr_cx, + &qhs_cpr_mmcx, + &qhs_cpr_mx, + &qhs_crypto0_cfg, + &qhs_cx_rdpm, + &qhs_dcc_cfg, + &qhs_display_cfg, + &qhs_gpuss_cfg, + &qhs_hwkm, + &qhs_imem_cfg, + &qhs_ipa, + &qhs_ipc_router, + &qhs_lpass_cfg, + &qhs_mss_cfg, + &qhs_mx_rdpm, + &qhs_pcie0_cfg, + &qhs_pcie1_cfg, + &qhs_pdm, + &qhs_pimem_cfg, + &qhs_pka_wrapper_cfg, + &qhs_pmu_wrapper_cfg, + &qhs_qdss_cfg, + &qhs_qspi, + &qhs_qup0, + &qhs_qup1, + &qhs_qup2, + &qhs_sdc2, + &qhs_sdc4, + &qhs_security, + &qhs_spss_cfg, + &qhs_tcsr, + &qhs_tlmm, + &qhs_ufs_card_cfg, + &qhs_ufs_mem_cfg, + &qhs_usb3_0, + &qhs_usb3_1, + &qhs_venus_cfg, + &qhs_vsense_ctrl_cfg, + &qns_a1_noc_cfg, + &qns_a2_noc_cfg, + &qns_ddrss_cfg, + &qns_mnoc_cfg, + &qns_snoc_cfg, + &qxs_boot_imem, + &qxs_imem, + &qxs_pimem, + &srvc_cnoc, + &xs_qdss_stm, + &xs_sys_tcu_cfg }, }; =20 static struct qcom_icc_node qnm_gemnoc_pcie =3D { .name =3D "qnm_gemnoc_pcie", - .id =3D SM8350_MASTER_GEM_NOC_PCIE_SNOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 2, - .links =3D { SM8350_SLAVE_PCIE_0, - SM8350_SLAVE_PCIE_1 - }, + .link_nodes =3D { &xs_pcie_0, + &xs_pcie_1 }, }; =20 static struct qcom_icc_node xm_qdss_dap =3D { .name =3D "xm_qdss_dap", - .id =3D SM8350_MASTER_QDSS_DAP, .channels =3D 1, .buswidth =3D 8, .num_links =3D 56, - .links =3D { SM8350_SLAVE_AHB2PHY_SOUTH, - SM8350_SLAVE_AHB2PHY_NORTH, - SM8350_SLAVE_AOSS, - SM8350_SLAVE_APPSS, - SM8350_SLAVE_CAMERA_CFG, - SM8350_SLAVE_CLK_CTL, - SM8350_SLAVE_CDSP_CFG, - SM8350_SLAVE_RBCPR_CX_CFG, - SM8350_SLAVE_RBCPR_MMCX_CFG, - SM8350_SLAVE_RBCPR_MX_CFG, - SM8350_SLAVE_CRYPTO_0_CFG, - SM8350_SLAVE_CX_RDPM, - SM8350_SLAVE_DCC_CFG, - SM8350_SLAVE_DISPLAY_CFG, - SM8350_SLAVE_GFX3D_CFG, - SM8350_SLAVE_HWKM, - SM8350_SLAVE_IMEM_CFG, - SM8350_SLAVE_IPA_CFG, - SM8350_SLAVE_IPC_ROUTER_CFG, - SM8350_SLAVE_LPASS, - SM8350_SLAVE_CNOC_MSS, - SM8350_SLAVE_MX_RDPM, - SM8350_SLAVE_PCIE_0_CFG, - SM8350_SLAVE_PCIE_1_CFG, - SM8350_SLAVE_PDM, - SM8350_SLAVE_PIMEM_CFG, - SM8350_SLAVE_PKA_WRAPPER_CFG, - SM8350_SLAVE_PMU_WRAPPER_CFG, - SM8350_SLAVE_QDSS_CFG, - SM8350_SLAVE_QSPI_0, - SM8350_SLAVE_QUP_0, - SM8350_SLAVE_QUP_1, - SM8350_SLAVE_QUP_2, - SM8350_SLAVE_SDCC_2, - SM8350_SLAVE_SDCC_4, - SM8350_SLAVE_SECURITY, - SM8350_SLAVE_SPSS_CFG, - SM8350_SLAVE_TCSR, - SM8350_SLAVE_TLMM, - SM8350_SLAVE_UFS_CARD_CFG, - SM8350_SLAVE_UFS_MEM_CFG, - SM8350_SLAVE_USB3_0, - SM8350_SLAVE_USB3_1, - SM8350_SLAVE_VENUS_CFG, - SM8350_SLAVE_VSENSE_CTRL_CFG, - SM8350_SLAVE_A1NOC_CFG, - SM8350_SLAVE_A2NOC_CFG, - SM8350_SLAVE_DDRSS_CFG, - SM8350_SLAVE_CNOC_MNOC_CFG, - SM8350_SLAVE_SNOC_CFG, - SM8350_SLAVE_BOOT_IMEM, - SM8350_SLAVE_IMEM, - SM8350_SLAVE_PIMEM, - SM8350_SLAVE_SERVICE_CNOC, - SM8350_SLAVE_QDSS_STM, - SM8350_SLAVE_TCU - }, + .link_nodes =3D { &qhs_ahb2phy0, + &qhs_ahb2phy1, + &qhs_aoss, + &qhs_apss, + &qhs_camera_cfg, + &qhs_clk_ctl, + &qhs_compute_cfg, + &qhs_cpr_cx, + &qhs_cpr_mmcx, + &qhs_cpr_mx, + &qhs_crypto0_cfg, + &qhs_cx_rdpm, + &qhs_dcc_cfg, + &qhs_display_cfg, + &qhs_gpuss_cfg, + &qhs_hwkm, + &qhs_imem_cfg, + &qhs_ipa, + &qhs_ipc_router, + &qhs_lpass_cfg, + &qhs_mss_cfg, + &qhs_mx_rdpm, + &qhs_pcie0_cfg, + &qhs_pcie1_cfg, + &qhs_pdm, + &qhs_pimem_cfg, + &qhs_pka_wrapper_cfg, + &qhs_pmu_wrapper_cfg, + &qhs_qdss_cfg, + &qhs_qspi, + &qhs_qup0, + &qhs_qup1, + &qhs_qup2, + &qhs_sdc2, + &qhs_sdc4, + &qhs_security, + &qhs_spss_cfg, + &qhs_tcsr, + &qhs_tlmm, + &qhs_ufs_card_cfg, + &qhs_ufs_mem_cfg, + &qhs_usb3_0, + &qhs_usb3_1, + &qhs_venus_cfg, + &qhs_vsense_ctrl_cfg, + &qns_a1_noc_cfg, + &qns_a2_noc_cfg, + &qns_ddrss_cfg, + &qns_mnoc_cfg, + &qns_snoc_cfg, + &qxs_boot_imem, + &qxs_imem, + &qxs_pimem, + &srvc_cnoc, + &xs_qdss_stm, + &xs_sys_tcu_cfg }, }; =20 static struct qcom_icc_node qnm_cnoc_dc_noc =3D { .name =3D "qnm_cnoc_dc_noc", - .id =3D SM8350_MASTER_CNOC_DC_NOC, .channels =3D 1, .buswidth =3D 4, .num_links =3D 2, - .links =3D { SM8350_SLAVE_LLCC_CFG, - SM8350_SLAVE_GEM_NOC_CFG - }, + .link_nodes =3D { &qhs_llcc, + &qns_gemnoc }, }; =20 static struct qcom_icc_node alm_gpu_tcu =3D { .name =3D "alm_gpu_tcu", - .id =3D SM8350_MASTER_GPU_TCU, .channels =3D 1, .buswidth =3D 8, .num_links =3D 2, - .links =3D { SM8350_SLAVE_GEM_NOC_CNOC, - SM8350_SLAVE_LLCC - }, + .link_nodes =3D { &qns_gem_noc_cnoc, + &qns_llcc }, }; =20 static struct qcom_icc_node alm_sys_tcu =3D { .name =3D "alm_sys_tcu", - .id =3D SM8350_MASTER_SYS_TCU, .channels =3D 1, .buswidth =3D 8, .num_links =3D 2, - .links =3D { SM8350_SLAVE_GEM_NOC_CNOC, - SM8350_SLAVE_LLCC - }, + .link_nodes =3D { &qns_gem_noc_cnoc, + &qns_llcc }, }; =20 static struct qcom_icc_node chm_apps =3D { .name =3D "chm_apps", - .id =3D SM8350_MASTER_APPSS_PROC, .channels =3D 2, .buswidth =3D 32, .num_links =3D 3, - .links =3D { SM8350_SLAVE_GEM_NOC_CNOC, - SM8350_SLAVE_LLCC, - SM8350_SLAVE_MEM_NOC_PCIE_SNOC - }, + .link_nodes =3D { &qns_gem_noc_cnoc, + &qns_llcc, + &qns_pcie }, }; =20 static struct qcom_icc_node qnm_cmpnoc =3D { .name =3D "qnm_cmpnoc", - .id =3D SM8350_MASTER_COMPUTE_NOC, .channels =3D 2, .buswidth =3D 32, .num_links =3D 2, - .links =3D { SM8350_SLAVE_GEM_NOC_CNOC, - SM8350_SLAVE_LLCC - }, + .link_nodes =3D { &qns_gem_noc_cnoc, + &qns_llcc }, }; =20 static struct qcom_icc_node qnm_gemnoc_cfg =3D { .name =3D "qnm_gemnoc_cfg", - .id =3D SM8350_MASTER_GEM_NOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 5, - .links =3D { SM8350_SLAVE_MSS_PROC_MS_MPU_CFG, - SM8350_SLAVE_MCDMA_MS_MPU_CFG, - SM8350_SLAVE_SERVICE_GEM_NOC_1, - SM8350_SLAVE_SERVICE_GEM_NOC_2, - SM8350_SLAVE_SERVICE_GEM_NOC - }, + .link_nodes =3D { &qhs_mdsp_ms_mpu_cfg, + &qhs_modem_ms_mpu_cfg, + &srvc_even_gemnoc, + &srvc_odd_gemnoc, + &srvc_sys_gemnoc }, }; =20 static struct qcom_icc_node qnm_gpu =3D { .name =3D "qnm_gpu", - .id =3D SM8350_MASTER_GFX3D, .channels =3D 2, .buswidth =3D 32, .num_links =3D 2, - .links =3D { SM8350_SLAVE_GEM_NOC_CNOC, - SM8350_SLAVE_LLCC - }, + .link_nodes =3D { &qns_gem_noc_cnoc, + &qns_llcc }, }; =20 static struct qcom_icc_node qnm_mnoc_hf =3D { .name =3D "qnm_mnoc_hf", - .id =3D SM8350_MASTER_MNOC_HF_MEM_NOC, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8350_SLAVE_LLCC }, + .link_nodes =3D { &qns_llcc }, }; =20 static struct qcom_icc_node qnm_mnoc_sf =3D { .name =3D "qnm_mnoc_sf", - .id =3D SM8350_MASTER_MNOC_SF_MEM_NOC, .channels =3D 2, .buswidth =3D 32, .num_links =3D 2, - .links =3D { SM8350_SLAVE_GEM_NOC_CNOC, - SM8350_SLAVE_LLCC - }, + .link_nodes =3D { &qns_gem_noc_cnoc, + &qns_llcc }, }; =20 static struct qcom_icc_node qnm_pcie =3D { .name =3D "qnm_pcie", - .id =3D SM8350_MASTER_ANOC_PCIE_GEM_NOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 2, - .links =3D { SM8350_SLAVE_GEM_NOC_CNOC, - SM8350_SLAVE_LLCC - }, + .link_nodes =3D { &qns_gem_noc_cnoc, + &qns_llcc }, }; =20 static struct qcom_icc_node qnm_snoc_gc =3D { .name =3D "qnm_snoc_gc", - .id =3D SM8350_MASTER_SNOC_GC_MEM_NOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8350_SLAVE_LLCC }, + .link_nodes =3D { &qns_llcc }, }; =20 static struct qcom_icc_node qnm_snoc_sf =3D { .name =3D "qnm_snoc_sf", - .id =3D SM8350_MASTER_SNOC_SF_MEM_NOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 3, - .links =3D { SM8350_SLAVE_GEM_NOC_CNOC, - SM8350_SLAVE_LLCC, - SM8350_SLAVE_MEM_NOC_PCIE_SNOC - }, + .link_nodes =3D { &qns_gem_noc_cnoc, + &qns_llcc, + &qns_pcie }, }; =20 static struct qcom_icc_node qhm_config_noc =3D { .name =3D "qhm_config_noc", - .id =3D SM8350_MASTER_CNOC_LPASS_AG_NOC, .channels =3D 1, .buswidth =3D 4, .num_links =3D 6, - .links =3D { SM8350_SLAVE_LPASS_CORE_CFG, - SM8350_SLAVE_LPASS_LPI_CFG, - SM8350_SLAVE_LPASS_MPU_CFG, - SM8350_SLAVE_LPASS_TOP_CFG, - SM8350_SLAVE_SERVICES_LPASS_AML_NOC, - SM8350_SLAVE_SERVICE_LPASS_AG_NOC - }, + .link_nodes =3D { &qhs_lpass_core, + &qhs_lpass_lpi, + &qhs_lpass_mpu, + &qhs_lpass_top, + &srvc_niu_aml_noc, + &srvc_niu_lpass_agnoc }, }; =20 static struct qcom_icc_node llcc_mc =3D { .name =3D "llcc_mc", - .id =3D SM8350_MASTER_LLCC, .channels =3D 4, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8350_SLAVE_EBI1 }, + .link_nodes =3D { &ebi }, }; =20 static struct qcom_icc_node qnm_camnoc_hf =3D { .name =3D "qnm_camnoc_hf", - .id =3D SM8350_MASTER_CAMNOC_HF, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8350_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_hf }, }; =20 static struct qcom_icc_node qnm_camnoc_icp =3D { .name =3D "qnm_camnoc_icp", - .id =3D SM8350_MASTER_CAMNOC_ICP, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8350_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static struct qcom_icc_node qnm_camnoc_sf =3D { .name =3D "qnm_camnoc_sf", - .id =3D SM8350_MASTER_CAMNOC_SF, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8350_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static struct qcom_icc_node qnm_mnoc_cfg =3D { .name =3D "qnm_mnoc_cfg", - .id =3D SM8350_MASTER_CNOC_MNOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8350_SLAVE_SERVICE_MNOC }, + .link_nodes =3D { &srvc_mnoc }, }; =20 static struct qcom_icc_node qnm_video0 =3D { .name =3D "qnm_video0", - .id =3D SM8350_MASTER_VIDEO_P0, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8350_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static struct qcom_icc_node qnm_video1 =3D { .name =3D "qnm_video1", - .id =3D SM8350_MASTER_VIDEO_P1, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8350_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static struct qcom_icc_node qnm_video_cvp =3D { .name =3D "qnm_video_cvp", - .id =3D SM8350_MASTER_VIDEO_PROC, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8350_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static struct qcom_icc_node qxm_mdp0 =3D { .name =3D "qxm_mdp0", - .id =3D SM8350_MASTER_MDP0, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8350_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_hf }, }; =20 static struct qcom_icc_node qxm_mdp1 =3D { .name =3D "qxm_mdp1", - .id =3D SM8350_MASTER_MDP1, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8350_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_hf }, }; =20 static struct qcom_icc_node qxm_rot =3D { .name =3D "qxm_rot", - .id =3D SM8350_MASTER_ROTATOR, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8350_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static struct qcom_icc_node qhm_nsp_noc_config =3D { .name =3D "qhm_nsp_noc_config", - .id =3D SM8350_MASTER_CDSP_NOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8350_SLAVE_SERVICE_NSP_NOC }, + .link_nodes =3D { &service_nsp_noc }, }; =20 static struct qcom_icc_node qxm_nsp =3D { .name =3D "qxm_nsp", - .id =3D SM8350_MASTER_CDSP_PROC, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8350_SLAVE_CDSP_MEM_NOC }, + .link_nodes =3D { &qns_nsp_gemnoc }, }; =20 static struct qcom_icc_node qnm_aggre1_noc =3D { .name =3D "qnm_aggre1_noc", - .id =3D SM8350_MASTER_A1NOC_SNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM8350_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes =3D { &qns_gemnoc_sf }, }; =20 static struct qcom_icc_node qnm_aggre2_noc =3D { .name =3D "qnm_aggre2_noc", - .id =3D SM8350_MASTER_A2NOC_SNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM8350_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes =3D { &qns_gemnoc_sf }, }; =20 static struct qcom_icc_node qnm_snoc_cfg =3D { .name =3D "qnm_snoc_cfg", - .id =3D SM8350_MASTER_SNOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8350_SLAVE_SERVICE_SNOC }, + .link_nodes =3D { &srvc_snoc }, }; =20 static struct qcom_icc_node qxm_pimem =3D { .name =3D "qxm_pimem", - .id =3D SM8350_MASTER_PIMEM, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8350_SLAVE_SNOC_GEM_NOC_GC }, + .link_nodes =3D { &qns_gemnoc_gc }, }; =20 static struct qcom_icc_node xm_gic =3D { .name =3D "xm_gic", - .id =3D SM8350_MASTER_GIC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8350_SLAVE_SNOC_GEM_NOC_GC }, + .link_nodes =3D { &qns_gemnoc_gc }, }; =20 static struct qcom_icc_node qns_a1noc_snoc =3D { .name =3D "qns_a1noc_snoc", - .id =3D SM8350_SLAVE_A1NOC_SNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM8350_MASTER_A1NOC_SNOC }, + .link_nodes =3D { &qnm_aggre1_noc }, }; =20 static struct qcom_icc_node srvc_aggre1_noc =3D { .name =3D "srvc_aggre1_noc", - .id =3D SM8350_SLAVE_SERVICE_A1NOC, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qns_a2noc_snoc =3D { .name =3D "qns_a2noc_snoc", - .id =3D SM8350_SLAVE_A2NOC_SNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM8350_MASTER_A2NOC_SNOC }, + .link_nodes =3D { &qnm_aggre2_noc }, }; =20 static struct qcom_icc_node qns_pcie_mem_noc =3D { .name =3D "qns_pcie_mem_noc", - .id =3D SM8350_SLAVE_ANOC_PCIE_GEM_NOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM8350_MASTER_ANOC_PCIE_GEM_NOC }, + .link_nodes =3D { &qnm_pcie }, }; =20 static struct qcom_icc_node srvc_aggre2_noc =3D { .name =3D "srvc_aggre2_noc", - .id =3D SM8350_SLAVE_SERVICE_A2NOC, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_ahb2phy0 =3D { .name =3D "qhs_ahb2phy0", - .id =3D SM8350_SLAVE_AHB2PHY_SOUTH, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_ahb2phy1 =3D { .name =3D "qhs_ahb2phy1", - .id =3D SM8350_SLAVE_AHB2PHY_NORTH, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_aoss =3D { .name =3D "qhs_aoss", - .id =3D SM8350_SLAVE_AOSS, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_apss =3D { .name =3D "qhs_apss", - .id =3D SM8350_SLAVE_APPSS, .channels =3D 1, .buswidth =3D 8, }; =20 static struct qcom_icc_node qhs_camera_cfg =3D { .name =3D "qhs_camera_cfg", - .id =3D SM8350_SLAVE_CAMERA_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_clk_ctl =3D { .name =3D "qhs_clk_ctl", - .id =3D SM8350_SLAVE_CLK_CTL, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_compute_cfg =3D { .name =3D "qhs_compute_cfg", - .id =3D SM8350_SLAVE_CDSP_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_cpr_cx =3D { .name =3D "qhs_cpr_cx", - .id =3D SM8350_SLAVE_RBCPR_CX_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_cpr_mmcx =3D { .name =3D "qhs_cpr_mmcx", - .id =3D SM8350_SLAVE_RBCPR_MMCX_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_cpr_mx =3D { .name =3D "qhs_cpr_mx", - .id =3D SM8350_SLAVE_RBCPR_MX_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_crypto0_cfg =3D { .name =3D "qhs_crypto0_cfg", - .id =3D SM8350_SLAVE_CRYPTO_0_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_cx_rdpm =3D { .name =3D "qhs_cx_rdpm", - .id =3D SM8350_SLAVE_CX_RDPM, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_dcc_cfg =3D { .name =3D "qhs_dcc_cfg", - .id =3D SM8350_SLAVE_DCC_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_display_cfg =3D { .name =3D "qhs_display_cfg", - .id =3D SM8350_SLAVE_DISPLAY_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_gpuss_cfg =3D { .name =3D "qhs_gpuss_cfg", - .id =3D SM8350_SLAVE_GFX3D_CFG, .channels =3D 1, .buswidth =3D 8, }; =20 static struct qcom_icc_node qhs_hwkm =3D { .name =3D "qhs_hwkm", - .id =3D SM8350_SLAVE_HWKM, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_imem_cfg =3D { .name =3D "qhs_imem_cfg", - .id =3D SM8350_SLAVE_IMEM_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_ipa =3D { .name =3D "qhs_ipa", - .id =3D SM8350_SLAVE_IPA_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_ipc_router =3D { .name =3D "qhs_ipc_router", - .id =3D SM8350_SLAVE_IPC_ROUTER_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_lpass_cfg =3D { .name =3D "qhs_lpass_cfg", - .id =3D SM8350_SLAVE_LPASS, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8350_MASTER_CNOC_LPASS_AG_NOC }, + .link_nodes =3D { &qhm_config_noc }, }; =20 static struct qcom_icc_node qhs_mss_cfg =3D { .name =3D "qhs_mss_cfg", - .id =3D SM8350_SLAVE_CNOC_MSS, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_mx_rdpm =3D { .name =3D "qhs_mx_rdpm", - .id =3D SM8350_SLAVE_MX_RDPM, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_pcie0_cfg =3D { .name =3D "qhs_pcie0_cfg", - .id =3D SM8350_SLAVE_PCIE_0_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_pcie1_cfg =3D { .name =3D "qhs_pcie1_cfg", - .id =3D SM8350_SLAVE_PCIE_1_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_pdm =3D { .name =3D "qhs_pdm", - .id =3D SM8350_SLAVE_PDM, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_pimem_cfg =3D { .name =3D "qhs_pimem_cfg", - .id =3D SM8350_SLAVE_PIMEM_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_pka_wrapper_cfg =3D { .name =3D "qhs_pka_wrapper_cfg", - .id =3D SM8350_SLAVE_PKA_WRAPPER_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_pmu_wrapper_cfg =3D { .name =3D "qhs_pmu_wrapper_cfg", - .id =3D SM8350_SLAVE_PMU_WRAPPER_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_qdss_cfg =3D { .name =3D "qhs_qdss_cfg", - .id =3D SM8350_SLAVE_QDSS_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_qspi =3D { .name =3D "qhs_qspi", - .id =3D SM8350_SLAVE_QSPI_0, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_qup0 =3D { .name =3D "qhs_qup0", - .id =3D SM8350_SLAVE_QUP_0, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_qup1 =3D { .name =3D "qhs_qup1", - .id =3D SM8350_SLAVE_QUP_1, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_qup2 =3D { .name =3D "qhs_qup2", - .id =3D SM8350_SLAVE_QUP_2, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_sdc2 =3D { .name =3D "qhs_sdc2", - .id =3D SM8350_SLAVE_SDCC_2, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_sdc4 =3D { .name =3D "qhs_sdc4", - .id =3D SM8350_SLAVE_SDCC_4, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_security =3D { .name =3D "qhs_security", - .id =3D SM8350_SLAVE_SECURITY, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_spss_cfg =3D { .name =3D "qhs_spss_cfg", - .id =3D SM8350_SLAVE_SPSS_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_tcsr =3D { .name =3D "qhs_tcsr", - .id =3D SM8350_SLAVE_TCSR, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_tlmm =3D { .name =3D "qhs_tlmm", - .id =3D SM8350_SLAVE_TLMM, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_ufs_card_cfg =3D { .name =3D "qhs_ufs_card_cfg", - .id =3D SM8350_SLAVE_UFS_CARD_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_ufs_mem_cfg =3D { .name =3D "qhs_ufs_mem_cfg", - .id =3D SM8350_SLAVE_UFS_MEM_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_usb3_0 =3D { .name =3D "qhs_usb3_0", - .id =3D SM8350_SLAVE_USB3_0, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_usb3_1 =3D { .name =3D "qhs_usb3_1", - .id =3D SM8350_SLAVE_USB3_1, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_venus_cfg =3D { .name =3D "qhs_venus_cfg", - .id =3D SM8350_SLAVE_VENUS_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_vsense_ctrl_cfg =3D { .name =3D "qhs_vsense_ctrl_cfg", - .id =3D SM8350_SLAVE_VSENSE_CTRL_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qns_a1_noc_cfg =3D { .name =3D "qns_a1_noc_cfg", - .id =3D SM8350_SLAVE_A1NOC_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qns_a2_noc_cfg =3D { .name =3D "qns_a2_noc_cfg", - .id =3D SM8350_SLAVE_A2NOC_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qns_ddrss_cfg =3D { .name =3D "qns_ddrss_cfg", - .id =3D SM8350_SLAVE_DDRSS_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qns_mnoc_cfg =3D { .name =3D "qns_mnoc_cfg", - .id =3D SM8350_SLAVE_CNOC_MNOC_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qns_snoc_cfg =3D { .name =3D "qns_snoc_cfg", - .id =3D SM8350_SLAVE_SNOC_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qxs_boot_imem =3D { .name =3D "qxs_boot_imem", - .id =3D SM8350_SLAVE_BOOT_IMEM, .channels =3D 1, .buswidth =3D 8, }; =20 static struct qcom_icc_node qxs_imem =3D { .name =3D "qxs_imem", - .id =3D SM8350_SLAVE_IMEM, .channels =3D 1, .buswidth =3D 8, }; =20 static struct qcom_icc_node qxs_pimem =3D { .name =3D "qxs_pimem", - .id =3D SM8350_SLAVE_PIMEM, .channels =3D 1, .buswidth =3D 8, }; =20 static struct qcom_icc_node srvc_cnoc =3D { .name =3D "srvc_cnoc", - .id =3D SM8350_SLAVE_SERVICE_CNOC, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node xs_pcie_0 =3D { .name =3D "xs_pcie_0", - .id =3D SM8350_SLAVE_PCIE_0, .channels =3D 1, .buswidth =3D 8, }; =20 static struct qcom_icc_node xs_pcie_1 =3D { .name =3D "xs_pcie_1", - .id =3D SM8350_SLAVE_PCIE_1, .channels =3D 1, .buswidth =3D 8, }; =20 static struct qcom_icc_node xs_qdss_stm =3D { .name =3D "xs_qdss_stm", - .id =3D SM8350_SLAVE_QDSS_STM, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node xs_sys_tcu_cfg =3D { .name =3D "xs_sys_tcu_cfg", - .id =3D SM8350_SLAVE_TCU, .channels =3D 1, .buswidth =3D 8, }; =20 static struct qcom_icc_node qhs_llcc =3D { .name =3D "qhs_llcc", - .id =3D SM8350_SLAVE_LLCC_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qns_gemnoc =3D { .name =3D "qns_gemnoc", - .id =3D SM8350_SLAVE_GEM_NOC_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg =3D { .name =3D "qhs_mdsp_ms_mpu_cfg", - .id =3D SM8350_SLAVE_MSS_PROC_MS_MPU_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_modem_ms_mpu_cfg =3D { .name =3D "qhs_modem_ms_mpu_cfg", - .id =3D SM8350_SLAVE_MCDMA_MS_MPU_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qns_gem_noc_cnoc =3D { .name =3D "qns_gem_noc_cnoc", - .id =3D SM8350_SLAVE_GEM_NOC_CNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM8350_MASTER_GEM_NOC_CNOC }, + .link_nodes =3D { &qnm_gemnoc_cnoc }, }; =20 static struct qcom_icc_node qns_llcc =3D { .name =3D "qns_llcc", - .id =3D SM8350_SLAVE_LLCC, .channels =3D 4, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM8350_MASTER_LLCC }, + .link_nodes =3D { &llcc_mc }, }; =20 static struct qcom_icc_node qns_pcie =3D { .name =3D "qns_pcie", - .id =3D SM8350_SLAVE_MEM_NOC_PCIE_SNOC, .channels =3D 1, .buswidth =3D 8, }; =20 static struct qcom_icc_node srvc_even_gemnoc =3D { .name =3D "srvc_even_gemnoc", - .id =3D SM8350_SLAVE_SERVICE_GEM_NOC_1, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node srvc_odd_gemnoc =3D { .name =3D "srvc_odd_gemnoc", - .id =3D SM8350_SLAVE_SERVICE_GEM_NOC_2, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node srvc_sys_gemnoc =3D { .name =3D "srvc_sys_gemnoc", - .id =3D SM8350_SLAVE_SERVICE_GEM_NOC, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_lpass_core =3D { .name =3D "qhs_lpass_core", - .id =3D SM8350_SLAVE_LPASS_CORE_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_lpass_lpi =3D { .name =3D "qhs_lpass_lpi", - .id =3D SM8350_SLAVE_LPASS_LPI_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_lpass_mpu =3D { .name =3D "qhs_lpass_mpu", - .id =3D SM8350_SLAVE_LPASS_MPU_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qhs_lpass_top =3D { .name =3D "qhs_lpass_top", - .id =3D SM8350_SLAVE_LPASS_TOP_CFG, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node srvc_niu_aml_noc =3D { .name =3D "srvc_niu_aml_noc", - .id =3D SM8350_SLAVE_SERVICES_LPASS_AML_NOC, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node srvc_niu_lpass_agnoc =3D { .name =3D "srvc_niu_lpass_agnoc", - .id =3D SM8350_SLAVE_SERVICE_LPASS_AG_NOC, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node ebi =3D { .name =3D "ebi", - .id =3D SM8350_SLAVE_EBI1, .channels =3D 4, .buswidth =3D 4, }; =20 static struct qcom_icc_node qns_mem_noc_hf =3D { .name =3D "qns_mem_noc_hf", - .id =3D SM8350_SLAVE_MNOC_HF_MEM_NOC, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8350_MASTER_MNOC_HF_MEM_NOC }, + .link_nodes =3D { &qnm_mnoc_hf }, }; =20 static struct qcom_icc_node qns_mem_noc_sf =3D { .name =3D "qns_mem_noc_sf", - .id =3D SM8350_SLAVE_MNOC_SF_MEM_NOC, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8350_MASTER_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qnm_mnoc_sf }, }; =20 static struct qcom_icc_node srvc_mnoc =3D { .name =3D "srvc_mnoc", - .id =3D SM8350_SLAVE_SERVICE_MNOC, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qns_nsp_gemnoc =3D { .name =3D "qns_nsp_gemnoc", - .id =3D SM8350_SLAVE_CDSP_MEM_NOC, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8350_MASTER_COMPUTE_NOC }, + .link_nodes =3D { &qnm_cmpnoc }, }; =20 static struct qcom_icc_node service_nsp_noc =3D { .name =3D "service_nsp_noc", - .id =3D SM8350_SLAVE_SERVICE_NSP_NOC, .channels =3D 1, .buswidth =3D 4, }; =20 static struct qcom_icc_node qns_gemnoc_gc =3D { .name =3D "qns_gemnoc_gc", - .id =3D SM8350_SLAVE_SNOC_GEM_NOC_GC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8350_MASTER_SNOC_GC_MEM_NOC }, + .link_nodes =3D { &qnm_snoc_gc }, }; =20 static struct qcom_icc_node qns_gemnoc_sf =3D { .name =3D "qns_gemnoc_sf", - .id =3D SM8350_SLAVE_SNOC_GEM_NOC_SF, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM8350_MASTER_SNOC_SF_MEM_NOC }, + .link_nodes =3D { &qnm_snoc_sf }, }; =20 static struct qcom_icc_node srvc_snoc =3D { .name =3D "srvc_snoc", - .id =3D SM8350_SLAVE_SERVICE_SNOC, .channels =3D 1, .buswidth =3D 4, }; @@ -1511,6 +1497,7 @@ static struct qcom_icc_node * const aggre1_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sm8350_aggre1_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D aggre1_noc_nodes, .num_nodes =3D ARRAY_SIZE(aggre1_noc_nodes), .bcms =3D aggre1_noc_bcms, @@ -1542,6 +1529,7 @@ static struct qcom_icc_node * const aggre2_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sm8350_aggre2_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D aggre2_noc_nodes, .num_nodes =3D ARRAY_SIZE(aggre2_noc_nodes), .bcms =3D aggre2_noc_bcms, @@ -1621,6 +1609,7 @@ static struct qcom_icc_node * const config_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sm8350_config_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D config_noc_nodes, .num_nodes =3D ARRAY_SIZE(config_noc_nodes), .bcms =3D config_noc_bcms, @@ -1637,6 +1626,7 @@ static struct qcom_icc_node * const dc_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sm8350_dc_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D dc_noc_nodes, .num_nodes =3D ARRAY_SIZE(dc_noc_nodes), .bcms =3D dc_noc_bcms, @@ -1673,6 +1663,7 @@ static struct qcom_icc_node * const gem_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sm8350_gem_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D gem_noc_nodes, .num_nodes =3D ARRAY_SIZE(gem_noc_nodes), .bcms =3D gem_noc_bcms, @@ -1693,6 +1684,7 @@ static struct qcom_icc_node * const lpass_ag_noc_node= s[] =3D { }; =20 static const struct qcom_icc_desc sm8350_lpass_ag_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D lpass_ag_noc_nodes, .num_nodes =3D ARRAY_SIZE(lpass_ag_noc_nodes), .bcms =3D lpass_ag_noc_bcms, @@ -1710,6 +1702,7 @@ static struct qcom_icc_node * const mc_virt_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sm8350_mc_virt =3D { + .alloc_dyn_id =3D true, .nodes =3D mc_virt_nodes, .num_nodes =3D ARRAY_SIZE(mc_virt_nodes), .bcms =3D mc_virt_bcms, @@ -1740,6 +1733,7 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sm8350_mmss_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D mmss_noc_nodes, .num_nodes =3D ARRAY_SIZE(mmss_noc_nodes), .bcms =3D mmss_noc_bcms, @@ -1759,6 +1753,7 @@ static struct qcom_icc_node * const nsp_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sm8350_compute_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D nsp_noc_nodes, .num_nodes =3D ARRAY_SIZE(nsp_noc_nodes), .bcms =3D nsp_noc_bcms, @@ -1784,6 +1779,7 @@ static struct qcom_icc_node * const system_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sm8350_system_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D system_noc_nodes, .num_nodes =3D ARRAY_SIZE(system_noc_nodes), .bcms =3D system_noc_bcms, diff --git a/drivers/interconnect/qcom/sm8350.h b/drivers/interconnect/qcom= /sm8350.h deleted file mode 100644 index 074c6131ab3674376aa4ebfb79d62a2f655df338..000000000000000000000000000= 0000000000000 --- a/drivers/interconnect/qcom/sm8350.h +++ /dev/null @@ -1,158 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Qualcomm SM8350 interconnect IDs - * - * Copyright (c) 2021, Linaro Limited - */ - -#ifndef __DRIVERS_INTERCONNECT_QCOM_SM8350_H -#define __DRIVERS_INTERCONNECT_QCOM_SM8350_H - -#define SM8350_MASTER_GPU_TCU 0 -#define SM8350_MASTER_SYS_TCU 1 -#define SM8350_MASTER_APPSS_PROC 2 -#define SM8350_MASTER_LLCC 3 -#define SM8350_MASTER_CNOC_LPASS_AG_NOC 4 -#define SM8350_MASTER_CDSP_NOC_CFG 5 -#define SM8350_MASTER_QDSS_BAM 6 -#define SM8350_MASTER_QSPI_0 7 -#define SM8350_MASTER_QUP_0 8 -#define SM8350_MASTER_QUP_1 9 -#define SM8350_MASTER_QUP_2 10 -#define SM8350_MASTER_A1NOC_CFG 11 -#define SM8350_MASTER_A2NOC_CFG 12 -#define SM8350_MASTER_A1NOC_SNOC 13 -#define SM8350_MASTER_A2NOC_SNOC 14 -#define SM8350_MASTER_CAMNOC_HF 15 -#define SM8350_MASTER_CAMNOC_ICP 16 -#define SM8350_MASTER_CAMNOC_SF 17 -#define SM8350_MASTER_COMPUTE_NOC 18 -#define SM8350_MASTER_CNOC_DC_NOC 19 -#define SM8350_MASTER_GEM_NOC_CFG 20 -#define SM8350_MASTER_GEM_NOC_CNOC 21 -#define SM8350_MASTER_GEM_NOC_PCIE_SNOC 22 -#define SM8350_MASTER_GFX3D 23 -#define SM8350_MASTER_CNOC_MNOC_CFG 24 -#define SM8350_MASTER_MNOC_HF_MEM_NOC 25 -#define SM8350_MASTER_MNOC_SF_MEM_NOC 26 -#define SM8350_MASTER_ANOC_PCIE_GEM_NOC 27 -#define SM8350_MASTER_SNOC_CFG 28 -#define SM8350_MASTER_SNOC_GC_MEM_NOC 29 -#define SM8350_MASTER_SNOC_SF_MEM_NOC 30 -#define SM8350_MASTER_VIDEO_P0 31 -#define SM8350_MASTER_VIDEO_P1 32 -#define SM8350_MASTER_VIDEO_PROC 33 -#define SM8350_MASTER_QUP_CORE_0 34 -#define SM8350_MASTER_QUP_CORE_1 35 -#define SM8350_MASTER_QUP_CORE_2 36 -#define SM8350_MASTER_CRYPTO 37 -#define SM8350_MASTER_IPA 38 -#define SM8350_MASTER_MDP0 39 -#define SM8350_MASTER_MDP1 40 -#define SM8350_MASTER_CDSP_PROC 41 -#define SM8350_MASTER_PIMEM 42 -#define SM8350_MASTER_ROTATOR 43 -#define SM8350_MASTER_GIC 44 -#define SM8350_MASTER_PCIE_0 45 -#define SM8350_MASTER_PCIE_1 46 -#define SM8350_MASTER_QDSS_DAP 47 -#define SM8350_MASTER_QDSS_ETR 48 -#define SM8350_MASTER_SDCC_2 49 -#define SM8350_MASTER_SDCC_4 50 -#define SM8350_MASTER_UFS_CARD 51 -#define SM8350_MASTER_UFS_MEM 52 -#define SM8350_MASTER_USB3_0 53 -#define SM8350_MASTER_USB3_1 54 -#define SM8350_SLAVE_EBI1 55 -#define SM8350_SLAVE_AHB2PHY_SOUTH 56 -#define SM8350_SLAVE_AHB2PHY_NORTH 57 -#define SM8350_SLAVE_AOSS 58 -#define SM8350_SLAVE_APPSS 59 -#define SM8350_SLAVE_CAMERA_CFG 60 -#define SM8350_SLAVE_CLK_CTL 61 -#define SM8350_SLAVE_CDSP_CFG 62 -#define SM8350_SLAVE_RBCPR_CX_CFG 63 -#define SM8350_SLAVE_RBCPR_MMCX_CFG 64 -#define SM8350_SLAVE_RBCPR_MX_CFG 65 -#define SM8350_SLAVE_CRYPTO_0_CFG 66 -#define SM8350_SLAVE_CX_RDPM 67 -#define SM8350_SLAVE_DCC_CFG 68 -#define SM8350_SLAVE_DISPLAY_CFG 69 -#define SM8350_SLAVE_GFX3D_CFG 70 -#define SM8350_SLAVE_HWKM 71 -#define SM8350_SLAVE_IMEM_CFG 72 -#define SM8350_SLAVE_IPA_CFG 73 -#define SM8350_SLAVE_IPC_ROUTER_CFG 74 -#define SM8350_SLAVE_LLCC_CFG 75 -#define SM8350_SLAVE_LPASS 76 -#define SM8350_SLAVE_LPASS_CORE_CFG 77 -#define SM8350_SLAVE_LPASS_LPI_CFG 78 -#define SM8350_SLAVE_LPASS_MPU_CFG 79 -#define SM8350_SLAVE_LPASS_TOP_CFG 80 -#define SM8350_SLAVE_MSS_PROC_MS_MPU_CFG 81 -#define SM8350_SLAVE_MCDMA_MS_MPU_CFG 82 -#define SM8350_SLAVE_CNOC_MSS 83 -#define SM8350_SLAVE_MX_RDPM 84 -#define SM8350_SLAVE_PCIE_0_CFG 85 -#define SM8350_SLAVE_PCIE_1_CFG 86 -#define SM8350_SLAVE_PDM 87 -#define SM8350_SLAVE_PIMEM_CFG 88 -#define SM8350_SLAVE_PKA_WRAPPER_CFG 89 -#define SM8350_SLAVE_PMU_WRAPPER_CFG 90 -#define SM8350_SLAVE_QDSS_CFG 91 -#define SM8350_SLAVE_QSPI_0 92 -#define SM8350_SLAVE_QUP_0 93 -#define SM8350_SLAVE_QUP_1 94 -#define SM8350_SLAVE_QUP_2 95 -#define SM8350_SLAVE_SDCC_2 96 -#define SM8350_SLAVE_SDCC_4 97 -#define SM8350_SLAVE_SECURITY 98 -#define SM8350_SLAVE_SPSS_CFG 99 -#define SM8350_SLAVE_TCSR 100 -#define SM8350_SLAVE_TLMM 101 -#define SM8350_SLAVE_UFS_CARD_CFG 102 -#define SM8350_SLAVE_UFS_MEM_CFG 103 -#define SM8350_SLAVE_USB3_0 104 -#define SM8350_SLAVE_USB3_1 105 -#define SM8350_SLAVE_VENUS_CFG 106 -#define SM8350_SLAVE_VSENSE_CTRL_CFG 107 -#define SM8350_SLAVE_A1NOC_CFG 108 -#define SM8350_SLAVE_A1NOC_SNOC 109 -#define SM8350_SLAVE_A2NOC_CFG 110 -#define SM8350_SLAVE_A2NOC_SNOC 111 -#define SM8350_SLAVE_DDRSS_CFG 112 -#define SM8350_SLAVE_GEM_NOC_CNOC 113 -#define SM8350_SLAVE_GEM_NOC_CFG 114 -#define SM8350_SLAVE_SNOC_GEM_NOC_GC 115 -#define SM8350_SLAVE_SNOC_GEM_NOC_SF 116 -#define SM8350_SLAVE_LLCC 117 -#define SM8350_SLAVE_MNOC_HF_MEM_NOC 118 -#define SM8350_SLAVE_MNOC_SF_MEM_NOC 119 -#define SM8350_SLAVE_CNOC_MNOC_CFG 120 -#define SM8350_SLAVE_CDSP_MEM_NOC 121 -#define SM8350_SLAVE_MEM_NOC_PCIE_SNOC 122 -#define SM8350_SLAVE_ANOC_PCIE_GEM_NOC 123 -#define SM8350_SLAVE_SNOC_CFG 124 -#define SM8350_SLAVE_QUP_CORE_0 125 -#define SM8350_SLAVE_QUP_CORE_1 126 -#define SM8350_SLAVE_QUP_CORE_2 127 -#define SM8350_SLAVE_BOOT_IMEM 128 -#define SM8350_SLAVE_IMEM 129 -#define SM8350_SLAVE_PIMEM 130 -#define SM8350_SLAVE_SERVICE_NSP_NOC 131 -#define SM8350_SLAVE_SERVICE_A1NOC 132 -#define SM8350_SLAVE_SERVICE_A2NOC 133 -#define SM8350_SLAVE_SERVICE_CNOC 134 -#define SM8350_SLAVE_SERVICE_GEM_NOC_1 135 -#define SM8350_SLAVE_SERVICE_MNOC 136 -#define SM8350_SLAVE_SERVICES_LPASS_AML_NOC 137 -#define SM8350_SLAVE_SERVICE_LPASS_AG_NOC 138 -#define SM8350_SLAVE_SERVICE_GEM_NOC_2 139 -#define SM8350_SLAVE_SERVICE_SNOC 140 -#define SM8350_SLAVE_SERVICE_GEM_NOC 141 -#define SM8350_SLAVE_PCIE_0 142 -#define SM8350_SLAVE_PCIE_1 143 -#define SM8350_SLAVE_QDSS_STM 144 -#define SM8350_SLAVE_TCU 145 - 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This gives more flexibility and also allows us to drop the .num_links member, saving from possible errors related to it being not set or set incorrectly. Signed-off-by: Dmitry Baryshkov --- drivers/interconnect/qcom/sm8450.c | 612 +++++++++++++++++----------------= ---- drivers/interconnect/qcom/sm8450.h | 169 ---------- 2 files changed, 280 insertions(+), 501 deletions(-) diff --git a/drivers/interconnect/qcom/sm8450.c b/drivers/interconnect/qcom= /sm8450.c index eb7e17df32ba656cf1934e0fc112189966b22ac2..dd61e03b5a819ac8842afe59288= 00ed8640ff5ed 100644 --- a/drivers/interconnect/qcom/sm8450.c +++ b/drivers/interconnect/qcom/sm8450.c @@ -16,1325 +16,1262 @@ #include "bcm-voter.h" #include "icc-common.h" #include "icc-rpmh.h" -#include "sm8450.h" + +static struct qcom_icc_node qhm_qspi; +static struct qcom_icc_node qhm_qup1; +static struct qcom_icc_node qnm_a1noc_cfg; +static struct qcom_icc_node xm_sdc4; +static struct qcom_icc_node xm_ufs_mem; +static struct qcom_icc_node xm_usb3_0; +static struct qcom_icc_node qhm_qdss_bam; +static struct qcom_icc_node qhm_qup0; +static struct qcom_icc_node qhm_qup2; +static struct qcom_icc_node qnm_a2noc_cfg; +static struct qcom_icc_node qxm_crypto; +static struct qcom_icc_node qxm_ipa; +static struct qcom_icc_node qxm_sensorss_q6; +static struct qcom_icc_node qxm_sp; +static struct qcom_icc_node xm_qdss_etr_0; +static struct qcom_icc_node xm_qdss_etr_1; +static struct qcom_icc_node xm_sdc2; +static struct qcom_icc_node qup0_core_master; +static struct qcom_icc_node qup1_core_master; +static struct qcom_icc_node qup2_core_master; +static struct qcom_icc_node qnm_gemnoc_cnoc; +static struct qcom_icc_node qnm_gemnoc_pcie; +static struct qcom_icc_node alm_gpu_tcu; +static struct qcom_icc_node alm_sys_tcu; +static struct qcom_icc_node chm_apps; +static struct qcom_icc_node qnm_gpu; +static struct qcom_icc_node qnm_mdsp; +static struct qcom_icc_node qnm_mnoc_hf; +static struct qcom_icc_node qnm_mnoc_sf; +static struct qcom_icc_node qnm_nsp_gemnoc; +static struct qcom_icc_node qnm_pcie; +static struct qcom_icc_node qnm_snoc_gc; +static struct qcom_icc_node qnm_snoc_sf; +static struct qcom_icc_node qhm_config_noc; +static struct qcom_icc_node qxm_lpass_dsp; +static struct qcom_icc_node llcc_mc; +static struct qcom_icc_node qnm_camnoc_hf; +static struct qcom_icc_node qnm_camnoc_icp; +static struct qcom_icc_node qnm_camnoc_sf; +static struct qcom_icc_node qnm_mdp; +static struct qcom_icc_node qnm_mnoc_cfg; +static struct qcom_icc_node qnm_rot; +static struct qcom_icc_node qnm_vapss_hcp; +static struct qcom_icc_node qnm_video; +static struct qcom_icc_node qnm_video_cv_cpu; +static struct qcom_icc_node qnm_video_cvp; +static struct qcom_icc_node qnm_video_v_cpu; +static struct qcom_icc_node qhm_nsp_noc_config; +static struct qcom_icc_node qxm_nsp; +static struct qcom_icc_node qnm_pcie_anoc_cfg; +static struct qcom_icc_node xm_pcie3_0; +static struct qcom_icc_node xm_pcie3_1; +static struct qcom_icc_node qhm_gic; +static struct qcom_icc_node qnm_aggre1_noc; +static struct qcom_icc_node qnm_aggre2_noc; +static struct qcom_icc_node qnm_lpass_noc; +static struct qcom_icc_node qnm_snoc_cfg; +static struct qcom_icc_node qxm_pimem; +static struct qcom_icc_node xm_gic; +static struct qcom_icc_node qnm_mnoc_hf_disp; +static struct qcom_icc_node qnm_mnoc_sf_disp; +static struct qcom_icc_node qnm_pcie_disp; +static struct qcom_icc_node llcc_mc_disp; +static struct qcom_icc_node qnm_mdp_disp; +static struct qcom_icc_node qnm_rot_disp; +static struct qcom_icc_node qns_a1noc_snoc; +static struct qcom_icc_node srvc_aggre1_noc; +static struct qcom_icc_node qns_a2noc_snoc; +static struct qcom_icc_node srvc_aggre2_noc; +static struct qcom_icc_node qup0_core_slave; +static struct qcom_icc_node qup1_core_slave; +static struct qcom_icc_node qup2_core_slave; +static struct qcom_icc_node qhs_ahb2phy0; +static struct qcom_icc_node qhs_ahb2phy1; +static struct qcom_icc_node qhs_aoss; +static struct qcom_icc_node qhs_camera_cfg; +static struct qcom_icc_node qhs_clk_ctl; +static struct qcom_icc_node qhs_compute_cfg; +static struct qcom_icc_node qhs_cpr_cx; +static struct qcom_icc_node qhs_cpr_mmcx; +static struct qcom_icc_node qhs_cpr_mxa; +static struct qcom_icc_node qhs_cpr_mxc; +static struct qcom_icc_node qhs_crypto0_cfg; +static struct qcom_icc_node qhs_cx_rdpm; +static struct qcom_icc_node qhs_display_cfg; +static struct qcom_icc_node qhs_gpuss_cfg; +static struct qcom_icc_node qhs_imem_cfg; +static struct qcom_icc_node qhs_ipa; +static struct qcom_icc_node qhs_ipc_router; +static struct qcom_icc_node qhs_lpass_cfg; +static struct qcom_icc_node qhs_mss_cfg; +static struct qcom_icc_node qhs_mx_rdpm; +static struct qcom_icc_node qhs_pcie0_cfg; +static struct qcom_icc_node qhs_pcie1_cfg; +static struct qcom_icc_node qhs_pdm; +static struct qcom_icc_node qhs_pimem_cfg; +static struct qcom_icc_node qhs_prng; +static struct qcom_icc_node qhs_qdss_cfg; +static struct qcom_icc_node qhs_qspi; +static struct qcom_icc_node qhs_qup0; +static struct qcom_icc_node qhs_qup1; +static struct qcom_icc_node qhs_qup2; +static struct qcom_icc_node qhs_sdc2; +static struct qcom_icc_node qhs_sdc4; +static struct qcom_icc_node qhs_spss_cfg; +static struct qcom_icc_node qhs_tcsr; +static struct qcom_icc_node qhs_tlmm; +static struct qcom_icc_node qhs_tme_cfg; +static struct qcom_icc_node qhs_ufs_mem_cfg; +static struct qcom_icc_node qhs_usb3_0; +static struct qcom_icc_node qhs_venus_cfg; +static struct qcom_icc_node qhs_vsense_ctrl_cfg; +static struct qcom_icc_node qns_a1_noc_cfg; +static struct qcom_icc_node qns_a2_noc_cfg; +static struct qcom_icc_node qns_ddrss_cfg; +static struct qcom_icc_node qns_mnoc_cfg; +static struct qcom_icc_node qns_pcie_anoc_cfg; +static struct qcom_icc_node qns_snoc_cfg; +static struct qcom_icc_node qxs_imem; +static struct qcom_icc_node qxs_pimem; +static struct qcom_icc_node srvc_cnoc; +static struct qcom_icc_node xs_pcie_0; +static struct qcom_icc_node xs_pcie_1; +static struct qcom_icc_node xs_qdss_stm; +static struct qcom_icc_node xs_sys_tcu_cfg; +static struct qcom_icc_node qns_gem_noc_cnoc; +static struct qcom_icc_node qns_llcc; +static struct qcom_icc_node qns_pcie; +static struct qcom_icc_node qhs_lpass_core; +static struct qcom_icc_node qhs_lpass_lpi; +static struct qcom_icc_node qhs_lpass_mpu; +static struct qcom_icc_node qhs_lpass_top; +static struct qcom_icc_node qns_sysnoc; +static struct qcom_icc_node srvc_niu_aml_noc; +static struct qcom_icc_node srvc_niu_lpass_agnoc; +static struct qcom_icc_node ebi; +static struct qcom_icc_node qns_mem_noc_hf; +static struct qcom_icc_node qns_mem_noc_sf; +static struct qcom_icc_node srvc_mnoc; +static struct qcom_icc_node qns_nsp_gemnoc; +static struct qcom_icc_node service_nsp_noc; +static struct qcom_icc_node qns_pcie_mem_noc; +static struct qcom_icc_node srvc_pcie_aggre_noc; +static struct qcom_icc_node qns_gemnoc_gc; +static struct qcom_icc_node qns_gemnoc_sf; +static struct qcom_icc_node srvc_snoc; +static struct qcom_icc_node qns_llcc_disp; +static struct qcom_icc_node ebi_disp; +static struct qcom_icc_node qns_mem_noc_hf_disp; +static struct qcom_icc_node qns_mem_noc_sf_disp; =20 static struct qcom_icc_node qhm_qspi =3D { .name =3D "qhm_qspi", - .id =3D SM8450_MASTER_QSPI_0, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8450_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node qhm_qup1 =3D { .name =3D "qhm_qup1", - .id =3D SM8450_MASTER_QUP_1, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8450_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node qnm_a1noc_cfg =3D { .name =3D "qnm_a1noc_cfg", - .id =3D SM8450_MASTER_A1NOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8450_SLAVE_SERVICE_A1NOC }, + .link_nodes =3D { &srvc_aggre1_noc }, }; =20 static struct qcom_icc_node xm_sdc4 =3D { .name =3D "xm_sdc4", - .id =3D SM8450_MASTER_SDCC_4, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8450_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node xm_ufs_mem =3D { .name =3D "xm_ufs_mem", - .id =3D SM8450_MASTER_UFS_MEM, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8450_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node xm_usb3_0 =3D { .name =3D "xm_usb3_0", - .id =3D SM8450_MASTER_USB3_0, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8450_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node qhm_qdss_bam =3D { .name =3D "qhm_qdss_bam", - .id =3D SM8450_MASTER_QDSS_BAM, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8450_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qhm_qup0 =3D { .name =3D "qhm_qup0", - .id =3D SM8450_MASTER_QUP_0, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8450_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qhm_qup2 =3D { .name =3D "qhm_qup2", - .id =3D SM8450_MASTER_QUP_2, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8450_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qnm_a2noc_cfg =3D { .name =3D "qnm_a2noc_cfg", - .id =3D SM8450_MASTER_A2NOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8450_SLAVE_SERVICE_A2NOC }, + .link_nodes =3D { &srvc_aggre2_noc }, }; =20 static struct qcom_icc_node qxm_crypto =3D { .name =3D "qxm_crypto", - .id =3D SM8450_MASTER_CRYPTO, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8450_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qxm_ipa =3D { .name =3D "qxm_ipa", - .id =3D SM8450_MASTER_IPA, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8450_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qxm_sensorss_q6 =3D { .name =3D "qxm_sensorss_q6", - .id =3D SM8450_MASTER_SENSORS_PROC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8450_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qxm_sp =3D { .name =3D "qxm_sp", - .id =3D SM8450_MASTER_SP, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8450_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node xm_qdss_etr_0 =3D { .name =3D "xm_qdss_etr_0", - .id =3D SM8450_MASTER_QDSS_ETR, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8450_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node xm_qdss_etr_1 =3D { .name =3D "xm_qdss_etr_1", - .id =3D SM8450_MASTER_QDSS_ETR_1, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8450_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node xm_sdc2 =3D { .name =3D "xm_sdc2", - .id =3D SM8450_MASTER_SDCC_2, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8450_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qup0_core_master =3D { .name =3D "qup0_core_master", - .id =3D SM8450_MASTER_QUP_CORE_0, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8450_SLAVE_QUP_CORE_0 }, + .link_nodes =3D { &qup0_core_slave }, }; =20 static struct qcom_icc_node qup1_core_master =3D { .name =3D "qup1_core_master", - .id =3D SM8450_MASTER_QUP_CORE_1, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8450_SLAVE_QUP_CORE_1 }, + .link_nodes =3D { &qup1_core_slave }, }; =20 static struct qcom_icc_node qup2_core_master =3D { .name =3D "qup2_core_master", - .id =3D SM8450_MASTER_QUP_CORE_2, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8450_SLAVE_QUP_CORE_2 }, + .link_nodes =3D { &qup2_core_slave }, }; =20 static struct qcom_icc_node qnm_gemnoc_cnoc =3D { .name =3D "qnm_gemnoc_cnoc", - .id =3D SM8450_MASTER_GEM_NOC_CNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 51, - .links =3D { SM8450_SLAVE_AHB2PHY_SOUTH, SM8450_SLAVE_AHB2PHY_NORTH, - SM8450_SLAVE_AOSS, SM8450_SLAVE_CAMERA_CFG, - SM8450_SLAVE_CLK_CTL, SM8450_SLAVE_CDSP_CFG, - SM8450_SLAVE_RBCPR_CX_CFG, SM8450_SLAVE_RBCPR_MMCX_CFG, - SM8450_SLAVE_RBCPR_MXA_CFG, SM8450_SLAVE_RBCPR_MXC_CFG, - SM8450_SLAVE_CRYPTO_0_CFG, SM8450_SLAVE_CX_RDPM, - SM8450_SLAVE_DISPLAY_CFG, SM8450_SLAVE_GFX3D_CFG, - SM8450_SLAVE_IMEM_CFG, SM8450_SLAVE_IPA_CFG, - SM8450_SLAVE_IPC_ROUTER_CFG, SM8450_SLAVE_LPASS, - SM8450_SLAVE_CNOC_MSS, SM8450_SLAVE_MX_RDPM, - SM8450_SLAVE_PCIE_0_CFG, SM8450_SLAVE_PCIE_1_CFG, - SM8450_SLAVE_PDM, SM8450_SLAVE_PIMEM_CFG, - SM8450_SLAVE_PRNG, SM8450_SLAVE_QDSS_CFG, - SM8450_SLAVE_QSPI_0, SM8450_SLAVE_QUP_0, - SM8450_SLAVE_QUP_1, SM8450_SLAVE_QUP_2, - SM8450_SLAVE_SDCC_2, SM8450_SLAVE_SDCC_4, - SM8450_SLAVE_SPSS_CFG, SM8450_SLAVE_TCSR, - SM8450_SLAVE_TLMM, SM8450_SLAVE_TME_CFG, - SM8450_SLAVE_UFS_MEM_CFG, SM8450_SLAVE_USB3_0, - SM8450_SLAVE_VENUS_CFG, SM8450_SLAVE_VSENSE_CTRL_CFG, - SM8450_SLAVE_A1NOC_CFG, SM8450_SLAVE_A2NOC_CFG, - SM8450_SLAVE_DDRSS_CFG, SM8450_SLAVE_CNOC_MNOC_CFG, - SM8450_SLAVE_PCIE_ANOC_CFG, SM8450_SLAVE_SNOC_CFG, - SM8450_SLAVE_IMEM, SM8450_SLAVE_PIMEM, - SM8450_SLAVE_SERVICE_CNOC, SM8450_SLAVE_QDSS_STM, - SM8450_SLAVE_TCU }, + .link_nodes =3D { &qhs_ahb2phy0, &qhs_ahb2phy1, + &qhs_aoss, &qhs_camera_cfg, + &qhs_clk_ctl, &qhs_compute_cfg, + &qhs_cpr_cx, &qhs_cpr_mmcx, + &qhs_cpr_mxa, &qhs_cpr_mxc, + &qhs_crypto0_cfg, &qhs_cx_rdpm, + &qhs_display_cfg, &qhs_gpuss_cfg, + &qhs_imem_cfg, &qhs_ipa, + &qhs_ipc_router, &qhs_lpass_cfg, + &qhs_mss_cfg, &qhs_mx_rdpm, + &qhs_pcie0_cfg, &qhs_pcie1_cfg, + &qhs_pdm, &qhs_pimem_cfg, + &qhs_prng, &qhs_qdss_cfg, + &qhs_qspi, &qhs_qup0, + &qhs_qup1, &qhs_qup2, + &qhs_sdc2, &qhs_sdc4, + &qhs_spss_cfg, &qhs_tcsr, + &qhs_tlmm, &qhs_tme_cfg, + &qhs_ufs_mem_cfg, &qhs_usb3_0, + &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, + &qns_a1_noc_cfg, &qns_a2_noc_cfg, + &qns_ddrss_cfg, &qns_mnoc_cfg, + &qns_pcie_anoc_cfg, &qns_snoc_cfg, + &qxs_imem, &qxs_pimem, + &srvc_cnoc, &xs_qdss_stm, + &xs_sys_tcu_cfg }, }; =20 static struct qcom_icc_node qnm_gemnoc_pcie =3D { .name =3D "qnm_gemnoc_pcie", - .id =3D SM8450_MASTER_GEM_NOC_PCIE_SNOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 2, - .links =3D { SM8450_SLAVE_PCIE_0, SM8450_SLAVE_PCIE_1 }, + .link_nodes =3D { &xs_pcie_0, &xs_pcie_1 }, }; =20 static struct qcom_icc_node alm_gpu_tcu =3D { .name =3D "alm_gpu_tcu", - .id =3D SM8450_MASTER_GPU_TCU, .channels =3D 1, .buswidth =3D 8, .num_links =3D 2, - .links =3D { SM8450_SLAVE_GEM_NOC_CNOC, SM8450_SLAVE_LLCC }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; =20 static struct qcom_icc_node alm_sys_tcu =3D { .name =3D "alm_sys_tcu", - .id =3D SM8450_MASTER_SYS_TCU, .channels =3D 1, .buswidth =3D 8, .num_links =3D 2, - .links =3D { SM8450_SLAVE_GEM_NOC_CNOC, SM8450_SLAVE_LLCC }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; =20 static struct qcom_icc_node chm_apps =3D { .name =3D "chm_apps", - .id =3D SM8450_MASTER_APPSS_PROC, .channels =3D 3, .buswidth =3D 32, .num_links =3D 3, - .links =3D { SM8450_SLAVE_GEM_NOC_CNOC, SM8450_SLAVE_LLCC, - SM8450_SLAVE_MEM_NOC_PCIE_SNOC }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, }; =20 static struct qcom_icc_node qnm_gpu =3D { .name =3D "qnm_gpu", - .id =3D SM8450_MASTER_GFX3D, .channels =3D 2, .buswidth =3D 32, .num_links =3D 2, - .links =3D { SM8450_SLAVE_GEM_NOC_CNOC, SM8450_SLAVE_LLCC }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; =20 static struct qcom_icc_node qnm_mdsp =3D { .name =3D "qnm_mdsp", - .id =3D SM8450_MASTER_MSS_PROC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 3, - .links =3D { SM8450_SLAVE_GEM_NOC_CNOC, SM8450_SLAVE_LLCC, - SM8450_SLAVE_MEM_NOC_PCIE_SNOC }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, }; =20 static struct qcom_icc_node qnm_mnoc_hf =3D { .name =3D "qnm_mnoc_hf", - .id =3D SM8450_MASTER_MNOC_HF_MEM_NOC, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8450_SLAVE_LLCC }, + .link_nodes =3D { &qns_llcc }, }; =20 static struct qcom_icc_node qnm_mnoc_sf =3D { .name =3D "qnm_mnoc_sf", - .id =3D SM8450_MASTER_MNOC_SF_MEM_NOC, .channels =3D 2, .buswidth =3D 32, .num_links =3D 2, - .links =3D { SM8450_SLAVE_GEM_NOC_CNOC, SM8450_SLAVE_LLCC }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; =20 static struct qcom_icc_node qnm_nsp_gemnoc =3D { .name =3D "qnm_nsp_gemnoc", - .id =3D SM8450_MASTER_COMPUTE_NOC, .channels =3D 2, .buswidth =3D 32, .num_links =3D 2, - .links =3D { SM8450_SLAVE_GEM_NOC_CNOC, SM8450_SLAVE_LLCC }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; =20 static struct qcom_icc_node qnm_pcie =3D { .name =3D "qnm_pcie", - .id =3D SM8450_MASTER_ANOC_PCIE_GEM_NOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 2, - .links =3D { SM8450_SLAVE_GEM_NOC_CNOC, SM8450_SLAVE_LLCC }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; =20 static struct qcom_icc_node qnm_snoc_gc =3D { .name =3D "qnm_snoc_gc", - .id =3D SM8450_MASTER_SNOC_GC_MEM_NOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8450_SLAVE_LLCC }, + .link_nodes =3D { &qns_llcc }, }; =20 static struct qcom_icc_node qnm_snoc_sf =3D { .name =3D "qnm_snoc_sf", - .id =3D SM8450_MASTER_SNOC_SF_MEM_NOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 3, - .links =3D { SM8450_SLAVE_GEM_NOC_CNOC, SM8450_SLAVE_LLCC, - SM8450_SLAVE_MEM_NOC_PCIE_SNOC }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, }; =20 static struct qcom_icc_node qhm_config_noc =3D { .name =3D "qhm_config_noc", - .id =3D SM8450_MASTER_CNOC_LPASS_AG_NOC, .channels =3D 1, .buswidth =3D 4, .num_links =3D 6, - .links =3D { SM8450_SLAVE_LPASS_CORE_CFG, SM8450_SLAVE_LPASS_LPI_CFG, - SM8450_SLAVE_LPASS_MPU_CFG, SM8450_SLAVE_LPASS_TOP_CFG, - SM8450_SLAVE_SERVICES_LPASS_AML_NOC, SM8450_SLAVE_SERVICE_LPASS_AG_NO= C }, + .link_nodes =3D { &qhs_lpass_core, &qhs_lpass_lpi, + &qhs_lpass_mpu, &qhs_lpass_top, + &srvc_niu_aml_noc, &srvc_niu_lpass_agnoc }, }; =20 static struct qcom_icc_node qxm_lpass_dsp =3D { .name =3D "qxm_lpass_dsp", - .id =3D SM8450_MASTER_LPASS_PROC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 4, - .links =3D { SM8450_SLAVE_LPASS_TOP_CFG, SM8450_SLAVE_LPASS_SNOC, - SM8450_SLAVE_SERVICES_LPASS_AML_NOC, SM8450_SLAVE_SERVICE_LPASS_AG_NO= C }, + .link_nodes =3D { &qhs_lpass_top, &qns_sysnoc, + &srvc_niu_aml_noc, &srvc_niu_lpass_agnoc }, }; =20 static struct qcom_icc_node llcc_mc =3D { .name =3D "llcc_mc", - .id =3D SM8450_MASTER_LLCC, .channels =3D 4, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8450_SLAVE_EBI1 }, + .link_nodes =3D { &ebi }, }; =20 static struct qcom_icc_node qnm_camnoc_hf =3D { .name =3D "qnm_camnoc_hf", - .id =3D SM8450_MASTER_CAMNOC_HF, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8450_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_hf }, }; =20 static struct qcom_icc_node qnm_camnoc_icp =3D { .name =3D "qnm_camnoc_icp", - .id =3D SM8450_MASTER_CAMNOC_ICP, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8450_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static struct qcom_icc_node qnm_camnoc_sf =3D { .name =3D "qnm_camnoc_sf", - .id =3D SM8450_MASTER_CAMNOC_SF, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8450_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static struct qcom_icc_node qnm_mdp =3D { .name =3D "qnm_mdp", - .id =3D SM8450_MASTER_MDP, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8450_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_hf }, }; =20 static struct qcom_icc_node qnm_mnoc_cfg =3D { .name =3D "qnm_mnoc_cfg", - .id =3D SM8450_MASTER_CNOC_MNOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8450_SLAVE_SERVICE_MNOC }, + .link_nodes =3D { &srvc_mnoc }, }; =20 static struct qcom_icc_node qnm_rot =3D { .name =3D "qnm_rot", - .id =3D SM8450_MASTER_ROTATOR, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8450_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static struct qcom_icc_node qnm_vapss_hcp =3D { .name =3D "qnm_vapss_hcp", - .id =3D SM8450_MASTER_CDSP_HCP, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8450_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static struct qcom_icc_node qnm_video =3D { .name =3D "qnm_video", - .id =3D SM8450_MASTER_VIDEO, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8450_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static struct qcom_icc_node qnm_video_cv_cpu =3D { .name =3D "qnm_video_cv_cpu", - .id =3D SM8450_MASTER_VIDEO_CV_PROC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8450_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static struct qcom_icc_node qnm_video_cvp =3D { .name =3D "qnm_video_cvp", - .id =3D SM8450_MASTER_VIDEO_PROC, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8450_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static struct qcom_icc_node qnm_video_v_cpu =3D { .name =3D "qnm_video_v_cpu", - .id =3D SM8450_MASTER_VIDEO_V_PROC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8450_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static struct qcom_icc_node qhm_nsp_noc_config =3D { .name =3D "qhm_nsp_noc_config", - .id =3D SM8450_MASTER_CDSP_NOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8450_SLAVE_SERVICE_NSP_NOC }, + .link_nodes =3D { &service_nsp_noc }, }; =20 static struct qcom_icc_node qxm_nsp =3D { .name =3D "qxm_nsp", - .id =3D SM8450_MASTER_CDSP_PROC, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8450_SLAVE_CDSP_MEM_NOC }, + .link_nodes =3D { &qns_nsp_gemnoc }, }; =20 static struct qcom_icc_node qnm_pcie_anoc_cfg =3D { .name =3D "qnm_pcie_anoc_cfg", - .id =3D SM8450_MASTER_PCIE_ANOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8450_SLAVE_SERVICE_PCIE_ANOC }, + .link_nodes =3D { &srvc_pcie_aggre_noc }, }; =20 static struct qcom_icc_node xm_pcie3_0 =3D { .name =3D "xm_pcie3_0", - .id =3D SM8450_MASTER_PCIE_0, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8450_SLAVE_ANOC_PCIE_GEM_NOC }, + .link_nodes =3D { &qns_pcie_mem_noc }, }; =20 static struct qcom_icc_node xm_pcie3_1 =3D { .name =3D "xm_pcie3_1", - .id =3D SM8450_MASTER_PCIE_1, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8450_SLAVE_ANOC_PCIE_GEM_NOC }, + .link_nodes =3D { &qns_pcie_mem_noc }, }; =20 static struct qcom_icc_node qhm_gic =3D { .name =3D "qhm_gic", - .id =3D SM8450_MASTER_GIC_AHB, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8450_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes =3D { &qns_gemnoc_sf }, }; =20 static struct qcom_icc_node qnm_aggre1_noc =3D { .name =3D "qnm_aggre1_noc", - .id =3D SM8450_MASTER_A1NOC_SNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM8450_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes =3D { &qns_gemnoc_sf }, }; =20 static struct qcom_icc_node qnm_aggre2_noc =3D { .name =3D "qnm_aggre2_noc", - .id =3D SM8450_MASTER_A2NOC_SNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM8450_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes =3D { &qns_gemnoc_sf }, }; =20 static struct qcom_icc_node qnm_lpass_noc =3D { .name =3D "qnm_lpass_noc", - .id =3D SM8450_MASTER_LPASS_ANOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM8450_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes =3D { &qns_gemnoc_sf }, }; =20 static struct qcom_icc_node qnm_snoc_cfg =3D { .name =3D "qnm_snoc_cfg", - .id =3D SM8450_MASTER_SNOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8450_SLAVE_SERVICE_SNOC }, + .link_nodes =3D { &srvc_snoc }, }; =20 static struct qcom_icc_node qxm_pimem =3D { .name =3D "qxm_pimem", - .id =3D SM8450_MASTER_PIMEM, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8450_SLAVE_SNOC_GEM_NOC_GC }, + .link_nodes =3D { &qns_gemnoc_gc }, }; =20 static struct qcom_icc_node xm_gic =3D { .name =3D "xm_gic", - .id =3D SM8450_MASTER_GIC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8450_SLAVE_SNOC_GEM_NOC_GC }, + .link_nodes =3D { &qns_gemnoc_gc }, }; =20 static struct qcom_icc_node qnm_mnoc_hf_disp =3D { .name =3D "qnm_mnoc_hf_disp", - .id =3D SM8450_MASTER_MNOC_HF_MEM_NOC_DISP, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8450_SLAVE_LLCC_DISP }, + .link_nodes =3D { &qns_llcc_disp }, }; =20 static struct qcom_icc_node qnm_mnoc_sf_disp =3D { .name =3D "qnm_mnoc_sf_disp", - .id =3D SM8450_MASTER_MNOC_SF_MEM_NOC_DISP, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8450_SLAVE_LLCC_DISP }, + .link_nodes =3D { &qns_llcc_disp }, }; =20 static struct qcom_icc_node qnm_pcie_disp =3D { .name =3D "qnm_pcie_disp", - .id =3D SM8450_MASTER_ANOC_PCIE_GEM_NOC_DISP, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM8450_SLAVE_LLCC_DISP }, + .link_nodes =3D { &qns_llcc_disp }, }; =20 static struct qcom_icc_node llcc_mc_disp =3D { .name =3D "llcc_mc_disp", - .id =3D SM8450_MASTER_LLCC_DISP, .channels =3D 4, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8450_SLAVE_EBI1_DISP }, + .link_nodes =3D { &ebi_disp }, }; =20 static struct qcom_icc_node qnm_mdp_disp =3D { .name =3D "qnm_mdp_disp", - .id =3D SM8450_MASTER_MDP_DISP, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8450_SLAVE_MNOC_HF_MEM_NOC_DISP }, + .link_nodes =3D { &qns_mem_noc_hf_disp }, }; =20 static struct qcom_icc_node qnm_rot_disp =3D { .name =3D "qnm_rot_disp", - .id =3D SM8450_MASTER_ROTATOR_DISP, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8450_SLAVE_MNOC_SF_MEM_NOC_DISP }, + .link_nodes =3D { &qns_mem_noc_sf_disp }, }; =20 static struct qcom_icc_node qns_a1noc_snoc =3D { .name =3D "qns_a1noc_snoc", - .id =3D SM8450_SLAVE_A1NOC_SNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM8450_MASTER_A1NOC_SNOC }, + .link_nodes =3D { &qnm_aggre1_noc }, }; =20 static struct qcom_icc_node srvc_aggre1_noc =3D { .name =3D "srvc_aggre1_noc", - .id =3D SM8450_SLAVE_SERVICE_A1NOC, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qns_a2noc_snoc =3D { .name =3D "qns_a2noc_snoc", - .id =3D SM8450_SLAVE_A2NOC_SNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM8450_MASTER_A2NOC_SNOC }, + .link_nodes =3D { &qnm_aggre2_noc }, }; =20 static struct qcom_icc_node srvc_aggre2_noc =3D { .name =3D "srvc_aggre2_noc", - .id =3D SM8450_SLAVE_SERVICE_A2NOC, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qup0_core_slave =3D { .name =3D "qup0_core_slave", - .id =3D SM8450_SLAVE_QUP_CORE_0, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qup1_core_slave =3D { .name =3D "qup1_core_slave", - .id =3D SM8450_SLAVE_QUP_CORE_1, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qup2_core_slave =3D { .name =3D "qup2_core_slave", - .id =3D SM8450_SLAVE_QUP_CORE_2, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_ahb2phy0 =3D { .name =3D "qhs_ahb2phy0", - .id =3D SM8450_SLAVE_AHB2PHY_SOUTH, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_ahb2phy1 =3D { .name =3D "qhs_ahb2phy1", - .id =3D SM8450_SLAVE_AHB2PHY_NORTH, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_aoss =3D { .name =3D "qhs_aoss", - .id =3D SM8450_SLAVE_AOSS, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_camera_cfg =3D { .name =3D "qhs_camera_cfg", - .id =3D SM8450_SLAVE_CAMERA_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_clk_ctl =3D { .name =3D "qhs_clk_ctl", - .id =3D SM8450_SLAVE_CLK_CTL, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_compute_cfg =3D { .name =3D "qhs_compute_cfg", - .id =3D SM8450_SLAVE_CDSP_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { MASTER_CDSP_NOC_CFG }, + .link_nodes =3D { MASTER_CDSP_NOC_CFG }, }; =20 static struct qcom_icc_node qhs_cpr_cx =3D { .name =3D "qhs_cpr_cx", - .id =3D SM8450_SLAVE_RBCPR_CX_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_cpr_mmcx =3D { .name =3D "qhs_cpr_mmcx", - .id =3D SM8450_SLAVE_RBCPR_MMCX_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_cpr_mxa =3D { .name =3D "qhs_cpr_mxa", - .id =3D SM8450_SLAVE_RBCPR_MXA_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_cpr_mxc =3D { .name =3D "qhs_cpr_mxc", - .id =3D SM8450_SLAVE_RBCPR_MXC_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_crypto0_cfg =3D { .name =3D "qhs_crypto0_cfg", - .id =3D SM8450_SLAVE_CRYPTO_0_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_cx_rdpm =3D { .name =3D "qhs_cx_rdpm", - .id =3D SM8450_SLAVE_CX_RDPM, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_display_cfg =3D { .name =3D "qhs_display_cfg", - .id =3D SM8450_SLAVE_DISPLAY_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_gpuss_cfg =3D { .name =3D "qhs_gpuss_cfg", - .id =3D SM8450_SLAVE_GFX3D_CFG, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_imem_cfg =3D { .name =3D "qhs_imem_cfg", - .id =3D SM8450_SLAVE_IMEM_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_ipa =3D { .name =3D "qhs_ipa", - .id =3D SM8450_SLAVE_IPA_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_ipc_router =3D { .name =3D "qhs_ipc_router", - .id =3D SM8450_SLAVE_IPC_ROUTER_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_lpass_cfg =3D { .name =3D "qhs_lpass_cfg", - .id =3D SM8450_SLAVE_LPASS, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { MASTER_CNOC_LPASS_AG_NOC }, + .link_nodes =3D { MASTER_CNOC_LPASS_AG_NOC }, }; =20 static struct qcom_icc_node qhs_mss_cfg =3D { .name =3D "qhs_mss_cfg", - .id =3D SM8450_SLAVE_CNOC_MSS, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_mx_rdpm =3D { .name =3D "qhs_mx_rdpm", - .id =3D SM8450_SLAVE_MX_RDPM, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_pcie0_cfg =3D { .name =3D "qhs_pcie0_cfg", - .id =3D SM8450_SLAVE_PCIE_0_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_pcie1_cfg =3D { .name =3D "qhs_pcie1_cfg", - .id =3D SM8450_SLAVE_PCIE_1_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_pdm =3D { .name =3D "qhs_pdm", - .id =3D SM8450_SLAVE_PDM, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_pimem_cfg =3D { .name =3D "qhs_pimem_cfg", - .id =3D SM8450_SLAVE_PIMEM_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_prng =3D { .name =3D "qhs_prng", - .id =3D SM8450_SLAVE_PRNG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_qdss_cfg =3D { .name =3D "qhs_qdss_cfg", - .id =3D SM8450_SLAVE_QDSS_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_qspi =3D { .name =3D "qhs_qspi", - .id =3D SM8450_SLAVE_QSPI_0, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_qup0 =3D { .name =3D "qhs_qup0", - .id =3D SM8450_SLAVE_QUP_0, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_qup1 =3D { .name =3D "qhs_qup1", - .id =3D SM8450_SLAVE_QUP_1, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_qup2 =3D { .name =3D "qhs_qup2", - .id =3D SM8450_SLAVE_QUP_2, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_sdc2 =3D { .name =3D "qhs_sdc2", - .id =3D SM8450_SLAVE_SDCC_2, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_sdc4 =3D { .name =3D "qhs_sdc4", - .id =3D SM8450_SLAVE_SDCC_4, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_spss_cfg =3D { .name =3D "qhs_spss_cfg", - .id =3D SM8450_SLAVE_SPSS_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_tcsr =3D { .name =3D "qhs_tcsr", - .id =3D SM8450_SLAVE_TCSR, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_tlmm =3D { .name =3D "qhs_tlmm", - .id =3D SM8450_SLAVE_TLMM, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_tme_cfg =3D { .name =3D "qhs_tme_cfg", - .id =3D SM8450_SLAVE_TME_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_ufs_mem_cfg =3D { .name =3D "qhs_ufs_mem_cfg", - .id =3D SM8450_SLAVE_UFS_MEM_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_usb3_0 =3D { .name =3D "qhs_usb3_0", - .id =3D SM8450_SLAVE_USB3_0, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_venus_cfg =3D { .name =3D "qhs_venus_cfg", - .id =3D SM8450_SLAVE_VENUS_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_vsense_ctrl_cfg =3D { .name =3D "qhs_vsense_ctrl_cfg", - .id =3D SM8450_SLAVE_VSENSE_CTRL_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qns_a1_noc_cfg =3D { .name =3D "qns_a1_noc_cfg", - .id =3D SM8450_SLAVE_A1NOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8450_MASTER_A1NOC_CFG }, + .link_nodes =3D { &qnm_a1noc_cfg }, }; =20 static struct qcom_icc_node qns_a2_noc_cfg =3D { .name =3D "qns_a2_noc_cfg", - .id =3D SM8450_SLAVE_A2NOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8450_MASTER_A2NOC_CFG }, + .link_nodes =3D { &qnm_a2noc_cfg }, }; =20 static struct qcom_icc_node qns_ddrss_cfg =3D { .name =3D "qns_ddrss_cfg", - .id =3D SM8450_SLAVE_DDRSS_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 1, //FIXME where is link }; =20 static struct qcom_icc_node qns_mnoc_cfg =3D { .name =3D "qns_mnoc_cfg", - .id =3D SM8450_SLAVE_CNOC_MNOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8450_MASTER_CNOC_MNOC_CFG }, + .link_nodes =3D { &qnm_mnoc_cfg }, }; =20 static struct qcom_icc_node qns_pcie_anoc_cfg =3D { .name =3D "qns_pcie_anoc_cfg", - .id =3D SM8450_SLAVE_PCIE_ANOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8450_MASTER_PCIE_ANOC_CFG }, + .link_nodes =3D { &qnm_pcie_anoc_cfg }, }; =20 static struct qcom_icc_node qns_snoc_cfg =3D { .name =3D "qns_snoc_cfg", - .id =3D SM8450_SLAVE_SNOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8450_MASTER_SNOC_CFG }, + .link_nodes =3D { &qnm_snoc_cfg }, }; =20 static struct qcom_icc_node qxs_imem =3D { .name =3D "qxs_imem", - .id =3D SM8450_SLAVE_IMEM, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 0, }; =20 static struct qcom_icc_node qxs_pimem =3D { .name =3D "qxs_pimem", - .id =3D SM8450_SLAVE_PIMEM, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 0, }; =20 static struct qcom_icc_node srvc_cnoc =3D { .name =3D "srvc_cnoc", - .id =3D SM8450_SLAVE_SERVICE_CNOC, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node xs_pcie_0 =3D { .name =3D "xs_pcie_0", - .id =3D SM8450_SLAVE_PCIE_0, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 0, }; =20 static struct qcom_icc_node xs_pcie_1 =3D { .name =3D "xs_pcie_1", - .id =3D SM8450_SLAVE_PCIE_1, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 0, }; =20 static struct qcom_icc_node xs_qdss_stm =3D { .name =3D "xs_qdss_stm", - .id =3D SM8450_SLAVE_QDSS_STM, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node xs_sys_tcu_cfg =3D { .name =3D "xs_sys_tcu_cfg", - .id =3D SM8450_SLAVE_TCU, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 0, }; =20 static struct qcom_icc_node qns_gem_noc_cnoc =3D { .name =3D "qns_gem_noc_cnoc", - .id =3D SM8450_SLAVE_GEM_NOC_CNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM8450_MASTER_GEM_NOC_CNOC }, + .link_nodes =3D { &qnm_gemnoc_cnoc }, }; =20 static struct qcom_icc_node qns_llcc =3D { .name =3D "qns_llcc", - .id =3D SM8450_SLAVE_LLCC, .channels =3D 4, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM8450_MASTER_LLCC }, + .link_nodes =3D { &llcc_mc }, }; =20 static struct qcom_icc_node qns_pcie =3D { .name =3D "qns_pcie", - .id =3D SM8450_SLAVE_MEM_NOC_PCIE_SNOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8450_MASTER_GEM_NOC_PCIE_SNOC }, + .link_nodes =3D { &qnm_gemnoc_pcie }, }; =20 static struct qcom_icc_node qhs_lpass_core =3D { .name =3D "qhs_lpass_core", - .id =3D SM8450_SLAVE_LPASS_CORE_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_lpass_lpi =3D { .name =3D "qhs_lpass_lpi", - .id =3D SM8450_SLAVE_LPASS_LPI_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_lpass_mpu =3D { .name =3D "qhs_lpass_mpu", - .id =3D SM8450_SLAVE_LPASS_MPU_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_lpass_top =3D { .name =3D "qhs_lpass_top", - .id =3D SM8450_SLAVE_LPASS_TOP_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qns_sysnoc =3D { .name =3D "qns_sysnoc", - .id =3D SM8450_SLAVE_LPASS_SNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM8450_MASTER_LPASS_ANOC }, + .link_nodes =3D { &qnm_lpass_noc }, }; =20 static struct qcom_icc_node srvc_niu_aml_noc =3D { .name =3D "srvc_niu_aml_noc", - .id =3D SM8450_SLAVE_SERVICES_LPASS_AML_NOC, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node srvc_niu_lpass_agnoc =3D { .name =3D "srvc_niu_lpass_agnoc", - .id =3D SM8450_SLAVE_SERVICE_LPASS_AG_NOC, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node ebi =3D { .name =3D "ebi", - .id =3D SM8450_SLAVE_EBI1, .channels =3D 4, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qns_mem_noc_hf =3D { .name =3D "qns_mem_noc_hf", - .id =3D SM8450_SLAVE_MNOC_HF_MEM_NOC, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8450_MASTER_MNOC_HF_MEM_NOC }, + .link_nodes =3D { &qnm_mnoc_hf }, }; =20 static struct qcom_icc_node qns_mem_noc_sf =3D { .name =3D "qns_mem_noc_sf", - .id =3D SM8450_SLAVE_MNOC_SF_MEM_NOC, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8450_MASTER_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qnm_mnoc_sf }, }; =20 static struct qcom_icc_node srvc_mnoc =3D { .name =3D "srvc_mnoc", - .id =3D SM8450_SLAVE_SERVICE_MNOC, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qns_nsp_gemnoc =3D { .name =3D "qns_nsp_gemnoc", - .id =3D SM8450_SLAVE_CDSP_MEM_NOC, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8450_MASTER_COMPUTE_NOC }, + .link_nodes =3D { &qnm_nsp_gemnoc }, }; =20 static struct qcom_icc_node service_nsp_noc =3D { .name =3D "service_nsp_noc", - .id =3D SM8450_SLAVE_SERVICE_NSP_NOC, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qns_pcie_mem_noc =3D { .name =3D "qns_pcie_mem_noc", - .id =3D SM8450_SLAVE_ANOC_PCIE_GEM_NOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM8450_MASTER_ANOC_PCIE_GEM_NOC }, + .link_nodes =3D { &qnm_pcie }, }; =20 static struct qcom_icc_node srvc_pcie_aggre_noc =3D { .name =3D "srvc_pcie_aggre_noc", - .id =3D SM8450_SLAVE_SERVICE_PCIE_ANOC, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qns_gemnoc_gc =3D { .name =3D "qns_gemnoc_gc", - .id =3D SM8450_SLAVE_SNOC_GEM_NOC_GC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8450_MASTER_SNOC_GC_MEM_NOC }, + .link_nodes =3D { &qnm_snoc_gc }, }; =20 static struct qcom_icc_node qns_gemnoc_sf =3D { .name =3D "qns_gemnoc_sf", - .id =3D SM8450_SLAVE_SNOC_GEM_NOC_SF, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM8450_MASTER_SNOC_SF_MEM_NOC }, + .link_nodes =3D { &qnm_snoc_sf }, }; =20 static struct qcom_icc_node srvc_snoc =3D { .name =3D "srvc_snoc", - .id =3D SM8450_SLAVE_SERVICE_SNOC, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qns_llcc_disp =3D { .name =3D "qns_llcc_disp", - .id =3D SM8450_SLAVE_LLCC_DISP, .channels =3D 4, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM8450_MASTER_LLCC_DISP }, + .link_nodes =3D { &llcc_mc_disp }, }; =20 static struct qcom_icc_node ebi_disp =3D { .name =3D "ebi_disp", - .id =3D SM8450_SLAVE_EBI1_DISP, .channels =3D 4, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qns_mem_noc_hf_disp =3D { .name =3D "qns_mem_noc_hf_disp", - .id =3D SM8450_SLAVE_MNOC_HF_MEM_NOC_DISP, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8450_MASTER_MNOC_HF_MEM_NOC_DISP }, + .link_nodes =3D { &qnm_mnoc_hf_disp }, }; =20 static struct qcom_icc_node qns_mem_noc_sf_disp =3D { .name =3D "qns_mem_noc_sf_disp", - .id =3D SM8450_SLAVE_MNOC_SF_MEM_NOC_DISP, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8450_MASTER_MNOC_SF_MEM_NOC_DISP }, + .link_nodes =3D { &qnm_mnoc_sf_disp }, }; =20 static struct qcom_icc_bcm bcm_acv =3D { @@ -1553,6 +1490,7 @@ static struct qcom_icc_node * const aggre1_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sm8450_aggre1_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D aggre1_noc_nodes, .num_nodes =3D ARRAY_SIZE(aggre1_noc_nodes), .bcms =3D aggre1_noc_bcms, @@ -1580,6 +1518,7 @@ static struct qcom_icc_node * const aggre2_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sm8450_aggre2_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D aggre2_noc_nodes, .num_nodes =3D ARRAY_SIZE(aggre2_noc_nodes), .bcms =3D aggre2_noc_bcms, @@ -1602,6 +1541,7 @@ static struct qcom_icc_node * const clk_virt_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sm8450_clk_virt =3D { + .alloc_dyn_id =3D true, .nodes =3D clk_virt_nodes, .num_nodes =3D ARRAY_SIZE(clk_virt_nodes), .bcms =3D clk_virt_bcms, @@ -1671,6 +1611,7 @@ static struct qcom_icc_node * const config_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sm8450_config_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D config_noc_nodes, .num_nodes =3D ARRAY_SIZE(config_noc_nodes), .bcms =3D config_noc_bcms, @@ -1706,6 +1647,7 @@ static struct qcom_icc_node * const gem_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sm8450_gem_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D gem_noc_nodes, .num_nodes =3D ARRAY_SIZE(gem_noc_nodes), .bcms =3D gem_noc_bcms, @@ -1728,6 +1670,7 @@ static struct qcom_icc_node * const lpass_ag_noc_node= s[] =3D { }; =20 static const struct qcom_icc_desc sm8450_lpass_ag_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D lpass_ag_noc_nodes, .num_nodes =3D ARRAY_SIZE(lpass_ag_noc_nodes), .bcms =3D lpass_ag_noc_bcms, @@ -1749,6 +1692,7 @@ static struct qcom_icc_node * const mc_virt_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sm8450_mc_virt =3D { + .alloc_dyn_id =3D true, .nodes =3D mc_virt_nodes, .num_nodes =3D ARRAY_SIZE(mc_virt_nodes), .bcms =3D mc_virt_bcms, @@ -1784,6 +1728,7 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sm8450_mmss_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D mmss_noc_nodes, .num_nodes =3D ARRAY_SIZE(mmss_noc_nodes), .bcms =3D mmss_noc_bcms, @@ -1802,6 +1747,7 @@ static struct qcom_icc_node * const nsp_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sm8450_nsp_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D nsp_noc_nodes, .num_nodes =3D ARRAY_SIZE(nsp_noc_nodes), .bcms =3D nsp_noc_bcms, @@ -1821,6 +1767,7 @@ static struct qcom_icc_node * const pcie_anoc_nodes[]= =3D { }; =20 static const struct qcom_icc_desc sm8450_pcie_anoc =3D { + .alloc_dyn_id =3D true, .nodes =3D pcie_anoc_nodes, .num_nodes =3D ARRAY_SIZE(pcie_anoc_nodes), .bcms =3D pcie_anoc_bcms, @@ -1849,6 +1796,7 @@ static struct qcom_icc_node * const system_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sm8450_system_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D system_noc_nodes, .num_nodes =3D ARRAY_SIZE(system_noc_nodes), .bcms =3D system_noc_bcms, diff --git a/drivers/interconnect/qcom/sm8450.h b/drivers/interconnect/qcom= /sm8450.h deleted file mode 100644 index a5790ec6767b36e15997d838339d024007f9f7be..000000000000000000000000000= 0000000000000 --- a/drivers/interconnect/qcom/sm8450.h +++ /dev/null @@ -1,169 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * SM8450 interconnect IDs - * - * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2021, Linaro Limited - */ - -#ifndef __DRIVERS_INTERCONNECT_QCOM_SM8450_H -#define __DRIVERS_INTERCONNECT_QCOM_SM8450_H - -#define SM8450_MASTER_GPU_TCU 0 -#define SM8450_MASTER_SYS_TCU 1 -#define SM8450_MASTER_APPSS_PROC 2 -#define SM8450_MASTER_LLCC 3 -#define SM8450_MASTER_CNOC_LPASS_AG_NOC 4 -#define SM8450_MASTER_GIC_AHB 5 -#define SM8450_MASTER_CDSP_NOC_CFG 6 -#define SM8450_MASTER_QDSS_BAM 7 -#define SM8450_MASTER_QSPI_0 8 -#define SM8450_MASTER_QUP_0 9 -#define SM8450_MASTER_QUP_1 10 -#define SM8450_MASTER_QUP_2 11 -#define SM8450_MASTER_A1NOC_CFG 12 -#define SM8450_MASTER_A2NOC_CFG 13 -#define SM8450_MASTER_A1NOC_SNOC 14 -#define SM8450_MASTER_A2NOC_SNOC 15 -#define SM8450_MASTER_CAMNOC_HF 16 -#define SM8450_MASTER_CAMNOC_ICP 17 -#define SM8450_MASTER_CAMNOC_SF 18 -#define SM8450_MASTER_GEM_NOC_CNOC 19 -#define SM8450_MASTER_GEM_NOC_PCIE_SNOC 20 -#define SM8450_MASTER_GFX3D 21 -#define SM8450_MASTER_LPASS_ANOC 22 -#define SM8450_MASTER_MDP 23 -#define SM8450_MASTER_MDP0 SM8450_MASTER_MDP -#define SM8450_MASTER_MDP1 SM8450_MASTER_MDP -#define SM8450_MASTER_MSS_PROC 24 -#define SM8450_MASTER_CNOC_MNOC_CFG 25 -#define SM8450_MASTER_MNOC_HF_MEM_NOC 26 -#define SM8450_MASTER_MNOC_SF_MEM_NOC 27 -#define SM8450_MASTER_COMPUTE_NOC 28 -#define SM8450_MASTER_ANOC_PCIE_GEM_NOC 29 -#define SM8450_MASTER_PCIE_ANOC_CFG 30 -#define SM8450_MASTER_ROTATOR 31 -#define SM8450_MASTER_SNOC_CFG 32 -#define SM8450_MASTER_SNOC_GC_MEM_NOC 33 -#define SM8450_MASTER_SNOC_SF_MEM_NOC 34 -#define SM8450_MASTER_CDSP_HCP 35 -#define SM8450_MASTER_VIDEO 36 -#define SM8450_MASTER_VIDEO_P0 SM8450_MASTER_VIDEO -#define SM8450_MASTER_VIDEO_P1 SM8450_MASTER_VIDEO -#define SM8450_MASTER_VIDEO_CV_PROC 37 -#define SM8450_MASTER_VIDEO_PROC 38 -#define SM8450_MASTER_VIDEO_V_PROC 39 -#define SM8450_MASTER_QUP_CORE_0 40 -#define SM8450_MASTER_QUP_CORE_1 41 -#define SM8450_MASTER_QUP_CORE_2 42 -#define SM8450_MASTER_CRYPTO 43 -#define SM8450_MASTER_IPA 44 -#define SM8450_MASTER_LPASS_PROC 45 -#define SM8450_MASTER_CDSP_PROC 46 -#define SM8450_MASTER_PIMEM 47 -#define SM8450_MASTER_SENSORS_PROC 48 -#define SM8450_MASTER_SP 49 -#define SM8450_MASTER_GIC 50 -#define SM8450_MASTER_PCIE_0 51 -#define SM8450_MASTER_PCIE_1 52 -#define SM8450_MASTER_QDSS_ETR 53 -#define SM8450_MASTER_QDSS_ETR_1 54 -#define SM8450_MASTER_SDCC_2 55 -#define SM8450_MASTER_SDCC_4 56 -#define SM8450_MASTER_UFS_MEM 57 -#define SM8450_MASTER_USB3_0 58 -#define SM8450_SLAVE_EBI1 512 -#define SM8450_SLAVE_AHB2PHY_SOUTH 513 -#define SM8450_SLAVE_AHB2PHY_NORTH 514 -#define SM8450_SLAVE_AOSS 515 -#define SM8450_SLAVE_CAMERA_CFG 516 -#define SM8450_SLAVE_CLK_CTL 517 -#define SM8450_SLAVE_CDSP_CFG 518 -#define SM8450_SLAVE_RBCPR_CX_CFG 519 -#define SM8450_SLAVE_RBCPR_MMCX_CFG 520 -#define SM8450_SLAVE_RBCPR_MXA_CFG 521 -#define SM8450_SLAVE_RBCPR_MXC_CFG 522 -#define SM8450_SLAVE_CRYPTO_0_CFG 523 -#define SM8450_SLAVE_CX_RDPM 524 -#define SM8450_SLAVE_DISPLAY_CFG 525 -#define SM8450_SLAVE_GFX3D_CFG 526 -#define SM8450_SLAVE_IMEM_CFG 527 -#define SM8450_SLAVE_IPA_CFG 528 -#define SM8450_SLAVE_IPC_ROUTER_CFG 529 -#define SM8450_SLAVE_LPASS 530 -#define SM8450_SLAVE_LPASS_CORE_CFG 531 -#define SM8450_SLAVE_LPASS_LPI_CFG 532 -#define SM8450_SLAVE_LPASS_MPU_CFG 533 -#define SM8450_SLAVE_LPASS_TOP_CFG 534 -#define SM8450_SLAVE_CNOC_MSS 535 -#define SM8450_SLAVE_MX_RDPM 536 -#define SM8450_SLAVE_PCIE_0_CFG 537 -#define SM8450_SLAVE_PCIE_1_CFG 538 -#define SM8450_SLAVE_PDM 539 -#define SM8450_SLAVE_PIMEM_CFG 540 -#define SM8450_SLAVE_PRNG 541 -#define SM8450_SLAVE_QDSS_CFG 542 -#define SM8450_SLAVE_QSPI_0 543 -#define SM8450_SLAVE_QUP_0 544 -#define SM8450_SLAVE_QUP_1 545 -#define SM8450_SLAVE_QUP_2 546 -#define SM8450_SLAVE_SDCC_2 547 -#define SM8450_SLAVE_SDCC_4 548 -#define SM8450_SLAVE_SPSS_CFG 549 -#define SM8450_SLAVE_TCSR 550 -#define SM8450_SLAVE_TLMM 551 -#define SM8450_SLAVE_TME_CFG 552 -#define SM8450_SLAVE_UFS_MEM_CFG 553 -#define SM8450_SLAVE_USB3_0 554 -#define SM8450_SLAVE_VENUS_CFG 555 -#define SM8450_SLAVE_VSENSE_CTRL_CFG 556 -#define SM8450_SLAVE_A1NOC_CFG 557 -#define SM8450_SLAVE_A1NOC_SNOC 558 -#define SM8450_SLAVE_A2NOC_CFG 559 -#define SM8450_SLAVE_A2NOC_SNOC 560 -#define SM8450_SLAVE_DDRSS_CFG 561 -#define SM8450_SLAVE_GEM_NOC_CNOC 562 -#define SM8450_SLAVE_SNOC_GEM_NOC_GC 563 -#define SM8450_SLAVE_SNOC_GEM_NOC_SF 564 -#define SM8450_SLAVE_LLCC 565 -#define SM8450_SLAVE_MNOC_HF_MEM_NOC 566 -#define SM8450_SLAVE_MNOC_SF_MEM_NOC 567 -#define SM8450_SLAVE_CNOC_MNOC_CFG 568 -#define SM8450_SLAVE_CDSP_MEM_NOC 569 -#define SM8450_SLAVE_MEM_NOC_PCIE_SNOC 570 -#define SM8450_SLAVE_PCIE_ANOC_CFG 571 -#define SM8450_SLAVE_ANOC_PCIE_GEM_NOC 572 -#define SM8450_SLAVE_SNOC_CFG 573 -#define SM8450_SLAVE_LPASS_SNOC 574 -#define SM8450_SLAVE_QUP_CORE_0 575 -#define SM8450_SLAVE_QUP_CORE_1 576 -#define SM8450_SLAVE_QUP_CORE_2 577 -#define SM8450_SLAVE_IMEM 578 -#define SM8450_SLAVE_PIMEM 579 -#define SM8450_SLAVE_SERVICE_NSP_NOC 580 -#define SM8450_SLAVE_SERVICE_A1NOC 581 -#define SM8450_SLAVE_SERVICE_A2NOC 582 -#define SM8450_SLAVE_SERVICE_CNOC 583 -#define SM8450_SLAVE_SERVICE_MNOC 584 -#define SM8450_SLAVE_SERVICES_LPASS_AML_NOC 585 -#define SM8450_SLAVE_SERVICE_LPASS_AG_NOC 586 -#define SM8450_SLAVE_SERVICE_PCIE_ANOC 587 -#define SM8450_SLAVE_SERVICE_SNOC 588 -#define SM8450_SLAVE_PCIE_0 589 -#define SM8450_SLAVE_PCIE_1 590 -#define SM8450_SLAVE_QDSS_STM 591 -#define SM8450_SLAVE_TCU 592 -#define SM8450_MASTER_LLCC_DISP 1000 -#define SM8450_MASTER_MDP_DISP 1001 -#define SM8450_MASTER_MDP0_DISP SM8450_MASTER_MDP_DISP -#define SM8450_MASTER_MDP1_DISP SM8450_MASTER_MDP_DISP -#define SM8450_MASTER_MNOC_HF_MEM_NOC_DISP 1002 -#define SM8450_MASTER_MNOC_SF_MEM_NOC_DISP 1003 -#define SM8450_MASTER_ANOC_PCIE_GEM_NOC_DISP 1004 -#define SM8450_MASTER_ROTATOR_DISP 1005 -#define SM8450_SLAVE_EBI1_DISP 1512 -#define SM8450_SLAVE_LLCC_DISP 1513 -#define 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This gives more flexibility and also allows us to drop the .num_links member, saving from possible errors related to it being not set or set incorrectly. Tested-by: Neil Armstrong # on QRD8550 Signed-off-by: Dmitry Baryshkov --- drivers/interconnect/qcom/sm8550.c | 515 +++++++++++++++++----------------= ---- drivers/interconnect/qcom/sm8550.h | 138 ---------- 2 files changed, 237 insertions(+), 416 deletions(-) diff --git a/drivers/interconnect/qcom/sm8550.c b/drivers/interconnect/qcom= /sm8550.c index fdb97d1f1d074d17b55f10a5852ce80388b611b7..24b682a5bdd1873b4e3e655a9c8= 021e43987f008 100644 --- a/drivers/interconnect/qcom/sm8550.c +++ b/drivers/interconnect/qcom/sm8550.c @@ -18,1103 +18,1048 @@ #include "bcm-voter.h" #include "icc-common.h" #include "icc-rpmh.h" -#include "sm8550.h" + +static struct qcom_icc_node qhm_qspi; +static struct qcom_icc_node qhm_qup1; +static struct qcom_icc_node xm_sdc4; +static struct qcom_icc_node xm_ufs_mem; +static struct qcom_icc_node xm_usb3_0; +static struct qcom_icc_node qhm_qdss_bam; +static struct qcom_icc_node qhm_qup2; +static struct qcom_icc_node qxm_crypto; +static struct qcom_icc_node qxm_ipa; +static struct qcom_icc_node qxm_sp; +static struct qcom_icc_node xm_qdss_etr_0; +static struct qcom_icc_node xm_qdss_etr_1; +static struct qcom_icc_node xm_sdc2; +static struct qcom_icc_node qup0_core_master; +static struct qcom_icc_node qup1_core_master; +static struct qcom_icc_node qup2_core_master; +static struct qcom_icc_node qsm_cfg; +static struct qcom_icc_node qnm_gemnoc_cnoc; +static struct qcom_icc_node qnm_gemnoc_pcie; +static struct qcom_icc_node alm_gpu_tcu; +static struct qcom_icc_node alm_sys_tcu; +static struct qcom_icc_node chm_apps; +static struct qcom_icc_node qnm_gpu; +static struct qcom_icc_node qnm_lpass_gemnoc; +static struct qcom_icc_node qnm_mdsp; +static struct qcom_icc_node qnm_mnoc_hf; +static struct qcom_icc_node qnm_mnoc_sf; +static struct qcom_icc_node qnm_nsp_gemnoc; +static struct qcom_icc_node qnm_pcie; +static struct qcom_icc_node qnm_snoc_gc; +static struct qcom_icc_node qnm_snoc_sf; +static struct qcom_icc_node qnm_lpiaon_noc; +static struct qcom_icc_node qnm_lpass_lpinoc; +static struct qcom_icc_node qxm_lpinoc_dsp_axim; +static struct qcom_icc_node llcc_mc; +static struct qcom_icc_node qnm_camnoc_hf; +static struct qcom_icc_node qnm_camnoc_icp; +static struct qcom_icc_node qnm_camnoc_sf; +static struct qcom_icc_node qnm_mdp; +static struct qcom_icc_node qnm_vapss_hcp; +static struct qcom_icc_node qnm_video; +static struct qcom_icc_node qnm_video_cv_cpu; +static struct qcom_icc_node qnm_video_cvp; +static struct qcom_icc_node qnm_video_v_cpu; +static struct qcom_icc_node qsm_mnoc_cfg; +static struct qcom_icc_node qxm_nsp; +static struct qcom_icc_node qsm_pcie_anoc_cfg; +static struct qcom_icc_node xm_pcie3_0; +static struct qcom_icc_node xm_pcie3_1; +static struct qcom_icc_node qhm_gic; +static struct qcom_icc_node qnm_aggre1_noc; +static struct qcom_icc_node qnm_aggre2_noc; +static struct qcom_icc_node xm_gic; +static struct qcom_icc_node qns_a1noc_snoc; +static struct qcom_icc_node qns_a2noc_snoc; +static struct qcom_icc_node qup0_core_slave; +static struct qcom_icc_node qup1_core_slave; +static struct qcom_icc_node qup2_core_slave; +static struct qcom_icc_node qhs_ahb2phy0; +static struct qcom_icc_node qhs_ahb2phy1; +static struct qcom_icc_node qhs_apss; +static struct qcom_icc_node qhs_camera_cfg; +static struct qcom_icc_node qhs_clk_ctl; +static struct qcom_icc_node qhs_cpr_cx; +static struct qcom_icc_node qhs_cpr_mmcx; +static struct qcom_icc_node qhs_cpr_mxa; +static struct qcom_icc_node qhs_cpr_mxc; +static struct qcom_icc_node qhs_cpr_nspcx; +static struct qcom_icc_node qhs_crypto0_cfg; +static struct qcom_icc_node qhs_cx_rdpm; +static struct qcom_icc_node qhs_display_cfg; +static struct qcom_icc_node qhs_gpuss_cfg; +static struct qcom_icc_node qhs_i2c; +static struct qcom_icc_node qhs_imem_cfg; +static struct qcom_icc_node qhs_ipa; +static struct qcom_icc_node qhs_ipc_router; +static struct qcom_icc_node qhs_mss_cfg; +static struct qcom_icc_node qhs_mx_rdpm; +static struct qcom_icc_node qhs_pcie0_cfg; +static struct qcom_icc_node qhs_pcie1_cfg; +static struct qcom_icc_node qhs_pdm; +static struct qcom_icc_node qhs_pimem_cfg; +static struct qcom_icc_node qhs_prng; +static struct qcom_icc_node qhs_qdss_cfg; +static struct qcom_icc_node qhs_qspi; +static struct qcom_icc_node qhs_qup1; +static struct qcom_icc_node qhs_qup2; +static struct qcom_icc_node qhs_sdc2; +static struct qcom_icc_node qhs_sdc4; +static struct qcom_icc_node qhs_spss_cfg; +static struct qcom_icc_node qhs_tcsr; +static struct qcom_icc_node qhs_tlmm; +static struct qcom_icc_node qhs_ufs_mem_cfg; +static struct qcom_icc_node qhs_usb3_0; +static struct qcom_icc_node qhs_venus_cfg; +static struct qcom_icc_node qhs_vsense_ctrl_cfg; +static struct qcom_icc_node qss_lpass_qtb_cfg; +static struct qcom_icc_node qss_mnoc_cfg; +static struct qcom_icc_node qss_nsp_qtb_cfg; +static struct qcom_icc_node qss_pcie_anoc_cfg; +static struct qcom_icc_node xs_qdss_stm; +static struct qcom_icc_node xs_sys_tcu_cfg; +static struct qcom_icc_node qhs_aoss; +static struct qcom_icc_node qhs_tme_cfg; +static struct qcom_icc_node qss_cfg; +static struct qcom_icc_node qss_ddrss_cfg; +static struct qcom_icc_node qxs_boot_imem; +static struct qcom_icc_node qxs_imem; +static struct qcom_icc_node xs_pcie_0; +static struct qcom_icc_node xs_pcie_1; +static struct qcom_icc_node qns_gem_noc_cnoc; +static struct qcom_icc_node qns_llcc; +static struct qcom_icc_node qns_pcie; +static struct qcom_icc_node qns_lpass_ag_noc_gemnoc; +static struct qcom_icc_node qns_lpass_aggnoc; +static struct qcom_icc_node qns_lpi_aon_noc; +static struct qcom_icc_node ebi; +static struct qcom_icc_node qns_mem_noc_hf; +static struct qcom_icc_node qns_mem_noc_sf; +static struct qcom_icc_node srvc_mnoc; +static struct qcom_icc_node qns_nsp_gemnoc; +static struct qcom_icc_node qns_pcie_mem_noc; +static struct qcom_icc_node srvc_pcie_aggre_noc; +static struct qcom_icc_node qns_gemnoc_gc; +static struct qcom_icc_node qns_gemnoc_sf; =20 static struct qcom_icc_node qhm_qspi =3D { .name =3D "qhm_qspi", - .id =3D SM8550_MASTER_QSPI_0, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8550_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node qhm_qup1 =3D { .name =3D "qhm_qup1", - .id =3D SM8550_MASTER_QUP_1, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8550_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node xm_sdc4 =3D { .name =3D "xm_sdc4", - .id =3D SM8550_MASTER_SDCC_4, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8550_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node xm_ufs_mem =3D { .name =3D "xm_ufs_mem", - .id =3D SM8550_MASTER_UFS_MEM, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM8550_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node xm_usb3_0 =3D { .name =3D "xm_usb3_0", - .id =3D SM8550_MASTER_USB3_0, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8550_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node qhm_qdss_bam =3D { .name =3D "qhm_qdss_bam", - .id =3D SM8550_MASTER_QDSS_BAM, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8550_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qhm_qup2 =3D { .name =3D "qhm_qup2", - .id =3D SM8550_MASTER_QUP_2, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8550_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qxm_crypto =3D { .name =3D "qxm_crypto", - .id =3D SM8550_MASTER_CRYPTO, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8550_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qxm_ipa =3D { .name =3D "qxm_ipa", - .id =3D SM8550_MASTER_IPA, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8550_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qxm_sp =3D { .name =3D "qxm_sp", - .id =3D SM8550_MASTER_SP, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8550_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node xm_qdss_etr_0 =3D { .name =3D "xm_qdss_etr_0", - .id =3D SM8550_MASTER_QDSS_ETR, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8550_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node xm_qdss_etr_1 =3D { .name =3D "xm_qdss_etr_1", - .id =3D SM8550_MASTER_QDSS_ETR_1, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8550_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node xm_sdc2 =3D { .name =3D "xm_sdc2", - .id =3D SM8550_MASTER_SDCC_2, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8550_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qup0_core_master =3D { .name =3D "qup0_core_master", - .id =3D SM8550_MASTER_QUP_CORE_0, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8550_SLAVE_QUP_CORE_0 }, + .link_nodes =3D { &qup0_core_slave }, }; =20 static struct qcom_icc_node qup1_core_master =3D { .name =3D "qup1_core_master", - .id =3D SM8550_MASTER_QUP_CORE_1, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8550_SLAVE_QUP_CORE_1 }, + .link_nodes =3D { &qup1_core_slave }, }; =20 static struct qcom_icc_node qup2_core_master =3D { .name =3D "qup2_core_master", - .id =3D SM8550_MASTER_QUP_CORE_2, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8550_SLAVE_QUP_CORE_2 }, + .link_nodes =3D { &qup2_core_slave }, }; =20 static struct qcom_icc_node qsm_cfg =3D { .name =3D "qsm_cfg", - .id =3D SM8550_MASTER_CNOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 44, - .links =3D { SM8550_SLAVE_AHB2PHY_SOUTH, SM8550_SLAVE_AHB2PHY_NORTH, - SM8550_SLAVE_APPSS, SM8550_SLAVE_CAMERA_CFG, - SM8550_SLAVE_CLK_CTL, SM8550_SLAVE_RBCPR_CX_CFG, - SM8550_SLAVE_RBCPR_MMCX_CFG, SM8550_SLAVE_RBCPR_MXA_CFG, - SM8550_SLAVE_RBCPR_MXC_CFG, SM8550_SLAVE_CPR_NSPCX, - SM8550_SLAVE_CRYPTO_0_CFG, SM8550_SLAVE_CX_RDPM, - SM8550_SLAVE_DISPLAY_CFG, SM8550_SLAVE_GFX3D_CFG, - SM8550_SLAVE_I2C, SM8550_SLAVE_IMEM_CFG, - SM8550_SLAVE_IPA_CFG, SM8550_SLAVE_IPC_ROUTER_CFG, - SM8550_SLAVE_CNOC_MSS, SM8550_SLAVE_MX_RDPM, - SM8550_SLAVE_PCIE_0_CFG, SM8550_SLAVE_PCIE_1_CFG, - SM8550_SLAVE_PDM, SM8550_SLAVE_PIMEM_CFG, - SM8550_SLAVE_PRNG, SM8550_SLAVE_QDSS_CFG, - SM8550_SLAVE_QSPI_0, SM8550_SLAVE_QUP_1, - SM8550_SLAVE_QUP_2, SM8550_SLAVE_SDCC_2, - SM8550_SLAVE_SDCC_4, SM8550_SLAVE_SPSS_CFG, - SM8550_SLAVE_TCSR, SM8550_SLAVE_TLMM, - SM8550_SLAVE_UFS_MEM_CFG, SM8550_SLAVE_USB3_0, - SM8550_SLAVE_VENUS_CFG, SM8550_SLAVE_VSENSE_CTRL_CFG, - SM8550_SLAVE_LPASS_QTB_CFG, SM8550_SLAVE_CNOC_MNOC_CFG, - SM8550_SLAVE_NSP_QTB_CFG, SM8550_SLAVE_PCIE_ANOC_CFG, - SM8550_SLAVE_QDSS_STM, SM8550_SLAVE_TCU }, + .link_nodes =3D { &qhs_ahb2phy0, &qhs_ahb2phy1, + &qhs_apss, &qhs_camera_cfg, + &qhs_clk_ctl, &qhs_cpr_cx, + &qhs_cpr_mmcx, &qhs_cpr_mxa, + &qhs_cpr_mxc, &qhs_cpr_nspcx, + &qhs_crypto0_cfg, &qhs_cx_rdpm, + &qhs_display_cfg, &qhs_gpuss_cfg, + &qhs_i2c, &qhs_imem_cfg, + &qhs_ipa, &qhs_ipc_router, + &qhs_mss_cfg, &qhs_mx_rdpm, + &qhs_pcie0_cfg, &qhs_pcie1_cfg, + &qhs_pdm, &qhs_pimem_cfg, + &qhs_prng, &qhs_qdss_cfg, + &qhs_qspi, &qhs_qup1, + &qhs_qup2, &qhs_sdc2, + &qhs_sdc4, &qhs_spss_cfg, + &qhs_tcsr, &qhs_tlmm, + &qhs_ufs_mem_cfg, &qhs_usb3_0, + &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, + &qss_lpass_qtb_cfg, &qss_mnoc_cfg, + &qss_nsp_qtb_cfg, &qss_pcie_anoc_cfg, + &xs_qdss_stm, &xs_sys_tcu_cfg }, }; =20 static struct qcom_icc_node qnm_gemnoc_cnoc =3D { .name =3D "qnm_gemnoc_cnoc", - .id =3D SM8550_MASTER_GEM_NOC_CNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 6, - .links =3D { SM8550_SLAVE_AOSS, SM8550_SLAVE_TME_CFG, - SM8550_SLAVE_CNOC_CFG, SM8550_SLAVE_DDRSS_CFG, - SM8550_SLAVE_BOOT_IMEM, SM8550_SLAVE_IMEM }, + .link_nodes =3D { &qhs_aoss, &qhs_tme_cfg, + &qss_cfg, &qss_ddrss_cfg, + &qxs_boot_imem, &qxs_imem }, }; =20 static struct qcom_icc_node qnm_gemnoc_pcie =3D { .name =3D "qnm_gemnoc_pcie", - .id =3D SM8550_MASTER_GEM_NOC_PCIE_SNOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 2, - .links =3D { SM8550_SLAVE_PCIE_0, SM8550_SLAVE_PCIE_1 }, + .link_nodes =3D { &xs_pcie_0, &xs_pcie_1 }, }; =20 static struct qcom_icc_node alm_gpu_tcu =3D { .name =3D "alm_gpu_tcu", - .id =3D SM8550_MASTER_GPU_TCU, .channels =3D 1, .buswidth =3D 8, .num_links =3D 2, - .links =3D { SM8550_SLAVE_GEM_NOC_CNOC, SM8550_SLAVE_LLCC }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; =20 static struct qcom_icc_node alm_sys_tcu =3D { .name =3D "alm_sys_tcu", - .id =3D SM8550_MASTER_SYS_TCU, .channels =3D 1, .buswidth =3D 8, .num_links =3D 2, - .links =3D { SM8550_SLAVE_GEM_NOC_CNOC, SM8550_SLAVE_LLCC }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; =20 static struct qcom_icc_node chm_apps =3D { .name =3D "chm_apps", - .id =3D SM8550_MASTER_APPSS_PROC, .channels =3D 3, .buswidth =3D 32, .num_links =3D 3, - .links =3D { SM8550_SLAVE_GEM_NOC_CNOC, SM8550_SLAVE_LLCC, - SM8550_SLAVE_MEM_NOC_PCIE_SNOC }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, }; =20 static struct qcom_icc_node qnm_gpu =3D { .name =3D "qnm_gpu", - .id =3D SM8550_MASTER_GFX3D, .channels =3D 2, .buswidth =3D 32, .num_links =3D 2, - .links =3D { SM8550_SLAVE_GEM_NOC_CNOC, SM8550_SLAVE_LLCC }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; =20 static struct qcom_icc_node qnm_lpass_gemnoc =3D { .name =3D "qnm_lpass_gemnoc", - .id =3D SM8550_MASTER_LPASS_GEM_NOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 3, - .links =3D { SM8550_SLAVE_GEM_NOC_CNOC, SM8550_SLAVE_LLCC, - SM8550_SLAVE_MEM_NOC_PCIE_SNOC }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, }; =20 static struct qcom_icc_node qnm_mdsp =3D { .name =3D "qnm_mdsp", - .id =3D SM8550_MASTER_MSS_PROC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 3, - .links =3D { SM8550_SLAVE_GEM_NOC_CNOC, SM8550_SLAVE_LLCC, - SM8550_SLAVE_MEM_NOC_PCIE_SNOC }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, }; =20 static struct qcom_icc_node qnm_mnoc_hf =3D { .name =3D "qnm_mnoc_hf", - .id =3D SM8550_MASTER_MNOC_HF_MEM_NOC, .channels =3D 2, .buswidth =3D 32, .num_links =3D 2, - .links =3D { SM8550_SLAVE_GEM_NOC_CNOC, SM8550_SLAVE_LLCC }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; =20 static struct qcom_icc_node qnm_mnoc_sf =3D { .name =3D "qnm_mnoc_sf", - .id =3D SM8550_MASTER_MNOC_SF_MEM_NOC, .channels =3D 2, .buswidth =3D 32, .num_links =3D 2, - .links =3D { SM8550_SLAVE_GEM_NOC_CNOC, SM8550_SLAVE_LLCC }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; =20 static struct qcom_icc_node qnm_nsp_gemnoc =3D { .name =3D "qnm_nsp_gemnoc", - .id =3D SM8550_MASTER_COMPUTE_NOC, .channels =3D 2, .buswidth =3D 32, .num_links =3D 2, - .links =3D { SM8550_SLAVE_GEM_NOC_CNOC, SM8550_SLAVE_LLCC }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; =20 static struct qcom_icc_node qnm_pcie =3D { .name =3D "qnm_pcie", - .id =3D SM8550_MASTER_ANOC_PCIE_GEM_NOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 2, - .links =3D { SM8550_SLAVE_GEM_NOC_CNOC, SM8550_SLAVE_LLCC }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; =20 static struct qcom_icc_node qnm_snoc_gc =3D { .name =3D "qnm_snoc_gc", - .id =3D SM8550_MASTER_SNOC_GC_MEM_NOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8550_SLAVE_LLCC }, + .link_nodes =3D { &qns_llcc }, }; =20 static struct qcom_icc_node qnm_snoc_sf =3D { .name =3D "qnm_snoc_sf", - .id =3D SM8550_MASTER_SNOC_SF_MEM_NOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 3, - .links =3D { SM8550_SLAVE_GEM_NOC_CNOC, SM8550_SLAVE_LLCC, - SM8550_SLAVE_MEM_NOC_PCIE_SNOC }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, }; =20 static struct qcom_icc_node qnm_lpiaon_noc =3D { .name =3D "qnm_lpiaon_noc", - .id =3D SM8550_MASTER_LPIAON_NOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM8550_SLAVE_LPASS_GEM_NOC }, + .link_nodes =3D { &qns_lpass_ag_noc_gemnoc }, }; =20 static struct qcom_icc_node qnm_lpass_lpinoc =3D { .name =3D "qnm_lpass_lpinoc", - .id =3D SM8550_MASTER_LPASS_LPINOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM8550_SLAVE_LPIAON_NOC_LPASS_AG_NOC }, + .link_nodes =3D { &qns_lpass_aggnoc }, }; =20 static struct qcom_icc_node qxm_lpinoc_dsp_axim =3D { .name =3D "qxm_lpinoc_dsp_axim", - .id =3D SM8550_MASTER_LPASS_PROC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM8550_SLAVE_LPICX_NOC_LPIAON_NOC }, + .link_nodes =3D { &qns_lpi_aon_noc }, }; =20 static struct qcom_icc_node llcc_mc =3D { .name =3D "llcc_mc", - .id =3D SM8550_MASTER_LLCC, .channels =3D 4, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8550_SLAVE_EBI1 }, + .link_nodes =3D { &ebi }, }; =20 static struct qcom_icc_node qnm_camnoc_hf =3D { .name =3D "qnm_camnoc_hf", - .id =3D SM8550_MASTER_CAMNOC_HF, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8550_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_hf }, }; =20 static struct qcom_icc_node qnm_camnoc_icp =3D { .name =3D "qnm_camnoc_icp", - .id =3D SM8550_MASTER_CAMNOC_ICP, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8550_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static struct qcom_icc_node qnm_camnoc_sf =3D { .name =3D "qnm_camnoc_sf", - .id =3D SM8550_MASTER_CAMNOC_SF, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8550_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static struct qcom_icc_node qnm_mdp =3D { .name =3D "qnm_mdp", - .id =3D SM8550_MASTER_MDP, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8550_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_hf }, }; =20 static struct qcom_icc_node qnm_vapss_hcp =3D { .name =3D "qnm_vapss_hcp", - .id =3D SM8550_MASTER_CDSP_HCP, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8550_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static struct qcom_icc_node qnm_video =3D { .name =3D "qnm_video", - .id =3D SM8550_MASTER_VIDEO, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8550_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static struct qcom_icc_node qnm_video_cv_cpu =3D { .name =3D "qnm_video_cv_cpu", - .id =3D SM8550_MASTER_VIDEO_CV_PROC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8550_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static struct qcom_icc_node qnm_video_cvp =3D { .name =3D "qnm_video_cvp", - .id =3D SM8550_MASTER_VIDEO_PROC, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8550_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static struct qcom_icc_node qnm_video_v_cpu =3D { .name =3D "qnm_video_v_cpu", - .id =3D SM8550_MASTER_VIDEO_V_PROC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8550_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static struct qcom_icc_node qsm_mnoc_cfg =3D { .name =3D "qsm_mnoc_cfg", - .id =3D SM8550_MASTER_CNOC_MNOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8550_SLAVE_SERVICE_MNOC }, + .link_nodes =3D { &srvc_mnoc }, }; =20 static struct qcom_icc_node qxm_nsp =3D { .name =3D "qxm_nsp", - .id =3D SM8550_MASTER_CDSP_PROC, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8550_SLAVE_CDSP_MEM_NOC }, + .link_nodes =3D { &qns_nsp_gemnoc }, }; =20 static struct qcom_icc_node qsm_pcie_anoc_cfg =3D { .name =3D "qsm_pcie_anoc_cfg", - .id =3D SM8550_MASTER_PCIE_ANOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8550_SLAVE_SERVICE_PCIE_ANOC }, + .link_nodes =3D { &srvc_pcie_aggre_noc }, }; =20 static struct qcom_icc_node xm_pcie3_0 =3D { .name =3D "xm_pcie3_0", - .id =3D SM8550_MASTER_PCIE_0, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8550_SLAVE_ANOC_PCIE_GEM_NOC }, + .link_nodes =3D { &qns_pcie_mem_noc }, }; =20 static struct qcom_icc_node xm_pcie3_1 =3D { .name =3D "xm_pcie3_1", - .id =3D SM8550_MASTER_PCIE_1, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM8550_SLAVE_ANOC_PCIE_GEM_NOC }, + .link_nodes =3D { &qns_pcie_mem_noc }, }; =20 static struct qcom_icc_node qhm_gic =3D { .name =3D "qhm_gic", - .id =3D SM8550_MASTER_GIC_AHB, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8550_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes =3D { &qns_gemnoc_sf }, }; =20 static struct qcom_icc_node qnm_aggre1_noc =3D { .name =3D "qnm_aggre1_noc", - .id =3D SM8550_MASTER_A1NOC_SNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM8550_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes =3D { &qns_gemnoc_sf }, }; =20 static struct qcom_icc_node qnm_aggre2_noc =3D { .name =3D "qnm_aggre2_noc", - .id =3D SM8550_MASTER_A2NOC_SNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM8550_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes =3D { &qns_gemnoc_sf }, }; =20 static struct qcom_icc_node xm_gic =3D { .name =3D "xm_gic", - .id =3D SM8550_MASTER_GIC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8550_SLAVE_SNOC_GEM_NOC_GC }, + .link_nodes =3D { &qns_gemnoc_gc }, }; =20 static struct qcom_icc_node qns_a1noc_snoc =3D { .name =3D "qns_a1noc_snoc", - .id =3D SM8550_SLAVE_A1NOC_SNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM8550_MASTER_A1NOC_SNOC }, + .link_nodes =3D { &qnm_aggre1_noc }, }; =20 static struct qcom_icc_node qns_a2noc_snoc =3D { .name =3D "qns_a2noc_snoc", - .id =3D SM8550_SLAVE_A2NOC_SNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM8550_MASTER_A2NOC_SNOC }, + .link_nodes =3D { &qnm_aggre2_noc }, }; =20 static struct qcom_icc_node qup0_core_slave =3D { .name =3D "qup0_core_slave", - .id =3D SM8550_SLAVE_QUP_CORE_0, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qup1_core_slave =3D { .name =3D "qup1_core_slave", - .id =3D SM8550_SLAVE_QUP_CORE_1, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qup2_core_slave =3D { .name =3D "qup2_core_slave", - .id =3D SM8550_SLAVE_QUP_CORE_2, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_ahb2phy0 =3D { .name =3D "qhs_ahb2phy0", - .id =3D SM8550_SLAVE_AHB2PHY_SOUTH, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_ahb2phy1 =3D { .name =3D "qhs_ahb2phy1", - .id =3D SM8550_SLAVE_AHB2PHY_NORTH, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_apss =3D { .name =3D "qhs_apss", - .id =3D SM8550_SLAVE_APPSS, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_camera_cfg =3D { .name =3D "qhs_camera_cfg", - .id =3D SM8550_SLAVE_CAMERA_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_clk_ctl =3D { .name =3D "qhs_clk_ctl", - .id =3D SM8550_SLAVE_CLK_CTL, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_cpr_cx =3D { .name =3D "qhs_cpr_cx", - .id =3D SM8550_SLAVE_RBCPR_CX_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_cpr_mmcx =3D { .name =3D "qhs_cpr_mmcx", - .id =3D SM8550_SLAVE_RBCPR_MMCX_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_cpr_mxa =3D { .name =3D "qhs_cpr_mxa", - .id =3D SM8550_SLAVE_RBCPR_MXA_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_cpr_mxc =3D { .name =3D "qhs_cpr_mxc", - .id =3D SM8550_SLAVE_RBCPR_MXC_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_cpr_nspcx =3D { .name =3D "qhs_cpr_nspcx", - .id =3D SM8550_SLAVE_CPR_NSPCX, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_crypto0_cfg =3D { .name =3D "qhs_crypto0_cfg", - .id =3D SM8550_SLAVE_CRYPTO_0_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_cx_rdpm =3D { .name =3D "qhs_cx_rdpm", - .id =3D SM8550_SLAVE_CX_RDPM, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_display_cfg =3D { .name =3D "qhs_display_cfg", - .id =3D SM8550_SLAVE_DISPLAY_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_gpuss_cfg =3D { .name =3D "qhs_gpuss_cfg", - .id =3D SM8550_SLAVE_GFX3D_CFG, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_i2c =3D { .name =3D "qhs_i2c", - .id =3D SM8550_SLAVE_I2C, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_imem_cfg =3D { .name =3D "qhs_imem_cfg", - .id =3D SM8550_SLAVE_IMEM_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_ipa =3D { .name =3D "qhs_ipa", - .id =3D SM8550_SLAVE_IPA_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_ipc_router =3D { .name =3D "qhs_ipc_router", - .id =3D SM8550_SLAVE_IPC_ROUTER_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_mss_cfg =3D { .name =3D "qhs_mss_cfg", - .id =3D SM8550_SLAVE_CNOC_MSS, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_mx_rdpm =3D { .name =3D "qhs_mx_rdpm", - .id =3D SM8550_SLAVE_MX_RDPM, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_pcie0_cfg =3D { .name =3D "qhs_pcie0_cfg", - .id =3D SM8550_SLAVE_PCIE_0_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_pcie1_cfg =3D { .name =3D "qhs_pcie1_cfg", - .id =3D SM8550_SLAVE_PCIE_1_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_pdm =3D { .name =3D "qhs_pdm", - .id =3D SM8550_SLAVE_PDM, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_pimem_cfg =3D { .name =3D "qhs_pimem_cfg", - .id =3D SM8550_SLAVE_PIMEM_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_prng =3D { .name =3D "qhs_prng", - .id =3D SM8550_SLAVE_PRNG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_qdss_cfg =3D { .name =3D "qhs_qdss_cfg", - .id =3D SM8550_SLAVE_QDSS_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_qspi =3D { .name =3D "qhs_qspi", - .id =3D SM8550_SLAVE_QSPI_0, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_qup1 =3D { .name =3D "qhs_qup1", - .id =3D SM8550_SLAVE_QUP_1, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_qup2 =3D { .name =3D "qhs_qup2", - .id =3D SM8550_SLAVE_QUP_2, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_sdc2 =3D { .name =3D "qhs_sdc2", - .id =3D SM8550_SLAVE_SDCC_2, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_sdc4 =3D { .name =3D "qhs_sdc4", - .id =3D SM8550_SLAVE_SDCC_4, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_spss_cfg =3D { .name =3D "qhs_spss_cfg", - .id =3D SM8550_SLAVE_SPSS_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_tcsr =3D { .name =3D "qhs_tcsr", - .id =3D SM8550_SLAVE_TCSR, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_tlmm =3D { .name =3D "qhs_tlmm", - .id =3D SM8550_SLAVE_TLMM, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_ufs_mem_cfg =3D { .name =3D "qhs_ufs_mem_cfg", - .id =3D SM8550_SLAVE_UFS_MEM_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_usb3_0 =3D { .name =3D "qhs_usb3_0", - .id =3D SM8550_SLAVE_USB3_0, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_venus_cfg =3D { .name =3D "qhs_venus_cfg", - .id =3D SM8550_SLAVE_VENUS_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_vsense_ctrl_cfg =3D { .name =3D "qhs_vsense_ctrl_cfg", - .id =3D SM8550_SLAVE_VSENSE_CTRL_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qss_lpass_qtb_cfg =3D { .name =3D "qss_lpass_qtb_cfg", - .id =3D SM8550_SLAVE_LPASS_QTB_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qss_mnoc_cfg =3D { .name =3D "qss_mnoc_cfg", - .id =3D SM8550_SLAVE_CNOC_MNOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8550_MASTER_CNOC_MNOC_CFG }, + .link_nodes =3D { &qsm_mnoc_cfg }, }; =20 static struct qcom_icc_node qss_nsp_qtb_cfg =3D { .name =3D "qss_nsp_qtb_cfg", - .id =3D SM8550_SLAVE_NSP_QTB_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qss_pcie_anoc_cfg =3D { .name =3D "qss_pcie_anoc_cfg", - .id =3D SM8550_SLAVE_PCIE_ANOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8550_MASTER_PCIE_ANOC_CFG }, + .link_nodes =3D { &qsm_pcie_anoc_cfg }, }; =20 static struct qcom_icc_node xs_qdss_stm =3D { .name =3D "xs_qdss_stm", - .id =3D SM8550_SLAVE_QDSS_STM, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node xs_sys_tcu_cfg =3D { .name =3D "xs_sys_tcu_cfg", - .id =3D SM8550_SLAVE_TCU, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_aoss =3D { .name =3D "qhs_aoss", - .id =3D SM8550_SLAVE_AOSS, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_tme_cfg =3D { .name =3D "qhs_tme_cfg", - .id =3D SM8550_SLAVE_TME_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qss_cfg =3D { .name =3D "qss_cfg", - .id =3D SM8550_SLAVE_CNOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8550_MASTER_CNOC_CFG }, + .link_nodes =3D { &qsm_cfg }, }; =20 static struct qcom_icc_node qss_ddrss_cfg =3D { .name =3D "qss_ddrss_cfg", - .id =3D SM8550_SLAVE_DDRSS_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qxs_boot_imem =3D { .name =3D "qxs_boot_imem", - .id =3D SM8550_SLAVE_BOOT_IMEM, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 0, }; =20 static struct qcom_icc_node qxs_imem =3D { .name =3D "qxs_imem", - .id =3D SM8550_SLAVE_IMEM, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 0, }; =20 static struct qcom_icc_node xs_pcie_0 =3D { .name =3D "xs_pcie_0", - .id =3D SM8550_SLAVE_PCIE_0, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 0, }; =20 static struct qcom_icc_node xs_pcie_1 =3D { .name =3D "xs_pcie_1", - .id =3D SM8550_SLAVE_PCIE_1, .channels =3D 1, .buswidth =3D 16, - .num_links =3D 0, }; =20 static struct qcom_icc_node qns_gem_noc_cnoc =3D { .name =3D "qns_gem_noc_cnoc", - .id =3D SM8550_SLAVE_GEM_NOC_CNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM8550_MASTER_GEM_NOC_CNOC }, + .link_nodes =3D { &qnm_gemnoc_cnoc }, }; =20 static struct qcom_icc_node qns_llcc =3D { .name =3D "qns_llcc", - .id =3D SM8550_SLAVE_LLCC, .channels =3D 4, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM8550_MASTER_LLCC }, + .link_nodes =3D { &llcc_mc }, }; =20 static struct qcom_icc_node qns_pcie =3D { .name =3D "qns_pcie", - .id =3D SM8550_SLAVE_MEM_NOC_PCIE_SNOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8550_MASTER_GEM_NOC_PCIE_SNOC }, + .link_nodes =3D { &qnm_gemnoc_pcie }, }; =20 static struct qcom_icc_node qns_lpass_ag_noc_gemnoc =3D { .name =3D "qns_lpass_ag_noc_gemnoc", - .id =3D SM8550_SLAVE_LPASS_GEM_NOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM8550_MASTER_LPASS_GEM_NOC }, + .link_nodes =3D { &qnm_lpass_gemnoc }, }; =20 static struct qcom_icc_node qns_lpass_aggnoc =3D { .name =3D "qns_lpass_aggnoc", - .id =3D SM8550_SLAVE_LPIAON_NOC_LPASS_AG_NOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM8550_MASTER_LPIAON_NOC }, + .link_nodes =3D { &qnm_lpiaon_noc }, }; =20 static struct qcom_icc_node qns_lpi_aon_noc =3D { .name =3D "qns_lpi_aon_noc", - .id =3D SM8550_SLAVE_LPICX_NOC_LPIAON_NOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM8550_MASTER_LPASS_LPINOC }, + .link_nodes =3D { &qnm_lpass_lpinoc }, }; =20 static struct qcom_icc_node ebi =3D { .name =3D "ebi", - .id =3D SM8550_SLAVE_EBI1, .channels =3D 4, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qns_mem_noc_hf =3D { .name =3D "qns_mem_noc_hf", - .id =3D SM8550_SLAVE_MNOC_HF_MEM_NOC, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8550_MASTER_MNOC_HF_MEM_NOC }, + .link_nodes =3D { &qnm_mnoc_hf }, }; =20 static struct qcom_icc_node qns_mem_noc_sf =3D { .name =3D "qns_mem_noc_sf", - .id =3D SM8550_SLAVE_MNOC_SF_MEM_NOC, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8550_MASTER_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qnm_mnoc_sf }, }; =20 static struct qcom_icc_node srvc_mnoc =3D { .name =3D "srvc_mnoc", - .id =3D SM8550_SLAVE_SERVICE_MNOC, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qns_nsp_gemnoc =3D { .name =3D "qns_nsp_gemnoc", - .id =3D SM8550_SLAVE_CDSP_MEM_NOC, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8550_MASTER_COMPUTE_NOC }, + .link_nodes =3D { &qnm_nsp_gemnoc }, }; =20 static struct qcom_icc_node qns_pcie_mem_noc =3D { .name =3D "qns_pcie_mem_noc", - .id =3D SM8550_SLAVE_ANOC_PCIE_GEM_NOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM8550_MASTER_ANOC_PCIE_GEM_NOC }, + .link_nodes =3D { &qnm_pcie }, }; =20 static struct qcom_icc_node srvc_pcie_aggre_noc =3D { .name =3D "srvc_pcie_aggre_noc", - .id =3D SM8550_SLAVE_SERVICE_PCIE_ANOC, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qns_gemnoc_gc =3D { .name =3D "qns_gemnoc_gc", - .id =3D SM8550_SLAVE_SNOC_GEM_NOC_GC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8550_MASTER_SNOC_GC_MEM_NOC }, + .link_nodes =3D { &qnm_snoc_gc }, }; =20 static struct qcom_icc_node qns_gemnoc_sf =3D { .name =3D "qns_gemnoc_sf", - .id =3D SM8550_SLAVE_SNOC_GEM_NOC_SF, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM8550_MASTER_SNOC_SF_MEM_NOC }, + .link_nodes =3D { &qnm_snoc_sf }, }; =20 static struct qcom_icc_bcm bcm_acv =3D { @@ -1296,6 +1241,7 @@ static struct qcom_icc_node * const aggre1_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sm8550_aggre1_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D aggre1_noc_nodes, .num_nodes =3D ARRAY_SIZE(aggre1_noc_nodes), .bcms =3D aggre1_noc_bcms, @@ -1319,6 +1265,7 @@ static struct qcom_icc_node * const aggre2_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sm8550_aggre2_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D aggre2_noc_nodes, .num_nodes =3D ARRAY_SIZE(aggre2_noc_nodes), .bcms =3D aggre2_noc_bcms, @@ -1341,6 +1288,7 @@ static struct qcom_icc_node * const clk_virt_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sm8550_clk_virt =3D { + .alloc_dyn_id =3D true, .nodes =3D clk_virt_nodes, .num_nodes =3D ARRAY_SIZE(clk_virt_nodes), .bcms =3D clk_virt_bcms, @@ -1401,6 +1349,7 @@ static struct qcom_icc_node * const config_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sm8550_config_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D config_noc_nodes, .num_nodes =3D ARRAY_SIZE(config_noc_nodes), .bcms =3D config_noc_bcms, @@ -1425,6 +1374,7 @@ static struct qcom_icc_node * const cnoc_main_nodes[]= =3D { }; =20 static const struct qcom_icc_desc sm8550_cnoc_main =3D { + .alloc_dyn_id =3D true, .nodes =3D cnoc_main_nodes, .num_nodes =3D ARRAY_SIZE(cnoc_main_nodes), .bcms =3D cnoc_main_bcms, @@ -1455,6 +1405,7 @@ static struct qcom_icc_node * const gem_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sm8550_gem_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D gem_noc_nodes, .num_nodes =3D ARRAY_SIZE(gem_noc_nodes), .bcms =3D gem_noc_bcms, @@ -1470,6 +1421,7 @@ static struct qcom_icc_node * const lpass_ag_noc_node= s[] =3D { }; =20 static const struct qcom_icc_desc sm8550_lpass_ag_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D lpass_ag_noc_nodes, .num_nodes =3D ARRAY_SIZE(lpass_ag_noc_nodes), .bcms =3D lpass_ag_noc_bcms, @@ -1486,6 +1438,7 @@ static struct qcom_icc_node * const lpass_lpiaon_noc_= nodes[] =3D { }; =20 static const struct qcom_icc_desc sm8550_lpass_lpiaon_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D lpass_lpiaon_noc_nodes, .num_nodes =3D ARRAY_SIZE(lpass_lpiaon_noc_nodes), .bcms =3D lpass_lpiaon_noc_bcms, @@ -1501,6 +1454,7 @@ static struct qcom_icc_node * const lpass_lpicx_noc_n= odes[] =3D { }; =20 static const struct qcom_icc_desc sm8550_lpass_lpicx_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D lpass_lpicx_noc_nodes, .num_nodes =3D ARRAY_SIZE(lpass_lpicx_noc_nodes), .bcms =3D lpass_lpicx_noc_bcms, @@ -1518,6 +1472,7 @@ static struct qcom_icc_node * const mc_virt_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sm8550_mc_virt =3D { + .alloc_dyn_id =3D true, .nodes =3D mc_virt_nodes, .num_nodes =3D ARRAY_SIZE(mc_virt_nodes), .bcms =3D mc_virt_bcms, @@ -1546,6 +1501,7 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sm8550_mmss_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D mmss_noc_nodes, .num_nodes =3D ARRAY_SIZE(mmss_noc_nodes), .bcms =3D mmss_noc_bcms, @@ -1562,6 +1518,7 @@ static struct qcom_icc_node * const nsp_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sm8550_nsp_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D nsp_noc_nodes, .num_nodes =3D ARRAY_SIZE(nsp_noc_nodes), .bcms =3D nsp_noc_bcms, @@ -1581,6 +1538,7 @@ static struct qcom_icc_node * const pcie_anoc_nodes[]= =3D { }; =20 static const struct qcom_icc_desc sm8550_pcie_anoc =3D { + .alloc_dyn_id =3D true, .nodes =3D pcie_anoc_nodes, .num_nodes =3D ARRAY_SIZE(pcie_anoc_nodes), .bcms =3D pcie_anoc_bcms, @@ -1604,6 +1562,7 @@ static struct qcom_icc_node * const system_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sm8550_system_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D system_noc_nodes, .num_nodes =3D ARRAY_SIZE(system_noc_nodes), .bcms =3D system_noc_bcms, diff --git a/drivers/interconnect/qcom/sm8550.h b/drivers/interconnect/qcom= /sm8550.h deleted file mode 100644 index c9b2986e129337c8b8e0dec208b950bea20d213f..000000000000000000000000000= 0000000000000 --- a/drivers/interconnect/qcom/sm8550.h +++ /dev/null @@ -1,138 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * SM8450 interconnect IDs - * - * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2021, Linaro Limited - */ - -#ifndef __DRIVERS_INTERCONNECT_QCOM_SM8450_H -#define __DRIVERS_INTERCONNECT_QCOM_SM8450_H - -#define SM8550_MASTER_A1NOC_SNOC 0 -#define SM8550_MASTER_A2NOC_SNOC 1 -#define SM8550_MASTER_ANOC_PCIE_GEM_NOC 2 -#define SM8550_MASTER_APPSS_PROC 3 -#define SM8550_MASTER_CAMNOC_HF 4 -#define SM8550_MASTER_CAMNOC_ICP 5 -#define SM8550_MASTER_CAMNOC_SF 6 -#define SM8550_MASTER_CDSP_HCP 7 -#define SM8550_MASTER_CDSP_PROC 8 -#define SM8550_MASTER_CNOC_CFG 9 -#define SM8550_MASTER_CNOC_MNOC_CFG 10 -#define SM8550_MASTER_COMPUTE_NOC 11 -#define SM8550_MASTER_CRYPTO 12 -#define SM8550_MASTER_GEM_NOC_CNOC 13 -#define SM8550_MASTER_GEM_NOC_PCIE_SNOC 14 -#define SM8550_MASTER_GFX3D 15 -#define SM8550_MASTER_GIC 16 -#define SM8550_MASTER_GIC_AHB 17 -#define SM8550_MASTER_GPU_TCU 18 -#define SM8550_MASTER_IPA 19 -#define SM8550_MASTER_LLCC 20 -#define SM8550_MASTER_LPASS_GEM_NOC 21 -#define SM8550_MASTER_LPASS_LPINOC 22 -#define SM8550_MASTER_LPASS_PROC 23 -#define SM8550_MASTER_LPIAON_NOC 24 -#define SM8550_MASTER_MDP 25 -#define SM8550_MASTER_MNOC_HF_MEM_NOC 26 -#define SM8550_MASTER_MNOC_SF_MEM_NOC 27 -#define SM8550_MASTER_MSS_PROC 28 -#define SM8550_MASTER_PCIE_0 29 -#define SM8550_MASTER_PCIE_1 30 -#define SM8550_MASTER_PCIE_ANOC_CFG 31 -#define SM8550_MASTER_QDSS_BAM 32 -#define SM8550_MASTER_QDSS_ETR 33 -#define SM8550_MASTER_QDSS_ETR_1 34 -#define SM8550_MASTER_QSPI_0 35 -#define SM8550_MASTER_QUP_1 36 -#define SM8550_MASTER_QUP_2 37 -#define SM8550_MASTER_QUP_CORE_0 38 -#define SM8550_MASTER_QUP_CORE_1 39 -#define SM8550_MASTER_QUP_CORE_2 40 -#define SM8550_MASTER_SDCC_2 41 -#define SM8550_MASTER_SDCC_4 42 -#define SM8550_MASTER_SNOC_GC_MEM_NOC 43 -#define SM8550_MASTER_SNOC_SF_MEM_NOC 44 -#define SM8550_MASTER_SP 45 -#define SM8550_MASTER_SYS_TCU 46 -#define SM8550_MASTER_UFS_MEM 47 -#define SM8550_MASTER_USB3_0 48 -#define SM8550_MASTER_VIDEO 49 -#define SM8550_MASTER_VIDEO_CV_PROC 50 -#define SM8550_MASTER_VIDEO_PROC 51 -#define SM8550_MASTER_VIDEO_V_PROC 52 -#define SM8550_SLAVE_A1NOC_SNOC 53 -#define SM8550_SLAVE_A2NOC_SNOC 54 -#define SM8550_SLAVE_AHB2PHY_NORTH 55 -#define SM8550_SLAVE_AHB2PHY_SOUTH 56 -#define SM8550_SLAVE_ANOC_PCIE_GEM_NOC 57 -#define SM8550_SLAVE_AOSS 58 -#define SM8550_SLAVE_APPSS 59 -#define SM8550_SLAVE_BOOT_IMEM 60 -#define SM8550_SLAVE_CAMERA_CFG 61 -#define SM8550_SLAVE_CDSP_MEM_NOC 62 -#define SM8550_SLAVE_CLK_CTL 63 -#define SM8550_SLAVE_CNOC_CFG 64 -#define SM8550_SLAVE_CNOC_MNOC_CFG 65 -#define SM8550_SLAVE_CNOC_MSS 66 -#define SM8550_SLAVE_CPR_NSPCX 67 -#define SM8550_SLAVE_CRYPTO_0_CFG 68 -#define SM8550_SLAVE_CX_RDPM 69 -#define SM8550_SLAVE_DDRSS_CFG 70 -#define SM8550_SLAVE_DISPLAY_CFG 71 -#define SM8550_SLAVE_EBI1 72 -#define SM8550_SLAVE_GEM_NOC_CNOC 73 -#define SM8550_SLAVE_GFX3D_CFG 74 -#define SM8550_SLAVE_I2C 75 -#define SM8550_SLAVE_IMEM 76 -#define SM8550_SLAVE_IMEM_CFG 77 -#define SM8550_SLAVE_IPA_CFG 78 -#define SM8550_SLAVE_IPC_ROUTER_CFG 79 -#define SM8550_SLAVE_LLCC 80 -#define SM8550_SLAVE_LPASS_GEM_NOC 81 -#define SM8550_SLAVE_LPASS_QTB_CFG 82 -#define SM8550_SLAVE_LPIAON_NOC_LPASS_AG_NOC 83 -#define SM8550_SLAVE_LPICX_NOC_LPIAON_NOC 84 -#define SM8550_SLAVE_MEM_NOC_PCIE_SNOC 85 -#define SM8550_SLAVE_MNOC_HF_MEM_NOC 86 -#define SM8550_SLAVE_MNOC_SF_MEM_NOC 87 -#define SM8550_SLAVE_MX_RDPM 88 -#define SM8550_SLAVE_NSP_QTB_CFG 89 -#define SM8550_SLAVE_PCIE_0 90 -#define SM8550_SLAVE_PCIE_0_CFG 91 -#define SM8550_SLAVE_PCIE_1 92 -#define SM8550_SLAVE_PCIE_1_CFG 93 -#define SM8550_SLAVE_PCIE_ANOC_CFG 94 -#define SM8550_SLAVE_PDM 95 -#define SM8550_SLAVE_PIMEM_CFG 96 -#define SM8550_SLAVE_PRNG 97 -#define SM8550_SLAVE_QDSS_CFG 98 -#define SM8550_SLAVE_QDSS_STM 99 -#define SM8550_SLAVE_QSPI_0 100 -#define SM8550_SLAVE_QUP_1 101 -#define SM8550_SLAVE_QUP_2 102 -#define SM8550_SLAVE_QUP_CORE_0 103 -#define SM8550_SLAVE_QUP_CORE_1 104 -#define SM8550_SLAVE_QUP_CORE_2 105 -#define SM8550_SLAVE_RBCPR_CX_CFG 106 -#define SM8550_SLAVE_RBCPR_MMCX_CFG 107 -#define SM8550_SLAVE_RBCPR_MXA_CFG 108 -#define SM8550_SLAVE_RBCPR_MXC_CFG 109 -#define SM8550_SLAVE_SDCC_2 110 -#define SM8550_SLAVE_SDCC_4 111 -#define SM8550_SLAVE_SERVICE_MNOC 112 -#define SM8550_SLAVE_SERVICE_PCIE_ANOC 113 -#define SM8550_SLAVE_SNOC_GEM_NOC_GC 114 -#define SM8550_SLAVE_SNOC_GEM_NOC_SF 115 -#define SM8550_SLAVE_SPSS_CFG 116 -#define SM8550_SLAVE_TCSR 117 -#define SM8550_SLAVE_TCU 118 -#define SM8550_SLAVE_TLMM 119 -#define SM8550_SLAVE_TME_CFG 120 -#define SM8550_SLAVE_UFS_MEM_CFG 121 -#define SM8550_SLAVE_USB3_0 122 -#define SM8550_SLAVE_VENUS_CFG 123 -#define SM8550_SLAVE_VSENSE_CTRL_CFG 124 - -#endif --=20 2.47.3 From nobody Mon Feb 9 06:05:00 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D71212D0611 for ; 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This gives more flexibility and also allows us to drop the .num_links member, saving from possible errors related to it being not set or set incorrectly. Tested-by: Neil Armstrong # on QRD8650 Signed-off-by: Dmitry Baryshkov --- drivers/interconnect/qcom/sm8650.c | 541 +++++++++++++++++----------------= ---- drivers/interconnect/qcom/sm8650.h | 144 ---------- 2 files changed, 247 insertions(+), 438 deletions(-) diff --git a/drivers/interconnect/qcom/sm8650.c b/drivers/interconnect/qcom= /sm8650.c index b7c321f4e4b51cbcb138e906e561325393e3e14e..629ff30e7ee70567beb4c9bd21b= 9b91f53b39526 100644 --- a/drivers/interconnect/qcom/sm8650.c +++ b/drivers/interconnect/qcom/sm8650.c @@ -15,8 +15,138 @@ #include "bcm-voter.h" #include "icc-common.h" #include "icc-rpmh.h" -#include "sm8650.h" =20 +static struct qcom_icc_node qhm_qspi; +static struct qcom_icc_node qhm_qup1; +static struct qcom_icc_node qxm_qup02; +static struct qcom_icc_node xm_sdc4; +static struct qcom_icc_node xm_ufs_mem; +static struct qcom_icc_node xm_usb3_0; +static struct qcom_icc_node qhm_qdss_bam; +static struct qcom_icc_node qhm_qup2; +static struct qcom_icc_node qxm_crypto; +static struct qcom_icc_node qxm_ipa; +static struct qcom_icc_node qxm_sp; +static struct qcom_icc_node xm_qdss_etr_0; +static struct qcom_icc_node xm_qdss_etr_1; +static struct qcom_icc_node xm_sdc2; +static struct qcom_icc_node qup0_core_master; +static struct qcom_icc_node qup1_core_master; +static struct qcom_icc_node qup2_core_master; +static struct qcom_icc_node qsm_cfg; +static struct qcom_icc_node qnm_gemnoc_cnoc; +static struct qcom_icc_node qnm_gemnoc_pcie; +static struct qcom_icc_node alm_gpu_tcu; +static struct qcom_icc_node alm_sys_tcu; +static struct qcom_icc_node alm_ubwc_p_tcu; +static struct qcom_icc_node chm_apps; +static struct qcom_icc_node qnm_gpu; +static struct qcom_icc_node qnm_lpass_gemnoc; +static struct qcom_icc_node qnm_mdsp; +static struct qcom_icc_node qnm_mnoc_hf; +static struct qcom_icc_node qnm_mnoc_sf; +static struct qcom_icc_node qnm_nsp_gemnoc; +static struct qcom_icc_node qnm_pcie; +static struct qcom_icc_node qnm_snoc_sf; +static struct qcom_icc_node qnm_ubwc_p; +static struct qcom_icc_node xm_gic; +static struct qcom_icc_node qnm_lpiaon_noc; +static struct qcom_icc_node qnm_lpass_lpinoc; +static struct qcom_icc_node qxm_lpinoc_dsp_axim; +static struct qcom_icc_node llcc_mc; +static struct qcom_icc_node qnm_camnoc_hf; +static struct qcom_icc_node qnm_camnoc_icp; +static struct qcom_icc_node qnm_camnoc_sf; +static struct qcom_icc_node qnm_mdp; +static struct qcom_icc_node qnm_vapss_hcp; +static struct qcom_icc_node qnm_video; +static struct qcom_icc_node qnm_video_cv_cpu; +static struct qcom_icc_node qnm_video_cvp; +static struct qcom_icc_node qnm_video_v_cpu; +static struct qcom_icc_node qsm_mnoc_cfg; +static struct qcom_icc_node qnm_nsp; +static struct qcom_icc_node qsm_pcie_anoc_cfg; +static struct qcom_icc_node xm_pcie3_0; +static struct qcom_icc_node xm_pcie3_1; +static struct qcom_icc_node qnm_aggre1_noc; +static struct qcom_icc_node qnm_aggre2_noc; +static struct qcom_icc_node qnm_apss_noc; +static struct qcom_icc_node qns_a1noc_snoc; +static struct qcom_icc_node qns_a2noc_snoc; +static struct qcom_icc_node qup0_core_slave; +static struct qcom_icc_node qup1_core_slave; +static struct qcom_icc_node qup2_core_slave; +static struct qcom_icc_node qhs_ahb2phy0; +static struct qcom_icc_node qhs_ahb2phy1; +static struct qcom_icc_node qhs_camera_cfg; +static struct qcom_icc_node qhs_clk_ctl; +static struct qcom_icc_node qhs_cpr_cx; +static struct qcom_icc_node qhs_cpr_hmx; +static struct qcom_icc_node qhs_cpr_mmcx; +static struct qcom_icc_node qhs_cpr_mxa; +static struct qcom_icc_node qhs_cpr_mxc; +static struct qcom_icc_node qhs_cpr_nspcx; +static struct qcom_icc_node qhs_crypto0_cfg; +static struct qcom_icc_node qhs_cx_rdpm; +static struct qcom_icc_node qhs_display_cfg; +static struct qcom_icc_node qhs_gpuss_cfg; +static struct qcom_icc_node qhs_i2c; +static struct qcom_icc_node qhs_i3c_ibi0_cfg; +static struct qcom_icc_node qhs_i3c_ibi1_cfg; +static struct qcom_icc_node qhs_imem_cfg; +static struct qcom_icc_node qhs_mss_cfg; +static struct qcom_icc_node qhs_mx_2_rdpm; +static struct qcom_icc_node qhs_mx_rdpm; +static struct qcom_icc_node qhs_pcie0_cfg; +static struct qcom_icc_node qhs_pcie1_cfg; +static struct qcom_icc_node qhs_pcie_rscc; +static struct qcom_icc_node qhs_pdm; +static struct qcom_icc_node qhs_prng; +static struct qcom_icc_node qhs_qdss_cfg; +static struct qcom_icc_node qhs_qspi; +static struct qcom_icc_node qhs_qup02; +static struct qcom_icc_node qhs_qup1; +static struct qcom_icc_node qhs_qup2; +static struct qcom_icc_node qhs_sdc2; +static struct qcom_icc_node qhs_sdc4; +static struct qcom_icc_node qhs_spss_cfg; +static struct qcom_icc_node qhs_tcsr; +static struct qcom_icc_node qhs_tlmm; +static struct qcom_icc_node qhs_ufs_mem_cfg; +static struct qcom_icc_node qhs_usb3_0; +static struct qcom_icc_node qhs_venus_cfg; +static struct qcom_icc_node qhs_vsense_ctrl_cfg; +static struct qcom_icc_node qss_mnoc_cfg; +static struct qcom_icc_node qss_nsp_qtb_cfg; +static struct qcom_icc_node qss_pcie_anoc_cfg; +static struct qcom_icc_node srvc_cnoc_cfg; +static struct qcom_icc_node xs_qdss_stm; +static struct qcom_icc_node xs_sys_tcu_cfg; +static struct qcom_icc_node qhs_aoss; +static struct qcom_icc_node qhs_ipa; +static struct qcom_icc_node qhs_ipc_router; +static struct qcom_icc_node qhs_tme_cfg; +static struct qcom_icc_node qss_apss; +static struct qcom_icc_node qss_cfg; +static struct qcom_icc_node qss_ddrss_cfg; +static struct qcom_icc_node qxs_imem; +static struct qcom_icc_node srvc_cnoc_main; +static struct qcom_icc_node xs_pcie_0; +static struct qcom_icc_node xs_pcie_1; +static struct qcom_icc_node qns_gem_noc_cnoc; +static struct qcom_icc_node qns_llcc; +static struct qcom_icc_node qns_pcie; +static struct qcom_icc_node qns_lpass_ag_noc_gemnoc; +static struct qcom_icc_node qns_lpass_aggnoc; +static struct qcom_icc_node qns_lpi_aon_noc; +static struct qcom_icc_node ebi; +static struct qcom_icc_node qns_mem_noc_hf; +static struct qcom_icc_node qns_mem_noc_sf; +static struct qcom_icc_node srvc_mnoc; +static struct qcom_icc_node qns_nsp_gemnoc; +static struct qcom_icc_node qns_pcie_mem_noc; +static struct qcom_icc_node srvc_pcie_aggre_noc; +static struct qcom_icc_node qns_gemnoc_sf; static const struct regmap_config icc_regmap_config =3D { .reg_bits =3D 32, .reg_stride =3D 4, @@ -34,12 +164,11 @@ static struct qcom_icc_qosbox qhm_qspi_qos =3D { =20 static struct qcom_icc_node qhm_qspi =3D { .name =3D "qhm_qspi", - .id =3D SM8650_MASTER_QSPI_0, .channels =3D 1, .buswidth =3D 4, .qosbox =3D &qhm_qspi_qos, .num_links =3D 1, - .links =3D { SM8650_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_qosbox qhm_qup1_qos =3D { @@ -52,21 +181,19 @@ static struct qcom_icc_qosbox qhm_qup1_qos =3D { =20 static struct qcom_icc_node qhm_qup1 =3D { .name =3D "qhm_qup1", - .id =3D SM8650_MASTER_QUP_1, .channels =3D 1, .buswidth =3D 4, .qosbox =3D &qhm_qup1_qos, .num_links =3D 1, - .links =3D { SM8650_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node qxm_qup02 =3D { .name =3D "qxm_qup02", - .id =3D SM8650_MASTER_QUP_3, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8650_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_qosbox xm_sdc4_qos =3D { @@ -79,12 +206,11 @@ static struct qcom_icc_qosbox xm_sdc4_qos =3D { =20 static struct qcom_icc_node xm_sdc4 =3D { .name =3D "xm_sdc4", - .id =3D SM8650_MASTER_SDCC_4, .channels =3D 1, .buswidth =3D 8, .qosbox =3D &xm_sdc4_qos, .num_links =3D 1, - .links =3D { SM8650_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_qosbox xm_ufs_mem_qos =3D { @@ -97,12 +223,11 @@ static struct qcom_icc_qosbox xm_ufs_mem_qos =3D { =20 static struct qcom_icc_node xm_ufs_mem =3D { .name =3D "xm_ufs_mem", - .id =3D SM8650_MASTER_UFS_MEM, .channels =3D 1, .buswidth =3D 16, .qosbox =3D &xm_ufs_mem_qos, .num_links =3D 1, - .links =3D { SM8650_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_qosbox xm_usb3_0_qos =3D { @@ -115,12 +240,11 @@ static struct qcom_icc_qosbox xm_usb3_0_qos =3D { =20 static struct qcom_icc_node xm_usb3_0 =3D { .name =3D "xm_usb3_0", - .id =3D SM8650_MASTER_USB3_0, .channels =3D 1, .buswidth =3D 8, .qosbox =3D &xm_usb3_0_qos, .num_links =3D 1, - .links =3D { SM8650_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_qosbox qhm_qdss_bam_qos =3D { @@ -133,12 +257,11 @@ static struct qcom_icc_qosbox qhm_qdss_bam_qos =3D { =20 static struct qcom_icc_node qhm_qdss_bam =3D { .name =3D "qhm_qdss_bam", - .id =3D SM8650_MASTER_QDSS_BAM, .channels =3D 1, .buswidth =3D 4, .qosbox =3D &qhm_qdss_bam_qos, .num_links =3D 1, - .links =3D { SM8650_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_qosbox qhm_qup2_qos =3D { @@ -151,12 +274,11 @@ static struct qcom_icc_qosbox qhm_qup2_qos =3D { =20 static struct qcom_icc_node qhm_qup2 =3D { .name =3D "qhm_qup2", - .id =3D SM8650_MASTER_QUP_2, .channels =3D 1, .buswidth =3D 4, .qosbox =3D &qhm_qup2_qos, .num_links =3D 1, - .links =3D { SM8650_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_qosbox qxm_crypto_qos =3D { @@ -169,12 +291,11 @@ static struct qcom_icc_qosbox qxm_crypto_qos =3D { =20 static struct qcom_icc_node qxm_crypto =3D { .name =3D "qxm_crypto", - .id =3D SM8650_MASTER_CRYPTO, .channels =3D 1, .buswidth =3D 8, .qosbox =3D &qxm_crypto_qos, .num_links =3D 1, - .links =3D { SM8650_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_qosbox qxm_ipa_qos =3D { @@ -187,21 +308,19 @@ static struct qcom_icc_qosbox qxm_ipa_qos =3D { =20 static struct qcom_icc_node qxm_ipa =3D { .name =3D "qxm_ipa", - .id =3D SM8650_MASTER_IPA, .channels =3D 1, .buswidth =3D 8, .qosbox =3D &qxm_ipa_qos, .num_links =3D 1, - .links =3D { SM8650_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qxm_sp =3D { .name =3D "qxm_sp", - .id =3D SM8650_MASTER_SP, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8650_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_qosbox xm_qdss_etr_0_qos =3D { @@ -214,12 +333,11 @@ static struct qcom_icc_qosbox xm_qdss_etr_0_qos =3D { =20 static struct qcom_icc_node xm_qdss_etr_0 =3D { .name =3D "xm_qdss_etr_0", - .id =3D SM8650_MASTER_QDSS_ETR, .channels =3D 1, .buswidth =3D 8, .qosbox =3D &xm_qdss_etr_0_qos, .num_links =3D 1, - .links =3D { SM8650_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_qosbox xm_qdss_etr_1_qos =3D { @@ -232,12 +350,11 @@ static struct qcom_icc_qosbox xm_qdss_etr_1_qos =3D { =20 static struct qcom_icc_node xm_qdss_etr_1 =3D { .name =3D "xm_qdss_etr_1", - .id =3D SM8650_MASTER_QDSS_ETR_1, .channels =3D 1, .buswidth =3D 8, .qosbox =3D &xm_qdss_etr_1_qos, .num_links =3D 1, - .links =3D { SM8650_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_qosbox xm_sdc2_qos =3D { @@ -250,92 +367,85 @@ static struct qcom_icc_qosbox xm_sdc2_qos =3D { =20 static struct qcom_icc_node xm_sdc2 =3D { .name =3D "xm_sdc2", - .id =3D SM8650_MASTER_SDCC_2, .channels =3D 1, .buswidth =3D 8, .qosbox =3D &xm_sdc2_qos, .num_links =3D 1, - .links =3D { SM8650_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qup0_core_master =3D { .name =3D "qup0_core_master", - .id =3D SM8650_MASTER_QUP_CORE_0, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8650_SLAVE_QUP_CORE_0 }, + .link_nodes =3D { &qup0_core_slave }, }; =20 static struct qcom_icc_node qup1_core_master =3D { .name =3D "qup1_core_master", - .id =3D SM8650_MASTER_QUP_CORE_1, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8650_SLAVE_QUP_CORE_1 }, + .link_nodes =3D { &qup1_core_slave }, }; =20 static struct qcom_icc_node qup2_core_master =3D { .name =3D "qup2_core_master", - .id =3D SM8650_MASTER_QUP_CORE_2, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8650_SLAVE_QUP_CORE_2 }, + .link_nodes =3D { &qup2_core_slave }, }; =20 static struct qcom_icc_node qsm_cfg =3D { .name =3D "qsm_cfg", - .id =3D SM8650_MASTER_CNOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 46, - .links =3D { SM8650_SLAVE_AHB2PHY_SOUTH, SM8650_SLAVE_AHB2PHY_NORTH, - SM8650_SLAVE_CAMERA_CFG, SM8650_SLAVE_CLK_CTL, - SM8650_SLAVE_RBCPR_CX_CFG, SM8650_SLAVE_CPR_HMX, - SM8650_SLAVE_RBCPR_MMCX_CFG, SM8650_SLAVE_RBCPR_MXA_CFG, - SM8650_SLAVE_RBCPR_MXC_CFG, SM8650_SLAVE_CPR_NSPCX, - SM8650_SLAVE_CRYPTO_0_CFG, SM8650_SLAVE_CX_RDPM, - SM8650_SLAVE_DISPLAY_CFG, SM8650_SLAVE_GFX3D_CFG, - SM8650_SLAVE_I2C, SM8650_SLAVE_I3C_IBI0_CFG, - SM8650_SLAVE_I3C_IBI1_CFG, SM8650_SLAVE_IMEM_CFG, - SM8650_SLAVE_CNOC_MSS, SM8650_SLAVE_MX_2_RDPM, - SM8650_SLAVE_MX_RDPM, SM8650_SLAVE_PCIE_0_CFG, - SM8650_SLAVE_PCIE_1_CFG, SM8650_SLAVE_PCIE_RSCC, - SM8650_SLAVE_PDM, SM8650_SLAVE_PRNG, - SM8650_SLAVE_QDSS_CFG, SM8650_SLAVE_QSPI_0, - SM8650_SLAVE_QUP_3, SM8650_SLAVE_QUP_1, - SM8650_SLAVE_QUP_2, SM8650_SLAVE_SDCC_2, - SM8650_SLAVE_SDCC_4, SM8650_SLAVE_SPSS_CFG, - SM8650_SLAVE_TCSR, SM8650_SLAVE_TLMM, - SM8650_SLAVE_UFS_MEM_CFG, SM8650_SLAVE_USB3_0, - SM8650_SLAVE_VENUS_CFG, SM8650_SLAVE_VSENSE_CTRL_CFG, - SM8650_SLAVE_CNOC_MNOC_CFG, SM8650_SLAVE_NSP_QTB_CFG, - SM8650_SLAVE_PCIE_ANOC_CFG, SM8650_SLAVE_SERVICE_CNOC_CFG, - SM8650_SLAVE_QDSS_STM, SM8650_SLAVE_TCU }, + .link_nodes =3D { &qhs_ahb2phy0, &qhs_ahb2phy1, + &qhs_camera_cfg, &qhs_clk_ctl, + &qhs_cpr_cx, &qhs_cpr_hmx, + &qhs_cpr_mmcx, &qhs_cpr_mxa, + &qhs_cpr_mxc, &qhs_cpr_nspcx, + &qhs_crypto0_cfg, &qhs_cx_rdpm, + &qhs_display_cfg, &qhs_gpuss_cfg, + &qhs_i2c, &qhs_i3c_ibi0_cfg, + &qhs_i3c_ibi1_cfg, &qhs_imem_cfg, + &qhs_mss_cfg, &qhs_mx_2_rdpm, + &qhs_mx_rdpm, &qhs_pcie0_cfg, + &qhs_pcie1_cfg, &qhs_pcie_rscc, + &qhs_pdm, &qhs_prng, + &qhs_qdss_cfg, &qhs_qspi, + &qhs_qup02, &qhs_qup1, + &qhs_qup2, &qhs_sdc2, + &qhs_sdc4, &qhs_spss_cfg, + &qhs_tcsr, &qhs_tlmm, + &qhs_ufs_mem_cfg, &qhs_usb3_0, + &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, + &qss_mnoc_cfg, &qss_nsp_qtb_cfg, + &qss_pcie_anoc_cfg, &srvc_cnoc_cfg, + &xs_qdss_stm, &xs_sys_tcu_cfg }, }; =20 static struct qcom_icc_node qnm_gemnoc_cnoc =3D { .name =3D "qnm_gemnoc_cnoc", - .id =3D SM8650_MASTER_GEM_NOC_CNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 9, - .links =3D { SM8650_SLAVE_AOSS, SM8650_SLAVE_IPA_CFG, - SM8650_SLAVE_IPC_ROUTER_CFG, SM8650_SLAVE_TME_CFG, - SM8650_SLAVE_APPSS, SM8650_SLAVE_CNOC_CFG, - SM8650_SLAVE_DDRSS_CFG, SM8650_SLAVE_IMEM, - SM8650_SLAVE_SERVICE_CNOC }, + .link_nodes =3D { &qhs_aoss, &qhs_ipa, + &qhs_ipc_router, &qhs_tme_cfg, + &qss_apss, &qss_cfg, + &qss_ddrss_cfg, &qxs_imem, + &srvc_cnoc_main }, }; =20 static struct qcom_icc_node qnm_gemnoc_pcie =3D { .name =3D "qnm_gemnoc_pcie", - .id =3D SM8650_MASTER_GEM_NOC_PCIE_SNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 2, - .links =3D { SM8650_SLAVE_PCIE_0, SM8650_SLAVE_PCIE_1 }, + .link_nodes =3D { &xs_pcie_0, &xs_pcie_1 }, }; =20 static struct qcom_icc_qosbox alm_gpu_tcu_qos =3D { @@ -348,12 +458,11 @@ static struct qcom_icc_qosbox alm_gpu_tcu_qos =3D { =20 static struct qcom_icc_node alm_gpu_tcu =3D { .name =3D "alm_gpu_tcu", - .id =3D SM8650_MASTER_GPU_TCU, .channels =3D 1, .buswidth =3D 8, .qosbox =3D &alm_gpu_tcu_qos, .num_links =3D 2, - .links =3D { SM8650_SLAVE_GEM_NOC_CNOC, SM8650_SLAVE_LLCC }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; =20 static struct qcom_icc_qosbox alm_sys_tcu_qos =3D { @@ -366,12 +475,11 @@ static struct qcom_icc_qosbox alm_sys_tcu_qos =3D { =20 static struct qcom_icc_node alm_sys_tcu =3D { .name =3D "alm_sys_tcu", - .id =3D SM8650_MASTER_SYS_TCU, .channels =3D 1, .buswidth =3D 8, .qosbox =3D &alm_sys_tcu_qos, .num_links =3D 2, - .links =3D { SM8650_SLAVE_GEM_NOC_CNOC, SM8650_SLAVE_LLCC }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; =20 static struct qcom_icc_qosbox alm_ubwc_p_tcu_qos =3D { @@ -384,22 +492,20 @@ static struct qcom_icc_qosbox alm_ubwc_p_tcu_qos =3D { =20 static struct qcom_icc_node alm_ubwc_p_tcu =3D { .name =3D "alm_ubwc_p_tcu", - .id =3D SM8650_MASTER_UBWC_P_TCU, .channels =3D 1, .buswidth =3D 8, .qosbox =3D &alm_ubwc_p_tcu_qos, .num_links =3D 2, - .links =3D { SM8650_SLAVE_GEM_NOC_CNOC, SM8650_SLAVE_LLCC }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; =20 static struct qcom_icc_node chm_apps =3D { .name =3D "chm_apps", - .id =3D SM8650_MASTER_APPSS_PROC, .channels =3D 3, .buswidth =3D 32, .num_links =3D 3, - .links =3D { SM8650_SLAVE_GEM_NOC_CNOC, SM8650_SLAVE_LLCC, - SM8650_SLAVE_MEM_NOC_PCIE_SNOC }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, }; =20 static struct qcom_icc_qosbox qnm_gpu_qos =3D { @@ -412,12 +518,11 @@ static struct qcom_icc_qosbox qnm_gpu_qos =3D { =20 static struct qcom_icc_node qnm_gpu =3D { .name =3D "qnm_gpu", - .id =3D SM8650_MASTER_GFX3D, .channels =3D 2, .buswidth =3D 32, .qosbox =3D &qnm_gpu_qos, .num_links =3D 2, - .links =3D { SM8650_SLAVE_GEM_NOC_CNOC, SM8650_SLAVE_LLCC }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; =20 static struct qcom_icc_qosbox qnm_lpass_gemnoc_qos =3D { @@ -430,23 +535,21 @@ static struct qcom_icc_qosbox qnm_lpass_gemnoc_qos = =3D { =20 static struct qcom_icc_node qnm_lpass_gemnoc =3D { .name =3D "qnm_lpass_gemnoc", - .id =3D SM8650_MASTER_LPASS_GEM_NOC, .channels =3D 1, .buswidth =3D 16, .qosbox =3D &qnm_lpass_gemnoc_qos, .num_links =3D 3, - .links =3D { SM8650_SLAVE_GEM_NOC_CNOC, SM8650_SLAVE_LLCC, - SM8650_SLAVE_MEM_NOC_PCIE_SNOC }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, }; =20 static struct qcom_icc_node qnm_mdsp =3D { .name =3D "qnm_mdsp", - .id =3D SM8650_MASTER_MSS_PROC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 3, - .links =3D { SM8650_SLAVE_GEM_NOC_CNOC, SM8650_SLAVE_LLCC, - SM8650_SLAVE_MEM_NOC_PCIE_SNOC }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, }; =20 static struct qcom_icc_qosbox qnm_mnoc_hf_qos =3D { @@ -459,12 +562,11 @@ static struct qcom_icc_qosbox qnm_mnoc_hf_qos =3D { =20 static struct qcom_icc_node qnm_mnoc_hf =3D { .name =3D "qnm_mnoc_hf", - .id =3D SM8650_MASTER_MNOC_HF_MEM_NOC, .channels =3D 2, .buswidth =3D 32, .qosbox =3D &qnm_mnoc_hf_qos, .num_links =3D 2, - .links =3D { SM8650_SLAVE_GEM_NOC_CNOC, SM8650_SLAVE_LLCC }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; =20 static struct qcom_icc_qosbox qnm_mnoc_sf_qos =3D { @@ -477,12 +579,11 @@ static struct qcom_icc_qosbox qnm_mnoc_sf_qos =3D { =20 static struct qcom_icc_node qnm_mnoc_sf =3D { .name =3D "qnm_mnoc_sf", - .id =3D SM8650_MASTER_MNOC_SF_MEM_NOC, .channels =3D 2, .buswidth =3D 32, .qosbox =3D &qnm_mnoc_sf_qos, .num_links =3D 2, - .links =3D { SM8650_SLAVE_GEM_NOC_CNOC, SM8650_SLAVE_LLCC }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; =20 static struct qcom_icc_qosbox qnm_nsp_gemnoc_qos =3D { @@ -495,13 +596,12 @@ static struct qcom_icc_qosbox qnm_nsp_gemnoc_qos =3D { =20 static struct qcom_icc_node qnm_nsp_gemnoc =3D { .name =3D "qnm_nsp_gemnoc", - .id =3D SM8650_MASTER_COMPUTE_NOC, .channels =3D 2, .buswidth =3D 32, .qosbox =3D &qnm_nsp_gemnoc_qos, .num_links =3D 3, - .links =3D { SM8650_SLAVE_GEM_NOC_CNOC, SM8650_SLAVE_LLCC, - SM8650_SLAVE_MEM_NOC_PCIE_SNOC }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, }; =20 static struct qcom_icc_qosbox qnm_pcie_qos =3D { @@ -514,12 +614,11 @@ static struct qcom_icc_qosbox qnm_pcie_qos =3D { =20 static struct qcom_icc_node qnm_pcie =3D { .name =3D "qnm_pcie", - .id =3D SM8650_MASTER_ANOC_PCIE_GEM_NOC, .channels =3D 1, .buswidth =3D 16, .qosbox =3D &qnm_pcie_qos, .num_links =3D 2, - .links =3D { SM8650_SLAVE_GEM_NOC_CNOC, SM8650_SLAVE_LLCC }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; =20 static struct qcom_icc_qosbox qnm_snoc_sf_qos =3D { @@ -532,13 +631,12 @@ static struct qcom_icc_qosbox qnm_snoc_sf_qos =3D { =20 static struct qcom_icc_node qnm_snoc_sf =3D { .name =3D "qnm_snoc_sf", - .id =3D SM8650_MASTER_SNOC_SF_MEM_NOC, .channels =3D 1, .buswidth =3D 16, .qosbox =3D &qnm_snoc_sf_qos, .num_links =3D 3, - .links =3D { SM8650_SLAVE_GEM_NOC_CNOC, SM8650_SLAVE_LLCC, - SM8650_SLAVE_MEM_NOC_PCIE_SNOC }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, }; =20 static struct qcom_icc_qosbox qnm_ubwc_p_qos =3D { @@ -551,12 +649,11 @@ static struct qcom_icc_qosbox qnm_ubwc_p_qos =3D { =20 static struct qcom_icc_node qnm_ubwc_p =3D { .name =3D "qnm_ubwc_p", - .id =3D SM8650_MASTER_UBWC_P, .channels =3D 1, .buswidth =3D 32, .qosbox =3D &qnm_ubwc_p_qos, .num_links =3D 1, - .links =3D { SM8650_SLAVE_LLCC }, + .link_nodes =3D { &qns_llcc }, }; =20 static struct qcom_icc_qosbox xm_gic_qos =3D { @@ -569,48 +666,43 @@ static struct qcom_icc_qosbox xm_gic_qos =3D { =20 static struct qcom_icc_node xm_gic =3D { .name =3D "xm_gic", - .id =3D SM8650_MASTER_GIC, .channels =3D 1, .buswidth =3D 8, .qosbox =3D &xm_gic_qos, .num_links =3D 1, - .links =3D { SM8650_SLAVE_LLCC }, + .link_nodes =3D { &qns_llcc }, }; =20 static struct qcom_icc_node qnm_lpiaon_noc =3D { .name =3D "qnm_lpiaon_noc", - .id =3D SM8650_MASTER_LPIAON_NOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM8650_SLAVE_LPASS_GEM_NOC }, + .link_nodes =3D { &qns_lpass_ag_noc_gemnoc }, }; =20 static struct qcom_icc_node qnm_lpass_lpinoc =3D { .name =3D "qnm_lpass_lpinoc", - .id =3D SM8650_MASTER_LPASS_LPINOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM8650_SLAVE_LPIAON_NOC_LPASS_AG_NOC }, + .link_nodes =3D { &qns_lpass_aggnoc }, }; =20 static struct qcom_icc_node qxm_lpinoc_dsp_axim =3D { .name =3D "qxm_lpinoc_dsp_axim", - .id =3D SM8650_MASTER_LPASS_PROC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM8650_SLAVE_LPICX_NOC_LPIAON_NOC }, + .link_nodes =3D { &qns_lpi_aon_noc }, }; =20 static struct qcom_icc_node llcc_mc =3D { .name =3D "llcc_mc", - .id =3D SM8650_MASTER_LLCC, .channels =3D 4, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8650_SLAVE_EBI1 }, + .link_nodes =3D { &ebi }, }; =20 static struct qcom_icc_qosbox qnm_camnoc_hf_qos =3D { @@ -623,12 +715,11 @@ static struct qcom_icc_qosbox qnm_camnoc_hf_qos =3D { =20 static struct qcom_icc_node qnm_camnoc_hf =3D { .name =3D "qnm_camnoc_hf", - .id =3D SM8650_MASTER_CAMNOC_HF, .channels =3D 2, .buswidth =3D 32, .qosbox =3D &qnm_camnoc_hf_qos, .num_links =3D 1, - .links =3D { SM8650_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_hf }, }; =20 static struct qcom_icc_qosbox qnm_camnoc_icp_qos =3D { @@ -641,12 +732,11 @@ static struct qcom_icc_qosbox qnm_camnoc_icp_qos =3D { =20 static struct qcom_icc_node qnm_camnoc_icp =3D { .name =3D "qnm_camnoc_icp", - .id =3D SM8650_MASTER_CAMNOC_ICP, .channels =3D 1, .buswidth =3D 8, .qosbox =3D &qnm_camnoc_icp_qos, .num_links =3D 1, - .links =3D { SM8650_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static struct qcom_icc_qosbox qnm_camnoc_sf_qos =3D { @@ -659,12 +749,11 @@ static struct qcom_icc_qosbox qnm_camnoc_sf_qos =3D { =20 static struct qcom_icc_node qnm_camnoc_sf =3D { .name =3D "qnm_camnoc_sf", - .id =3D SM8650_MASTER_CAMNOC_SF, .channels =3D 2, .buswidth =3D 32, .qosbox =3D &qnm_camnoc_sf_qos, .num_links =3D 1, - .links =3D { SM8650_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static struct qcom_icc_qosbox qnm_mdp_qos =3D { @@ -677,21 +766,19 @@ static struct qcom_icc_qosbox qnm_mdp_qos =3D { =20 static struct qcom_icc_node qnm_mdp =3D { .name =3D "qnm_mdp", - .id =3D SM8650_MASTER_MDP, .channels =3D 2, .buswidth =3D 32, .qosbox =3D &qnm_mdp_qos, .num_links =3D 1, - .links =3D { SM8650_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_hf }, }; =20 static struct qcom_icc_node qnm_vapss_hcp =3D { .name =3D "qnm_vapss_hcp", - .id =3D SM8650_MASTER_CDSP_HCP, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8650_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static struct qcom_icc_qosbox qnm_video_qos =3D { @@ -704,12 +791,11 @@ static struct qcom_icc_qosbox qnm_video_qos =3D { =20 static struct qcom_icc_node qnm_video =3D { .name =3D "qnm_video", - .id =3D SM8650_MASTER_VIDEO, .channels =3D 2, .buswidth =3D 32, .qosbox =3D &qnm_video_qos, .num_links =3D 1, - .links =3D { SM8650_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static struct qcom_icc_qosbox qnm_video_cv_cpu_qos =3D { @@ -722,12 +808,11 @@ static struct qcom_icc_qosbox qnm_video_cv_cpu_qos = =3D { =20 static struct qcom_icc_node qnm_video_cv_cpu =3D { .name =3D "qnm_video_cv_cpu", - .id =3D SM8650_MASTER_VIDEO_CV_PROC, .channels =3D 1, .buswidth =3D 8, .qosbox =3D &qnm_video_cv_cpu_qos, .num_links =3D 1, - .links =3D { SM8650_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static struct qcom_icc_qosbox qnm_video_cvp_qos =3D { @@ -740,12 +825,11 @@ static struct qcom_icc_qosbox qnm_video_cvp_qos =3D { =20 static struct qcom_icc_node qnm_video_cvp =3D { .name =3D "qnm_video_cvp", - .id =3D SM8650_MASTER_VIDEO_PROC, .channels =3D 2, .buswidth =3D 32, .qosbox =3D &qnm_video_cvp_qos, .num_links =3D 1, - .links =3D { SM8650_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static struct qcom_icc_qosbox qnm_video_v_cpu_qos =3D { @@ -758,39 +842,35 @@ static struct qcom_icc_qosbox qnm_video_v_cpu_qos =3D= { =20 static struct qcom_icc_node qnm_video_v_cpu =3D { .name =3D "qnm_video_v_cpu", - .id =3D SM8650_MASTER_VIDEO_V_PROC, .channels =3D 1, .buswidth =3D 8, .qosbox =3D &qnm_video_v_cpu_qos, .num_links =3D 1, - .links =3D { SM8650_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static struct qcom_icc_node qsm_mnoc_cfg =3D { .name =3D "qsm_mnoc_cfg", - .id =3D SM8650_MASTER_CNOC_MNOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8650_SLAVE_SERVICE_MNOC }, + .link_nodes =3D { &srvc_mnoc }, }; =20 static struct qcom_icc_node qnm_nsp =3D { .name =3D "qnm_nsp", - .id =3D SM8650_MASTER_CDSP_PROC, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8650_SLAVE_CDSP_MEM_NOC }, + .link_nodes =3D { &qns_nsp_gemnoc }, }; =20 static struct qcom_icc_node qsm_pcie_anoc_cfg =3D { .name =3D "qsm_pcie_anoc_cfg", - .id =3D SM8650_MASTER_PCIE_ANOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8650_SLAVE_SERVICE_PCIE_ANOC }, + .link_nodes =3D { &srvc_pcie_aggre_noc }, }; =20 static struct qcom_icc_qosbox xm_pcie3_0_qos =3D { @@ -803,12 +883,11 @@ static struct qcom_icc_qosbox xm_pcie3_0_qos =3D { =20 static struct qcom_icc_node xm_pcie3_0 =3D { .name =3D "xm_pcie3_0", - .id =3D SM8650_MASTER_PCIE_0, .channels =3D 1, .buswidth =3D 8, .qosbox =3D &xm_pcie3_0_qos, .num_links =3D 1, - .links =3D { SM8650_SLAVE_ANOC_PCIE_GEM_NOC }, + .link_nodes =3D { &qns_pcie_mem_noc }, }; =20 static struct qcom_icc_qosbox xm_pcie3_1_qos =3D { @@ -821,30 +900,27 @@ static struct qcom_icc_qosbox xm_pcie3_1_qos =3D { =20 static struct qcom_icc_node xm_pcie3_1 =3D { .name =3D "xm_pcie3_1", - .id =3D SM8650_MASTER_PCIE_1, .channels =3D 1, .buswidth =3D 16, .qosbox =3D &xm_pcie3_1_qos, .num_links =3D 1, - .links =3D { SM8650_SLAVE_ANOC_PCIE_GEM_NOC }, + .link_nodes =3D { &qns_pcie_mem_noc }, }; =20 static struct qcom_icc_node qnm_aggre1_noc =3D { .name =3D "qnm_aggre1_noc", - .id =3D SM8650_MASTER_A1NOC_SNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM8650_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes =3D { &qns_gemnoc_sf }, }; =20 static struct qcom_icc_node qnm_aggre2_noc =3D { .name =3D "qnm_aggre2_noc", - .id =3D SM8650_MASTER_A2NOC_SNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM8650_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes =3D { &qns_gemnoc_sf }, }; =20 static struct qcom_icc_qosbox qnm_apss_noc_qos =3D { @@ -857,636 +933,499 @@ static struct qcom_icc_qosbox qnm_apss_noc_qos =3D { =20 static struct qcom_icc_node qnm_apss_noc =3D { .name =3D "qnm_apss_noc", - .id =3D SM8650_MASTER_APSS_NOC, .channels =3D 1, .buswidth =3D 4, .qosbox =3D &qnm_apss_noc_qos, .num_links =3D 1, - .links =3D { SM8650_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes =3D { &qns_gemnoc_sf }, }; =20 static struct qcom_icc_node qns_a1noc_snoc =3D { .name =3D "qns_a1noc_snoc", - .id =3D SM8650_SLAVE_A1NOC_SNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM8650_MASTER_A1NOC_SNOC }, + .link_nodes =3D { &qnm_aggre1_noc }, }; =20 static struct qcom_icc_node qns_a2noc_snoc =3D { .name =3D "qns_a2noc_snoc", - .id =3D SM8650_SLAVE_A2NOC_SNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM8650_MASTER_A2NOC_SNOC }, + .link_nodes =3D { &qnm_aggre2_noc }, }; =20 static struct qcom_icc_node qup0_core_slave =3D { .name =3D "qup0_core_slave", - .id =3D SM8650_SLAVE_QUP_CORE_0, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qup1_core_slave =3D { .name =3D "qup1_core_slave", - .id =3D SM8650_SLAVE_QUP_CORE_1, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qup2_core_slave =3D { .name =3D "qup2_core_slave", - .id =3D SM8650_SLAVE_QUP_CORE_2, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_ahb2phy0 =3D { .name =3D "qhs_ahb2phy0", - .id =3D SM8650_SLAVE_AHB2PHY_SOUTH, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_ahb2phy1 =3D { .name =3D "qhs_ahb2phy1", - .id =3D SM8650_SLAVE_AHB2PHY_NORTH, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_camera_cfg =3D { .name =3D "qhs_camera_cfg", - .id =3D SM8650_SLAVE_CAMERA_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_clk_ctl =3D { .name =3D "qhs_clk_ctl", - .id =3D SM8650_SLAVE_CLK_CTL, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_cpr_cx =3D { .name =3D "qhs_cpr_cx", - .id =3D SM8650_SLAVE_RBCPR_CX_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_cpr_hmx =3D { .name =3D "qhs_cpr_hmx", - .id =3D SM8650_SLAVE_CPR_HMX, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_cpr_mmcx =3D { .name =3D "qhs_cpr_mmcx", - .id =3D SM8650_SLAVE_RBCPR_MMCX_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_cpr_mxa =3D { .name =3D "qhs_cpr_mxa", - .id =3D SM8650_SLAVE_RBCPR_MXA_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_cpr_mxc =3D { .name =3D "qhs_cpr_mxc", - .id =3D SM8650_SLAVE_RBCPR_MXC_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_cpr_nspcx =3D { .name =3D "qhs_cpr_nspcx", - .id =3D SM8650_SLAVE_CPR_NSPCX, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_crypto0_cfg =3D { .name =3D "qhs_crypto0_cfg", - .id =3D SM8650_SLAVE_CRYPTO_0_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_cx_rdpm =3D { .name =3D "qhs_cx_rdpm", - .id =3D SM8650_SLAVE_CX_RDPM, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_display_cfg =3D { .name =3D "qhs_display_cfg", - .id =3D SM8650_SLAVE_DISPLAY_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_gpuss_cfg =3D { .name =3D "qhs_gpuss_cfg", - .id =3D SM8650_SLAVE_GFX3D_CFG, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_i2c =3D { .name =3D "qhs_i2c", - .id =3D SM8650_SLAVE_I2C, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_i3c_ibi0_cfg =3D { .name =3D "qhs_i3c_ibi0_cfg", - .id =3D SM8650_SLAVE_I3C_IBI0_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_i3c_ibi1_cfg =3D { .name =3D "qhs_i3c_ibi1_cfg", - .id =3D SM8650_SLAVE_I3C_IBI1_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_imem_cfg =3D { .name =3D "qhs_imem_cfg", - .id =3D SM8650_SLAVE_IMEM_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_mss_cfg =3D { .name =3D "qhs_mss_cfg", - .id =3D SM8650_SLAVE_CNOC_MSS, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_mx_2_rdpm =3D { .name =3D "qhs_mx_2_rdpm", - .id =3D SM8650_SLAVE_MX_2_RDPM, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_mx_rdpm =3D { .name =3D "qhs_mx_rdpm", - .id =3D SM8650_SLAVE_MX_RDPM, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_pcie0_cfg =3D { .name =3D "qhs_pcie0_cfg", - .id =3D SM8650_SLAVE_PCIE_0_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_pcie1_cfg =3D { .name =3D "qhs_pcie1_cfg", - .id =3D SM8650_SLAVE_PCIE_1_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_pcie_rscc =3D { .name =3D "qhs_pcie_rscc", - .id =3D SM8650_SLAVE_PCIE_RSCC, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_pdm =3D { .name =3D "qhs_pdm", - .id =3D SM8650_SLAVE_PDM, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_prng =3D { .name =3D "qhs_prng", - .id =3D SM8650_SLAVE_PRNG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_qdss_cfg =3D { .name =3D "qhs_qdss_cfg", - .id =3D SM8650_SLAVE_QDSS_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_qspi =3D { .name =3D "qhs_qspi", - .id =3D SM8650_SLAVE_QSPI_0, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_qup02 =3D { .name =3D "qhs_qup02", - .id =3D SM8650_SLAVE_QUP_3, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_qup1 =3D { .name =3D "qhs_qup1", - .id =3D SM8650_SLAVE_QUP_1, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_qup2 =3D { .name =3D "qhs_qup2", - .id =3D SM8650_SLAVE_QUP_2, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_sdc2 =3D { .name =3D "qhs_sdc2", - .id =3D SM8650_SLAVE_SDCC_2, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_sdc4 =3D { .name =3D "qhs_sdc4", - .id =3D SM8650_SLAVE_SDCC_4, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_spss_cfg =3D { .name =3D "qhs_spss_cfg", - .id =3D SM8650_SLAVE_SPSS_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_tcsr =3D { .name =3D "qhs_tcsr", - .id =3D SM8650_SLAVE_TCSR, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_tlmm =3D { .name =3D "qhs_tlmm", - .id =3D SM8650_SLAVE_TLMM, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_ufs_mem_cfg =3D { .name =3D "qhs_ufs_mem_cfg", - .id =3D SM8650_SLAVE_UFS_MEM_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_usb3_0 =3D { .name =3D "qhs_usb3_0", - .id =3D SM8650_SLAVE_USB3_0, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_venus_cfg =3D { .name =3D "qhs_venus_cfg", - .id =3D SM8650_SLAVE_VENUS_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_vsense_ctrl_cfg =3D { .name =3D "qhs_vsense_ctrl_cfg", - .id =3D SM8650_SLAVE_VSENSE_CTRL_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qss_mnoc_cfg =3D { .name =3D "qss_mnoc_cfg", - .id =3D SM8650_SLAVE_CNOC_MNOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8650_MASTER_CNOC_MNOC_CFG }, + .link_nodes =3D { &qsm_mnoc_cfg }, }; =20 static struct qcom_icc_node qss_nsp_qtb_cfg =3D { .name =3D "qss_nsp_qtb_cfg", - .id =3D SM8650_SLAVE_NSP_QTB_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qss_pcie_anoc_cfg =3D { .name =3D "qss_pcie_anoc_cfg", - .id =3D SM8650_SLAVE_PCIE_ANOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8650_MASTER_PCIE_ANOC_CFG }, + .link_nodes =3D { &qsm_pcie_anoc_cfg }, }; =20 static struct qcom_icc_node srvc_cnoc_cfg =3D { .name =3D "srvc_cnoc_cfg", - .id =3D SM8650_SLAVE_SERVICE_CNOC_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node xs_qdss_stm =3D { .name =3D "xs_qdss_stm", - .id =3D SM8650_SLAVE_QDSS_STM, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node xs_sys_tcu_cfg =3D { .name =3D "xs_sys_tcu_cfg", - .id =3D SM8650_SLAVE_TCU, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_aoss =3D { .name =3D "qhs_aoss", - .id =3D SM8650_SLAVE_AOSS, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_ipa =3D { .name =3D "qhs_ipa", - .id =3D SM8650_SLAVE_IPA_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_ipc_router =3D { .name =3D "qhs_ipc_router", - .id =3D SM8650_SLAVE_IPC_ROUTER_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_tme_cfg =3D { .name =3D "qhs_tme_cfg", - .id =3D SM8650_SLAVE_TME_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qss_apss =3D { .name =3D "qss_apss", - .id =3D SM8650_SLAVE_APPSS, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qss_cfg =3D { .name =3D "qss_cfg", - .id =3D SM8650_SLAVE_CNOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8650_MASTER_CNOC_CFG }, + .link_nodes =3D { &qsm_cfg }, }; =20 static struct qcom_icc_node qss_ddrss_cfg =3D { .name =3D "qss_ddrss_cfg", - .id =3D SM8650_SLAVE_DDRSS_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qxs_imem =3D { .name =3D "qxs_imem", - .id =3D SM8650_SLAVE_IMEM, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 0, }; =20 static struct qcom_icc_node srvc_cnoc_main =3D { .name =3D "srvc_cnoc_main", - .id =3D SM8650_SLAVE_SERVICE_CNOC, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node xs_pcie_0 =3D { .name =3D "xs_pcie_0", - .id =3D SM8650_SLAVE_PCIE_0, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 0, }; =20 static struct qcom_icc_node xs_pcie_1 =3D { .name =3D "xs_pcie_1", - .id =3D SM8650_SLAVE_PCIE_1, .channels =3D 1, .buswidth =3D 16, - .num_links =3D 0, }; =20 static struct qcom_icc_node qns_gem_noc_cnoc =3D { .name =3D "qns_gem_noc_cnoc", - .id =3D SM8650_SLAVE_GEM_NOC_CNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM8650_MASTER_GEM_NOC_CNOC }, + .link_nodes =3D { &qnm_gemnoc_cnoc }, }; =20 static struct qcom_icc_node qns_llcc =3D { .name =3D "qns_llcc", - .id =3D SM8650_SLAVE_LLCC, .channels =3D 4, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM8650_MASTER_LLCC }, + .link_nodes =3D { &llcc_mc }, }; =20 static struct qcom_icc_node qns_pcie =3D { .name =3D "qns_pcie", - .id =3D SM8650_SLAVE_MEM_NOC_PCIE_SNOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8650_MASTER_GEM_NOC_PCIE_SNOC }, + .link_nodes =3D { &qnm_gemnoc_pcie }, }; =20 static struct qcom_icc_node qns_lpass_ag_noc_gemnoc =3D { .name =3D "qns_lpass_ag_noc_gemnoc", - .id =3D SM8650_SLAVE_LPASS_GEM_NOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM8650_MASTER_LPASS_GEM_NOC }, + .link_nodes =3D { &qnm_lpass_gemnoc }, }; =20 static struct qcom_icc_node qns_lpass_aggnoc =3D { .name =3D "qns_lpass_aggnoc", - .id =3D SM8650_SLAVE_LPIAON_NOC_LPASS_AG_NOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM8650_MASTER_LPIAON_NOC }, + .link_nodes =3D { &qnm_lpiaon_noc }, }; =20 static struct qcom_icc_node qns_lpi_aon_noc =3D { .name =3D "qns_lpi_aon_noc", - .id =3D SM8650_SLAVE_LPICX_NOC_LPIAON_NOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM8650_MASTER_LPASS_LPINOC }, + .link_nodes =3D { &qnm_lpass_lpinoc }, }; =20 static struct qcom_icc_node ebi =3D { .name =3D "ebi", - .id =3D SM8650_SLAVE_EBI1, .channels =3D 4, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qns_mem_noc_hf =3D { .name =3D "qns_mem_noc_hf", - .id =3D SM8650_SLAVE_MNOC_HF_MEM_NOC, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8650_MASTER_MNOC_HF_MEM_NOC }, + .link_nodes =3D { &qnm_mnoc_hf }, }; =20 static struct qcom_icc_node qns_mem_noc_sf =3D { .name =3D "qns_mem_noc_sf", - .id =3D SM8650_SLAVE_MNOC_SF_MEM_NOC, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8650_MASTER_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qnm_mnoc_sf }, }; =20 static struct qcom_icc_node srvc_mnoc =3D { .name =3D "srvc_mnoc", - .id =3D SM8650_SLAVE_SERVICE_MNOC, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qns_nsp_gemnoc =3D { .name =3D "qns_nsp_gemnoc", - .id =3D SM8650_SLAVE_CDSP_MEM_NOC, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8650_MASTER_COMPUTE_NOC }, + .link_nodes =3D { &qnm_nsp_gemnoc }, }; =20 static struct qcom_icc_node qns_pcie_mem_noc =3D { .name =3D "qns_pcie_mem_noc", - .id =3D SM8650_SLAVE_ANOC_PCIE_GEM_NOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM8650_MASTER_ANOC_PCIE_GEM_NOC }, + .link_nodes =3D { &qnm_pcie }, }; =20 static struct qcom_icc_node srvc_pcie_aggre_noc =3D { .name =3D "srvc_pcie_aggre_noc", - .id =3D SM8650_SLAVE_SERVICE_PCIE_ANOC, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qns_gemnoc_sf =3D { .name =3D "qns_gemnoc_sf", - .id =3D SM8650_SLAVE_SNOC_GEM_NOC_SF, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM8650_MASTER_SNOC_SF_MEM_NOC }, + .link_nodes =3D { &qnm_snoc_sf }, }; =20 static struct qcom_icc_bcm bcm_acv =3D { @@ -1656,6 +1595,7 @@ static struct qcom_icc_node * const aggre1_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sm8650_aggre1_noc =3D { + .alloc_dyn_id =3D true, .config =3D &icc_regmap_config, .nodes =3D aggre1_noc_nodes, .num_nodes =3D ARRAY_SIZE(aggre1_noc_nodes), @@ -1678,6 +1618,7 @@ static struct qcom_icc_node * const aggre2_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sm8650_aggre2_noc =3D { + .alloc_dyn_id =3D true, .config =3D &icc_regmap_config, .nodes =3D aggre2_noc_nodes, .num_nodes =3D ARRAY_SIZE(aggre2_noc_nodes), @@ -1701,6 +1642,7 @@ static struct qcom_icc_node * const clk_virt_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sm8650_clk_virt =3D { + .alloc_dyn_id =3D true, .nodes =3D clk_virt_nodes, .num_nodes =3D ARRAY_SIZE(clk_virt_nodes), .bcms =3D clk_virt_bcms, @@ -1762,6 +1704,7 @@ static struct qcom_icc_node * const config_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sm8650_config_noc =3D { + .alloc_dyn_id =3D true, .config =3D &icc_regmap_config, .nodes =3D config_noc_nodes, .num_nodes =3D ARRAY_SIZE(config_noc_nodes), @@ -1790,6 +1733,7 @@ static struct qcom_icc_node * const cnoc_main_nodes[]= =3D { }; =20 static const struct qcom_icc_desc sm8650_cnoc_main =3D { + .alloc_dyn_id =3D true, .config =3D &icc_regmap_config, .nodes =3D cnoc_main_nodes, .num_nodes =3D ARRAY_SIZE(cnoc_main_nodes), @@ -1823,6 +1767,7 @@ static struct qcom_icc_node * const gem_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sm8650_gem_noc =3D { + .alloc_dyn_id =3D true, .config =3D &icc_regmap_config, .nodes =3D gem_noc_nodes, .num_nodes =3D ARRAY_SIZE(gem_noc_nodes), @@ -1836,6 +1781,7 @@ static struct qcom_icc_node * const lpass_ag_noc_node= s[] =3D { }; =20 static const struct qcom_icc_desc sm8650_lpass_ag_noc =3D { + .alloc_dyn_id =3D true, .config =3D &icc_regmap_config, .nodes =3D lpass_ag_noc_nodes, .num_nodes =3D ARRAY_SIZE(lpass_ag_noc_nodes), @@ -1851,6 +1797,7 @@ static struct qcom_icc_node * const lpass_lpiaon_noc_= nodes[] =3D { }; =20 static const struct qcom_icc_desc sm8650_lpass_lpiaon_noc =3D { + .alloc_dyn_id =3D true, .config =3D &icc_regmap_config, .nodes =3D lpass_lpiaon_noc_nodes, .num_nodes =3D ARRAY_SIZE(lpass_lpiaon_noc_nodes), @@ -1864,6 +1811,7 @@ static struct qcom_icc_node * const lpass_lpicx_noc_n= odes[] =3D { }; =20 static const struct qcom_icc_desc sm8650_lpass_lpicx_noc =3D { + .alloc_dyn_id =3D true, .config =3D &icc_regmap_config, .nodes =3D lpass_lpicx_noc_nodes, .num_nodes =3D ARRAY_SIZE(lpass_lpicx_noc_nodes), @@ -1880,6 +1828,7 @@ static struct qcom_icc_node * const mc_virt_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sm8650_mc_virt =3D { + .alloc_dyn_id =3D true, .nodes =3D mc_virt_nodes, .num_nodes =3D ARRAY_SIZE(mc_virt_nodes), .bcms =3D mc_virt_bcms, @@ -1908,6 +1857,7 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sm8650_mmss_noc =3D { + .alloc_dyn_id =3D true, .config =3D &icc_regmap_config, .nodes =3D mmss_noc_nodes, .num_nodes =3D ARRAY_SIZE(mmss_noc_nodes), @@ -1925,6 +1875,7 @@ static struct qcom_icc_node * const nsp_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sm8650_nsp_noc =3D { + .alloc_dyn_id =3D true, .config =3D &icc_regmap_config, .nodes =3D nsp_noc_nodes, .num_nodes =3D ARRAY_SIZE(nsp_noc_nodes), @@ -1945,6 +1896,7 @@ static struct qcom_icc_node * const pcie_anoc_nodes[]= =3D { }; =20 static const struct qcom_icc_desc sm8650_pcie_anoc =3D { + .alloc_dyn_id =3D true, .config =3D &icc_regmap_config, .nodes =3D pcie_anoc_nodes, .num_nodes =3D ARRAY_SIZE(pcie_anoc_nodes), @@ -1966,6 +1918,7 @@ static struct qcom_icc_node * const system_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sm8650_system_noc =3D { + .alloc_dyn_id =3D true, .config =3D &icc_regmap_config, .nodes =3D system_noc_nodes, .num_nodes =3D ARRAY_SIZE(system_noc_nodes), diff --git a/drivers/interconnect/qcom/sm8650.h b/drivers/interconnect/qcom= /sm8650.h deleted file mode 100644 index b6610225b38acce12c47046769bb0460a1ae4229..000000000000000000000000000= 0000000000000 --- a/drivers/interconnect/qcom/sm8650.h +++ /dev/null @@ -1,144 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * SM8650 interconnect IDs - * - * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2023, Linaro Limited - */ - -#ifndef __DRIVERS_INTERCONNECT_QCOM_SM8650_H -#define __DRIVERS_INTERCONNECT_QCOM_SM8650_H - -#define SM8650_MASTER_A1NOC_SNOC 0 -#define SM8650_MASTER_A2NOC_SNOC 1 -#define SM8650_MASTER_ANOC_PCIE_GEM_NOC 2 -#define SM8650_MASTER_APPSS_PROC 3 -#define SM8650_MASTER_CAMNOC_HF 4 -#define SM8650_MASTER_CAMNOC_ICP 5 -#define SM8650_MASTER_CAMNOC_SF 6 -#define SM8650_MASTER_CDSP_HCP 7 -#define SM8650_MASTER_CDSP_PROC 8 -#define SM8650_MASTER_CNOC_CFG 9 -#define SM8650_MASTER_CNOC_MNOC_CFG 10 -#define SM8650_MASTER_COMPUTE_NOC 11 -#define SM8650_MASTER_CRYPTO 12 -#define SM8650_MASTER_GEM_NOC_CNOC 13 -#define SM8650_MASTER_GEM_NOC_PCIE_SNOC 14 -#define SM8650_MASTER_GFX3D 15 -#define SM8650_MASTER_GIC 16 -#define SM8650_MASTER_GPU_TCU 17 -#define SM8650_MASTER_IPA 18 -#define SM8650_MASTER_LLCC 19 -#define SM8650_MASTER_LPASS_GEM_NOC 20 -#define SM8650_MASTER_LPASS_LPINOC 21 -#define SM8650_MASTER_LPASS_PROC 22 -#define SM8650_MASTER_LPIAON_NOC 23 -#define SM8650_MASTER_MDP 24 -#define SM8650_MASTER_MNOC_HF_MEM_NOC 25 -#define SM8650_MASTER_MNOC_SF_MEM_NOC 26 -#define SM8650_MASTER_MSS_PROC 27 -#define SM8650_MASTER_PCIE_0 28 -#define SM8650_MASTER_PCIE_1 29 -#define SM8650_MASTER_PCIE_ANOC_CFG 30 -#define SM8650_MASTER_QDSS_BAM 31 -#define SM8650_MASTER_QDSS_ETR 32 -#define SM8650_MASTER_QDSS_ETR_1 33 -#define SM8650_MASTER_QSPI_0 34 -#define SM8650_MASTER_QUP_1 35 -#define SM8650_MASTER_QUP_2 36 -#define SM8650_MASTER_QUP_3 37 -#define SM8650_MASTER_QUP_CORE_0 38 -#define SM8650_MASTER_QUP_CORE_1 39 -#define SM8650_MASTER_QUP_CORE_2 40 -#define SM8650_MASTER_SDCC_2 41 -#define SM8650_MASTER_SDCC_4 42 -#define SM8650_MASTER_SNOC_SF_MEM_NOC 43 -#define SM8650_MASTER_SP 44 -#define SM8650_MASTER_SYS_TCU 45 -#define SM8650_MASTER_UBWC_P 46 -#define SM8650_MASTER_UBWC_P_TCU 47 -#define SM8650_MASTER_UFS_MEM 48 -#define SM8650_MASTER_USB3_0 49 -#define SM8650_MASTER_VIDEO 50 -#define SM8650_MASTER_VIDEO_CV_PROC 51 -#define SM8650_MASTER_VIDEO_PROC 52 -#define SM8650_MASTER_VIDEO_V_PROC 53 -#define SM8650_SLAVE_A1NOC_SNOC 54 -#define SM8650_SLAVE_A2NOC_SNOC 55 -#define SM8650_SLAVE_AHB2PHY_NORTH 56 -#define SM8650_SLAVE_AHB2PHY_SOUTH 57 -#define SM8650_SLAVE_ANOC_PCIE_GEM_NOC 58 -#define SM8650_SLAVE_AOSS 59 -#define SM8650_SLAVE_APPSS 60 -#define SM8650_SLAVE_CAMERA_CFG 61 -#define SM8650_SLAVE_CDSP_MEM_NOC 62 -#define SM8650_SLAVE_CLK_CTL 63 -#define SM8650_SLAVE_CNOC_CFG 64 -#define SM8650_SLAVE_CNOC_MNOC_CFG 65 -#define SM8650_SLAVE_CNOC_MSS 66 -#define SM8650_SLAVE_CPR_HMX 67 -#define SM8650_SLAVE_CPR_NSPCX 68 -#define SM8650_SLAVE_CRYPTO_0_CFG 69 -#define SM8650_SLAVE_CX_RDPM 70 -#define SM8650_SLAVE_DDRSS_CFG 71 -#define SM8650_SLAVE_DISPLAY_CFG 72 -#define SM8650_SLAVE_EBI1 73 -#define SM8650_SLAVE_GEM_NOC_CNOC 74 -#define SM8650_SLAVE_GFX3D_CFG 75 -#define SM8650_SLAVE_I2C 76 -#define SM8650_SLAVE_I3C_IBI0_CFG 77 -#define SM8650_SLAVE_I3C_IBI1_CFG 78 -#define SM8650_SLAVE_IMEM 79 -#define SM8650_SLAVE_IMEM_CFG 80 -#define SM8650_SLAVE_IPA_CFG 81 -#define SM8650_SLAVE_IPC_ROUTER_CFG 82 -#define SM8650_SLAVE_LLCC 83 -#define SM8650_SLAVE_LPASS_GEM_NOC 84 -#define SM8650_SLAVE_LPIAON_NOC_LPASS_AG_NOC 85 -#define SM8650_SLAVE_LPICX_NOC_LPIAON_NOC 86 -#define SM8650_SLAVE_MEM_NOC_PCIE_SNOC 87 -#define SM8650_SLAVE_MNOC_HF_MEM_NOC 88 -#define SM8650_SLAVE_MNOC_SF_MEM_NOC 89 -#define SM8650_SLAVE_MX_2_RDPM 90 -#define SM8650_SLAVE_MX_RDPM 91 -#define SM8650_SLAVE_NSP_QTB_CFG 92 -#define SM8650_SLAVE_PCIE_0 93 -#define SM8650_SLAVE_PCIE_1 94 -#define SM8650_SLAVE_PCIE_0_CFG 95 -#define SM8650_SLAVE_PCIE_1_CFG 96 -#define SM8650_SLAVE_PCIE_ANOC_CFG 97 -#define SM8650_SLAVE_PCIE_RSCC 98 -#define SM8650_SLAVE_PDM 99 -#define SM8650_SLAVE_PRNG 100 -#define SM8650_SLAVE_QDSS_CFG 101 -#define SM8650_SLAVE_QDSS_STM 102 -#define SM8650_SLAVE_QSPI_0 103 -#define SM8650_SLAVE_QUP_1 104 -#define SM8650_SLAVE_QUP_2 105 -#define SM8650_SLAVE_QUP_3 106 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This gives more flexibility and also allows us to drop the .num_links member, saving from possible errors related to it being not set or set incorrectly. Signed-off-by: Dmitry Baryshkov --- drivers/interconnect/qcom/sm8750.c | 616 ++++++++++++++-------------------= ---- 1 file changed, 230 insertions(+), 386 deletions(-) diff --git a/drivers/interconnect/qcom/sm8750.c b/drivers/interconnect/qcom= /sm8750.c index 69bc22222075280365eb419f1ad140d1aa4e752d..a46c1553ce0fd13b99a7d327eb5= 75b232bc36509 100644 --- a/drivers/interconnect/qcom/sm8750.c +++ b/drivers/interconnect/qcom/sm8750.c @@ -14,1181 +14,1011 @@ #include "bcm-voter.h" #include "icc-rpmh.h" =20 -#define SM8750_MASTER_GPU_TCU 0 -#define SM8750_MASTER_SYS_TCU 1 -#define SM8750_MASTER_APPSS_PROC 2 -#define SM8750_MASTER_LLCC 3 -#define SM8750_MASTER_QDSS_BAM 4 -#define SM8750_MASTER_QSPI_0 5 -#define SM8750_MASTER_QUP_1 6 -#define SM8750_MASTER_QUP_2 7 -#define SM8750_MASTER_A1NOC_SNOC 8 -#define SM8750_MASTER_A2NOC_SNOC 9 -#define SM8750_MASTER_CAMNOC_HF 10 -#define SM8750_MASTER_CAMNOC_NRT_ICP_SF 11 -#define SM8750_MASTER_CAMNOC_RT_CDM_SF 12 -#define SM8750_MASTER_CAMNOC_SF 13 -#define SM8750_MASTER_GEM_NOC_CNOC 14 -#define SM8750_MASTER_GEM_NOC_PCIE_SNOC 15 -#define SM8750_MASTER_GFX3D 16 -#define SM8750_MASTER_LPASS_GEM_NOC 17 -#define SM8750_MASTER_LPASS_LPINOC 18 -#define SM8750_MASTER_LPIAON_NOC 19 -#define SM8750_MASTER_LPASS_PROC 20 -#define SM8750_MASTER_MDP 21 -#define SM8750_MASTER_MSS_PROC 22 -#define SM8750_MASTER_MNOC_HF_MEM_NOC 23 -#define SM8750_MASTER_MNOC_SF_MEM_NOC 24 -#define SM8750_MASTER_CDSP_PROC 25 -#define SM8750_MASTER_COMPUTE_NOC 26 -#define SM8750_MASTER_ANOC_PCIE_GEM_NOC 27 -#define SM8750_MASTER_SNOC_SF_MEM_NOC 28 -#define SM8750_MASTER_UBWC_P 29 -#define SM8750_MASTER_CDSP_HCP 30 -#define SM8750_MASTER_VIDEO_CV_PROC 31 -#define SM8750_MASTER_VIDEO_EVA 32 -#define SM8750_MASTER_VIDEO_MVP 33 -#define SM8750_MASTER_VIDEO_V_PROC 34 -#define SM8750_MASTER_CNOC_CFG 35 -#define SM8750_MASTER_CNOC_MNOC_CFG 36 -#define SM8750_MASTER_PCIE_ANOC_CFG 37 -#define SM8750_MASTER_QUP_CORE_0 38 -#define SM8750_MASTER_QUP_CORE_1 39 -#define SM8750_MASTER_QUP_CORE_2 40 -#define SM8750_MASTER_CRYPTO 41 -#define SM8750_MASTER_IPA 42 -#define SM8750_MASTER_QUP_3 43 -#define SM8750_MASTER_SOCCP_AGGR_NOC 44 -#define SM8750_MASTER_SP 45 -#define SM8750_MASTER_GIC 46 -#define SM8750_MASTER_PCIE_0 47 -#define SM8750_MASTER_QDSS_ETR 48 -#define SM8750_MASTER_QDSS_ETR_1 49 -#define SM8750_MASTER_SDCC_2 50 -#define SM8750_MASTER_SDCC_4 51 -#define SM8750_MASTER_UFS_MEM 52 -#define SM8750_MASTER_USB3_0 53 -#define SM8750_SLAVE_UBWC_P 54 -#define SM8750_SLAVE_EBI1 55 -#define SM8750_SLAVE_AHB2PHY_SOUTH 56 -#define SM8750_SLAVE_AHB2PHY_NORTH 57 -#define SM8750_SLAVE_AOSS 58 -#define SM8750_SLAVE_CAMERA_CFG 59 -#define SM8750_SLAVE_CLK_CTL 60 -#define SM8750_SLAVE_CRYPTO_0_CFG 61 -#define SM8750_SLAVE_DISPLAY_CFG 62 -#define SM8750_SLAVE_EVA_CFG 63 -#define SM8750_SLAVE_GFX3D_CFG 64 -#define SM8750_SLAVE_I2C 65 -#define SM8750_SLAVE_I3C_IBI0_CFG 66 -#define SM8750_SLAVE_I3C_IBI1_CFG 67 -#define SM8750_SLAVE_IMEM_CFG 68 -#define SM8750_SLAVE_IPA_CFG 69 -#define SM8750_SLAVE_IPC_ROUTER_CFG 70 -#define SM8750_SLAVE_CNOC_MSS 71 -#define SM8750_SLAVE_PCIE_CFG 72 -#define SM8750_SLAVE_PRNG 73 -#define SM8750_SLAVE_QDSS_CFG 74 -#define SM8750_SLAVE_QSPI_0 75 -#define SM8750_SLAVE_QUP_3 76 -#define SM8750_SLAVE_QUP_1 77 -#define SM8750_SLAVE_QUP_2 78 -#define SM8750_SLAVE_SDCC_2 79 -#define SM8750_SLAVE_SDCC_4 80 -#define SM8750_SLAVE_SOCCP 81 -#define SM8750_SLAVE_SPSS_CFG 82 -#define SM8750_SLAVE_TCSR 83 -#define SM8750_SLAVE_TLMM 84 -#define SM8750_SLAVE_TME_CFG 85 -#define SM8750_SLAVE_UFS_MEM_CFG 86 -#define SM8750_SLAVE_USB3_0 87 -#define SM8750_SLAVE_VENUS_CFG 88 -#define SM8750_SLAVE_VSENSE_CTRL_CFG 89 -#define SM8750_SLAVE_A1NOC_SNOC 90 -#define SM8750_SLAVE_A2NOC_SNOC 91 -#define SM8750_SLAVE_APPSS 92 -#define SM8750_SLAVE_GEM_NOC_CNOC 93 -#define SM8750_SLAVE_SNOC_GEM_NOC_SF 94 -#define SM8750_SLAVE_LLCC 95 -#define SM8750_SLAVE_LPASS_GEM_NOC 96 -#define SM8750_SLAVE_LPIAON_NOC_LPASS_AG_NOC 97 -#define SM8750_SLAVE_LPICX_NOC_LPIAON_NOC 98 -#define SM8750_SLAVE_MNOC_HF_MEM_NOC 99 -#define SM8750_SLAVE_MNOC_SF_MEM_NOC 100 -#define SM8750_SLAVE_CDSP_MEM_NOC 101 -#define SM8750_SLAVE_MEM_NOC_PCIE_SNOC 102 -#define SM8750_SLAVE_ANOC_PCIE_GEM_NOC 103 -#define SM8750_SLAVE_CNOC_CFG 104 -#define SM8750_SLAVE_DDRSS_CFG 105 -#define SM8750_SLAVE_CNOC_MNOC_CFG 106 -#define SM8750_SLAVE_PCIE_ANOC_CFG 107 -#define SM8750_SLAVE_QUP_CORE_0 108 -#define SM8750_SLAVE_QUP_CORE_1 109 -#define SM8750_SLAVE_QUP_CORE_2 110 -#define SM8750_SLAVE_BOOT_IMEM 111 -#define SM8750_SLAVE_IMEM 112 -#define SM8750_SLAVE_BOOT_IMEM_2 113 -#define SM8750_SLAVE_SERVICE_CNOC 114 -#define SM8750_SLAVE_SERVICE_MNOC 115 -#define SM8750_SLAVE_SERVICE_PCIE_ANOC 116 -#define SM8750_SLAVE_PCIE_0 117 -#define SM8750_SLAVE_QDSS_STM 118 -#define SM8750_SLAVE_TCU 119 +static struct qcom_icc_node qhm_qspi; +static struct qcom_icc_node qhm_qup1; +static struct qcom_icc_node qxm_qup02; +static struct qcom_icc_node xm_sdc4; +static struct qcom_icc_node xm_ufs_mem; +static struct qcom_icc_node xm_usb3_0; +static struct qcom_icc_node qhm_qdss_bam; +static struct qcom_icc_node qhm_qup2; +static struct qcom_icc_node qxm_crypto; +static struct qcom_icc_node qxm_ipa; +static struct qcom_icc_node qxm_soccp; +static struct qcom_icc_node qxm_sp; +static struct qcom_icc_node xm_qdss_etr_0; +static struct qcom_icc_node xm_qdss_etr_1; +static struct qcom_icc_node xm_sdc2; +static struct qcom_icc_node qup0_core_master; +static struct qcom_icc_node qup1_core_master; +static struct qcom_icc_node qup2_core_master; +static struct qcom_icc_node qsm_cfg; +static struct qcom_icc_node qnm_gemnoc_cnoc; +static struct qcom_icc_node qnm_gemnoc_pcie; +static struct qcom_icc_node alm_gpu_tcu; +static struct qcom_icc_node alm_sys_tcu; +static struct qcom_icc_node chm_apps; +static struct qcom_icc_node qnm_gpu; +static struct qcom_icc_node qnm_lpass_gemnoc; +static struct qcom_icc_node qnm_mdsp; +static struct qcom_icc_node qnm_mnoc_hf; +static struct qcom_icc_node qnm_mnoc_sf; +static struct qcom_icc_node qnm_nsp_gemnoc; +static struct qcom_icc_node qnm_pcie; +static struct qcom_icc_node qnm_snoc_sf; +static struct qcom_icc_node qnm_ubwc_p; +static struct qcom_icc_node xm_gic; +static struct qcom_icc_node qnm_lpiaon_noc; +static struct qcom_icc_node qnm_lpass_lpinoc; +static struct qcom_icc_node qnm_lpinoc_dsp_qns4m; +static struct qcom_icc_node llcc_mc; +static struct qcom_icc_node qnm_camnoc_hf; +static struct qcom_icc_node qnm_camnoc_nrt_icp_sf; +static struct qcom_icc_node qnm_camnoc_rt_cdm_sf; +static struct qcom_icc_node qnm_camnoc_sf; +static struct qcom_icc_node qnm_mdp; +static struct qcom_icc_node qnm_vapss_hcp; +static struct qcom_icc_node qnm_video_cv_cpu; +static struct qcom_icc_node qnm_video_eva; +static struct qcom_icc_node qnm_video_mvp; +static struct qcom_icc_node qnm_video_v_cpu; +static struct qcom_icc_node qsm_mnoc_cfg; +static struct qcom_icc_node qnm_nsp; +static struct qcom_icc_node qsm_pcie_anoc_cfg; +static struct qcom_icc_node xm_pcie3; +static struct qcom_icc_node qnm_aggre1_noc; +static struct qcom_icc_node qnm_aggre2_noc; +static struct qcom_icc_node qns_a1noc_snoc; +static struct qcom_icc_node qns_a2noc_snoc; +static struct qcom_icc_node qup0_core_slave; +static struct qcom_icc_node qup1_core_slave; +static struct qcom_icc_node qup2_core_slave; +static struct qcom_icc_node qhs_ahb2phy0; +static struct qcom_icc_node qhs_ahb2phy1; +static struct qcom_icc_node qhs_camera_cfg; +static struct qcom_icc_node qhs_clk_ctl; +static struct qcom_icc_node qhs_crypto0_cfg; +static struct qcom_icc_node qhs_display_cfg; +static struct qcom_icc_node qhs_eva_cfg; +static struct qcom_icc_node qhs_gpuss_cfg; +static struct qcom_icc_node qhs_i2c; +static struct qcom_icc_node qhs_i3c_ibi0_cfg; +static struct qcom_icc_node qhs_i3c_ibi1_cfg; +static struct qcom_icc_node qhs_imem_cfg; +static struct qcom_icc_node qhs_mss_cfg; +static struct qcom_icc_node qhs_pcie_cfg; +static struct qcom_icc_node qhs_prng; +static struct qcom_icc_node qhs_qdss_cfg; +static struct qcom_icc_node qhs_qspi; +static struct qcom_icc_node qhs_qup02; +static struct qcom_icc_node qhs_qup1; +static struct qcom_icc_node qhs_qup2; +static struct qcom_icc_node qhs_sdc2; +static struct qcom_icc_node qhs_sdc4; +static struct qcom_icc_node qhs_spss_cfg; +static struct qcom_icc_node qhs_tcsr; +static struct qcom_icc_node qhs_tlmm; +static struct qcom_icc_node qhs_ufs_mem_cfg; +static struct qcom_icc_node qhs_usb3_0; +static struct qcom_icc_node qhs_venus_cfg; +static struct qcom_icc_node qhs_vsense_ctrl_cfg; +static struct qcom_icc_node qss_mnoc_cfg; +static struct qcom_icc_node qss_pcie_anoc_cfg; +static struct qcom_icc_node xs_qdss_stm; +static struct qcom_icc_node xs_sys_tcu_cfg; +static struct qcom_icc_node qhs_aoss; +static struct qcom_icc_node qhs_ipa; +static struct qcom_icc_node qhs_ipc_router; +static struct qcom_icc_node qhs_soccp; +static struct qcom_icc_node qhs_tme_cfg; +static struct qcom_icc_node qns_apss; +static struct qcom_icc_node qss_cfg; +static struct qcom_icc_node qss_ddrss_cfg; +static struct qcom_icc_node qxs_boot_imem; +static struct qcom_icc_node qxs_imem; +static struct qcom_icc_node qxs_modem_boot_imem; +static struct qcom_icc_node srvc_cnoc_main; +static struct qcom_icc_node xs_pcie; +static struct qcom_icc_node chs_ubwc_p; +static struct qcom_icc_node qns_gem_noc_cnoc; +static struct qcom_icc_node qns_llcc; +static struct qcom_icc_node qns_pcie; +static struct qcom_icc_node qns_lpass_ag_noc_gemnoc; +static struct qcom_icc_node qns_lpass_aggnoc; +static struct qcom_icc_node qns_lpi_aon_noc; +static struct qcom_icc_node ebi; +static struct qcom_icc_node qns_mem_noc_hf; +static struct qcom_icc_node qns_mem_noc_sf; +static struct qcom_icc_node srvc_mnoc; +static struct qcom_icc_node qns_nsp_gemnoc; +static struct qcom_icc_node qns_pcie_mem_noc; +static struct qcom_icc_node srvc_pcie_aggre_noc; +static struct qcom_icc_node qns_gemnoc_sf; =20 static struct qcom_icc_node qhm_qspi =3D { .name =3D "qhm_qspi", - .id =3D SM8750_MASTER_QSPI_0, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8750_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node qhm_qup1 =3D { .name =3D "qhm_qup1", - .id =3D SM8750_MASTER_QUP_1, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8750_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node qxm_qup02 =3D { .name =3D "qxm_qup02", - .id =3D SM8750_MASTER_QUP_3, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8750_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node xm_sdc4 =3D { .name =3D "xm_sdc4", - .id =3D SM8750_MASTER_SDCC_4, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8750_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node xm_ufs_mem =3D { .name =3D "xm_ufs_mem", - .id =3D SM8750_MASTER_UFS_MEM, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM8750_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node xm_usb3_0 =3D { .name =3D "xm_usb3_0", - .id =3D SM8750_MASTER_USB3_0, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8750_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc }, }; =20 static struct qcom_icc_node qhm_qdss_bam =3D { .name =3D "qhm_qdss_bam", - .id =3D SM8750_MASTER_QDSS_BAM, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8750_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qhm_qup2 =3D { .name =3D "qhm_qup2", - .id =3D SM8750_MASTER_QUP_2, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8750_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qxm_crypto =3D { .name =3D "qxm_crypto", - .id =3D SM8750_MASTER_CRYPTO, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8750_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qxm_ipa =3D { .name =3D "qxm_ipa", - .id =3D SM8750_MASTER_IPA, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8750_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qxm_soccp =3D { .name =3D "qxm_soccp", - .id =3D SM8750_MASTER_SOCCP_AGGR_NOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8750_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qxm_sp =3D { .name =3D "qxm_sp", - .id =3D SM8750_MASTER_SP, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8750_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node xm_qdss_etr_0 =3D { .name =3D "xm_qdss_etr_0", - .id =3D SM8750_MASTER_QDSS_ETR, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8750_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node xm_qdss_etr_1 =3D { .name =3D "xm_qdss_etr_1", - .id =3D SM8750_MASTER_QDSS_ETR_1, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8750_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node xm_sdc2 =3D { .name =3D "xm_sdc2", - .id =3D SM8750_MASTER_SDCC_2, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8750_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc }, }; =20 static struct qcom_icc_node qup0_core_master =3D { .name =3D "qup0_core_master", - .id =3D SM8750_MASTER_QUP_CORE_0, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8750_SLAVE_QUP_CORE_0 }, + .link_nodes =3D { &qup0_core_slave }, }; =20 static struct qcom_icc_node qup1_core_master =3D { .name =3D "qup1_core_master", - .id =3D SM8750_MASTER_QUP_CORE_1, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8750_SLAVE_QUP_CORE_1 }, + .link_nodes =3D { &qup1_core_slave }, }; =20 static struct qcom_icc_node qup2_core_master =3D { .name =3D "qup2_core_master", - .id =3D SM8750_MASTER_QUP_CORE_2, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8750_SLAVE_QUP_CORE_2 }, + .link_nodes =3D { &qup2_core_slave }, }; =20 static struct qcom_icc_node qsm_cfg =3D { .name =3D "qsm_cfg", - .id =3D SM8750_MASTER_CNOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 33, - .links =3D { SM8750_SLAVE_AHB2PHY_SOUTH, SM8750_SLAVE_AHB2PHY_NORTH, - SM8750_SLAVE_CAMERA_CFG, SM8750_SLAVE_CLK_CTL, - SM8750_SLAVE_CRYPTO_0_CFG, SM8750_SLAVE_DISPLAY_CFG, - SM8750_SLAVE_EVA_CFG, SM8750_SLAVE_GFX3D_CFG, - SM8750_SLAVE_I2C, SM8750_SLAVE_I3C_IBI0_CFG, - SM8750_SLAVE_I3C_IBI1_CFG, SM8750_SLAVE_IMEM_CFG, - SM8750_SLAVE_CNOC_MSS, SM8750_SLAVE_PCIE_CFG, - SM8750_SLAVE_PRNG, SM8750_SLAVE_QDSS_CFG, - SM8750_SLAVE_QSPI_0, SM8750_SLAVE_QUP_3, - SM8750_SLAVE_QUP_1, SM8750_SLAVE_QUP_2, - SM8750_SLAVE_SDCC_2, SM8750_SLAVE_SDCC_4, - SM8750_SLAVE_SPSS_CFG, SM8750_SLAVE_TCSR, - SM8750_SLAVE_TLMM, SM8750_SLAVE_UFS_MEM_CFG, - SM8750_SLAVE_USB3_0, SM8750_SLAVE_VENUS_CFG, - SM8750_SLAVE_VSENSE_CTRL_CFG, SM8750_SLAVE_CNOC_MNOC_CFG, - SM8750_SLAVE_PCIE_ANOC_CFG, SM8750_SLAVE_QDSS_STM, - SM8750_SLAVE_TCU }, + .link_nodes =3D { &qhs_ahb2phy0, &qhs_ahb2phy1, + &qhs_camera_cfg, &qhs_clk_ctl, + &qhs_crypto0_cfg, &qhs_display_cfg, + &qhs_eva_cfg, &qhs_gpuss_cfg, + &qhs_i2c, &qhs_i3c_ibi0_cfg, + &qhs_i3c_ibi1_cfg, &qhs_imem_cfg, + &qhs_mss_cfg, &qhs_pcie_cfg, + &qhs_prng, &qhs_qdss_cfg, + &qhs_qspi, &qhs_qup02, + &qhs_qup1, &qhs_qup2, + &qhs_sdc2, &qhs_sdc4, + &qhs_spss_cfg, &qhs_tcsr, + &qhs_tlmm, &qhs_ufs_mem_cfg, + &qhs_usb3_0, &qhs_venus_cfg, + &qhs_vsense_ctrl_cfg, &qss_mnoc_cfg, + &qss_pcie_anoc_cfg, &xs_qdss_stm, + &xs_sys_tcu_cfg }, }; =20 static struct qcom_icc_node qnm_gemnoc_cnoc =3D { .name =3D "qnm_gemnoc_cnoc", - .id =3D SM8750_MASTER_GEM_NOC_CNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 12, - .links =3D { SM8750_SLAVE_AOSS, SM8750_SLAVE_IPA_CFG, - SM8750_SLAVE_IPC_ROUTER_CFG, SM8750_SLAVE_SOCCP, - SM8750_SLAVE_TME_CFG, SM8750_SLAVE_APPSS, - SM8750_SLAVE_CNOC_CFG, SM8750_SLAVE_DDRSS_CFG, - SM8750_SLAVE_BOOT_IMEM, SM8750_SLAVE_IMEM, - SM8750_SLAVE_BOOT_IMEM_2, SM8750_SLAVE_SERVICE_CNOC }, + .link_nodes =3D { &qhs_aoss, &qhs_ipa, + &qhs_ipc_router, &qhs_soccp, + &qhs_tme_cfg, &qns_apss, + &qss_cfg, &qss_ddrss_cfg, + &qxs_boot_imem, &qxs_imem, + &qxs_modem_boot_imem, &srvc_cnoc_main }, }; =20 static struct qcom_icc_node qnm_gemnoc_pcie =3D { .name =3D "qnm_gemnoc_pcie", - .id =3D SM8750_MASTER_GEM_NOC_PCIE_SNOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8750_SLAVE_PCIE_0 }, + .link_nodes =3D { &xs_pcie }, }; =20 static struct qcom_icc_node alm_gpu_tcu =3D { .name =3D "alm_gpu_tcu", - .id =3D SM8750_MASTER_GPU_TCU, .channels =3D 1, .buswidth =3D 8, .num_links =3D 2, - .links =3D { SM8750_SLAVE_GEM_NOC_CNOC, SM8750_SLAVE_LLCC }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; =20 static struct qcom_icc_node alm_sys_tcu =3D { .name =3D "alm_sys_tcu", - .id =3D SM8750_MASTER_SYS_TCU, .channels =3D 1, .buswidth =3D 8, .num_links =3D 2, - .links =3D { SM8750_SLAVE_GEM_NOC_CNOC, SM8750_SLAVE_LLCC }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; =20 static struct qcom_icc_node chm_apps =3D { .name =3D "chm_apps", - .id =3D SM8750_MASTER_APPSS_PROC, .channels =3D 4, .buswidth =3D 32, .num_links =3D 4, - .links =3D { SM8750_SLAVE_UBWC_P, SM8750_SLAVE_GEM_NOC_CNOC, - SM8750_SLAVE_LLCC, SM8750_SLAVE_MEM_NOC_PCIE_SNOC }, + .link_nodes =3D { &chs_ubwc_p, &qns_gem_noc_cnoc, + &qns_llcc, &qns_pcie }, }; =20 static struct qcom_icc_node qnm_gpu =3D { .name =3D "qnm_gpu", - .id =3D SM8750_MASTER_GFX3D, .channels =3D 2, .buswidth =3D 32, .num_links =3D 2, - .links =3D { SM8750_SLAVE_GEM_NOC_CNOC, SM8750_SLAVE_LLCC }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; =20 static struct qcom_icc_node qnm_lpass_gemnoc =3D { .name =3D "qnm_lpass_gemnoc", - .id =3D SM8750_MASTER_LPASS_GEM_NOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 3, - .links =3D { SM8750_SLAVE_GEM_NOC_CNOC, SM8750_SLAVE_LLCC, - SM8750_SLAVE_MEM_NOC_PCIE_SNOC }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, }; =20 static struct qcom_icc_node qnm_mdsp =3D { .name =3D "qnm_mdsp", - .id =3D SM8750_MASTER_MSS_PROC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 3, - .links =3D { SM8750_SLAVE_GEM_NOC_CNOC, SM8750_SLAVE_LLCC, - SM8750_SLAVE_MEM_NOC_PCIE_SNOC }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, }; =20 static struct qcom_icc_node qnm_mnoc_hf =3D { .name =3D "qnm_mnoc_hf", - .id =3D SM8750_MASTER_MNOC_HF_MEM_NOC, .channels =3D 2, .buswidth =3D 32, .num_links =3D 2, - .links =3D { SM8750_SLAVE_GEM_NOC_CNOC, SM8750_SLAVE_LLCC }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; =20 static struct qcom_icc_node qnm_mnoc_sf =3D { .name =3D "qnm_mnoc_sf", - .id =3D SM8750_MASTER_MNOC_SF_MEM_NOC, .channels =3D 2, .buswidth =3D 32, .num_links =3D 2, - .links =3D { SM8750_SLAVE_GEM_NOC_CNOC, SM8750_SLAVE_LLCC }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; =20 static struct qcom_icc_node qnm_nsp_gemnoc =3D { .name =3D "qnm_nsp_gemnoc", - .id =3D SM8750_MASTER_COMPUTE_NOC, .channels =3D 2, .buswidth =3D 32, .num_links =3D 3, - .links =3D { SM8750_SLAVE_GEM_NOC_CNOC, SM8750_SLAVE_LLCC, - SM8750_SLAVE_MEM_NOC_PCIE_SNOC }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, }; =20 static struct qcom_icc_node qnm_pcie =3D { .name =3D "qnm_pcie", - .id =3D SM8750_MASTER_ANOC_PCIE_GEM_NOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 2, - .links =3D { SM8750_SLAVE_GEM_NOC_CNOC, SM8750_SLAVE_LLCC }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc }, }; =20 static struct qcom_icc_node qnm_snoc_sf =3D { .name =3D "qnm_snoc_sf", - .id =3D SM8750_MASTER_SNOC_SF_MEM_NOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 3, - .links =3D { SM8750_SLAVE_GEM_NOC_CNOC, SM8750_SLAVE_LLCC, - SM8750_SLAVE_MEM_NOC_PCIE_SNOC }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, }; =20 static struct qcom_icc_node qnm_ubwc_p =3D { .name =3D "qnm_ubwc_p", - .id =3D SM8750_MASTER_UBWC_P, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8750_SLAVE_LLCC }, + .link_nodes =3D { &qns_llcc }, }; =20 static struct qcom_icc_node xm_gic =3D { .name =3D "xm_gic", - .id =3D SM8750_MASTER_GIC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8750_SLAVE_LLCC }, + .link_nodes =3D { &qns_llcc }, }; =20 static struct qcom_icc_node qnm_lpiaon_noc =3D { .name =3D "qnm_lpiaon_noc", - .id =3D SM8750_MASTER_LPIAON_NOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM8750_SLAVE_LPASS_GEM_NOC }, + .link_nodes =3D { &qns_lpass_ag_noc_gemnoc }, }; =20 static struct qcom_icc_node qnm_lpass_lpinoc =3D { .name =3D "qnm_lpass_lpinoc", - .id =3D SM8750_MASTER_LPASS_LPINOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM8750_SLAVE_LPIAON_NOC_LPASS_AG_NOC }, + .link_nodes =3D { &qns_lpass_aggnoc }, }; =20 static struct qcom_icc_node qnm_lpinoc_dsp_qns4m =3D { .name =3D "qnm_lpinoc_dsp_qns4m", - .id =3D SM8750_MASTER_LPASS_PROC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM8750_SLAVE_LPICX_NOC_LPIAON_NOC }, + .link_nodes =3D { &qns_lpi_aon_noc }, }; =20 static struct qcom_icc_node llcc_mc =3D { .name =3D "llcc_mc", - .id =3D SM8750_MASTER_LLCC, .channels =3D 4, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8750_SLAVE_EBI1 }, + .link_nodes =3D { &ebi }, }; =20 static struct qcom_icc_node qnm_camnoc_hf =3D { .name =3D "qnm_camnoc_hf", - .id =3D SM8750_MASTER_CAMNOC_HF, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8750_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_hf }, }; =20 static struct qcom_icc_node qnm_camnoc_nrt_icp_sf =3D { .name =3D "qnm_camnoc_nrt_icp_sf", - .id =3D SM8750_MASTER_CAMNOC_NRT_ICP_SF, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8750_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static struct qcom_icc_node qnm_camnoc_rt_cdm_sf =3D { .name =3D "qnm_camnoc_rt_cdm_sf", - .id =3D SM8750_MASTER_CAMNOC_RT_CDM_SF, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8750_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static struct qcom_icc_node qnm_camnoc_sf =3D { .name =3D "qnm_camnoc_sf", - .id =3D SM8750_MASTER_CAMNOC_SF, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8750_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static struct qcom_icc_node qnm_mdp =3D { .name =3D "qnm_mdp", - .id =3D SM8750_MASTER_MDP, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8750_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_hf }, }; =20 static struct qcom_icc_node qnm_vapss_hcp =3D { .name =3D "qnm_vapss_hcp", - .id =3D SM8750_MASTER_CDSP_HCP, .channels =3D 1, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8750_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static struct qcom_icc_node qnm_video_cv_cpu =3D { .name =3D "qnm_video_cv_cpu", - .id =3D SM8750_MASTER_VIDEO_CV_PROC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8750_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static struct qcom_icc_node qnm_video_eva =3D { .name =3D "qnm_video_eva", - .id =3D SM8750_MASTER_VIDEO_EVA, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8750_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static struct qcom_icc_node qnm_video_mvp =3D { .name =3D "qnm_video_mvp", - .id =3D SM8750_MASTER_VIDEO_MVP, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8750_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static struct qcom_icc_node qnm_video_v_cpu =3D { .name =3D "qnm_video_v_cpu", - .id =3D SM8750_MASTER_VIDEO_V_PROC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8750_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_sf }, }; =20 static struct qcom_icc_node qsm_mnoc_cfg =3D { .name =3D "qsm_mnoc_cfg", - .id =3D SM8750_MASTER_CNOC_MNOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8750_SLAVE_SERVICE_MNOC }, + .link_nodes =3D { &srvc_mnoc }, }; =20 static struct qcom_icc_node qnm_nsp =3D { .name =3D "qnm_nsp", - .id =3D SM8750_MASTER_CDSP_PROC, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8750_SLAVE_CDSP_MEM_NOC }, + .link_nodes =3D { &qns_nsp_gemnoc }, }; =20 static struct qcom_icc_node qsm_pcie_anoc_cfg =3D { .name =3D "qsm_pcie_anoc_cfg", - .id =3D SM8750_MASTER_PCIE_ANOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8750_SLAVE_SERVICE_PCIE_ANOC }, + .link_nodes =3D { &srvc_pcie_aggre_noc }, }; =20 static struct qcom_icc_node xm_pcie3 =3D { .name =3D "xm_pcie3", - .id =3D SM8750_MASTER_PCIE_0, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8750_SLAVE_ANOC_PCIE_GEM_NOC }, + .link_nodes =3D { &qns_pcie_mem_noc }, }; =20 static struct qcom_icc_node qnm_aggre1_noc =3D { .name =3D "qnm_aggre1_noc", - .id =3D SM8750_MASTER_A1NOC_SNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM8750_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes =3D { &qns_gemnoc_sf }, }; =20 static struct qcom_icc_node qnm_aggre2_noc =3D { .name =3D "qnm_aggre2_noc", - .id =3D SM8750_MASTER_A2NOC_SNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM8750_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes =3D { &qns_gemnoc_sf }, }; =20 static struct qcom_icc_node qns_a1noc_snoc =3D { .name =3D "qns_a1noc_snoc", - .id =3D SM8750_SLAVE_A1NOC_SNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM8750_MASTER_A1NOC_SNOC }, + .link_nodes =3D { &qnm_aggre1_noc }, }; =20 static struct qcom_icc_node qns_a2noc_snoc =3D { .name =3D "qns_a2noc_snoc", - .id =3D SM8750_SLAVE_A2NOC_SNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM8750_MASTER_A2NOC_SNOC }, + .link_nodes =3D { &qnm_aggre2_noc }, }; =20 static struct qcom_icc_node qup0_core_slave =3D { .name =3D "qup0_core_slave", - .id =3D SM8750_SLAVE_QUP_CORE_0, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qup1_core_slave =3D { .name =3D "qup1_core_slave", - .id =3D SM8750_SLAVE_QUP_CORE_1, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qup2_core_slave =3D { .name =3D "qup2_core_slave", - .id =3D SM8750_SLAVE_QUP_CORE_2, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_ahb2phy0 =3D { .name =3D "qhs_ahb2phy0", - .id =3D SM8750_SLAVE_AHB2PHY_SOUTH, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_ahb2phy1 =3D { .name =3D "qhs_ahb2phy1", - .id =3D SM8750_SLAVE_AHB2PHY_NORTH, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_camera_cfg =3D { .name =3D "qhs_camera_cfg", - .id =3D SM8750_SLAVE_CAMERA_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_clk_ctl =3D { .name =3D "qhs_clk_ctl", - .id =3D SM8750_SLAVE_CLK_CTL, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_crypto0_cfg =3D { .name =3D "qhs_crypto0_cfg", - .id =3D SM8750_SLAVE_CRYPTO_0_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_display_cfg =3D { .name =3D "qhs_display_cfg", - .id =3D SM8750_SLAVE_DISPLAY_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_eva_cfg =3D { .name =3D "qhs_eva_cfg", - .id =3D SM8750_SLAVE_EVA_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_gpuss_cfg =3D { .name =3D "qhs_gpuss_cfg", - .id =3D SM8750_SLAVE_GFX3D_CFG, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_i2c =3D { .name =3D "qhs_i2c", - .id =3D SM8750_SLAVE_I2C, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_i3c_ibi0_cfg =3D { .name =3D "qhs_i3c_ibi0_cfg", - .id =3D SM8750_SLAVE_I3C_IBI0_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_i3c_ibi1_cfg =3D { .name =3D "qhs_i3c_ibi1_cfg", - .id =3D SM8750_SLAVE_I3C_IBI1_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_imem_cfg =3D { .name =3D "qhs_imem_cfg", - .id =3D SM8750_SLAVE_IMEM_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_mss_cfg =3D { .name =3D "qhs_mss_cfg", - .id =3D SM8750_SLAVE_CNOC_MSS, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_pcie_cfg =3D { .name =3D "qhs_pcie_cfg", - .id =3D SM8750_SLAVE_PCIE_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_prng =3D { .name =3D "qhs_prng", - .id =3D SM8750_SLAVE_PRNG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_qdss_cfg =3D { .name =3D "qhs_qdss_cfg", - .id =3D SM8750_SLAVE_QDSS_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_qspi =3D { .name =3D "qhs_qspi", - .id =3D SM8750_SLAVE_QSPI_0, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_qup02 =3D { .name =3D "qhs_qup02", - .id =3D SM8750_SLAVE_QUP_3, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_qup1 =3D { .name =3D "qhs_qup1", - .id =3D SM8750_SLAVE_QUP_1, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_qup2 =3D { .name =3D "qhs_qup2", - .id =3D SM8750_SLAVE_QUP_2, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_sdc2 =3D { .name =3D "qhs_sdc2", - .id =3D SM8750_SLAVE_SDCC_2, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_sdc4 =3D { .name =3D "qhs_sdc4", - .id =3D SM8750_SLAVE_SDCC_4, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_spss_cfg =3D { .name =3D "qhs_spss_cfg", - .id =3D SM8750_SLAVE_SPSS_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_tcsr =3D { .name =3D "qhs_tcsr", - .id =3D SM8750_SLAVE_TCSR, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_tlmm =3D { .name =3D "qhs_tlmm", - .id =3D SM8750_SLAVE_TLMM, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_ufs_mem_cfg =3D { .name =3D "qhs_ufs_mem_cfg", - .id =3D SM8750_SLAVE_UFS_MEM_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_usb3_0 =3D { .name =3D "qhs_usb3_0", - .id =3D SM8750_SLAVE_USB3_0, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_venus_cfg =3D { .name =3D "qhs_venus_cfg", - .id =3D SM8750_SLAVE_VENUS_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_vsense_ctrl_cfg =3D { .name =3D "qhs_vsense_ctrl_cfg", - .id =3D SM8750_SLAVE_VSENSE_CTRL_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qss_mnoc_cfg =3D { .name =3D "qss_mnoc_cfg", - .id =3D SM8750_SLAVE_CNOC_MNOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8750_MASTER_CNOC_MNOC_CFG }, + .link_nodes =3D { &qsm_mnoc_cfg }, }; =20 static struct qcom_icc_node qss_pcie_anoc_cfg =3D { .name =3D "qss_pcie_anoc_cfg", - .id =3D SM8750_SLAVE_PCIE_ANOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8750_MASTER_PCIE_ANOC_CFG }, + .link_nodes =3D { &qsm_pcie_anoc_cfg }, }; =20 static struct qcom_icc_node xs_qdss_stm =3D { .name =3D "xs_qdss_stm", - .id =3D SM8750_SLAVE_QDSS_STM, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node xs_sys_tcu_cfg =3D { .name =3D "xs_sys_tcu_cfg", - .id =3D SM8750_SLAVE_TCU, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_aoss =3D { .name =3D "qhs_aoss", - .id =3D SM8750_SLAVE_AOSS, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_ipa =3D { .name =3D "qhs_ipa", - .id =3D SM8750_SLAVE_IPA_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_ipc_router =3D { .name =3D "qhs_ipc_router", - .id =3D SM8750_SLAVE_IPC_ROUTER_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_soccp =3D { .name =3D "qhs_soccp", - .id =3D SM8750_SLAVE_SOCCP, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qhs_tme_cfg =3D { .name =3D "qhs_tme_cfg", - .id =3D SM8750_SLAVE_TME_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qns_apss =3D { .name =3D "qns_apss", - .id =3D SM8750_SLAVE_APPSS, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 0, }; =20 static struct qcom_icc_node qss_cfg =3D { .name =3D "qss_cfg", - .id =3D SM8750_SLAVE_CNOC_CFG, .channels =3D 1, .buswidth =3D 4, .num_links =3D 1, - .links =3D { SM8750_MASTER_CNOC_CFG }, + .link_nodes =3D { &qsm_cfg }, }; =20 static struct qcom_icc_node qss_ddrss_cfg =3D { .name =3D "qss_ddrss_cfg", - .id =3D SM8750_SLAVE_DDRSS_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qxs_boot_imem =3D { .name =3D "qxs_boot_imem", - .id =3D SM8750_SLAVE_BOOT_IMEM, .channels =3D 1, .buswidth =3D 16, - .num_links =3D 0, }; =20 static struct qcom_icc_node qxs_imem =3D { .name =3D "qxs_imem", - .id =3D SM8750_SLAVE_IMEM, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 0, }; =20 static struct qcom_icc_node qxs_modem_boot_imem =3D { .name =3D "qxs_modem_boot_imem", - .id =3D SM8750_SLAVE_BOOT_IMEM_2, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 0, }; =20 static struct qcom_icc_node srvc_cnoc_main =3D { .name =3D "srvc_cnoc_main", - .id =3D SM8750_SLAVE_SERVICE_CNOC, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node xs_pcie =3D { .name =3D "xs_pcie", - .id =3D SM8750_SLAVE_PCIE_0, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 0, }; =20 static struct qcom_icc_node chs_ubwc_p =3D { .name =3D "chs_ubwc_p", - .id =3D SM8750_SLAVE_UBWC_P, .channels =3D 1, .buswidth =3D 32, - .num_links =3D 0, }; =20 static struct qcom_icc_node qns_gem_noc_cnoc =3D { .name =3D "qns_gem_noc_cnoc", - .id =3D SM8750_SLAVE_GEM_NOC_CNOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM8750_MASTER_GEM_NOC_CNOC }, + .link_nodes =3D { &qnm_gemnoc_cnoc }, }; =20 static struct qcom_icc_node qns_llcc =3D { .name =3D "qns_llcc", - .id =3D SM8750_SLAVE_LLCC, .channels =3D 4, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM8750_MASTER_LLCC }, + .link_nodes =3D { &llcc_mc }, }; =20 static struct qcom_icc_node qns_pcie =3D { .name =3D "qns_pcie", - .id =3D SM8750_SLAVE_MEM_NOC_PCIE_SNOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8750_MASTER_GEM_NOC_PCIE_SNOC }, + .link_nodes =3D { &qnm_gemnoc_pcie }, }; =20 static struct qcom_icc_node qns_lpass_ag_noc_gemnoc =3D { .name =3D "qns_lpass_ag_noc_gemnoc", - .id =3D SM8750_SLAVE_LPASS_GEM_NOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM8750_MASTER_LPASS_GEM_NOC }, + .link_nodes =3D { &qnm_lpass_gemnoc }, }; =20 static struct qcom_icc_node qns_lpass_aggnoc =3D { .name =3D "qns_lpass_aggnoc", - .id =3D SM8750_SLAVE_LPIAON_NOC_LPASS_AG_NOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM8750_MASTER_LPIAON_NOC }, + .link_nodes =3D { &qnm_lpiaon_noc }, }; =20 static struct qcom_icc_node qns_lpi_aon_noc =3D { .name =3D "qns_lpi_aon_noc", - .id =3D SM8750_SLAVE_LPICX_NOC_LPIAON_NOC, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM8750_MASTER_LPASS_LPINOC }, + .link_nodes =3D { &qnm_lpass_lpinoc }, }; =20 static struct qcom_icc_node ebi =3D { .name =3D "ebi", - .id =3D SM8750_SLAVE_EBI1, .channels =3D 4, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qns_mem_noc_hf =3D { .name =3D "qns_mem_noc_hf", - .id =3D SM8750_SLAVE_MNOC_HF_MEM_NOC, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8750_MASTER_MNOC_HF_MEM_NOC }, + .link_nodes =3D { &qnm_mnoc_hf }, }; =20 static struct qcom_icc_node qns_mem_noc_sf =3D { .name =3D "qns_mem_noc_sf", - .id =3D SM8750_SLAVE_MNOC_SF_MEM_NOC, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8750_MASTER_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qnm_mnoc_sf }, }; =20 static struct qcom_icc_node srvc_mnoc =3D { .name =3D "srvc_mnoc", - .id =3D SM8750_SLAVE_SERVICE_MNOC, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qns_nsp_gemnoc =3D { .name =3D "qns_nsp_gemnoc", - .id =3D SM8750_SLAVE_CDSP_MEM_NOC, .channels =3D 2, .buswidth =3D 32, .num_links =3D 1, - .links =3D { SM8750_MASTER_COMPUTE_NOC }, + .link_nodes =3D { &qnm_nsp_gemnoc }, }; =20 static struct qcom_icc_node qns_pcie_mem_noc =3D { .name =3D "qns_pcie_mem_noc", - .id =3D SM8750_SLAVE_ANOC_PCIE_GEM_NOC, .channels =3D 1, .buswidth =3D 8, .num_links =3D 1, - .links =3D { SM8750_MASTER_ANOC_PCIE_GEM_NOC }, + .link_nodes =3D { &qnm_pcie }, }; =20 static struct qcom_icc_node srvc_pcie_aggre_noc =3D { .name =3D "srvc_pcie_aggre_noc", - .id =3D SM8750_SLAVE_SERVICE_PCIE_ANOC, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, }; =20 static struct qcom_icc_node qns_gemnoc_sf =3D { .name =3D "qns_gemnoc_sf", - .id =3D SM8750_SLAVE_SNOC_GEM_NOC_SF, .channels =3D 1, .buswidth =3D 16, .num_links =3D 1, - .links =3D { SM8750_MASTER_SNOC_SF_MEM_NOC }, + .link_nodes =3D { &qnm_snoc_sf }, }; =20 static struct qcom_icc_bcm bcm_acv =3D { @@ -1364,6 +1194,7 @@ static struct qcom_icc_node * const aggre1_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sm8750_aggre1_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D aggre1_noc_nodes, .num_nodes =3D ARRAY_SIZE(aggre1_noc_nodes), }; @@ -1386,6 +1217,7 @@ static struct qcom_icc_node * const aggre2_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sm8750_aggre2_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D aggre2_noc_nodes, .num_nodes =3D ARRAY_SIZE(aggre2_noc_nodes), .bcms =3D aggre2_noc_bcms, @@ -1408,6 +1240,7 @@ static struct qcom_icc_node * const clk_virt_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sm8750_clk_virt =3D { + .alloc_dyn_id =3D true, .nodes =3D clk_virt_nodes, .num_nodes =3D ARRAY_SIZE(clk_virt_nodes), .bcms =3D clk_virt_bcms, @@ -1457,6 +1290,7 @@ static struct qcom_icc_node * const config_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sm8750_config_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D config_noc_nodes, .num_nodes =3D ARRAY_SIZE(config_noc_nodes), .bcms =3D config_noc_bcms, @@ -1486,6 +1320,7 @@ static struct qcom_icc_node * const cnoc_main_nodes[]= =3D { }; =20 static const struct qcom_icc_desc sm8750_cnoc_main =3D { + .alloc_dyn_id =3D true, .nodes =3D cnoc_main_nodes, .num_nodes =3D ARRAY_SIZE(cnoc_main_nodes), .bcms =3D cnoc_main_bcms, @@ -1519,6 +1354,7 @@ static struct qcom_icc_node * const gem_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sm8750_gem_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D gem_noc_nodes, .num_nodes =3D ARRAY_SIZE(gem_noc_nodes), .bcms =3D gem_noc_bcms, @@ -1531,6 +1367,7 @@ static struct qcom_icc_node * const lpass_ag_noc_node= s[] =3D { }; =20 static const struct qcom_icc_desc sm8750_lpass_ag_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D lpass_ag_noc_nodes, .num_nodes =3D ARRAY_SIZE(lpass_ag_noc_nodes), }; @@ -1545,6 +1382,7 @@ static struct qcom_icc_node * const lpass_lpiaon_noc_= nodes[] =3D { }; =20 static const struct qcom_icc_desc sm8750_lpass_lpiaon_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D lpass_lpiaon_noc_nodes, .num_nodes =3D ARRAY_SIZE(lpass_lpiaon_noc_nodes), .bcms =3D lpass_lpiaon_noc_bcms, @@ -1557,6 +1395,7 @@ static struct qcom_icc_node * const lpass_lpicx_noc_n= odes[] =3D { }; =20 static const struct qcom_icc_desc sm8750_lpass_lpicx_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D lpass_lpicx_noc_nodes, .num_nodes =3D ARRAY_SIZE(lpass_lpicx_noc_nodes), }; @@ -1572,6 +1411,7 @@ static struct qcom_icc_node * const mc_virt_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sm8750_mc_virt =3D { + .alloc_dyn_id =3D true, .nodes =3D mc_virt_nodes, .num_nodes =3D ARRAY_SIZE(mc_virt_nodes), .bcms =3D mc_virt_bcms, @@ -1601,6 +1441,7 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sm8750_mmss_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D mmss_noc_nodes, .num_nodes =3D ARRAY_SIZE(mmss_noc_nodes), .bcms =3D mmss_noc_bcms, @@ -1617,6 +1458,7 @@ static struct qcom_icc_node * const nsp_noc_nodes[] = =3D { }; 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Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio --- drivers/interconnect/qcom/glymur.c | 21 --------------------- drivers/interconnect/qcom/icc-rpmh.c | 18 +++++------------- drivers/interconnect/qcom/icc-rpmh.h | 5 ----- drivers/interconnect/qcom/milos.c | 12 ------------ drivers/interconnect/qcom/qcs615.c | 8 -------- drivers/interconnect/qcom/qcs8300.c | 13 ------------- drivers/interconnect/qcom/qdu1000.c | 4 ---- drivers/interconnect/qcom/sa8775p.c | 14 -------------- drivers/interconnect/qcom/sar2130p.c | 9 --------- drivers/interconnect/qcom/sc7180.c | 12 ------------ drivers/interconnect/qcom/sc7280.c | 12 ------------ drivers/interconnect/qcom/sc8180x.c | 11 ----------- drivers/interconnect/qcom/sc8280xp.c | 12 ------------ drivers/interconnect/qcom/sdm670.c | 8 -------- drivers/interconnect/qcom/sdm845.c | 8 -------- drivers/interconnect/qcom/sdx55.c | 3 --- drivers/interconnect/qcom/sdx65.c | 3 --- drivers/interconnect/qcom/sdx75.c | 6 ------ drivers/interconnect/qcom/sm6350.c | 10 ---------- drivers/interconnect/qcom/sm7150.c | 10 ---------- drivers/interconnect/qcom/sm8150.c | 10 ---------- drivers/interconnect/qcom/sm8350.c | 10 ---------- drivers/interconnect/qcom/sm8450.c | 11 ----------- drivers/interconnect/qcom/sm8550.c | 14 -------------- drivers/interconnect/qcom/sm8650.c | 14 -------------- drivers/interconnect/qcom/sm8750.c | 14 -------------- drivers/interconnect/qcom/x1e80100.c | 19 ------------------- 27 files changed, 5 insertions(+), 286 deletions(-) diff --git a/drivers/interconnect/qcom/glymur.c b/drivers/interconnect/qcom= /glymur.c index 104ac6c1bd3665de92e15d577cb51111289c794a..e5c07795a6c67ab8a59daf2fc4b= 8a5fa6dd014d6 100644 --- a/drivers/interconnect/qcom/glymur.c +++ b/drivers/interconnect/qcom/glymur.c @@ -1878,7 +1878,6 @@ static const struct qcom_icc_desc glymur_aggre1_noc = =3D { .num_nodes =3D ARRAY_SIZE(aggre1_noc_nodes), .bcms =3D aggre1_noc_bcms, .num_bcms =3D ARRAY_SIZE(aggre1_noc_bcms), - .alloc_dyn_id =3D true, }; =20 static struct qcom_icc_node * const aggre2_noc_nodes[] =3D { @@ -1900,7 +1899,6 @@ static const struct qcom_icc_desc glymur_aggre2_noc = =3D { .config =3D &glymur_aggre2_noc_regmap_config, .nodes =3D aggre2_noc_nodes, .num_nodes =3D ARRAY_SIZE(aggre2_noc_nodes), - .alloc_dyn_id =3D true, .qos_requires_clocks =3D true, }; =20 @@ -1929,7 +1927,6 @@ static const struct qcom_icc_desc glymur_aggre3_noc = =3D { .config =3D &glymur_aggre3_noc_regmap_config, .nodes =3D aggre3_noc_nodes, .num_nodes =3D ARRAY_SIZE(aggre3_noc_nodes), - .alloc_dyn_id =3D true, }; =20 static struct qcom_icc_bcm * const aggre4_noc_bcms[] =3D { @@ -1958,7 +1955,6 @@ static const struct qcom_icc_desc glymur_aggre4_noc = =3D { .num_nodes =3D ARRAY_SIZE(aggre4_noc_nodes), .bcms =3D aggre4_noc_bcms, .num_bcms =3D ARRAY_SIZE(aggre4_noc_bcms), - .alloc_dyn_id =3D true, .qos_requires_clocks =3D true, }; =20 @@ -1982,7 +1978,6 @@ static const struct qcom_icc_desc glymur_clk_virt =3D= { .num_nodes =3D ARRAY_SIZE(clk_virt_nodes), .bcms =3D clk_virt_bcms, .num_bcms =3D ARRAY_SIZE(clk_virt_bcms), - .alloc_dyn_id =3D true, }; =20 static struct qcom_icc_bcm * const cnoc_cfg_bcms[] =3D { @@ -2059,7 +2054,6 @@ static const struct qcom_icc_desc glymur_cnoc_cfg =3D= { .num_nodes =3D ARRAY_SIZE(cnoc_cfg_nodes), .bcms =3D cnoc_cfg_bcms, .num_bcms =3D ARRAY_SIZE(cnoc_cfg_bcms), - .alloc_dyn_id =3D true, }; =20 static struct qcom_icc_bcm * const cnoc_main_bcms[] =3D { @@ -2092,7 +2086,6 @@ static const struct qcom_icc_desc glymur_cnoc_main = =3D { .num_nodes =3D ARRAY_SIZE(cnoc_main_nodes), .bcms =3D cnoc_main_bcms, .num_bcms =3D ARRAY_SIZE(cnoc_main_bcms), - .alloc_dyn_id =3D true, }; =20 static struct qcom_icc_bcm * const hscnoc_bcms[] =3D { @@ -2136,7 +2129,6 @@ static const struct qcom_icc_desc glymur_hscnoc =3D { .num_nodes =3D ARRAY_SIZE(hscnoc_nodes), .bcms =3D hscnoc_bcms, .num_bcms =3D ARRAY_SIZE(hscnoc_bcms), - .alloc_dyn_id =3D true, }; =20 static struct qcom_icc_node * const lpass_ag_noc_nodes[] =3D { @@ -2156,7 +2148,6 @@ static const struct qcom_icc_desc glymur_lpass_ag_noc= =3D { .config =3D &glymur_lpass_ag_noc_regmap_config, .nodes =3D lpass_ag_noc_nodes, .num_nodes =3D ARRAY_SIZE(lpass_ag_noc_nodes), - .alloc_dyn_id =3D true, }; =20 static struct qcom_icc_bcm * const lpass_lpiaon_noc_bcms[] =3D { @@ -2182,7 +2173,6 @@ static const struct qcom_icc_desc glymur_lpass_lpiaon= _noc =3D { .num_nodes =3D ARRAY_SIZE(lpass_lpiaon_noc_nodes), .bcms =3D lpass_lpiaon_noc_bcms, .num_bcms =3D ARRAY_SIZE(lpass_lpiaon_noc_bcms), - .alloc_dyn_id =3D true, }; =20 static struct qcom_icc_node * const lpass_lpicx_noc_nodes[] =3D { @@ -2202,7 +2192,6 @@ static const struct qcom_icc_desc glymur_lpass_lpicx_= noc =3D { .config =3D &glymur_lpass_lpicx_noc_regmap_config, .nodes =3D lpass_lpicx_noc_nodes, .num_nodes =3D ARRAY_SIZE(lpass_lpicx_noc_nodes), - .alloc_dyn_id =3D true, }; =20 static struct qcom_icc_bcm * const mc_virt_bcms[] =3D { @@ -2220,7 +2209,6 @@ static const struct qcom_icc_desc glymur_mc_virt =3D { .num_nodes =3D ARRAY_SIZE(mc_virt_nodes), .bcms =3D mc_virt_bcms, .num_bcms =3D ARRAY_SIZE(mc_virt_bcms), - .alloc_dyn_id =3D true, }; =20 static struct qcom_icc_bcm * const mmss_noc_bcms[] =3D { @@ -2259,7 +2247,6 @@ static const struct qcom_icc_desc glymur_mmss_noc =3D= { .num_nodes =3D ARRAY_SIZE(mmss_noc_nodes), .bcms =3D mmss_noc_bcms, .num_bcms =3D ARRAY_SIZE(mmss_noc_bcms), - .alloc_dyn_id =3D true, }; =20 static struct qcom_icc_node * const nsinoc_nodes[] =3D { @@ -2280,7 +2267,6 @@ static const struct qcom_icc_desc glymur_nsinoc =3D { .config =3D &glymur_nsinoc_regmap_config, .nodes =3D nsinoc_nodes, .num_nodes =3D ARRAY_SIZE(nsinoc_nodes), - .alloc_dyn_id =3D true, }; =20 static struct qcom_icc_bcm * const nsp_noc_bcms[] =3D { @@ -2306,7 +2292,6 @@ static const struct qcom_icc_desc glymur_nsp_noc =3D { .num_nodes =3D ARRAY_SIZE(nsp_noc_nodes), .bcms =3D nsp_noc_bcms, .num_bcms =3D ARRAY_SIZE(nsp_noc_bcms), - .alloc_dyn_id =3D true, }; =20 static struct qcom_icc_node * const oobm_ss_noc_nodes[] =3D { @@ -2326,7 +2311,6 @@ static const struct qcom_icc_desc glymur_oobm_ss_noc = =3D { .config =3D &glymur_oobm_ss_noc_regmap_config, .nodes =3D oobm_ss_noc_nodes, .num_nodes =3D ARRAY_SIZE(oobm_ss_noc_nodes), - .alloc_dyn_id =3D true, }; =20 static struct qcom_icc_bcm * const pcie_east_anoc_bcms[] =3D { @@ -2356,7 +2340,6 @@ static const struct qcom_icc_desc glymur_pcie_east_an= oc =3D { .num_nodes =3D ARRAY_SIZE(pcie_east_anoc_nodes), .bcms =3D pcie_east_anoc_bcms, .num_bcms =3D ARRAY_SIZE(pcie_east_anoc_bcms), - .alloc_dyn_id =3D true, .qos_requires_clocks =3D true, }; =20 @@ -2388,7 +2371,6 @@ static const struct qcom_icc_desc glymur_pcie_east_sl= v_noc =3D { .num_nodes =3D ARRAY_SIZE(pcie_east_slv_noc_nodes), .bcms =3D pcie_east_slv_noc_bcms, .num_bcms =3D ARRAY_SIZE(pcie_east_slv_noc_bcms), - .alloc_dyn_id =3D true, }; =20 static struct qcom_icc_bcm * const pcie_west_anoc_bcms[] =3D { @@ -2420,7 +2402,6 @@ static const struct qcom_icc_desc glymur_pcie_west_an= oc =3D { .num_nodes =3D ARRAY_SIZE(pcie_west_anoc_nodes), .bcms =3D pcie_west_anoc_bcms, .num_bcms =3D ARRAY_SIZE(pcie_west_anoc_bcms), - .alloc_dyn_id =3D true, .qos_requires_clocks =3D true, }; =20 @@ -2454,7 +2435,6 @@ static const struct qcom_icc_desc glymur_pcie_west_sl= v_noc =3D { .num_nodes =3D ARRAY_SIZE(pcie_west_slv_noc_nodes), .bcms =3D pcie_west_slv_noc_bcms, .num_bcms =3D ARRAY_SIZE(pcie_west_slv_noc_bcms), - .alloc_dyn_id =3D true, }; =20 static struct qcom_icc_bcm * const system_noc_bcms[] =3D { @@ -2488,7 +2468,6 @@ static const struct qcom_icc_desc glymur_system_noc = =3D { .num_nodes =3D ARRAY_SIZE(system_noc_nodes), .bcms =3D system_noc_bcms, .num_bcms =3D ARRAY_SIZE(system_noc_bcms), - .alloc_dyn_id =3D true, }; =20 static const struct of_device_id qnoc_of_match[] =3D { diff --git a/drivers/interconnect/qcom/icc-rpmh.c b/drivers/interconnect/qc= om/icc-rpmh.c index 001404e91041597eab7f251606873182e52e360c..f90c29111f48ef810a8949ecd25= bfbacf20805cb 100644 --- a/drivers/interconnect/qcom/icc-rpmh.c +++ b/drivers/interconnect/qcom/icc-rpmh.c @@ -280,14 +280,10 @@ int qcom_icc_rpmh_probe(struct platform_device *pdev) if (!qn) continue; =20 - if (desc->alloc_dyn_id) { - if (!qn->node) - qn->node =3D icc_node_create_dyn(); - node =3D qn->node; - } else { - node =3D icc_node_create(qn->id); - } + if (!qn->node) + qn->node =3D icc_node_create_dyn(); =20 + node =3D qn->node; if (IS_ERR(node)) { ret =3D PTR_ERR(node); goto err_remove_nodes; @@ -302,12 +298,8 @@ int qcom_icc_rpmh_probe(struct platform_device *pdev) node->data =3D qn; icc_node_add(node, provider); =20 - for (j =3D 0; j < qn->num_links; j++) { - if (desc->alloc_dyn_id) - icc_link_nodes(node, &qn->link_nodes[j]->node); - else - icc_link_create(node, qn->links[j]); - } + for (j =3D 0; j < qn->num_links; j++) + icc_link_nodes(node, &qn->link_nodes[j]->node); =20 data->nodes[i] =3D node; } diff --git a/drivers/interconnect/qcom/icc-rpmh.h b/drivers/interconnect/qc= om/icc-rpmh.h index b72939cceba38e92154f6af5a93149337fa13479..09d8791402dc4bd67fd092268eb= 1458bcd8c6c8f 100644 --- a/drivers/interconnect/qcom/icc-rpmh.h +++ b/drivers/interconnect/qcom/icc-rpmh.h @@ -81,8 +81,6 @@ struct qcom_icc_qosbox { /** * struct qcom_icc_node - Qualcomm specific interconnect nodes * @name: the node name used in debugfs - * @links: an array of nodes where we can go next while traversing - * @id: a unique node identifier * @link_nodes: links associated with this node * @node: icc_node associated with this node * @num_links: the total number of @links @@ -96,8 +94,6 @@ struct qcom_icc_qosbox { */ struct qcom_icc_node { const char *name; - u16 links[MAX_LINKS]; - u16 id; struct icc_node *node; u16 num_links; u16 channels; @@ -158,7 +154,6 @@ struct qcom_icc_desc { struct qcom_icc_bcm * const *bcms; size_t num_bcms; bool qos_requires_clocks; - bool alloc_dyn_id; }; =20 int qcom_icc_aggregate(struct icc_node *node, u32 tag, u32 avg_bw, diff --git a/drivers/interconnect/qcom/milos.c b/drivers/interconnect/qcom/= milos.c index 814ec0517f6b8f42ae9d7ce3cd5cebcbaae35ae8..d010b106728a37c9384cd0625e5= 3a4f93466ada4 100644 --- a/drivers/interconnect/qcom/milos.c +++ b/drivers/interconnect/qcom/milos.c @@ -1522,7 +1522,6 @@ static const struct qcom_icc_desc milos_aggre1_noc = =3D { .config =3D &milos_aggre1_noc_regmap_config, .nodes =3D aggre1_noc_nodes, .num_nodes =3D ARRAY_SIZE(aggre1_noc_nodes), - .alloc_dyn_id =3D true, }; =20 static struct qcom_icc_bcm * const aggre2_noc_bcms[] =3D { @@ -1556,7 +1555,6 @@ static const struct qcom_icc_desc milos_aggre2_noc = =3D { .num_nodes =3D ARRAY_SIZE(aggre2_noc_nodes), .bcms =3D aggre2_noc_bcms, .num_bcms =3D ARRAY_SIZE(aggre2_noc_bcms), - .alloc_dyn_id =3D true, }; =20 static struct qcom_icc_bcm * const clk_virt_bcms[] =3D { @@ -1576,7 +1574,6 @@ static const struct qcom_icc_desc milos_clk_virt =3D { .num_nodes =3D ARRAY_SIZE(clk_virt_nodes), .bcms =3D clk_virt_bcms, .num_bcms =3D ARRAY_SIZE(clk_virt_bcms), - .alloc_dyn_id =3D true, }; =20 static struct qcom_icc_bcm * const cnoc_cfg_bcms[] =3D { @@ -1637,7 +1634,6 @@ static const struct qcom_icc_desc milos_cnoc_cfg =3D { .num_nodes =3D ARRAY_SIZE(cnoc_cfg_nodes), .bcms =3D cnoc_cfg_bcms, .num_bcms =3D ARRAY_SIZE(cnoc_cfg_bcms), - .alloc_dyn_id =3D true, }; =20 static struct qcom_icc_bcm * const cnoc_main_bcms[] =3D { @@ -1680,7 +1676,6 @@ static const struct qcom_icc_desc milos_cnoc_main =3D= { .num_nodes =3D ARRAY_SIZE(cnoc_main_nodes), .bcms =3D cnoc_main_bcms, .num_bcms =3D ARRAY_SIZE(cnoc_main_bcms), - .alloc_dyn_id =3D true, }; =20 static struct qcom_icc_bcm * const gem_noc_bcms[] =3D { @@ -1721,7 +1716,6 @@ static const struct qcom_icc_desc milos_gem_noc =3D { .num_nodes =3D ARRAY_SIZE(gem_noc_nodes), .bcms =3D gem_noc_bcms, .num_bcms =3D ARRAY_SIZE(gem_noc_bcms), - .alloc_dyn_id =3D true, }; =20 static struct qcom_icc_node * const lpass_ag_noc_nodes[] =3D { @@ -1741,7 +1735,6 @@ static const struct qcom_icc_desc milos_lpass_ag_noc = =3D { .config =3D &milos_lpass_ag_noc_regmap_config, .nodes =3D lpass_ag_noc_nodes, .num_nodes =3D ARRAY_SIZE(lpass_ag_noc_nodes), - .alloc_dyn_id =3D true, }; =20 static struct qcom_icc_bcm * const mc_virt_bcms[] =3D { @@ -1759,7 +1752,6 @@ static const struct qcom_icc_desc milos_mc_virt =3D { .num_nodes =3D ARRAY_SIZE(mc_virt_nodes), .bcms =3D mc_virt_bcms, .num_bcms =3D ARRAY_SIZE(mc_virt_bcms), - .alloc_dyn_id =3D true, }; =20 static struct qcom_icc_bcm * const mmss_noc_bcms[] =3D { @@ -1795,7 +1787,6 @@ static const struct qcom_icc_desc milos_mmss_noc =3D { .num_nodes =3D ARRAY_SIZE(mmss_noc_nodes), .bcms =3D mmss_noc_bcms, .num_bcms =3D ARRAY_SIZE(mmss_noc_bcms), - .alloc_dyn_id =3D true, }; =20 static struct qcom_icc_bcm * const nsp_noc_bcms[] =3D { @@ -1821,7 +1812,6 @@ static const struct qcom_icc_desc milos_nsp_noc =3D { .num_nodes =3D ARRAY_SIZE(nsp_noc_nodes), .bcms =3D nsp_noc_bcms, .num_bcms =3D ARRAY_SIZE(nsp_noc_bcms), - .alloc_dyn_id =3D true, }; =20 static struct qcom_icc_bcm * const pcie_anoc_bcms[] =3D { @@ -1850,7 +1840,6 @@ static const struct qcom_icc_desc milos_pcie_anoc =3D= { .num_nodes =3D ARRAY_SIZE(pcie_anoc_nodes), .bcms =3D pcie_anoc_bcms, .num_bcms =3D ARRAY_SIZE(pcie_anoc_bcms), - .alloc_dyn_id =3D true, }; =20 static struct qcom_icc_bcm * const system_noc_bcms[] =3D { @@ -1885,7 +1874,6 @@ static const struct qcom_icc_desc milos_system_noc = =3D { .num_nodes =3D ARRAY_SIZE(system_noc_nodes), .bcms =3D system_noc_bcms, .num_bcms =3D ARRAY_SIZE(system_noc_bcms), - .alloc_dyn_id =3D true, }; =20 static const struct of_device_id qnoc_of_match[] =3D { diff --git a/drivers/interconnect/qcom/qcs615.c b/drivers/interconnect/qcom= /qcs615.c index fb0f623c0e645dce540afb9857c6f11a24a70cd8..797956eb6ff542c8d9a25a4b564= f1683409e43b9 100644 --- a/drivers/interconnect/qcom/qcs615.c +++ b/drivers/interconnect/qcom/qcs615.c @@ -1214,7 +1214,6 @@ static struct qcom_icc_node * const aggre1_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc qcs615_aggre1_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D aggre1_noc_nodes, .num_nodes =3D ARRAY_SIZE(aggre1_noc_nodes), .bcms =3D aggre1_noc_bcms, @@ -1233,7 +1232,6 @@ static struct qcom_icc_node * const camnoc_virt_nodes= [] =3D { }; =20 static const struct qcom_icc_desc qcs615_camnoc_virt =3D { - .alloc_dyn_id =3D true, .nodes =3D camnoc_virt_nodes, .num_nodes =3D ARRAY_SIZE(camnoc_virt_nodes), .bcms =3D camnoc_virt_bcms, @@ -1292,7 +1290,6 @@ static struct qcom_icc_node * const config_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc qcs615_config_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D config_noc_nodes, .num_nodes =3D ARRAY_SIZE(config_noc_nodes), .bcms =3D config_noc_bcms, @@ -1306,7 +1303,6 @@ static struct qcom_icc_node * const dc_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc qcs615_dc_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D dc_noc_nodes, .num_nodes =3D ARRAY_SIZE(dc_noc_nodes), }; @@ -1336,7 +1332,6 @@ static struct qcom_icc_node * const gem_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc qcs615_gem_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D gem_noc_nodes, .num_nodes =3D ARRAY_SIZE(gem_noc_nodes), .bcms =3D gem_noc_bcms, @@ -1354,7 +1349,6 @@ static struct qcom_icc_node * const mc_virt_nodes[] = =3D { }; =20 static const struct qcom_icc_desc qcs615_mc_virt =3D { - .alloc_dyn_id =3D true, .nodes =3D mc_virt_nodes, .num_nodes =3D ARRAY_SIZE(mc_virt_nodes), .bcms =3D mc_virt_bcms, @@ -1383,7 +1377,6 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc qcs615_mmss_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D mmss_noc_nodes, .num_nodes =3D ARRAY_SIZE(mmss_noc_nodes), .bcms =3D mmss_noc_bcms, @@ -1426,7 +1419,6 @@ static struct qcom_icc_node * const system_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc qcs615_system_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D system_noc_nodes, .num_nodes =3D ARRAY_SIZE(system_noc_nodes), .bcms =3D system_noc_bcms, diff --git a/drivers/interconnect/qcom/qcs8300.c b/drivers/interconnect/qco= m/qcs8300.c index 077f4beb4bd1ae0e508c0683296f0a38cecc0471..70a377bbcf2930a4bdddcf6c3d9= 8e95e4ad92561 100644 --- a/drivers/interconnect/qcom/qcs8300.c +++ b/drivers/interconnect/qcom/qcs8300.c @@ -1600,7 +1600,6 @@ static struct qcom_icc_node * const aggre1_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc qcs8300_aggre1_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D aggre1_noc_nodes, .num_nodes =3D ARRAY_SIZE(aggre1_noc_nodes), .bcms =3D aggre1_noc_bcms, @@ -1626,7 +1625,6 @@ static struct qcom_icc_node * const aggre2_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc qcs8300_aggre2_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D aggre2_noc_nodes, .num_nodes =3D ARRAY_SIZE(aggre2_noc_nodes), .bcms =3D aggre2_noc_bcms, @@ -1649,7 +1647,6 @@ static struct qcom_icc_node * const clk_virt_nodes[] = =3D { }; =20 static const struct qcom_icc_desc qcs8300_clk_virt =3D { - .alloc_dyn_id =3D true, .nodes =3D clk_virt_nodes, .num_nodes =3D ARRAY_SIZE(clk_virt_nodes), .bcms =3D clk_virt_bcms, @@ -1744,7 +1741,6 @@ static struct qcom_icc_node * const config_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc qcs8300_config_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D config_noc_nodes, .num_nodes =3D ARRAY_SIZE(config_noc_nodes), .bcms =3D config_noc_bcms, @@ -1758,7 +1754,6 @@ static struct qcom_icc_node * const dc_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc qcs8300_dc_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D dc_noc_nodes, .num_nodes =3D ARRAY_SIZE(dc_noc_nodes), }; @@ -1792,7 +1787,6 @@ static struct qcom_icc_node * const gem_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc qcs8300_gem_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D gem_noc_nodes, .num_nodes =3D ARRAY_SIZE(gem_noc_nodes), .bcms =3D gem_noc_bcms, @@ -1810,7 +1804,6 @@ static struct qcom_icc_node * const gpdsp_anoc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc qcs8300_gpdsp_anoc =3D { - .alloc_dyn_id =3D true, .nodes =3D gpdsp_anoc_nodes, .num_nodes =3D ARRAY_SIZE(gpdsp_anoc_nodes), .bcms =3D gpdsp_anoc_bcms, @@ -1834,7 +1827,6 @@ static struct qcom_icc_node * const lpass_ag_noc_node= s[] =3D { }; =20 static const struct qcom_icc_desc qcs8300_lpass_ag_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D lpass_ag_noc_nodes, .num_nodes =3D ARRAY_SIZE(lpass_ag_noc_nodes), .bcms =3D lpass_ag_noc_bcms, @@ -1852,7 +1844,6 @@ static struct qcom_icc_node * const mc_virt_nodes[] = =3D { }; =20 static const struct qcom_icc_desc qcs8300_mc_virt =3D { - .alloc_dyn_id =3D true, .nodes =3D mc_virt_nodes, .num_nodes =3D ARRAY_SIZE(mc_virt_nodes), .bcms =3D mc_virt_bcms, @@ -1882,7 +1873,6 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc qcs8300_mmss_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D mmss_noc_nodes, .num_nodes =3D ARRAY_SIZE(mmss_noc_nodes), .bcms =3D mmss_noc_bcms, @@ -1903,7 +1893,6 @@ static struct qcom_icc_node * const nspa_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc qcs8300_nspa_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D nspa_noc_nodes, .num_nodes =3D ARRAY_SIZE(nspa_noc_nodes), .bcms =3D nspa_noc_bcms, @@ -1921,7 +1910,6 @@ static struct qcom_icc_node * const pcie_anoc_nodes[]= =3D { }; =20 static const struct qcom_icc_desc qcs8300_pcie_anoc =3D { - .alloc_dyn_id =3D true, .nodes =3D pcie_anoc_nodes, .num_nodes =3D ARRAY_SIZE(pcie_anoc_nodes), .bcms =3D pcie_anoc_bcms, @@ -1950,7 +1938,6 @@ static struct qcom_icc_node * const system_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc qcs8300_system_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D system_noc_nodes, .num_nodes =3D ARRAY_SIZE(system_noc_nodes), .bcms =3D system_noc_bcms, diff --git a/drivers/interconnect/qcom/qdu1000.c b/drivers/interconnect/qco= m/qdu1000.c index 4de0f17e4c57f77e9bd6f8bc7108359c4370c396..0006413241dc88bcc4397abc5be= ab1b8705dee27 100644 --- a/drivers/interconnect/qcom/qdu1000.c +++ b/drivers/interconnect/qcom/qdu1000.c @@ -834,7 +834,6 @@ static struct qcom_icc_node * const clk_virt_nodes[] = =3D { }; =20 static const struct qcom_icc_desc qdu1000_clk_virt =3D { - .alloc_dyn_id =3D true, .nodes =3D clk_virt_nodes, .num_nodes =3D ARRAY_SIZE(clk_virt_nodes), .bcms =3D clk_virt_bcms, @@ -862,7 +861,6 @@ static struct qcom_icc_node * const gem_noc_nodes[] =3D= { }; =20 static const struct qcom_icc_desc qdu1000_gem_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D gem_noc_nodes, .num_nodes =3D ARRAY_SIZE(gem_noc_nodes), .bcms =3D gem_noc_bcms, @@ -880,7 +878,6 @@ static struct qcom_icc_node * const mc_virt_nodes[] =3D= { }; =20 static const struct qcom_icc_desc qdu1000_mc_virt =3D { - .alloc_dyn_id =3D true, .nodes =3D mc_virt_nodes, .num_nodes =3D ARRAY_SIZE(mc_virt_nodes), .bcms =3D mc_virt_bcms, @@ -967,7 +964,6 @@ static struct qcom_icc_node * const system_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc qdu1000_system_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D system_noc_nodes, .num_nodes =3D ARRAY_SIZE(system_noc_nodes), .bcms =3D system_noc_bcms, diff --git a/drivers/interconnect/qcom/sa8775p.c b/drivers/interconnect/qco= m/sa8775p.c index d144e8cb5d1e3a69410975bd6b7abd9578c01407..8ce4e5fe05f2e5d0ad5cee0eb41= 00877ecd144cc 100644 --- a/drivers/interconnect/qcom/sa8775p.c +++ b/drivers/interconnect/qcom/sa8775p.c @@ -1841,7 +1841,6 @@ static const struct qcom_icc_desc sa8775p_aggre1_noc = =3D { .num_nodes =3D ARRAY_SIZE(aggre1_noc_nodes), .bcms =3D aggre1_noc_bcms, .num_bcms =3D ARRAY_SIZE(aggre1_noc_bcms), - .alloc_dyn_id =3D true, }; =20 static struct qcom_icc_bcm * const aggre2_noc_bcms[] =3D { @@ -1869,7 +1868,6 @@ static const struct qcom_icc_desc sa8775p_aggre2_noc = =3D { .num_nodes =3D ARRAY_SIZE(aggre2_noc_nodes), .bcms =3D aggre2_noc_bcms, .num_bcms =3D ARRAY_SIZE(aggre2_noc_bcms), - .alloc_dyn_id =3D true, }; =20 static struct qcom_icc_bcm * const clk_virt_bcms[] =3D { @@ -1894,7 +1892,6 @@ static const struct qcom_icc_desc sa8775p_clk_virt = =3D { .num_nodes =3D ARRAY_SIZE(clk_virt_nodes), .bcms =3D clk_virt_bcms, .num_bcms =3D ARRAY_SIZE(clk_virt_bcms), - .alloc_dyn_id =3D true, }; =20 static struct qcom_icc_bcm * const config_noc_bcms[] =3D { @@ -2000,7 +1997,6 @@ static const struct qcom_icc_desc sa8775p_config_noc = =3D { .num_nodes =3D ARRAY_SIZE(config_noc_nodes), .bcms =3D config_noc_bcms, .num_bcms =3D ARRAY_SIZE(config_noc_bcms), - .alloc_dyn_id =3D true, }; =20 static struct qcom_icc_bcm * const dc_noc_bcms[] =3D { @@ -2017,7 +2013,6 @@ static const struct qcom_icc_desc sa8775p_dc_noc =3D { .num_nodes =3D ARRAY_SIZE(dc_noc_nodes), .bcms =3D dc_noc_bcms, .num_bcms =3D ARRAY_SIZE(dc_noc_bcms), - .alloc_dyn_id =3D true, }; =20 static struct qcom_icc_bcm * const gem_noc_bcms[] =3D { @@ -2054,7 +2049,6 @@ static const struct qcom_icc_desc sa8775p_gem_noc =3D= { .num_nodes =3D ARRAY_SIZE(gem_noc_nodes), .bcms =3D gem_noc_bcms, .num_bcms =3D ARRAY_SIZE(gem_noc_bcms), - .alloc_dyn_id =3D true, }; =20 static struct qcom_icc_bcm * const gpdsp_anoc_bcms[] =3D { @@ -2073,7 +2067,6 @@ static const struct qcom_icc_desc sa8775p_gpdsp_anoc = =3D { .num_nodes =3D ARRAY_SIZE(gpdsp_anoc_nodes), .bcms =3D gpdsp_anoc_bcms, .num_bcms =3D ARRAY_SIZE(gpdsp_anoc_bcms), - .alloc_dyn_id =3D true, }; =20 static struct qcom_icc_bcm * const lpass_ag_noc_bcms[] =3D { @@ -2097,7 +2090,6 @@ static const struct qcom_icc_desc sa8775p_lpass_ag_no= c =3D { .num_nodes =3D ARRAY_SIZE(lpass_ag_noc_nodes), .bcms =3D lpass_ag_noc_bcms, .num_bcms =3D ARRAY_SIZE(lpass_ag_noc_bcms), - .alloc_dyn_id =3D true, }; =20 static struct qcom_icc_bcm * const mc_virt_bcms[] =3D { @@ -2115,7 +2107,6 @@ static const struct qcom_icc_desc sa8775p_mc_virt =3D= { .num_nodes =3D ARRAY_SIZE(mc_virt_nodes), .bcms =3D mc_virt_bcms, .num_bcms =3D ARRAY_SIZE(mc_virt_bcms), - .alloc_dyn_id =3D true, }; =20 static struct qcom_icc_bcm * const mmss_noc_bcms[] =3D { @@ -2148,7 +2139,6 @@ static const struct qcom_icc_desc sa8775p_mmss_noc = =3D { .num_nodes =3D ARRAY_SIZE(mmss_noc_nodes), .bcms =3D mmss_noc_bcms, .num_bcms =3D ARRAY_SIZE(mmss_noc_bcms), - .alloc_dyn_id =3D true, }; =20 static struct qcom_icc_bcm * const nspa_noc_bcms[] =3D { @@ -2169,7 +2159,6 @@ static const struct qcom_icc_desc sa8775p_nspa_noc = =3D { .num_nodes =3D ARRAY_SIZE(nspa_noc_nodes), .bcms =3D nspa_noc_bcms, .num_bcms =3D ARRAY_SIZE(nspa_noc_bcms), - .alloc_dyn_id =3D true, }; =20 static struct qcom_icc_bcm * const nspb_noc_bcms[] =3D { @@ -2190,7 +2179,6 @@ static const struct qcom_icc_desc sa8775p_nspb_noc = =3D { .num_nodes =3D ARRAY_SIZE(nspb_noc_nodes), .bcms =3D nspb_noc_bcms, .num_bcms =3D ARRAY_SIZE(nspb_noc_bcms), - .alloc_dyn_id =3D true, }; =20 static struct qcom_icc_bcm * const pcie_anoc_bcms[] =3D { @@ -2208,7 +2196,6 @@ static const struct qcom_icc_desc sa8775p_pcie_anoc = =3D { .num_nodes =3D ARRAY_SIZE(pcie_anoc_nodes), .bcms =3D pcie_anoc_bcms, .num_bcms =3D ARRAY_SIZE(pcie_anoc_bcms), - .alloc_dyn_id =3D true, }; =20 static struct qcom_icc_bcm * const system_noc_bcms[] =3D { @@ -2237,7 +2224,6 @@ static const struct qcom_icc_desc sa8775p_system_noc = =3D { .num_nodes =3D ARRAY_SIZE(system_noc_nodes), .bcms =3D system_noc_bcms, .num_bcms =3D ARRAY_SIZE(system_noc_bcms), - .alloc_dyn_id =3D true, }; =20 static const struct of_device_id qnoc_of_match[] =3D { diff --git a/drivers/interconnect/qcom/sar2130p.c b/drivers/interconnect/qc= om/sar2130p.c index a0b04929058f7e92a60e441b2cc82ee8984daf41..34cb3fc1f99575d25f397f02b84= 8e4d4066f060d 100644 --- a/drivers/interconnect/qcom/sar2130p.c +++ b/drivers/interconnect/qcom/sar2130p.c @@ -1474,7 +1474,6 @@ static struct qcom_icc_node * const clk_virt_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sar2130p_clk_virt =3D { - .alloc_dyn_id =3D true, .nodes =3D clk_virt_nodes, .num_nodes =3D ARRAY_SIZE(clk_virt_nodes), .bcms =3D clk_virt_bcms, @@ -1537,7 +1536,6 @@ static struct qcom_icc_node * const config_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sar2130p_config_noc =3D { - .alloc_dyn_id =3D true, .config =3D &icc_regmap_config, .nodes =3D config_noc_nodes, .num_nodes =3D ARRAY_SIZE(config_noc_nodes), @@ -1568,7 +1566,6 @@ static struct qcom_icc_node * const gem_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sar2130p_gem_noc =3D { - .alloc_dyn_id =3D true, .config =3D &icc_regmap_config, .nodes =3D gem_noc_nodes, .num_nodes =3D ARRAY_SIZE(gem_noc_nodes), @@ -1592,7 +1589,6 @@ static struct qcom_icc_node * const lpass_ag_noc_node= s[] =3D { }; =20 static const struct qcom_icc_desc sar2130p_lpass_ag_noc =3D { - .alloc_dyn_id =3D true, .config =3D &icc_regmap_config, .nodes =3D lpass_ag_noc_nodes, .num_nodes =3D ARRAY_SIZE(lpass_ag_noc_nodes), @@ -1611,7 +1607,6 @@ static struct qcom_icc_node * const mc_virt_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sar2130p_mc_virt =3D { - .alloc_dyn_id =3D true, .nodes =3D mc_virt_nodes, .num_nodes =3D ARRAY_SIZE(mc_virt_nodes), .bcms =3D mc_virt_bcms, @@ -1640,7 +1635,6 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sar2130p_mmss_noc =3D { - .alloc_dyn_id =3D true, .config =3D &icc_regmap_config, .nodes =3D mmss_noc_nodes, .num_nodes =3D ARRAY_SIZE(mmss_noc_nodes), @@ -1660,7 +1654,6 @@ static struct qcom_icc_node * const nsp_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sar2130p_nsp_noc =3D { - .alloc_dyn_id =3D true, .config =3D &icc_regmap_config, .nodes =3D nsp_noc_nodes, .num_nodes =3D ARRAY_SIZE(nsp_noc_nodes), @@ -1679,7 +1672,6 @@ static struct qcom_icc_node * const pcie_anoc_nodes[]= =3D { }; =20 static const struct qcom_icc_desc sar2130p_pcie_anoc =3D { - .alloc_dyn_id =3D true, .config =3D &icc_regmap_config, .nodes =3D pcie_anoc_nodes, .num_nodes =3D ARRAY_SIZE(pcie_anoc_nodes), @@ -1719,7 +1711,6 @@ static struct qcom_icc_node * const system_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sar2130p_system_noc =3D { - .alloc_dyn_id =3D true, .config =3D &icc_regmap_config, .nodes =3D system_noc_nodes, .num_nodes =3D ARRAY_SIZE(system_noc_nodes), diff --git a/drivers/interconnect/qcom/sc7180.c b/drivers/interconnect/qcom= /sc7180.c index 9f94b987c4448a04dc984ad09b0733c33c9bb76a..0ea06facf81e2592e26e36bdf1d= b0fb27a6d8c51 100644 --- a/drivers/interconnect/qcom/sc7180.c +++ b/drivers/interconnect/qcom/sc7180.c @@ -1471,7 +1471,6 @@ static struct qcom_icc_node * const aggre1_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sc7180_aggre1_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D aggre1_noc_nodes, .num_nodes =3D ARRAY_SIZE(aggre1_noc_nodes), .bcms =3D aggre1_noc_bcms, @@ -1495,7 +1494,6 @@ static struct qcom_icc_node * const aggre2_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sc7180_aggre2_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D aggre2_noc_nodes, .num_nodes =3D ARRAY_SIZE(aggre2_noc_nodes), .bcms =3D aggre2_noc_bcms, @@ -1514,7 +1512,6 @@ static struct qcom_icc_node * const camnoc_virt_nodes= [] =3D { }; =20 static const struct qcom_icc_desc sc7180_camnoc_virt =3D { - .alloc_dyn_id =3D true, .nodes =3D camnoc_virt_nodes, .num_nodes =3D ARRAY_SIZE(camnoc_virt_nodes), .bcms =3D camnoc_virt_bcms, @@ -1534,7 +1531,6 @@ static struct qcom_icc_node * const compute_noc_nodes= [] =3D { }; =20 static const struct qcom_icc_desc sc7180_compute_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D compute_noc_nodes, .num_nodes =3D ARRAY_SIZE(compute_noc_nodes), .bcms =3D compute_noc_bcms, @@ -1603,7 +1599,6 @@ static struct qcom_icc_node * const config_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sc7180_config_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D config_noc_nodes, .num_nodes =3D ARRAY_SIZE(config_noc_nodes), .bcms =3D config_noc_bcms, @@ -1617,7 +1612,6 @@ static struct qcom_icc_node * const dc_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sc7180_dc_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D dc_noc_nodes, .num_nodes =3D ARRAY_SIZE(dc_noc_nodes), }; @@ -1646,7 +1640,6 @@ static struct qcom_icc_node * const gem_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sc7180_gem_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D gem_noc_nodes, .num_nodes =3D ARRAY_SIZE(gem_noc_nodes), .bcms =3D gem_noc_bcms, @@ -1664,7 +1657,6 @@ static struct qcom_icc_node * const mc_virt_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sc7180_mc_virt =3D { - .alloc_dyn_id =3D true, .nodes =3D mc_virt_nodes, .num_nodes =3D ARRAY_SIZE(mc_virt_nodes), .bcms =3D mc_virt_bcms, @@ -1692,7 +1684,6 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sc7180_mmss_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D mmss_noc_nodes, .num_nodes =3D ARRAY_SIZE(mmss_noc_nodes), .bcms =3D mmss_noc_bcms, @@ -1714,7 +1705,6 @@ static struct qcom_icc_node * const npu_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sc7180_npu_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D npu_noc_nodes, .num_nodes =3D ARRAY_SIZE(npu_noc_nodes), }; @@ -1731,7 +1721,6 @@ static struct qcom_icc_node * const qup_virt_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sc7180_qup_virt =3D { - .alloc_dyn_id =3D true, .nodes =3D qup_virt_nodes, .num_nodes =3D ARRAY_SIZE(qup_virt_nodes), .bcms =3D qup_virt_bcms, @@ -1767,7 +1756,6 @@ static struct qcom_icc_node * const system_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sc7180_system_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D system_noc_nodes, .num_nodes =3D ARRAY_SIZE(system_noc_nodes), .bcms =3D system_noc_bcms, diff --git a/drivers/interconnect/qcom/sc7280.c b/drivers/interconnect/qcom= /sc7280.c index 3dc8b81f917d5de69f67112bd313326b4658f77c..c4cb6443f2d49c132b779429d89= 9d660d02ffa2a 100644 --- a/drivers/interconnect/qcom/sc7280.c +++ b/drivers/interconnect/qcom/sc7280.c @@ -1620,7 +1620,6 @@ static const struct regmap_config sc7280_aggre1_noc_r= egmap_config =3D { }; =20 static const struct qcom_icc_desc sc7280_aggre1_noc =3D { - .alloc_dyn_id =3D true, .config =3D &sc7280_aggre1_noc_regmap_config, .nodes =3D aggre1_noc_nodes, .num_nodes =3D ARRAY_SIZE(aggre1_noc_nodes), @@ -1653,7 +1652,6 @@ static struct qcom_icc_node * const aggre2_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sc7280_aggre2_noc =3D { - .alloc_dyn_id =3D true, .config =3D &sc7280_aggre2_noc_regmap_config, .nodes =3D aggre2_noc_nodes, .num_nodes =3D ARRAY_SIZE(aggre2_noc_nodes), @@ -1675,7 +1673,6 @@ static struct qcom_icc_node * const clk_virt_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sc7280_clk_virt =3D { - .alloc_dyn_id =3D true, .nodes =3D clk_virt_nodes, .num_nodes =3D ARRAY_SIZE(clk_virt_nodes), .bcms =3D clk_virt_bcms, @@ -1746,7 +1743,6 @@ static const struct regmap_config sc7280_cnoc2_regmap= _config =3D { }; =20 static const struct qcom_icc_desc sc7280_cnoc2 =3D { - .alloc_dyn_id =3D true, .config =3D &sc7280_cnoc2_regmap_config, .nodes =3D cnoc2_nodes, .num_nodes =3D ARRAY_SIZE(cnoc2_nodes), @@ -1788,7 +1784,6 @@ static const struct regmap_config sc7280_cnoc3_regmap= _config =3D { }; =20 static const struct qcom_icc_desc sc7280_cnoc3 =3D { - .alloc_dyn_id =3D true, .config =3D &sc7280_cnoc3_regmap_config, .nodes =3D cnoc3_nodes, .num_nodes =3D ARRAY_SIZE(cnoc3_nodes), @@ -1814,7 +1809,6 @@ static const struct regmap_config sc7280_dc_noc_regma= p_config =3D { }; =20 static const struct qcom_icc_desc sc7280_dc_noc =3D { - .alloc_dyn_id =3D true, .config =3D &sc7280_dc_noc_regmap_config, .nodes =3D dc_noc_nodes, .num_nodes =3D ARRAY_SIZE(dc_noc_nodes), @@ -1860,7 +1854,6 @@ static const struct regmap_config sc7280_gem_noc_regm= ap_config =3D { }; =20 static const struct qcom_icc_desc sc7280_gem_noc =3D { - .alloc_dyn_id =3D true, .config =3D &sc7280_gem_noc_regmap_config, .nodes =3D gem_noc_nodes, .num_nodes =3D ARRAY_SIZE(gem_noc_nodes), @@ -1890,7 +1883,6 @@ static const struct regmap_config sc7280_lpass_ag_noc= _regmap_config =3D { }; =20 static const struct qcom_icc_desc sc7280_lpass_ag_noc =3D { - .alloc_dyn_id =3D true, .config =3D &sc7280_lpass_ag_noc_regmap_config, .nodes =3D lpass_ag_noc_nodes, .num_nodes =3D ARRAY_SIZE(lpass_ag_noc_nodes), @@ -1917,7 +1909,6 @@ static const struct regmap_config sc7280_mc_virt_regm= ap_config =3D { }; =20 static const struct qcom_icc_desc sc7280_mc_virt =3D { - .alloc_dyn_id =3D true, .config =3D &sc7280_mc_virt_regmap_config, .nodes =3D mc_virt_nodes, .num_nodes =3D ARRAY_SIZE(mc_virt_nodes), @@ -1954,7 +1945,6 @@ static const struct regmap_config sc7280_mmss_noc_reg= map_config =3D { }; =20 static const struct qcom_icc_desc sc7280_mmss_noc =3D { - .alloc_dyn_id =3D true, .config =3D &sc7280_mmss_noc_regmap_config, .nodes =3D mmss_noc_nodes, .num_nodes =3D ARRAY_SIZE(mmss_noc_nodes), @@ -1983,7 +1973,6 @@ static const struct regmap_config sc7280_nsp_noc_regm= ap_config =3D { }; =20 static const struct qcom_icc_desc sc7280_nsp_noc =3D { - .alloc_dyn_id =3D true, .config =3D &sc7280_nsp_noc_regmap_config, .nodes =3D nsp_noc_nodes, .num_nodes =3D ARRAY_SIZE(nsp_noc_nodes), @@ -2018,7 +2007,6 @@ static const struct regmap_config sc7280_system_noc_r= egmap_config =3D { }; =20 static const struct qcom_icc_desc sc7280_system_noc =3D { - .alloc_dyn_id =3D true, .config =3D &sc7280_system_noc_regmap_config, .nodes =3D system_noc_nodes, .num_nodes =3D ARRAY_SIZE(system_noc_nodes), diff --git a/drivers/interconnect/qcom/sc8180x.c b/drivers/interconnect/qco= m/sc8180x.c index b80a255ba8c322f72f436a351ee3ea4a354be1fa..c9bf1af54e37f0d67575dfd805e= 2c02ca000f759 100644 --- a/drivers/interconnect/qcom/sc8180x.c +++ b/drivers/interconnect/qcom/sc8180x.c @@ -1790,7 +1790,6 @@ static struct qcom_icc_node * const system_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sc8180x_aggre1_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D aggre1_noc_nodes, .num_nodes =3D ARRAY_SIZE(aggre1_noc_nodes), .bcms =3D aggre1_noc_bcms, @@ -1798,7 +1797,6 @@ static const struct qcom_icc_desc sc8180x_aggre1_noc = =3D { }; =20 static const struct qcom_icc_desc sc8180x_aggre2_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D aggre2_noc_nodes, .num_nodes =3D ARRAY_SIZE(aggre2_noc_nodes), .bcms =3D aggre2_noc_bcms, @@ -1806,7 +1804,6 @@ static const struct qcom_icc_desc sc8180x_aggre2_noc = =3D { }; =20 static const struct qcom_icc_desc sc8180x_camnoc_virt =3D { - .alloc_dyn_id =3D true, .nodes =3D camnoc_virt_nodes, .num_nodes =3D ARRAY_SIZE(camnoc_virt_nodes), .bcms =3D camnoc_virt_bcms, @@ -1814,7 +1811,6 @@ static const struct qcom_icc_desc sc8180x_camnoc_virt= =3D { }; =20 static const struct qcom_icc_desc sc8180x_compute_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D compute_noc_nodes, .num_nodes =3D ARRAY_SIZE(compute_noc_nodes), .bcms =3D compute_noc_bcms, @@ -1822,7 +1818,6 @@ static const struct qcom_icc_desc sc8180x_compute_noc= =3D { }; =20 static const struct qcom_icc_desc sc8180x_config_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D config_noc_nodes, .num_nodes =3D ARRAY_SIZE(config_noc_nodes), .bcms =3D config_noc_bcms, @@ -1830,13 +1825,11 @@ static const struct qcom_icc_desc sc8180x_config_no= c =3D { }; =20 static const struct qcom_icc_desc sc8180x_dc_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D dc_noc_nodes, .num_nodes =3D ARRAY_SIZE(dc_noc_nodes), }; =20 static const struct qcom_icc_desc sc8180x_gem_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D gem_noc_nodes, .num_nodes =3D ARRAY_SIZE(gem_noc_nodes), .bcms =3D gem_noc_bcms, @@ -1844,7 +1837,6 @@ static const struct qcom_icc_desc sc8180x_gem_noc = =3D { }; =20 static const struct qcom_icc_desc sc8180x_mc_virt =3D { - .alloc_dyn_id =3D true, .nodes =3D mc_virt_nodes, .num_nodes =3D ARRAY_SIZE(mc_virt_nodes), .bcms =3D mc_virt_bcms, @@ -1852,7 +1844,6 @@ static const struct qcom_icc_desc sc8180x_mc_virt = =3D { }; =20 static const struct qcom_icc_desc sc8180x_mmss_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D mmss_noc_nodes, .num_nodes =3D ARRAY_SIZE(mmss_noc_nodes), .bcms =3D mmss_noc_bcms, @@ -1860,7 +1851,6 @@ static const struct qcom_icc_desc sc8180x_mmss_noc = =3D { }; =20 static const struct qcom_icc_desc sc8180x_system_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D system_noc_nodes, .num_nodes =3D ARRAY_SIZE(system_noc_nodes), .bcms =3D system_noc_bcms, @@ -1881,7 +1871,6 @@ static struct qcom_icc_node * const qup_virt_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sc8180x_qup_virt =3D { - .alloc_dyn_id =3D true, .nodes =3D qup_virt_nodes, .num_nodes =3D ARRAY_SIZE(qup_virt_nodes), .bcms =3D qup_virt_bcms, diff --git a/drivers/interconnect/qcom/sc8280xp.c b/drivers/interconnect/qc= om/sc8280xp.c index c46846191e63f41a16dd3af5f0a77919b4b14568..ed2161da37bfee48ac96876f4cf= 9d2054064b868 100644 --- a/drivers/interconnect/qcom/sc8280xp.c +++ b/drivers/interconnect/qcom/sc8280xp.c @@ -1998,7 +1998,6 @@ static struct qcom_icc_node * const aggre1_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sc8280xp_aggre1_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D aggre1_noc_nodes, .num_nodes =3D ARRAY_SIZE(aggre1_noc_nodes), .bcms =3D aggre1_noc_bcms, @@ -2035,7 +2034,6 @@ static struct qcom_icc_node * const aggre2_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sc8280xp_aggre2_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D aggre2_noc_nodes, .num_nodes =3D ARRAY_SIZE(aggre2_noc_nodes), .bcms =3D aggre2_noc_bcms, @@ -2058,7 +2056,6 @@ static struct qcom_icc_node * const clk_virt_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sc8280xp_clk_virt =3D { - .alloc_dyn_id =3D true, .nodes =3D clk_virt_nodes, .num_nodes =3D ARRAY_SIZE(clk_virt_nodes), .bcms =3D clk_virt_bcms, @@ -2163,7 +2160,6 @@ static struct qcom_icc_node * const config_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sc8280xp_config_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D config_noc_nodes, .num_nodes =3D ARRAY_SIZE(config_noc_nodes), .bcms =3D config_noc_bcms, @@ -2180,7 +2176,6 @@ static struct qcom_icc_node * const dc_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sc8280xp_dc_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D dc_noc_nodes, .num_nodes =3D ARRAY_SIZE(dc_noc_nodes), .bcms =3D dc_noc_bcms, @@ -2215,7 +2210,6 @@ static struct qcom_icc_node * const gem_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sc8280xp_gem_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D gem_noc_nodes, .num_nodes =3D ARRAY_SIZE(gem_noc_nodes), .bcms =3D gem_noc_bcms, @@ -2239,7 +2233,6 @@ static struct qcom_icc_node * const lpass_ag_noc_node= s[] =3D { }; =20 static const struct qcom_icc_desc sc8280xp_lpass_ag_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D lpass_ag_noc_nodes, .num_nodes =3D ARRAY_SIZE(lpass_ag_noc_nodes), .bcms =3D lpass_ag_noc_bcms, @@ -2257,7 +2250,6 @@ static struct qcom_icc_node * const mc_virt_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sc8280xp_mc_virt =3D { - .alloc_dyn_id =3D true, .nodes =3D mc_virt_nodes, .num_nodes =3D ARRAY_SIZE(mc_virt_nodes), .bcms =3D mc_virt_bcms, @@ -2289,7 +2281,6 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sc8280xp_mmss_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D mmss_noc_nodes, .num_nodes =3D ARRAY_SIZE(mmss_noc_nodes), .bcms =3D mmss_noc_bcms, @@ -2310,7 +2301,6 @@ static struct qcom_icc_node * const nspa_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sc8280xp_nspa_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D nspa_noc_nodes, .num_nodes =3D ARRAY_SIZE(nspa_noc_nodes), .bcms =3D nspa_noc_bcms, @@ -2331,7 +2321,6 @@ static struct qcom_icc_node * const nspb_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sc8280xp_nspb_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D nspb_noc_nodes, .num_nodes =3D ARRAY_SIZE(nspb_noc_nodes), .bcms =3D nspb_noc_bcms, @@ -2361,7 +2350,6 @@ static struct qcom_icc_node * const system_noc_main_n= odes[] =3D { }; =20 static const struct qcom_icc_desc sc8280xp_system_noc_main =3D { - .alloc_dyn_id =3D true, .nodes =3D system_noc_main_nodes, .num_nodes =3D ARRAY_SIZE(system_noc_main_nodes), .bcms =3D system_noc_main_bcms, diff --git a/drivers/interconnect/qcom/sdm670.c b/drivers/interconnect/qcom= /sdm670.c index 5e6a5c54f485ebef7be619d76e4d901811956ee4..88f4768b765c58f7338aac34185= 9f7221b4ebc82 100644 --- a/drivers/interconnect/qcom/sdm670.c +++ b/drivers/interconnect/qcom/sdm670.c @@ -1266,7 +1266,6 @@ static struct qcom_icc_node * const aggre1_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sdm670_aggre1_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D aggre1_noc_nodes, .num_nodes =3D ARRAY_SIZE(aggre1_noc_nodes), .bcms =3D aggre1_noc_bcms, @@ -1293,7 +1292,6 @@ static struct qcom_icc_node * const aggre2_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sdm670_aggre2_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D aggre2_noc_nodes, .num_nodes =3D ARRAY_SIZE(aggre2_noc_nodes), .bcms =3D aggre2_noc_bcms, @@ -1349,7 +1347,6 @@ static struct qcom_icc_node * const config_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sdm670_config_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D config_noc_nodes, .num_nodes =3D ARRAY_SIZE(config_noc_nodes), .bcms =3D config_noc_bcms, @@ -1366,7 +1363,6 @@ static struct qcom_icc_node * const dc_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sdm670_dc_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D dc_noc_nodes, .num_nodes =3D ARRAY_SIZE(dc_noc_nodes), .bcms =3D dc_noc_bcms, @@ -1385,7 +1381,6 @@ static struct qcom_icc_node * const gladiator_noc_nod= es[] =3D { }; =20 static const struct qcom_icc_desc sdm670_gladiator_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D gladiator_noc_nodes, .num_nodes =3D ARRAY_SIZE(gladiator_noc_nodes), .bcms =3D gladiator_noc_bcms, @@ -1421,7 +1416,6 @@ static struct qcom_icc_node * const mem_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sdm670_mem_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D mem_noc_nodes, .num_nodes =3D ARRAY_SIZE(mem_noc_nodes), .bcms =3D mem_noc_bcms, @@ -1452,7 +1446,6 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sdm670_mmss_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D mmss_noc_nodes, .num_nodes =3D ARRAY_SIZE(mmss_noc_nodes), .bcms =3D mmss_noc_bcms, @@ -1497,7 +1490,6 @@ static struct qcom_icc_node * const system_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sdm670_system_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D system_noc_nodes, .num_nodes =3D ARRAY_SIZE(system_noc_nodes), .bcms =3D system_noc_bcms, diff --git a/drivers/interconnect/qcom/sdm845.c b/drivers/interconnect/qcom= /sdm845.c index 83d7a611cdf72d4b1cc17f86455106574a13cc9b..6d5bbeda0689d7ec8bec575fd38= 4b0414c67ae03 100644 --- a/drivers/interconnect/qcom/sdm845.c +++ b/drivers/interconnect/qcom/sdm845.c @@ -1514,7 +1514,6 @@ static struct qcom_icc_node * const aggre1_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sdm845_aggre1_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D aggre1_noc_nodes, .num_nodes =3D ARRAY_SIZE(aggre1_noc_nodes), .bcms =3D aggre1_noc_bcms, @@ -1544,7 +1543,6 @@ static struct qcom_icc_node * const aggre2_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sdm845_aggre2_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D aggre2_noc_nodes, .num_nodes =3D ARRAY_SIZE(aggre2_noc_nodes), .bcms =3D aggre2_noc_bcms, @@ -1606,7 +1604,6 @@ static struct qcom_icc_node * const config_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sdm845_config_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D config_noc_nodes, .num_nodes =3D ARRAY_SIZE(config_noc_nodes), .bcms =3D config_noc_bcms, @@ -1623,7 +1620,6 @@ static struct qcom_icc_node * const dc_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sdm845_dc_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D dc_noc_nodes, .num_nodes =3D ARRAY_SIZE(dc_noc_nodes), .bcms =3D dc_noc_bcms, @@ -1642,7 +1638,6 @@ static struct qcom_icc_node * const gladiator_noc_nod= es[] =3D { }; =20 static const struct qcom_icc_desc sdm845_gladiator_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D gladiator_noc_nodes, .num_nodes =3D ARRAY_SIZE(gladiator_noc_nodes), .bcms =3D gladiator_noc_bcms, @@ -1678,7 +1673,6 @@ static struct qcom_icc_node * const mem_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sdm845_mem_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D mem_noc_nodes, .num_nodes =3D ARRAY_SIZE(mem_noc_nodes), .bcms =3D mem_noc_bcms, @@ -1713,7 +1707,6 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sdm845_mmss_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D mmss_noc_nodes, .num_nodes =3D ARRAY_SIZE(mmss_noc_nodes), .bcms =3D mmss_noc_bcms, @@ -1760,7 +1753,6 @@ static struct qcom_icc_node * const system_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sdm845_system_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D system_noc_nodes, .num_nodes =3D ARRAY_SIZE(system_noc_nodes), .bcms =3D system_noc_bcms, diff --git a/drivers/interconnect/qcom/sdx55.c b/drivers/interconnect/qcom/= sdx55.c index b1a69e430ef444784fdc31edbe1f80877fc63cec..75ced12869198f53ebb5bfbccc6= 03cbf2316aa1b 100644 --- a/drivers/interconnect/qcom/sdx55.c +++ b/drivers/interconnect/qcom/sdx55.c @@ -782,7 +782,6 @@ static struct qcom_icc_node * const mc_virt_nodes[] =3D= { }; =20 static const struct qcom_icc_desc sdx55_mc_virt =3D { - .alloc_dyn_id =3D true, .nodes =3D mc_virt_nodes, .num_nodes =3D ARRAY_SIZE(mc_virt_nodes), .bcms =3D mc_virt_bcms, @@ -805,7 +804,6 @@ static struct qcom_icc_node * const mem_noc_nodes[] =3D= { }; =20 static const struct qcom_icc_desc sdx55_mem_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D mem_noc_nodes, .num_nodes =3D ARRAY_SIZE(mem_noc_nodes), .bcms =3D mem_noc_bcms, @@ -885,7 +883,6 @@ static struct qcom_icc_node * const system_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sdx55_system_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D system_noc_nodes, .num_nodes =3D ARRAY_SIZE(system_noc_nodes), .bcms =3D system_noc_bcms, diff --git a/drivers/interconnect/qcom/sdx65.c b/drivers/interconnect/qcom/= sdx65.c index 7c8798174e026c9d1fa06b60a75bf15e01a34049..6c5b4e1ec82f5f7cce1a63584cf= 1b718f158d315 100644 --- a/drivers/interconnect/qcom/sdx65.c +++ b/drivers/interconnect/qcom/sdx65.c @@ -769,7 +769,6 @@ static struct qcom_icc_node * const mc_virt_nodes[] =3D= { }; =20 static const struct qcom_icc_desc sdx65_mc_virt =3D { - .alloc_dyn_id =3D true, .nodes =3D mc_virt_nodes, .num_nodes =3D ARRAY_SIZE(mc_virt_nodes), .bcms =3D mc_virt_bcms, @@ -792,7 +791,6 @@ static struct qcom_icc_node * const mem_noc_nodes[] =3D= { }; =20 static const struct qcom_icc_desc sdx65_mem_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D mem_noc_nodes, .num_nodes =3D ARRAY_SIZE(mem_noc_nodes), .bcms =3D mem_noc_bcms, @@ -869,7 +867,6 @@ static struct qcom_icc_node * const system_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sdx65_system_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D system_noc_nodes, .num_nodes =3D ARRAY_SIZE(system_noc_nodes), .bcms =3D system_noc_bcms, diff --git a/drivers/interconnect/qcom/sdx75.c b/drivers/interconnect/qcom/= sdx75.c index 3721d8f503a022e4c5fde62b0aa9eed9989c1554..e56202b9bc4b66e7824f5969ff0= 01ea67e0e70d4 100644 --- a/drivers/interconnect/qcom/sdx75.c +++ b/drivers/interconnect/qcom/sdx75.c @@ -868,7 +868,6 @@ static struct qcom_icc_node * const clk_virt_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sdx75_clk_virt =3D { - .alloc_dyn_id =3D true, .nodes =3D clk_virt_nodes, .num_nodes =3D ARRAY_SIZE(clk_virt_nodes), .bcms =3D clk_virt_bcms, @@ -884,7 +883,6 @@ static struct qcom_icc_node * const dc_noc_nodes[] =3D { }; =20 static const struct qcom_icc_desc sdx75_dc_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D dc_noc_nodes, .num_nodes =3D ARRAY_SIZE(dc_noc_nodes), }; @@ -911,7 +909,6 @@ static struct qcom_icc_node * const gem_noc_nodes[] =3D= { }; =20 static const struct qcom_icc_desc sdx75_gem_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D gem_noc_nodes, .num_nodes =3D ARRAY_SIZE(gem_noc_nodes), .bcms =3D gem_noc_bcms, @@ -928,7 +925,6 @@ static struct qcom_icc_node * const mc_virt_nodes[] =3D= { }; =20 static const struct qcom_icc_desc sdx75_mc_virt =3D { - .alloc_dyn_id =3D true, .nodes =3D mc_virt_nodes, .num_nodes =3D ARRAY_SIZE(mc_virt_nodes), .bcms =3D mc_virt_bcms, @@ -948,7 +944,6 @@ static struct qcom_icc_node * const pcie_anoc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sdx75_pcie_anoc =3D { - .alloc_dyn_id =3D true, .nodes =3D pcie_anoc_nodes, .num_nodes =3D ARRAY_SIZE(pcie_anoc_nodes), .bcms =3D pcie_anoc_bcms, @@ -1027,7 +1022,6 @@ static struct qcom_icc_node * const system_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sdx75_system_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D system_noc_nodes, .num_nodes =3D ARRAY_SIZE(system_noc_nodes), .bcms =3D system_noc_bcms, diff --git a/drivers/interconnect/qcom/sm6350.c b/drivers/interconnect/qcom= /sm6350.c index df2511dbfa96ba7454612ea0fcdf4a8f5fc39540..99c435a5968f6eb659e4713599d= 8cef73965a586 100644 --- a/drivers/interconnect/qcom/sm6350.c +++ b/drivers/interconnect/qcom/sm6350.c @@ -1389,7 +1389,6 @@ static struct qcom_icc_node * const aggre1_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sm6350_aggre1_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D aggre1_noc_nodes, .num_nodes =3D ARRAY_SIZE(aggre1_noc_nodes), .bcms =3D aggre1_noc_bcms, @@ -1415,7 +1414,6 @@ static struct qcom_icc_node * const aggre2_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sm6350_aggre2_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D aggre2_noc_nodes, .num_nodes =3D ARRAY_SIZE(aggre2_noc_nodes), .bcms =3D aggre2_noc_bcms, @@ -1443,7 +1441,6 @@ static struct qcom_icc_node * const clk_virt_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sm6350_clk_virt =3D { - .alloc_dyn_id =3D true, .nodes =3D clk_virt_nodes, .num_nodes =3D ARRAY_SIZE(clk_virt_nodes), .bcms =3D clk_virt_bcms, @@ -1463,7 +1460,6 @@ static struct qcom_icc_node * const compute_noc_nodes= [] =3D { }; =20 static const struct qcom_icc_desc sm6350_compute_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D compute_noc_nodes, .num_nodes =3D ARRAY_SIZE(compute_noc_nodes), .bcms =3D compute_noc_bcms, @@ -1524,7 +1520,6 @@ static struct qcom_icc_node * const config_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sm6350_config_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D config_noc_nodes, .num_nodes =3D ARRAY_SIZE(config_noc_nodes), .bcms =3D config_noc_bcms, @@ -1541,7 +1536,6 @@ static struct qcom_icc_node * const dc_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sm6350_dc_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D dc_noc_nodes, .num_nodes =3D ARRAY_SIZE(dc_noc_nodes), .bcms =3D dc_noc_bcms, @@ -1573,7 +1567,6 @@ static struct qcom_icc_node * const gem_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sm6350_gem_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D gem_noc_nodes, .num_nodes =3D ARRAY_SIZE(gem_noc_nodes), .bcms =3D gem_noc_bcms, @@ -1601,7 +1594,6 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sm6350_mmss_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D mmss_noc_nodes, .num_nodes =3D ARRAY_SIZE(mmss_noc_nodes), .bcms =3D mmss_noc_bcms, @@ -1626,7 +1618,6 @@ static struct qcom_icc_node * const npu_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sm6350_npu_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D npu_noc_nodes, .num_nodes =3D ARRAY_SIZE(npu_noc_nodes), .bcms =3D npu_noc_bcms, @@ -1663,7 +1654,6 @@ static struct qcom_icc_node * const system_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sm6350_system_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D system_noc_nodes, .num_nodes =3D ARRAY_SIZE(system_noc_nodes), .bcms =3D system_noc_bcms, diff --git a/drivers/interconnect/qcom/sm7150.c b/drivers/interconnect/qcom= /sm7150.c index 296cf350a08fb521ea12fce69a6b1ab19b6c97a8..0390d0468b48c10b7bb254c7376= 6fac24e5d6c72 100644 --- a/drivers/interconnect/qcom/sm7150.c +++ b/drivers/interconnect/qcom/sm7150.c @@ -1431,7 +1431,6 @@ static struct qcom_icc_node * const aggre1_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sm7150_aggre1_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D aggre1_noc_nodes, .num_nodes =3D ARRAY_SIZE(aggre1_noc_nodes), .bcms =3D aggre1_noc_bcms, @@ -1461,7 +1460,6 @@ static struct qcom_icc_node * const aggre2_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sm7150_aggre2_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D aggre2_noc_nodes, .num_nodes =3D ARRAY_SIZE(aggre2_noc_nodes), .bcms =3D aggre2_noc_bcms, @@ -1481,7 +1479,6 @@ static struct qcom_icc_node * const camnoc_virt_nodes= [] =3D { }; =20 static const struct qcom_icc_desc sm7150_camnoc_virt =3D { - .alloc_dyn_id =3D true, .nodes =3D camnoc_virt_nodes, .num_nodes =3D ARRAY_SIZE(camnoc_virt_nodes), .bcms =3D camnoc_virt_bcms, @@ -1499,7 +1496,6 @@ static struct qcom_icc_node * const compute_noc_nodes= [] =3D { }; =20 static const struct qcom_icc_desc sm7150_compute_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D compute_noc_nodes, .num_nodes =3D ARRAY_SIZE(compute_noc_nodes), .bcms =3D compute_noc_bcms, @@ -1565,7 +1561,6 @@ static struct qcom_icc_node * const config_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sm7150_config_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D config_noc_nodes, .num_nodes =3D ARRAY_SIZE(config_noc_nodes), .bcms =3D config_noc_bcms, @@ -1582,7 +1577,6 @@ static struct qcom_icc_node * const dc_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sm7150_dc_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D dc_noc_nodes, .num_nodes =3D ARRAY_SIZE(dc_noc_nodes), .bcms =3D dc_noc_bcms, @@ -1614,7 +1608,6 @@ static struct qcom_icc_node * const gem_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sm7150_gem_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D gem_noc_nodes, .num_nodes =3D ARRAY_SIZE(gem_noc_nodes), .bcms =3D gem_noc_bcms, @@ -1632,7 +1625,6 @@ static struct qcom_icc_node * const mc_virt_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sm7150_mc_virt =3D { - .alloc_dyn_id =3D true, .nodes =3D mc_virt_nodes, .num_nodes =3D ARRAY_SIZE(mc_virt_nodes), .bcms =3D mc_virt_bcms, @@ -1664,7 +1656,6 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sm7150_mmss_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D mmss_noc_nodes, .num_nodes =3D ARRAY_SIZE(mmss_noc_nodes), .bcms =3D mmss_noc_bcms, @@ -1701,7 +1692,6 @@ static struct qcom_icc_node * const system_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sm7150_system_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D system_noc_nodes, .num_nodes =3D ARRAY_SIZE(system_noc_nodes), .bcms =3D system_noc_bcms, diff --git a/drivers/interconnect/qcom/sm8150.c b/drivers/interconnect/qcom= /sm8150.c index 58a6643921bb4e9c3298352e3fb5755b92162a6d..ae732afbd155864137644e0789c= 6b61ef81a1414 100644 --- a/drivers/interconnect/qcom/sm8150.c +++ b/drivers/interconnect/qcom/sm8150.c @@ -1538,7 +1538,6 @@ static struct qcom_icc_node * const aggre1_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sm8150_aggre1_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D aggre1_noc_nodes, .num_nodes =3D ARRAY_SIZE(aggre1_noc_nodes), .bcms =3D aggre1_noc_bcms, @@ -1574,7 +1573,6 @@ static struct qcom_icc_node * const aggre2_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sm8150_aggre2_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D aggre2_noc_nodes, .num_nodes =3D ARRAY_SIZE(aggre2_noc_nodes), .bcms =3D aggre2_noc_bcms, @@ -1593,7 +1591,6 @@ static struct qcom_icc_node * const camnoc_virt_nodes= [] =3D { }; =20 static const struct qcom_icc_desc sm8150_camnoc_virt =3D { - .alloc_dyn_id =3D true, .nodes =3D camnoc_virt_nodes, .num_nodes =3D ARRAY_SIZE(camnoc_virt_nodes), .bcms =3D camnoc_virt_bcms, @@ -1611,7 +1608,6 @@ static struct qcom_icc_node * const compute_noc_nodes= [] =3D { }; =20 static const struct qcom_icc_desc sm8150_compute_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D compute_noc_nodes, .num_nodes =3D ARRAY_SIZE(compute_noc_nodes), .bcms =3D compute_noc_bcms, @@ -1680,7 +1676,6 @@ static struct qcom_icc_node * const config_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sm8150_config_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D config_noc_nodes, .num_nodes =3D ARRAY_SIZE(config_noc_nodes), .bcms =3D config_noc_bcms, @@ -1697,7 +1692,6 @@ static struct qcom_icc_node * const dc_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sm8150_dc_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D dc_noc_nodes, .num_nodes =3D ARRAY_SIZE(dc_noc_nodes), .bcms =3D dc_noc_bcms, @@ -1733,7 +1727,6 @@ static struct qcom_icc_node * const gem_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sm8150_gem_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D gem_noc_nodes, .num_nodes =3D ARRAY_SIZE(gem_noc_nodes), .bcms =3D gem_noc_bcms, @@ -1751,7 +1744,6 @@ static struct qcom_icc_node * const mc_virt_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sm8150_mc_virt =3D { - .alloc_dyn_id =3D true, .nodes =3D mc_virt_nodes, .num_nodes =3D ARRAY_SIZE(mc_virt_nodes), .bcms =3D mc_virt_bcms, @@ -1782,7 +1774,6 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sm8150_mmss_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D mmss_noc_nodes, .num_nodes =3D ARRAY_SIZE(mmss_noc_nodes), .bcms =3D mmss_noc_bcms, @@ -1824,7 +1815,6 @@ static struct qcom_icc_node * const system_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sm8150_system_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D system_noc_nodes, .num_nodes =3D ARRAY_SIZE(system_noc_nodes), .bcms =3D system_noc_bcms, diff --git a/drivers/interconnect/qcom/sm8350.c b/drivers/interconnect/qcom= /sm8350.c index 75a9b0ddb8d5c5a3d990bbe0e5067a06d5903a86..bb793d72489335aa145c99b0932= 0f8b7faaa37d6 100644 --- a/drivers/interconnect/qcom/sm8350.c +++ b/drivers/interconnect/qcom/sm8350.c @@ -1497,7 +1497,6 @@ static struct qcom_icc_node * const aggre1_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sm8350_aggre1_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D aggre1_noc_nodes, .num_nodes =3D ARRAY_SIZE(aggre1_noc_nodes), .bcms =3D aggre1_noc_bcms, @@ -1529,7 +1528,6 @@ static struct qcom_icc_node * const aggre2_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sm8350_aggre2_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D aggre2_noc_nodes, .num_nodes =3D ARRAY_SIZE(aggre2_noc_nodes), .bcms =3D aggre2_noc_bcms, @@ -1609,7 +1607,6 @@ static struct qcom_icc_node * const config_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sm8350_config_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D config_noc_nodes, .num_nodes =3D ARRAY_SIZE(config_noc_nodes), .bcms =3D config_noc_bcms, @@ -1626,7 +1623,6 @@ static struct qcom_icc_node * const dc_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sm8350_dc_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D dc_noc_nodes, .num_nodes =3D ARRAY_SIZE(dc_noc_nodes), .bcms =3D dc_noc_bcms, @@ -1663,7 +1659,6 @@ static struct qcom_icc_node * const gem_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sm8350_gem_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D gem_noc_nodes, .num_nodes =3D ARRAY_SIZE(gem_noc_nodes), .bcms =3D gem_noc_bcms, @@ -1684,7 +1679,6 @@ static struct qcom_icc_node * const lpass_ag_noc_node= s[] =3D { }; =20 static const struct qcom_icc_desc sm8350_lpass_ag_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D lpass_ag_noc_nodes, .num_nodes =3D ARRAY_SIZE(lpass_ag_noc_nodes), .bcms =3D lpass_ag_noc_bcms, @@ -1702,7 +1696,6 @@ static struct qcom_icc_node * const mc_virt_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sm8350_mc_virt =3D { - .alloc_dyn_id =3D true, .nodes =3D mc_virt_nodes, .num_nodes =3D ARRAY_SIZE(mc_virt_nodes), .bcms =3D mc_virt_bcms, @@ -1733,7 +1726,6 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sm8350_mmss_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D mmss_noc_nodes, .num_nodes =3D ARRAY_SIZE(mmss_noc_nodes), .bcms =3D mmss_noc_bcms, @@ -1753,7 +1745,6 @@ static struct qcom_icc_node * const nsp_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sm8350_compute_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D nsp_noc_nodes, .num_nodes =3D ARRAY_SIZE(nsp_noc_nodes), .bcms =3D nsp_noc_bcms, @@ -1779,7 +1770,6 @@ static struct qcom_icc_node * const system_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sm8350_system_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D system_noc_nodes, .num_nodes =3D ARRAY_SIZE(system_noc_nodes), .bcms =3D system_noc_bcms, diff --git a/drivers/interconnect/qcom/sm8450.c b/drivers/interconnect/qcom= /sm8450.c index dd61e03b5a819ac8842afe5928800ed8640ff5ed..669a638bf3efcd9ed594d63f25c= 9022314fa1d54 100644 --- a/drivers/interconnect/qcom/sm8450.c +++ b/drivers/interconnect/qcom/sm8450.c @@ -1490,7 +1490,6 @@ static struct qcom_icc_node * const aggre1_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sm8450_aggre1_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D aggre1_noc_nodes, .num_nodes =3D ARRAY_SIZE(aggre1_noc_nodes), .bcms =3D aggre1_noc_bcms, @@ -1518,7 +1517,6 @@ static struct qcom_icc_node * const aggre2_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sm8450_aggre2_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D aggre2_noc_nodes, .num_nodes =3D ARRAY_SIZE(aggre2_noc_nodes), .bcms =3D aggre2_noc_bcms, @@ -1541,7 +1539,6 @@ static struct qcom_icc_node * const clk_virt_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sm8450_clk_virt =3D { - .alloc_dyn_id =3D true, .nodes =3D clk_virt_nodes, .num_nodes =3D ARRAY_SIZE(clk_virt_nodes), .bcms =3D clk_virt_bcms, @@ -1611,7 +1608,6 @@ static struct qcom_icc_node * const config_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sm8450_config_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D config_noc_nodes, .num_nodes =3D ARRAY_SIZE(config_noc_nodes), .bcms =3D config_noc_bcms, @@ -1647,7 +1643,6 @@ static struct qcom_icc_node * const gem_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sm8450_gem_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D gem_noc_nodes, .num_nodes =3D ARRAY_SIZE(gem_noc_nodes), .bcms =3D gem_noc_bcms, @@ -1670,7 +1665,6 @@ static struct qcom_icc_node * const lpass_ag_noc_node= s[] =3D { }; =20 static const struct qcom_icc_desc sm8450_lpass_ag_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D lpass_ag_noc_nodes, .num_nodes =3D ARRAY_SIZE(lpass_ag_noc_nodes), .bcms =3D lpass_ag_noc_bcms, @@ -1692,7 +1686,6 @@ static struct qcom_icc_node * const mc_virt_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sm8450_mc_virt =3D { - .alloc_dyn_id =3D true, .nodes =3D mc_virt_nodes, .num_nodes =3D ARRAY_SIZE(mc_virt_nodes), .bcms =3D mc_virt_bcms, @@ -1728,7 +1721,6 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sm8450_mmss_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D mmss_noc_nodes, .num_nodes =3D ARRAY_SIZE(mmss_noc_nodes), .bcms =3D mmss_noc_bcms, @@ -1747,7 +1739,6 @@ static struct qcom_icc_node * const nsp_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sm8450_nsp_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D nsp_noc_nodes, .num_nodes =3D ARRAY_SIZE(nsp_noc_nodes), .bcms =3D nsp_noc_bcms, @@ -1767,7 +1758,6 @@ static struct qcom_icc_node * const pcie_anoc_nodes[]= =3D { }; =20 static const struct qcom_icc_desc sm8450_pcie_anoc =3D { - .alloc_dyn_id =3D true, .nodes =3D pcie_anoc_nodes, .num_nodes =3D ARRAY_SIZE(pcie_anoc_nodes), .bcms =3D pcie_anoc_bcms, @@ -1796,7 +1786,6 @@ static struct qcom_icc_node * const system_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sm8450_system_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D system_noc_nodes, .num_nodes =3D ARRAY_SIZE(system_noc_nodes), .bcms =3D system_noc_bcms, diff --git a/drivers/interconnect/qcom/sm8550.c b/drivers/interconnect/qcom= /sm8550.c index 24b682a5bdd1873b4e3e655a9c8021e43987f008..d01762e132722ff445e41efa9a2= 3e898aa66fb74 100644 --- a/drivers/interconnect/qcom/sm8550.c +++ b/drivers/interconnect/qcom/sm8550.c @@ -1241,7 +1241,6 @@ static struct qcom_icc_node * const aggre1_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sm8550_aggre1_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D aggre1_noc_nodes, .num_nodes =3D ARRAY_SIZE(aggre1_noc_nodes), .bcms =3D aggre1_noc_bcms, @@ -1265,7 +1264,6 @@ static struct qcom_icc_node * const aggre2_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sm8550_aggre2_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D aggre2_noc_nodes, .num_nodes =3D ARRAY_SIZE(aggre2_noc_nodes), .bcms =3D aggre2_noc_bcms, @@ -1288,7 +1286,6 @@ static struct qcom_icc_node * const clk_virt_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sm8550_clk_virt =3D { - .alloc_dyn_id =3D true, .nodes =3D clk_virt_nodes, .num_nodes =3D ARRAY_SIZE(clk_virt_nodes), .bcms =3D clk_virt_bcms, @@ -1349,7 +1346,6 @@ static struct qcom_icc_node * const config_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sm8550_config_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D config_noc_nodes, .num_nodes =3D ARRAY_SIZE(config_noc_nodes), .bcms =3D config_noc_bcms, @@ -1374,7 +1370,6 @@ static struct qcom_icc_node * const cnoc_main_nodes[]= =3D { }; =20 static const struct qcom_icc_desc sm8550_cnoc_main =3D { - .alloc_dyn_id =3D true, .nodes =3D cnoc_main_nodes, .num_nodes =3D ARRAY_SIZE(cnoc_main_nodes), .bcms =3D cnoc_main_bcms, @@ -1405,7 +1400,6 @@ static struct qcom_icc_node * const gem_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sm8550_gem_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D gem_noc_nodes, .num_nodes =3D ARRAY_SIZE(gem_noc_nodes), .bcms =3D gem_noc_bcms, @@ -1421,7 +1415,6 @@ static struct qcom_icc_node * const lpass_ag_noc_node= s[] =3D { }; =20 static const struct qcom_icc_desc sm8550_lpass_ag_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D lpass_ag_noc_nodes, .num_nodes =3D ARRAY_SIZE(lpass_ag_noc_nodes), .bcms =3D lpass_ag_noc_bcms, @@ -1438,7 +1431,6 @@ static struct qcom_icc_node * const lpass_lpiaon_noc_= nodes[] =3D { }; =20 static const struct qcom_icc_desc sm8550_lpass_lpiaon_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D lpass_lpiaon_noc_nodes, .num_nodes =3D ARRAY_SIZE(lpass_lpiaon_noc_nodes), .bcms =3D lpass_lpiaon_noc_bcms, @@ -1454,7 +1446,6 @@ static struct qcom_icc_node * const lpass_lpicx_noc_n= odes[] =3D { }; =20 static const struct qcom_icc_desc sm8550_lpass_lpicx_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D lpass_lpicx_noc_nodes, .num_nodes =3D ARRAY_SIZE(lpass_lpicx_noc_nodes), .bcms =3D lpass_lpicx_noc_bcms, @@ -1472,7 +1463,6 @@ static struct qcom_icc_node * const mc_virt_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sm8550_mc_virt =3D { - .alloc_dyn_id =3D true, .nodes =3D mc_virt_nodes, .num_nodes =3D ARRAY_SIZE(mc_virt_nodes), .bcms =3D mc_virt_bcms, @@ -1501,7 +1491,6 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sm8550_mmss_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D mmss_noc_nodes, .num_nodes =3D ARRAY_SIZE(mmss_noc_nodes), .bcms =3D mmss_noc_bcms, @@ -1518,7 +1507,6 @@ static struct qcom_icc_node * const nsp_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sm8550_nsp_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D nsp_noc_nodes, .num_nodes =3D ARRAY_SIZE(nsp_noc_nodes), .bcms =3D nsp_noc_bcms, @@ -1538,7 +1526,6 @@ static struct qcom_icc_node * const pcie_anoc_nodes[]= =3D { }; =20 static const struct qcom_icc_desc sm8550_pcie_anoc =3D { - .alloc_dyn_id =3D true, .nodes =3D pcie_anoc_nodes, .num_nodes =3D ARRAY_SIZE(pcie_anoc_nodes), .bcms =3D pcie_anoc_bcms, @@ -1562,7 +1549,6 @@ static struct qcom_icc_node * const system_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sm8550_system_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D system_noc_nodes, .num_nodes =3D ARRAY_SIZE(system_noc_nodes), .bcms =3D system_noc_bcms, diff --git a/drivers/interconnect/qcom/sm8650.c b/drivers/interconnect/qcom= /sm8650.c index 629ff30e7ee70567beb4c9bd21b9b91f53b39526..cf3ae734d4c357d526d4e310bc0= 3bda7ea602e2a 100644 --- a/drivers/interconnect/qcom/sm8650.c +++ b/drivers/interconnect/qcom/sm8650.c @@ -1595,7 +1595,6 @@ static struct qcom_icc_node * const aggre1_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sm8650_aggre1_noc =3D { - .alloc_dyn_id =3D true, .config =3D &icc_regmap_config, .nodes =3D aggre1_noc_nodes, .num_nodes =3D ARRAY_SIZE(aggre1_noc_nodes), @@ -1618,7 +1617,6 @@ static struct qcom_icc_node * const aggre2_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sm8650_aggre2_noc =3D { - .alloc_dyn_id =3D true, .config =3D &icc_regmap_config, .nodes =3D aggre2_noc_nodes, .num_nodes =3D ARRAY_SIZE(aggre2_noc_nodes), @@ -1642,7 +1640,6 @@ static struct qcom_icc_node * const clk_virt_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sm8650_clk_virt =3D { - .alloc_dyn_id =3D true, .nodes =3D clk_virt_nodes, .num_nodes =3D ARRAY_SIZE(clk_virt_nodes), .bcms =3D clk_virt_bcms, @@ -1704,7 +1701,6 @@ static struct qcom_icc_node * const config_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sm8650_config_noc =3D { - .alloc_dyn_id =3D true, .config =3D &icc_regmap_config, .nodes =3D config_noc_nodes, .num_nodes =3D ARRAY_SIZE(config_noc_nodes), @@ -1733,7 +1729,6 @@ static struct qcom_icc_node * const cnoc_main_nodes[]= =3D { }; =20 static const struct qcom_icc_desc sm8650_cnoc_main =3D { - .alloc_dyn_id =3D true, .config =3D &icc_regmap_config, .nodes =3D cnoc_main_nodes, .num_nodes =3D ARRAY_SIZE(cnoc_main_nodes), @@ -1767,7 +1762,6 @@ static struct qcom_icc_node * const gem_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sm8650_gem_noc =3D { - .alloc_dyn_id =3D true, .config =3D &icc_regmap_config, .nodes =3D gem_noc_nodes, .num_nodes =3D ARRAY_SIZE(gem_noc_nodes), @@ -1781,7 +1775,6 @@ static struct qcom_icc_node * const lpass_ag_noc_node= s[] =3D { }; =20 static const struct qcom_icc_desc sm8650_lpass_ag_noc =3D { - .alloc_dyn_id =3D true, .config =3D &icc_regmap_config, .nodes =3D lpass_ag_noc_nodes, .num_nodes =3D ARRAY_SIZE(lpass_ag_noc_nodes), @@ -1797,7 +1790,6 @@ static struct qcom_icc_node * const lpass_lpiaon_noc_= nodes[] =3D { }; =20 static const struct qcom_icc_desc sm8650_lpass_lpiaon_noc =3D { - .alloc_dyn_id =3D true, .config =3D &icc_regmap_config, .nodes =3D lpass_lpiaon_noc_nodes, .num_nodes =3D ARRAY_SIZE(lpass_lpiaon_noc_nodes), @@ -1811,7 +1803,6 @@ static struct qcom_icc_node * const lpass_lpicx_noc_n= odes[] =3D { }; =20 static const struct qcom_icc_desc sm8650_lpass_lpicx_noc =3D { - .alloc_dyn_id =3D true, .config =3D &icc_regmap_config, .nodes =3D lpass_lpicx_noc_nodes, .num_nodes =3D ARRAY_SIZE(lpass_lpicx_noc_nodes), @@ -1828,7 +1819,6 @@ static struct qcom_icc_node * const mc_virt_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sm8650_mc_virt =3D { - .alloc_dyn_id =3D true, .nodes =3D mc_virt_nodes, .num_nodes =3D ARRAY_SIZE(mc_virt_nodes), .bcms =3D mc_virt_bcms, @@ -1857,7 +1847,6 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sm8650_mmss_noc =3D { - .alloc_dyn_id =3D true, .config =3D &icc_regmap_config, .nodes =3D mmss_noc_nodes, .num_nodes =3D ARRAY_SIZE(mmss_noc_nodes), @@ -1875,7 +1864,6 @@ static struct qcom_icc_node * const nsp_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sm8650_nsp_noc =3D { - .alloc_dyn_id =3D true, .config =3D &icc_regmap_config, .nodes =3D nsp_noc_nodes, .num_nodes =3D ARRAY_SIZE(nsp_noc_nodes), @@ -1896,7 +1884,6 @@ static struct qcom_icc_node * const pcie_anoc_nodes[]= =3D { }; =20 static const struct qcom_icc_desc sm8650_pcie_anoc =3D { - .alloc_dyn_id =3D true, .config =3D &icc_regmap_config, .nodes =3D pcie_anoc_nodes, .num_nodes =3D ARRAY_SIZE(pcie_anoc_nodes), @@ -1918,7 +1905,6 @@ static struct qcom_icc_node * const system_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sm8650_system_noc =3D { - .alloc_dyn_id =3D true, .config =3D &icc_regmap_config, .nodes =3D system_noc_nodes, .num_nodes =3D ARRAY_SIZE(system_noc_nodes), diff --git a/drivers/interconnect/qcom/sm8750.c b/drivers/interconnect/qcom= /sm8750.c index a46c1553ce0fd13b99a7d327eb575b232bc36509..1486c0b8f4c163030913dfcfc4c= 2af7fd3d36fb1 100644 --- a/drivers/interconnect/qcom/sm8750.c +++ b/drivers/interconnect/qcom/sm8750.c @@ -1194,7 +1194,6 @@ static struct qcom_icc_node * const aggre1_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sm8750_aggre1_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D aggre1_noc_nodes, .num_nodes =3D ARRAY_SIZE(aggre1_noc_nodes), }; @@ -1217,7 +1216,6 @@ static struct qcom_icc_node * const aggre2_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sm8750_aggre2_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D aggre2_noc_nodes, .num_nodes =3D ARRAY_SIZE(aggre2_noc_nodes), .bcms =3D aggre2_noc_bcms, @@ -1240,7 +1238,6 @@ static struct qcom_icc_node * const clk_virt_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sm8750_clk_virt =3D { - .alloc_dyn_id =3D true, .nodes =3D clk_virt_nodes, .num_nodes =3D ARRAY_SIZE(clk_virt_nodes), .bcms =3D clk_virt_bcms, @@ -1290,7 +1287,6 @@ static struct qcom_icc_node * const config_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sm8750_config_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D config_noc_nodes, .num_nodes =3D ARRAY_SIZE(config_noc_nodes), .bcms =3D config_noc_bcms, @@ -1320,7 +1316,6 @@ static struct qcom_icc_node * const cnoc_main_nodes[]= =3D { }; =20 static const struct qcom_icc_desc sm8750_cnoc_main =3D { - .alloc_dyn_id =3D true, .nodes =3D cnoc_main_nodes, .num_nodes =3D ARRAY_SIZE(cnoc_main_nodes), .bcms =3D cnoc_main_bcms, @@ -1354,7 +1349,6 @@ static struct qcom_icc_node * const gem_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sm8750_gem_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D gem_noc_nodes, .num_nodes =3D ARRAY_SIZE(gem_noc_nodes), .bcms =3D gem_noc_bcms, @@ -1367,7 +1361,6 @@ static struct qcom_icc_node * const lpass_ag_noc_node= s[] =3D { }; =20 static const struct qcom_icc_desc sm8750_lpass_ag_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D lpass_ag_noc_nodes, .num_nodes =3D ARRAY_SIZE(lpass_ag_noc_nodes), }; @@ -1382,7 +1375,6 @@ static struct qcom_icc_node * const lpass_lpiaon_noc_= nodes[] =3D { }; =20 static const struct qcom_icc_desc sm8750_lpass_lpiaon_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D lpass_lpiaon_noc_nodes, .num_nodes =3D ARRAY_SIZE(lpass_lpiaon_noc_nodes), .bcms =3D lpass_lpiaon_noc_bcms, @@ -1395,7 +1387,6 @@ static struct qcom_icc_node * const lpass_lpicx_noc_n= odes[] =3D { }; =20 static const struct qcom_icc_desc sm8750_lpass_lpicx_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D lpass_lpicx_noc_nodes, .num_nodes =3D ARRAY_SIZE(lpass_lpicx_noc_nodes), }; @@ -1411,7 +1402,6 @@ static struct qcom_icc_node * const mc_virt_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sm8750_mc_virt =3D { - .alloc_dyn_id =3D true, .nodes =3D mc_virt_nodes, .num_nodes =3D ARRAY_SIZE(mc_virt_nodes), .bcms =3D mc_virt_bcms, @@ -1441,7 +1431,6 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sm8750_mmss_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D mmss_noc_nodes, .num_nodes =3D ARRAY_SIZE(mmss_noc_nodes), .bcms =3D mmss_noc_bcms, @@ -1458,7 +1447,6 @@ static struct qcom_icc_node * const nsp_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sm8750_nsp_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D nsp_noc_nodes, .num_nodes =3D ARRAY_SIZE(nsp_noc_nodes), .bcms =3D nsp_noc_bcms, @@ -1477,7 +1465,6 @@ static struct qcom_icc_node * const pcie_anoc_nodes[]= =3D { }; =20 static const struct qcom_icc_desc sm8750_pcie_anoc =3D { - .alloc_dyn_id =3D true, .nodes =3D pcie_anoc_nodes, .num_nodes =3D ARRAY_SIZE(pcie_anoc_nodes), .bcms =3D pcie_anoc_bcms, @@ -1497,7 +1484,6 @@ static struct qcom_icc_node * const system_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sm8750_system_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D system_noc_nodes, .num_nodes =3D ARRAY_SIZE(system_noc_nodes), .bcms =3D system_noc_bcms, diff --git a/drivers/interconnect/qcom/x1e80100.c b/drivers/interconnect/qc= om/x1e80100.c index d5df26f02675de0150e2903df09fe419a8bd8892..2ba2823c7860e98bfbc2e018e8c= b2e6f26be9911 100644 --- a/drivers/interconnect/qcom/x1e80100.c +++ b/drivers/interconnect/qcom/x1e80100.c @@ -1467,7 +1467,6 @@ static struct qcom_icc_node * const aggre1_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc x1e80100_aggre1_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D aggre1_noc_nodes, .num_nodes =3D ARRAY_SIZE(aggre1_noc_nodes), .bcms =3D aggre1_noc_bcms, @@ -1490,7 +1489,6 @@ static struct qcom_icc_node * const aggre2_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc x1e80100_aggre2_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D aggre2_noc_nodes, .num_nodes =3D ARRAY_SIZE(aggre2_noc_nodes), .bcms =3D aggre2_noc_bcms, @@ -1513,7 +1511,6 @@ static struct qcom_icc_node * const clk_virt_nodes[] = =3D { }; =20 static const struct qcom_icc_desc x1e80100_clk_virt =3D { - .alloc_dyn_id =3D true, .nodes =3D clk_virt_nodes, .num_nodes =3D ARRAY_SIZE(clk_virt_nodes), .bcms =3D clk_virt_bcms, @@ -1577,7 +1574,6 @@ static struct qcom_icc_node * const cnoc_cfg_nodes[] = =3D { }; =20 static const struct qcom_icc_desc x1e80100_cnoc_cfg =3D { - .alloc_dyn_id =3D true, .nodes =3D cnoc_cfg_nodes, .num_nodes =3D ARRAY_SIZE(cnoc_cfg_nodes), .bcms =3D cnoc_cfg_bcms, @@ -1608,7 +1604,6 @@ static struct qcom_icc_node * const cnoc_main_nodes[]= =3D { }; =20 static const struct qcom_icc_desc x1e80100_cnoc_main =3D { - .alloc_dyn_id =3D true, .nodes =3D cnoc_main_nodes, .num_nodes =3D ARRAY_SIZE(cnoc_main_nodes), .bcms =3D cnoc_main_bcms, @@ -1639,7 +1634,6 @@ static struct qcom_icc_node * const gem_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc x1e80100_gem_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D gem_noc_nodes, .num_nodes =3D ARRAY_SIZE(gem_noc_nodes), .bcms =3D gem_noc_bcms, @@ -1655,7 +1649,6 @@ static struct qcom_icc_node * const lpass_ag_noc_node= s[] =3D { }; =20 static const struct qcom_icc_desc x1e80100_lpass_ag_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D lpass_ag_noc_nodes, .num_nodes =3D ARRAY_SIZE(lpass_ag_noc_nodes), .bcms =3D lpass_ag_noc_bcms, @@ -1672,7 +1665,6 @@ static struct qcom_icc_node * const lpass_lpiaon_noc_= nodes[] =3D { }; =20 static const struct qcom_icc_desc x1e80100_lpass_lpiaon_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D lpass_lpiaon_noc_nodes, .num_nodes =3D ARRAY_SIZE(lpass_lpiaon_noc_nodes), .bcms =3D lpass_lpiaon_noc_bcms, @@ -1688,7 +1680,6 @@ static struct qcom_icc_node * const lpass_lpicx_noc_n= odes[] =3D { }; =20 static const struct qcom_icc_desc x1e80100_lpass_lpicx_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D lpass_lpicx_noc_nodes, .num_nodes =3D ARRAY_SIZE(lpass_lpicx_noc_nodes), .bcms =3D lpass_lpicx_noc_bcms, @@ -1706,7 +1697,6 @@ static struct qcom_icc_node * const mc_virt_nodes[] = =3D { }; =20 static const struct qcom_icc_desc x1e80100_mc_virt =3D { - .alloc_dyn_id =3D true, .nodes =3D mc_virt_nodes, .num_nodes =3D ARRAY_SIZE(mc_virt_nodes), .bcms =3D mc_virt_bcms, @@ -1735,7 +1725,6 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc x1e80100_mmss_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D mmss_noc_nodes, .num_nodes =3D ARRAY_SIZE(mmss_noc_nodes), .bcms =3D mmss_noc_bcms, @@ -1752,7 +1741,6 @@ static struct qcom_icc_node * const nsp_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc x1e80100_nsp_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D nsp_noc_nodes, .num_nodes =3D ARRAY_SIZE(nsp_noc_nodes), .bcms =3D nsp_noc_bcms, @@ -1770,7 +1758,6 @@ static struct qcom_icc_node * const pcie_center_anoc_= nodes[] =3D { }; =20 static const struct qcom_icc_desc x1e80100_pcie_center_anoc =3D { - .alloc_dyn_id =3D true, .nodes =3D pcie_center_anoc_nodes, .num_nodes =3D ARRAY_SIZE(pcie_center_anoc_nodes), .bcms =3D pcie_center_anoc_bcms, @@ -1788,7 +1775,6 @@ static struct qcom_icc_node * const pcie_north_anoc_n= odes[] =3D { }; =20 static const struct qcom_icc_desc x1e80100_pcie_north_anoc =3D { - .alloc_dyn_id =3D true, .nodes =3D pcie_north_anoc_nodes, .num_nodes =3D ARRAY_SIZE(pcie_north_anoc_nodes), .bcms =3D pcie_north_anoc_bcms, @@ -1808,7 +1794,6 @@ static struct qcom_icc_node * const pcie_south_anoc_n= odes[] =3D { }; =20 static const struct qcom_icc_desc x1e80100_pcie_south_anoc =3D { - .alloc_dyn_id =3D true, .nodes =3D pcie_south_anoc_nodes, .num_nodes =3D ARRAY_SIZE(pcie_south_anoc_nodes), .bcms =3D pcie_south_anoc_bcms, @@ -1831,7 +1816,6 @@ static struct qcom_icc_node * const system_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc x1e80100_system_noc =3D { - .alloc_dyn_id =3D true, .nodes =3D system_noc_nodes, .num_nodes =3D ARRAY_SIZE(system_noc_nodes), .bcms =3D system_noc_bcms, @@ -1848,7 +1832,6 @@ static struct qcom_icc_node * const usb_center_anoc_n= odes[] =3D { }; =20 static const struct qcom_icc_desc x1e80100_usb_center_anoc =3D { - .alloc_dyn_id =3D true, .nodes =3D usb_center_anoc_nodes, .num_nodes =3D ARRAY_SIZE(usb_center_anoc_nodes), .bcms =3D usb_center_anoc_bcms, @@ -1865,7 +1848,6 @@ static struct qcom_icc_node * const usb_north_anoc_no= des[] =3D { }; =20 static const struct qcom_icc_desc x1e80100_usb_north_anoc =3D { - .alloc_dyn_id =3D true, .nodes =3D usb_north_anoc_nodes, .num_nodes =3D ARRAY_SIZE(usb_north_anoc_nodes), .bcms =3D usb_north_anoc_bcms, @@ -1886,7 +1868,6 @@ static struct qcom_icc_node * const usb_south_anoc_no= des[] =3D { }; =20 static const struct qcom_icc_desc x1e80100_usb_south_anoc =3D { - .alloc_dyn_id =3D true, .nodes =3D usb_south_anoc_nodes, .num_nodes =3D ARRAY_SIZE(usb_south_anoc_nodes), .bcms =3D usb_south_anoc_bcms, --=20 2.47.3