From nobody Sun Feb 8 18:41:29 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2011D3358B3; Fri, 31 Oct 2025 08:10:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761898232; cv=none; b=U2th3ydRsnWB1CgXIpfRWTyt06y+YDr94uFsdMP+Yh1sVqBSFxRceziSqVIdO4ATP0cB4nsaIN+vDCAhcPA2d1F4uSTROiQ46njUZl0E/P0ZRCn9rkdKHnydtnkwGmAaD30WblJEsMGNFChDr78bltn1Zyq6Sd8O4GWiKpufBPg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761898232; c=relaxed/simple; bh=5tLSRE6BInQejsiPR/fc5RiDlVZ9iOn8Or4TkaTc/g4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=HSvC0nBYkpNTs9qbe4zZ9Z8qJ3HKQY8ZlRI2BWsOr7GidYi7OL5LpyACOttH+czr/QAUe+GpEBZ0Roxv+ILcnoG0EQ2/o617C4ya7dZjM9dBQEW+9tqCvoRGt3xM1HY2pzpNff+8YxtajGnxkaWvNwR2yRnpn7uCLNFs43i1+Ws= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=VxXPJYx5; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="VxXPJYx5" Received: by smtp.kernel.org (Postfix) with ESMTPS id B6D74C4CEF8; Fri, 31 Oct 2025 08:10:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1761898231; bh=5tLSRE6BInQejsiPR/fc5RiDlVZ9iOn8Or4TkaTc/g4=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=VxXPJYx5ExMJP2rAbhU4KIO8npVjh6DbnR2J6BRPtkKWcYGt9MmiqrDMZLVKjz+gS VVGTho99vx4Ak2zm0QIou05MCrjuMm4p0ECVsYS4MdpGLnR/xBCFYucgEwO4Qv99fv O9Y9aRIKvUxODjPwdU/RKNfmAOOL8SLMrBCrygOeDB4rhpxvro+5x0JJNW19yYWyqZ +cYK4u0ZdJBc7f92wjyC9oeY1xs161fYawAzN0EMiyDcyr5ThUKEIr4Gh0TdTtWbpA JTihv25gg1Jx61Fl/K47Jnc31oduDUl+zQa10nHeDIX1QLDofzw+evX9w9sNvhuKRA t/SqoC0Kja9Ew== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id A53CECCF9FF; Fri, 31 Oct 2025 08:10:31 +0000 (UTC) From: Chuan Liu via B4 Relay Date: Fri, 31 Oct 2025 16:10:08 +0800 Subject: [PATCH v3 1/4] clk: amlogic: Fix out-of-range PLL frequency setting Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251031-optimize_pll_driver-v3-1-92f3b2f36a83@amlogic.com> References: <20251031-optimize_pll_driver-v3-0-92f3b2f36a83@amlogic.com> In-Reply-To: <20251031-optimize_pll_driver-v3-0-92f3b2f36a83@amlogic.com> To: Neil Armstrong , Jerome Brunet , Michael Turquette , Stephen Boyd , Kevin Hilman , Martin Blumenstingl Cc: linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Chuan Liu X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1761898227; l=991; i=chuan.liu@amlogic.com; s=20240902; h=from:subject:message-id; bh=6onhzW3ODDG4bFoHZLKVZ14BJkN4o2IaabjNVGrsFP0=; b=y7Jqs7z4QNs/tnWA3pjqpJDu6y8SCyMGOt9v1jYNHZ6CEi+bTOQkabAxtRF0VzG2xjZecfXcr Ey9zrxitmMGAFOuk4W44evTpq2JS4qNTWd0Jzg04fNoUjRao6J2tWaX X-Developer-Key: i=chuan.liu@amlogic.com; a=ed25519; pk=fnKDB+81SoWGKW2GJNFkKy/ULvsDmJZRGBE7pR5Xcpo= X-Endpoint-Received: by B4 Relay for chuan.liu@amlogic.com/20240902 with auth_id=203 X-Original-From: Chuan Liu Reply-To: chuan.liu@amlogic.com From: Chuan Liu If the calculated 'm' falls into the range: pll->range->max < m < (1 << pll->m.width) Here an incorrect 'm' value could be obtained, so an additional condition is added to ensure that the calculated 'm' stays within a valid range. Fixes: 8eed1db1adec6 ("clk: meson: pll: update driver for the g12a") Signed-off-by: Chuan Liu --- drivers/clk/meson/clk-pll.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/meson/clk-pll.c b/drivers/clk/meson/clk-pll.c index 1ea6579a760f..629f6af18ea1 100644 --- a/drivers/clk/meson/clk-pll.c +++ b/drivers/clk/meson/clk-pll.c @@ -191,7 +191,7 @@ static int meson_clk_get_pll_range_index(unsigned long = rate, *m =3D meson_clk_get_pll_range_m(rate, parent_rate, *n, pll); =20 /* the pre-divider gives a multiplier too big - stop */ - if (*m >=3D (1 << pll->m.width)) + if (*m > pll->range->max || *m >=3D (1 << pll->m.width)) return -EINVAL; =20 return 0; --=20 2.42.0 From nobody Sun Feb 8 18:41:29 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 296673358D5; Fri, 31 Oct 2025 08:10:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761898232; cv=none; b=RRdt9qtlzHbfcnx7X0OhO76tBMkp6Myh7le9sKrFoB5CK6nf1t3zf37/C3B2f+io+XCcQ47umZ1uG15vtBjuig1IadJEjtd1C80LYk6pFlsQOTdwQhw/TOMxh7iVub5pJvwZ4w5m6la6Uwl82TSQza4RuLriIoFbabExYISOdzw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761898232; c=relaxed/simple; bh=1nwGVO3Zcpwv2pMSFVgY8O3SNOwGFq6oSEOulqqDP4g=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Hhwus25z1qnd7FSZHvLKDJSo0/ocE81NUAwHxjVNpVjeo4dfWHcU60OizEKDnYmEIn4goY2bXwQFDptXnl3QNuLFC+AmZ5OTRJ6wJrmyJMGe6KMfOtr8rA4n7WuGY2+JqLbf/1cjcpZn259mId2DLI/UbcKpAnEqBIxVG3cAOX0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=OCjhTnB7; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="OCjhTnB7" Received: by smtp.kernel.org (Postfix) with ESMTPS id C230AC116C6; Fri, 31 Oct 2025 08:10:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1761898231; bh=1nwGVO3Zcpwv2pMSFVgY8O3SNOwGFq6oSEOulqqDP4g=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=OCjhTnB7jSnhLcmJ7VtvvseYnBLme3xRFIwGaVusZkch//5kW/wh8rfiA8SkwHoE6 a9S6E8NuavPmKYq9WR/KlEutmjvCmSvQCYHd+JtLr/2LuG7IVjNxZii1Ryu9Tk9JPn mIi3KzMUNZ7HtkWKeEV7VYVlc2Lw9r1iXziqI+D23YUk1z+kvAG3Bjuy8EtFeOeLEH Fh8DINuV09NA2PpsRMGsKCZQUJY9M2+NtseMUN5dXChkM+7wkQr9BUYTHihiWMNqT4 jdvdXbJg2Dlc/cDgJxJB762tStticMvzAm8ndPoD6TbhfN5Hw8+RXiC9RQZOG8MobY ySg0YMJBwU45A== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id B8343CCFA00; Fri, 31 Oct 2025 08:10:31 +0000 (UTC) From: Chuan Liu via B4 Relay Date: Fri, 31 Oct 2025 16:10:09 +0800 Subject: [PATCH v3 2/4] clk: amlogic: Improve the issue of PLL lock failures Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251031-optimize_pll_driver-v3-2-92f3b2f36a83@amlogic.com> References: <20251031-optimize_pll_driver-v3-0-92f3b2f36a83@amlogic.com> In-Reply-To: <20251031-optimize_pll_driver-v3-0-92f3b2f36a83@amlogic.com> To: Neil Armstrong , Jerome Brunet , Michael Turquette , Stephen Boyd , Kevin Hilman , Martin Blumenstingl Cc: linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Chuan Liu X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1761898227; l=1398; i=chuan.liu@amlogic.com; s=20240902; h=from:subject:message-id; bh=D0Ch0klWiiVBvP2nT1dWsPIBdVptw/u95TcZFxvGJ48=; b=DFTPIpZdSO64xPMi6d1dN9YKt56tCq1oo7YedKHM2Vk59/bE+owHEUbdaDAlE8itMPMMh1Xdy t1Z8vWX+hKYDRPWTkbvGi2VhLlPZnlaiFKx/mnKCdN2qQMzjD8T7dGO X-Developer-Key: i=chuan.liu@amlogic.com; a=ed25519; pk=fnKDB+81SoWGKW2GJNFkKy/ULvsDmJZRGBE7pR5Xcpo= X-Endpoint-Received: by B4 Relay for chuan.liu@amlogic.com/20240902 with auth_id=203 X-Original-From: Chuan Liu Reply-To: chuan.liu@amlogic.com From: Chuan Liu Due to factors such as temperature and process variations, the internal circuits of the PLL may require a longer time to reach a steady state, which can result in occasional lock failures on some SoCs under low-temperature conditions. After enabling the PLL and releasing its reset, a 20 us delay is added at each step to provide enough time for the internal PLL circuit to stabilize, thus reducing the probability of PLL lock failure. Signed-off-by: Chuan Liu Tested-by: Martin Blumenstingl # Odroi= d-C1 --- drivers/clk/meson/clk-pll.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/clk/meson/clk-pll.c b/drivers/clk/meson/clk-pll.c index 629f6af18ea1..70c8c7078046 100644 --- a/drivers/clk/meson/clk-pll.c +++ b/drivers/clk/meson/clk-pll.c @@ -369,10 +369,17 @@ static int meson_clk_pll_enable(struct clk_hw *hw) /* Enable the pll */ meson_parm_write(clk->map, &pll->en, 1); =20 + /* Wait for Bandgap and LDO to power up and stabilize */ + udelay(20); + /* Take the pll out reset */ - if (MESON_PARM_APPLICABLE(&pll->rst)) + if (MESON_PARM_APPLICABLE(&pll->rst)) { meson_parm_write(clk->map, &pll->rst, 0); =20 + /* Wait for PLL loop stabilization */ + udelay(20); + } + /* * Compared with the previous SoCs, self-adaption current module * is newly added for A1, keep the new power-on sequence to enable the --=20 2.42.0 From nobody Sun Feb 8 18:41:29 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 295E73358D3; Fri, 31 Oct 2025 08:10:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761898232; cv=none; b=S2++ZzFdHku9eGkkBxR1j20TO7qm/MaWStrdjRJ2YpVZ9TL3jzrHt2w76SYIubFZbe2lG5Shnh9DrsxO8eH8m64XSyfy3K+gpFyq87T2qvFSOoGRrM3KoQqNHmbVfwY4CfHKLy8QcWiq+Ymdx5Bq+FuO/BDZtyDD7mxMKYk5dU4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761898232; c=relaxed/simple; bh=vGQHDMPDFqEek7AC7vioPrkUtMWkS6rFq2XnbYgZrn8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=DyghyAnGYDroAFvzso/Zm55fysplFfFKL5HnJXq4OEJuNdeb2h0NkMtzvuDHumUG/b0T0w0TR0VaPSR0d3NWGij0NuzxXqKObLnt05Bq16ed0p9kjbOnb/1cT1yKcrCkrAgplWCUsFujrdF3O8NyVazQDYA2GGRJgBnQo3eGJbQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=baDVtwGw; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="baDVtwGw" Received: by smtp.kernel.org (Postfix) with ESMTPS id D85D0C16AAE; Fri, 31 Oct 2025 08:10:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1761898231; bh=vGQHDMPDFqEek7AC7vioPrkUtMWkS6rFq2XnbYgZrn8=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=baDVtwGwWEZYt+UDEM1ar6vK3vKVjULz9eLKORPnskN2po4rxCskU8oFZenmpRKkr qs14Pz+dSqjSVp2Jhh5SXuTiPua8NeDGm43iSI0QKdZ83Nms1S67eaylQ4QKcoCSc2 RvtBpF5jtR21A2OvzBiOlYe8c2l4ua+Zq5R76SnJ/n/H7v6h0/q97KeefItvZVruLQ CcrYPFXGr8b1eqzFqbDIsogDr1KBNllpGrpHmStINcgRVd1P9+KPD89J/QFz37gpzj blqY/wtXsqdGU58bMuzu4ybC/bGybzSZLWuLU6Jvn6kUr7QuV7rb6qJjJX98xyJ01T mc2Gnog6RucHw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id CEB94CCFA03; Fri, 31 Oct 2025 08:10:31 +0000 (UTC) From: Chuan Liu via B4 Relay Date: Fri, 31 Oct 2025 16:10:10 +0800 Subject: [PATCH v3 3/4] clk: amlogic: Add handling for PLL lock failure Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251031-optimize_pll_driver-v3-3-92f3b2f36a83@amlogic.com> References: <20251031-optimize_pll_driver-v3-0-92f3b2f36a83@amlogic.com> In-Reply-To: <20251031-optimize_pll_driver-v3-0-92f3b2f36a83@amlogic.com> To: Neil Armstrong , Jerome Brunet , Michael Turquette , Stephen Boyd , Kevin Hilman , Martin Blumenstingl Cc: linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Chuan Liu X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1761898227; l=2329; i=chuan.liu@amlogic.com; s=20240902; h=from:subject:message-id; bh=hkOzDZETVE19YzYRyq9fWVkEGr8gDuc+o46inhx8Qtg=; b=0yISSorwaI3PsvRLs+sLpQCAQG8APu1fcHkVfPqejUNW58Qb+QbEUwch0hht03EjjJUmhPrDL YPlIXd+xxd+BAdMzBnAflA8/WX+agqrhOJvNxWA2XSdMK3A0BrXGNW+ X-Developer-Key: i=chuan.liu@amlogic.com; a=ed25519; pk=fnKDB+81SoWGKW2GJNFkKy/ULvsDmJZRGBE7pR5Xcpo= X-Endpoint-Received: by B4 Relay for chuan.liu@amlogic.com/20240902 with auth_id=203 X-Original-From: Chuan Liu Reply-To: chuan.liu@amlogic.com From: Chuan Liu If the PLL fails to lock, it should be disabled, This makes the logic more complete, and also helps save unnecessary power consumption when the PLL is malfunctioning. Signed-off-by: Chuan Liu --- drivers/clk/meson/clk-pll.c | 41 +++++++++++++++++++++++------------------ 1 file changed, 23 insertions(+), 18 deletions(-) diff --git a/drivers/clk/meson/clk-pll.c b/drivers/clk/meson/clk-pll.c index 70c8c7078046..cdb39a723bd0 100644 --- a/drivers/clk/meson/clk-pll.c +++ b/drivers/clk/meson/clk-pll.c @@ -353,6 +353,23 @@ static int meson_clk_pcie_pll_enable(struct clk_hw *hw) return -EIO; } =20 +static void meson_clk_pll_disable(struct clk_hw *hw) +{ + struct clk_regmap *clk =3D to_clk_regmap(hw); + struct meson_clk_pll_data *pll =3D meson_clk_pll_data(clk); + + /* Put the pll is in reset */ + if (MESON_PARM_APPLICABLE(&pll->rst)) + meson_parm_write(clk->map, &pll->rst, 1); + + /* Disable the pll */ + meson_parm_write(clk->map, &pll->en, 0); + + /* Disable PLL internal self-adaption current module */ + if (MESON_PARM_APPLICABLE(&pll->current_en)) + meson_parm_write(clk->map, &pll->current_en, 0); +} + static int meson_clk_pll_enable(struct clk_hw *hw) { struct clk_regmap *clk =3D to_clk_regmap(hw); @@ -399,29 +416,17 @@ static int meson_clk_pll_enable(struct clk_hw *hw) meson_parm_write(clk->map, &pll->l_detect, 0); } =20 - if (meson_clk_pll_wait_lock(hw)) + if (meson_clk_pll_wait_lock(hw)) { + /* disable PLL when PLL lock failed. */ + meson_clk_pll_disable(hw); + pr_warn("%s: PLL lock failed!\n", clk_hw_get_name(hw)); + return -EIO; + } =20 return 0; } =20 -static void meson_clk_pll_disable(struct clk_hw *hw) -{ - struct clk_regmap *clk =3D to_clk_regmap(hw); - struct meson_clk_pll_data *pll =3D meson_clk_pll_data(clk); - - /* Put the pll is in reset */ - if (MESON_PARM_APPLICABLE(&pll->rst)) - meson_parm_write(clk->map, &pll->rst, 1); - - /* Disable the pll */ - meson_parm_write(clk->map, &pll->en, 0); - - /* Disable PLL internal self-adaption current module */ - if (MESON_PARM_APPLICABLE(&pll->current_en)) - meson_parm_write(clk->map, &pll->current_en, 0); -} - static int meson_clk_pll_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { --=20 2.42.0 From nobody Sun Feb 8 18:41:29 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 296DD335BB4; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="TA0APZqY" Received: by smtp.kernel.org (Postfix) with ESMTPS id E9AF6C19424; Fri, 31 Oct 2025 08:10:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1761898232; bh=6ESWC7weu+fkakS/P318zzkxwK20bhDH2SY7HZ3vBd4=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=TA0APZqYRrCONMPdDPvTaxyKas30+zpO3qlC5h0QacSccmboZAZwOmgto7v+aINr0 RquKFP8xA1ZM4h0z6SJ8CaDXbEyDhB8nfvBsJTFCs4O/gvlv5MTS2fC0BCJS/H8TUm 8upEULcZZcKPynxXnmfgMD92mVO6+jyGkFsRfZ7aCIuFZGSSGpGUlkTYJHRGYoEZ0/ 0K8YwZQF4J4kiqlhiO9iFiiL8j6FzUn7R3zoE8YmjSSiQDwHrh2qvYQMYM+CsKqPZT fFursmhuoa7zdd7nUr7yXo3QbqaQZKFg91r9m8W/gZ/9qyQ3rYlZPOc/KywCo3snA+ NZFAGnBDl2k5g== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id E1091CCFA00; Fri, 31 Oct 2025 08:10:31 +0000 (UTC) From: Chuan Liu via B4 Relay Date: Fri, 31 Oct 2025 16:10:11 +0800 Subject: [PATCH v3 4/4] clk: amlogic: Optimize PLL enable timing Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251031-optimize_pll_driver-v3-4-92f3b2f36a83@amlogic.com> References: <20251031-optimize_pll_driver-v3-0-92f3b2f36a83@amlogic.com> In-Reply-To: <20251031-optimize_pll_driver-v3-0-92f3b2f36a83@amlogic.com> To: Neil Armstrong , Jerome Brunet , Michael Turquette , Stephen Boyd , Kevin Hilman , Martin Blumenstingl Cc: linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Chuan Liu X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1761898227; l=2090; i=chuan.liu@amlogic.com; s=20240902; h=from:subject:message-id; bh=3bVoQCKgnuZ/IY+cWp9z2timk+2eNG6PU6hMfKQ9QKc=; b=PaR4cC+nx1zlBGR24Xc20vUT2lEJgJbv9J7AWiZu9QbNIDq2BkxtlT0lPMVoKhLR7ofEt/Xpz XzFQVzImYksCF6+t+rElWpS5+OSqL/J/xLPNCqFmzWFOpoFoJvkbaTD X-Developer-Key: i=chuan.liu@amlogic.com; a=ed25519; pk=fnKDB+81SoWGKW2GJNFkKy/ULvsDmJZRGBE7pR5Xcpo= X-Endpoint-Received: by B4 Relay for chuan.liu@amlogic.com/20240902 with auth_id=203 X-Original-From: Chuan Liu Reply-To: chuan.liu@amlogic.com From: Chuan Liu l_detect controls the enablement of the PLL lock detection module. It should remain disabled while the internal PLL circuits are reaching a steady state; otherwise, the lock signal may be falsely triggered high. A 20 us delay has been added before enabling the PLL, so there=E2=80=99s no need for an additional 10 us delay before enabling current_en. Currently, only A1 supports both l_detect and current_en, so this patch will only affect A1. Signed-off-by: Chuan Liu --- drivers/clk/meson/clk-pll.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/clk/meson/clk-pll.c b/drivers/clk/meson/clk-pll.c index cdb39a723bd0..c9b941adf688 100644 --- a/drivers/clk/meson/clk-pll.c +++ b/drivers/clk/meson/clk-pll.c @@ -383,6 +383,10 @@ static int meson_clk_pll_enable(struct clk_hw *hw) if (MESON_PARM_APPLICABLE(&pll->rst)) meson_parm_write(clk->map, &pll->rst, 1); =20 + /* Disable the PLL lock-detect module */ + if (MESON_PARM_APPLICABLE(&pll->l_detect)) + meson_parm_write(clk->map, &pll->l_detect, 1); + /* Enable the pll */ meson_parm_write(clk->map, &pll->en, 1); =20 @@ -401,20 +405,18 @@ static int meson_clk_pll_enable(struct clk_hw *hw) * Compared with the previous SoCs, self-adaption current module * is newly added for A1, keep the new power-on sequence to enable the * PLL. The sequence is: - * 1. enable the pll, delay for 10us + * 1. enable the pll, delay for 20us * 2. enable the pll self-adaption current module, delay for 40us * 3. enable the lock detect module */ if (MESON_PARM_APPLICABLE(&pll->current_en)) { - udelay(10); meson_parm_write(clk->map, &pll->current_en, 1); udelay(40); } =20 - if (MESON_PARM_APPLICABLE(&pll->l_detect)) { - meson_parm_write(clk->map, &pll->l_detect, 1); + /* Enable the lock-detect module */ + if (MESON_PARM_APPLICABLE(&pll->l_detect)) meson_parm_write(clk->map, &pll->l_detect, 0); - } =20 if (meson_clk_pll_wait_lock(hw)) { /* disable PLL when PLL lock failed. */ --=20 2.42.0