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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-295268716e4sm17913115ad.9.2025.10.31.02.51.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 31 Oct 2025 02:51:38 -0700 (PDT) From: Wangao Wang Date: Fri, 31 Oct 2025 17:50:39 +0800 Subject: [PATCH v2 1/5] media: qcom: iris: Improve format alignment for encoder Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251031-iris_encoder_enhancements-v2-1-319cd75cbb45@oss.qualcomm.com> References: <20251031-iris_encoder_enhancements-v2-0-319cd75cbb45@oss.qualcomm.com> In-Reply-To: <20251031-iris_encoder_enhancements-v2-0-319cd75cbb45@oss.qualcomm.com> To: Vikash Garodia , Dikshita Agarwal , Abhinav Kumar , Bryan O'Donoghue , Mauro Carvalho Chehab Cc: linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Wangao Wang , quic_qiweil@quicinc.com, quic_renjiang@quicinc.com X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1761904292; l=5100; i=wangao.wang@oss.qualcomm.com; s=20251021; h=from:subject:message-id; bh=tNK3w71T6e4PjaLm8LNoJvsCCYX65B4pzJT4mQrjvDk=; b=Q4iIB9stru17MD9UZUYytGkrWrUBUyuuXSktuZYZYOqDim0VX168jtjnEXBefVLUYccPi1hM3 7S6Ym5Adh9eDox4MDWXxS+H8rDvdS/4OhqMBZ4HTCLE6XwXI/BfDZkm X-Developer-Key: i=wangao.wang@oss.qualcomm.com; a=ed25519; pk=bUPgYblBUAsoPyGfssbNR7ZXUSGF8v1VF4FJzSO6/aA= X-Proofpoint-ORIG-GUID: CDQC2QOebX0iUnCchK6G8St2kh6ORgW1 X-Proofpoint-GUID: CDQC2QOebX0iUnCchK6G8St2kh6ORgW1 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDMxMDA4OCBTYWx0ZWRfX/jM5pTxWGUDv WvJ/Oq6iSPBdUbLLUM0h6D/ZqEteYaumZIG0sz5Sge6DROeReIWSsXbdLfKeDqnhUlP0SEcjUri xwHLEYd7XQqzZVzAu19AWeSYz/mqxAo5a2h/M4Kssd7VoDLxTszx9sVmyxInAi4oPeWGx1M4Zhe s0ATs4sjxixKFZDUe+nYNl86CWJKJ+NDd96eLlEpj54u09LZaKObwYUGJu/jd9N/KzIdq8HjuEv KcYOXk87WX0PeZeDlOvCY487fubJcl1vCWjVcm6Q0RnpsfIT40uZPxyOYem/vtfnmPAgUARIhQ9 mbWKK9FsWfIJoQuTvGnWly2YMwwcF09htuO3hbOj1sRB07JXmQrjhNovbjhbQ3FQf//jr5eJgNI MrI/1BKFb6jfMSs5ksPpPCFCxm8lJw== X-Authority-Analysis: v=2.4 cv=XoP3+FF9 c=1 sm=1 tr=0 ts=690486ac cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=x6icFKpwvdMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=Ua5b2oKhh2CtpjQe1ZYA:9 a=QEXdDO2ut3YA:10 a=324X-CrmTo6CU4MGRt3R:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-10-31_02,2025-10-29_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 impostorscore=0 spamscore=0 lowpriorityscore=0 clxscore=1015 priorityscore=1501 suspectscore=0 phishscore=0 malwarescore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2510310088 Add members enc_raw_width, enc_raw_height to the struct iris_inst to support codec alignment requirements. HFI_PROP_CROP_OFFSETS is used to inform the firmware of the region of interest, rather than indicating that the codec supports crop. Therefore, the crop handling has been corrected accordingly. Signed-off-by: Wangao Wang --- .../media/platform/qcom/iris/iris_hfi_gen2_command.c | 18 ++++++++++++--= ---- drivers/media/platform/qcom/iris/iris_instance.h | 4 ++++ drivers/media/platform/qcom/iris/iris_venc.c | 10 +++++++--- 3 files changed, 23 insertions(+), 9 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c b/dri= vers/media/platform/qcom/iris/iris_hfi_gen2_command.c index 4ce71a14250832440099e4cf3835b4aedfb749e8..ada9b4d298ef10ac47a57306136= 9828a1e150f85 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c @@ -168,8 +168,7 @@ static int iris_hfi_gen2_session_set_property(struct ir= is_inst *inst, u32 packet =20 static int iris_hfi_gen2_set_raw_resolution(struct iris_inst *inst, u32 pl= ane) { - u32 resolution =3D inst->fmt_src->fmt.pix_mp.width << 16 | - inst->fmt_src->fmt.pix_mp.height; + u32 resolution =3D inst->enc_raw_width << 16 | inst->enc_raw_height; u32 port =3D iris_hfi_gen2_get_port(inst, plane); =20 return iris_hfi_gen2_session_set_property(inst, @@ -216,8 +215,11 @@ static int iris_hfi_gen2_set_crop_offsets(struct iris_= inst *inst, u32 plane) u32 port =3D iris_hfi_gen2_get_port(inst, plane); u32 bottom_offset, right_offset; u32 left_offset, top_offset; + u32 codec_align; u32 payload[2]; =20 + codec_align =3D inst->codec =3D=3D V4L2_PIX_FMT_HEVC ? 32 : 16; + if (inst->domain =3D=3D DECODER) { if (V4L2_TYPE_IS_OUTPUT(plane)) { bottom_offset =3D (inst->fmt_src->fmt.pix_mp.height - inst->crop.height= ); @@ -231,10 +233,14 @@ static int iris_hfi_gen2_set_crop_offsets(struct iris= _inst *inst, u32 plane) top_offset =3D inst->compose.top; } } else { - bottom_offset =3D (inst->fmt_src->fmt.pix_mp.height - inst->crop.height); - right_offset =3D (inst->fmt_src->fmt.pix_mp.width - inst->crop.width); - left_offset =3D inst->crop.left; - top_offset =3D inst->crop.top; + if (V4L2_TYPE_IS_CAPTURE(plane)) { + bottom_offset =3D (ALIGN(inst->enc_raw_height, codec_align) - + inst->enc_raw_height); + right_offset =3D (ALIGN(inst->enc_raw_width, codec_align) - + inst->enc_raw_width); + left_offset =3D inst->crop.left; + top_offset =3D inst->crop.top; + } } =20 payload[0] =3D FIELD_PREP(GENMASK(31, 16), left_offset) | top_offset; diff --git a/drivers/media/platform/qcom/iris/iris_instance.h b/drivers/med= ia/platform/qcom/iris/iris_instance.h index 5982d7adefeab80905478b32cddba7bd4651a691..fbae1662947df73bb3d10b78928= 39fa1076b7e61 100644 --- a/drivers/media/platform/qcom/iris/iris_instance.h +++ b/drivers/media/platform/qcom/iris/iris_instance.h @@ -64,6 +64,8 @@ struct iris_fmt { * @frame_rate: frame rate of current instance * @operating_rate: operating rate of current instance * @hfi_rc_type: rate control type + * @enc_raw_width: raw image width for encoder instance + * @enc_raw_height: raw image height for encoder instance */ =20 struct iris_inst { @@ -102,6 +104,8 @@ struct iris_inst { u32 frame_rate; u32 operating_rate; u32 hfi_rc_type; + u32 enc_raw_width; + u32 enc_raw_height; }; =20 #endif diff --git a/drivers/media/platform/qcom/iris/iris_venc.c b/drivers/media/p= latform/qcom/iris/iris_venc.c index 099bd5ed4ae0294725860305254c4cad1ec88d7e..6adadc89e360a6e4bebe1f839d3= 8892990e10fa2 100644 --- a/drivers/media/platform/qcom/iris/iris_venc.c +++ b/drivers/media/platform/qcom/iris/iris_venc.c @@ -68,6 +68,9 @@ int iris_venc_inst_init(struct iris_inst *inst) inst->operating_rate =3D DEFAULT_FPS; inst->frame_rate =3D DEFAULT_FPS; =20 + inst->enc_raw_width =3D DEFAULT_WIDTH; + inst->enc_raw_height =3D DEFAULT_HEIGHT; + memcpy(&inst->fw_caps[0], &core->inst_fw_caps_enc[0], INST_FW_CAP_MAX * sizeof(struct platform_inst_fw_cap)); =20 @@ -249,6 +252,9 @@ static int iris_venc_s_fmt_input(struct iris_inst *inst= , struct v4l2_format *f) inst->buffers[BUF_INPUT].min_count =3D iris_vpu_buf_count(inst, BUF_INPUT= ); inst->buffers[BUF_INPUT].size =3D fmt->fmt.pix_mp.plane_fmt[0].sizeimage; =20 + inst->enc_raw_width =3D f->fmt.pix_mp.width; + inst->enc_raw_height =3D f->fmt.pix_mp.height; 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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-295268716e4sm17913115ad.9.2025.10.31.02.51.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 31 Oct 2025 02:51:41 -0700 (PDT) From: Wangao Wang Date: Fri, 31 Oct 2025 17:50:40 +0800 Subject: [PATCH v2 2/5] media: qcom: iris: Add scale support for encoder Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251031-iris_encoder_enhancements-v2-2-319cd75cbb45@oss.qualcomm.com> References: <20251031-iris_encoder_enhancements-v2-0-319cd75cbb45@oss.qualcomm.com> In-Reply-To: <20251031-iris_encoder_enhancements-v2-0-319cd75cbb45@oss.qualcomm.com> To: Vikash Garodia , Dikshita Agarwal , Abhinav Kumar , Bryan O'Donoghue , Mauro Carvalho Chehab Cc: linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Wangao Wang , quic_qiweil@quicinc.com, quic_renjiang@quicinc.com X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1761904292; l=8809; i=wangao.wang@oss.qualcomm.com; s=20251021; h=from:subject:message-id; bh=jpNsgj9gdELo185+96j7Hr3sSN9WRvVVARbrZ2cVqXA=; b=/t2SCGADFdiqGYukGPuv90oUoJa6lBIq7gXXXMMaqiCwZT3NPm9majCNdN2P9RGtdT7RQdyMq LRddCQYK3naBpDXs3gadn/9T07d2S4wdIzfJWjVgPH08DfZxmY6uKpK X-Developer-Key: i=wangao.wang@oss.qualcomm.com; a=ed25519; pk=bUPgYblBUAsoPyGfssbNR7ZXUSGF8v1VF4FJzSO6/aA= X-Authority-Analysis: v=2.4 cv=RL2+3oi+ c=1 sm=1 tr=0 ts=690486af cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=x6icFKpwvdMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=WTz_1cNxA-dsg9Q2lx4A:9 a=QEXdDO2ut3YA:10 a=324X-CrmTo6CU4MGRt3R:22 X-Proofpoint-ORIG-GUID: awY4EzPZEonfBSGDQhNAnCwcbq7ckjKT X-Proofpoint-GUID: awY4EzPZEonfBSGDQhNAnCwcbq7ckjKT X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDMxMDA4OSBTYWx0ZWRfXzyQ4yKbJvo4v VQ7N9l6guwsFuXIX8IDUDtXp7rii1aK1vd5pOIcsxEtkbfo6xSAsIZUHChFNW5hBolvlzTOlw3o MvYjkVXtop6P7iiW+XJ6C+0Tds1UaiR5qRJMaJX0k0UWkJs0IItxwwWKHc1xGKudm/FJP1xkd4J KOx1U69Cley/LJSdfvjjzSA19DWeO/nYQ9ugPeoxS7UHlsU7F4RxTjp9jkF6TFIWet6ycE11mJX 0nCztwuubLpd5WSd/sRBa0HFcHGfJirNJIAMOpyxCt8r4mY2gAYADmZpMrCftHhHn4AYVosRQSb 6vlnkktQOdgBFjdaCPF0mlZXzA2RrYZOLg/QidAvTfGfw9fu9KZ96dopEpihusypT6W/d3nMwCD ZCO9F3WmlnwcVmkBd11iKr2jGvKFVg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-10-31_02,2025-10-29_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 lowpriorityscore=0 malwarescore=0 impostorscore=0 phishscore=0 bulkscore=0 adultscore=0 spamscore=0 clxscore=1015 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2510310089 Add members enc_scale_width, enc_scale_height to the struct iris_inst to support scale requirements. Add output width and height settings in iris_venc_s_fmt_output to enable scaling functionality. Add VPSS buffer to platform data, which the scale function requires. Signed-off-by: Wangao Wang Tested-by: Neil Armstrong # on SM8650-HDK --- .../platform/qcom/iris/iris_hfi_gen2_command.c | 4 ++-- .../platform/qcom/iris/iris_hfi_gen2_response.c | 2 ++ drivers/media/platform/qcom/iris/iris_instance.h | 4 ++++ .../media/platform/qcom/iris/iris_platform_gen2.c | 12 +++++++++++ drivers/media/platform/qcom/iris/iris_venc.c | 23 ++++++++++++++++++= +++- drivers/media/platform/qcom/iris/iris_vpu_buffer.c | 9 +++++---- 6 files changed, 47 insertions(+), 7 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c b/dri= vers/media/platform/qcom/iris/iris_hfi_gen2_command.c index ada9b4d298ef10ac47a573061369828a1e150f85..6ec217268a2bc1f939fa33820c1= ae19adaad2e96 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c @@ -194,8 +194,8 @@ static int iris_hfi_gen2_set_bitstream_resolution(struc= t iris_inst *inst, u32 pl payload_type =3D HFI_PAYLOAD_U32; } else { codec_align =3D inst->codec =3D=3D V4L2_PIX_FMT_HEVC ? 32 : 16; - resolution =3D ALIGN(inst->fmt_dst->fmt.pix_mp.width, codec_align) << 16= | - ALIGN(inst->fmt_dst->fmt.pix_mp.height, codec_align); + resolution =3D ALIGN(inst->enc_scale_width, codec_align) << 16 | + ALIGN(inst->enc_scale_height, codec_align); inst_hfi_gen2->dst_subcr_params.bitstream_resolution =3D resolution; payload_type =3D HFI_PAYLOAD_32_PACKED; } diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c b/dr= ivers/media/platform/qcom/iris/iris_hfi_gen2_response.c index 2f1f118eae4f6462ab1aa1d16844b34e6e699f1e..dc3e606b6ab429a1d15536fa831= 6afb1e384d674 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c @@ -54,6 +54,8 @@ static u32 iris_hfi_gen2_buf_type_to_driver(struct iris_i= nst *inst, return BUF_SCRATCH_2; case HFI_BUFFER_PERSIST: return BUF_PERSIST; + case HFI_BUFFER_VPSS: + return BUF_VPSS; default: return 0; } diff --git a/drivers/media/platform/qcom/iris/iris_instance.h b/drivers/med= ia/platform/qcom/iris/iris_instance.h index fbae1662947df73bb3d10b7892839fa1076b7e61..5ff01dd7177fc919d0cc69553fa= dede5801592a1 100644 --- a/drivers/media/platform/qcom/iris/iris_instance.h +++ b/drivers/media/platform/qcom/iris/iris_instance.h @@ -66,6 +66,8 @@ struct iris_fmt { * @hfi_rc_type: rate control type * @enc_raw_width: raw image width for encoder instance * @enc_raw_height: raw image height for encoder instance + * @enc_scale_width: scale width for encoder instance + * @enc_scale_height: scale height for encoder instance */ =20 struct iris_inst { @@ -106,6 +108,8 @@ struct iris_inst { u32 hfi_rc_type; u32 enc_raw_width; u32 enc_raw_height; + u32 enc_scale_width; + u32 enc_scale_height; }; =20 #endif diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/driver= s/media/platform/qcom/iris/iris_platform_gen2.c index 36d69cc73986b74534a2912524c8553970fd862e..d3306189d902a1f42666010468c= 9e4e4316a66e1 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c +++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c @@ -729,6 +729,10 @@ static const u32 sm8550_dec_op_int_buf_tbl[] =3D { BUF_DPB, }; =20 +static const u32 sm8550_enc_ip_int_buf_tbl[] =3D { + BUF_VPSS, +}; + static const u32 sm8550_enc_op_int_buf_tbl[] =3D { BUF_BIN, BUF_COMV, @@ -816,6 +820,8 @@ struct iris_platform_data sm8550_data =3D { .dec_op_int_buf_tbl =3D sm8550_dec_op_int_buf_tbl, .dec_op_int_buf_tbl_size =3D ARRAY_SIZE(sm8550_dec_op_int_buf_tbl), =20 + .enc_ip_int_buf_tbl =3D sm8550_enc_ip_int_buf_tbl, + .enc_ip_int_buf_tbl_size =3D ARRAY_SIZE(sm8550_enc_ip_int_buf_tbl), .enc_op_int_buf_tbl =3D sm8550_enc_op_int_buf_tbl, .enc_op_int_buf_tbl_size =3D ARRAY_SIZE(sm8550_enc_op_int_buf_tbl), }; @@ -908,6 +914,8 @@ struct iris_platform_data sm8650_data =3D { .dec_op_int_buf_tbl =3D sm8550_dec_op_int_buf_tbl, .dec_op_int_buf_tbl_size =3D ARRAY_SIZE(sm8550_dec_op_int_buf_tbl), =20 + .enc_ip_int_buf_tbl =3D sm8550_enc_ip_int_buf_tbl, + .enc_ip_int_buf_tbl_size =3D ARRAY_SIZE(sm8550_enc_ip_int_buf_tbl), .enc_op_int_buf_tbl =3D sm8550_enc_op_int_buf_tbl, .enc_op_int_buf_tbl_size =3D ARRAY_SIZE(sm8550_enc_op_int_buf_tbl), }; @@ -989,6 +997,8 @@ struct iris_platform_data sm8750_data =3D { .dec_op_int_buf_tbl =3D sm8550_dec_op_int_buf_tbl, .dec_op_int_buf_tbl_size =3D ARRAY_SIZE(sm8550_dec_op_int_buf_tbl), =20 + .enc_ip_int_buf_tbl =3D sm8550_enc_ip_int_buf_tbl, + .enc_ip_int_buf_tbl_size =3D ARRAY_SIZE(sm8550_enc_ip_int_buf_tbl), .enc_op_int_buf_tbl =3D sm8550_enc_op_int_buf_tbl, .enc_op_int_buf_tbl_size =3D ARRAY_SIZE(sm8550_enc_op_int_buf_tbl), }; @@ -1077,6 +1087,8 @@ struct iris_platform_data qcs8300_data =3D { .dec_op_int_buf_tbl =3D sm8550_dec_op_int_buf_tbl, .dec_op_int_buf_tbl_size =3D ARRAY_SIZE(sm8550_dec_op_int_buf_tbl), =20 + .enc_ip_int_buf_tbl =3D sm8550_enc_ip_int_buf_tbl, + .enc_ip_int_buf_tbl_size =3D ARRAY_SIZE(sm8550_enc_ip_int_buf_tbl), .enc_op_int_buf_tbl =3D sm8550_enc_op_int_buf_tbl, .enc_op_int_buf_tbl_size =3D ARRAY_SIZE(sm8550_enc_op_int_buf_tbl), }; diff --git a/drivers/media/platform/qcom/iris/iris_venc.c b/drivers/media/p= latform/qcom/iris/iris_venc.c index 6adadc89e360a6e4bebe1f839d38892990e10fa2..17a2e59e4ba8ff650895dde9fe5= 69da39ef88093 100644 --- a/drivers/media/platform/qcom/iris/iris_venc.c +++ b/drivers/media/platform/qcom/iris/iris_venc.c @@ -70,6 +70,8 @@ int iris_venc_inst_init(struct iris_inst *inst) =20 inst->enc_raw_width =3D DEFAULT_WIDTH; inst->enc_raw_height =3D DEFAULT_HEIGHT; + inst->enc_scale_width =3D DEFAULT_WIDTH; + inst->enc_scale_height =3D DEFAULT_HEIGHT; =20 memcpy(&inst->fw_caps[0], &core->inst_fw_caps_enc[0], INST_FW_CAP_MAX * sizeof(struct platform_inst_fw_cap)); @@ -188,15 +190,32 @@ int iris_venc_try_fmt(struct iris_inst *inst, struct = v4l2_format *f) =20 static int iris_venc_s_fmt_output(struct iris_inst *inst, struct v4l2_form= at *f) { + const struct iris_fmt *venc_fmt; struct v4l2_format *fmt; + u32 codec_align; =20 iris_venc_try_fmt(inst, f); =20 - if (!(find_format(inst, f->fmt.pix_mp.pixelformat, f->type))) + venc_fmt =3D find_format(inst, f->fmt.pix_mp.pixelformat, f->type); + if (!venc_fmt) return -EINVAL; =20 + codec_align =3D venc_fmt->pixfmt =3D=3D V4L2_PIX_FMT_HEVC ? 32 : 16; + fmt =3D inst->fmt_dst; fmt->type =3D V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE; + /* + * If output format size !=3D input format size, + * it is considered a scaling case, + * and the scaled size needs to be saved. + */ + if (f->fmt.pix_mp.width !=3D fmt->fmt.pix_mp.width || + f->fmt.pix_mp.height !=3D fmt->fmt.pix_mp.height) { + fmt->fmt.pix_mp.width =3D ALIGN(f->fmt.pix_mp.width, codec_align); + fmt->fmt.pix_mp.height =3D ALIGN(f->fmt.pix_mp.height, codec_align); + inst->enc_scale_width =3D f->fmt.pix_mp.width; + inst->enc_scale_height =3D f->fmt.pix_mp.height; + } fmt->fmt.pix_mp.num_planes =3D 1; fmt->fmt.pix_mp.plane_fmt[0].bytesperline =3D 0; fmt->fmt.pix_mp.plane_fmt[0].sizeimage =3D iris_get_buffer_size(inst, BUF= _OUTPUT); @@ -254,6 +273,8 @@ static int iris_venc_s_fmt_input(struct iris_inst *inst= , struct v4l2_format *f) =20 inst->enc_raw_width =3D f->fmt.pix_mp.width; inst->enc_raw_height =3D f->fmt.pix_mp.height; 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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-295268716e4sm17913115ad.9.2025.10.31.02.51.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 31 Oct 2025 02:51:45 -0700 (PDT) From: Wangao Wang Date: Fri, 31 Oct 2025 17:50:41 +0800 Subject: [PATCH v2 3/5] media: qcom: iris: Add rotation support for encoder Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251031-iris_encoder_enhancements-v2-3-319cd75cbb45@oss.qualcomm.com> References: <20251031-iris_encoder_enhancements-v2-0-319cd75cbb45@oss.qualcomm.com> In-Reply-To: <20251031-iris_encoder_enhancements-v2-0-319cd75cbb45@oss.qualcomm.com> To: Vikash Garodia , Dikshita Agarwal , Abhinav Kumar , Bryan O'Donoghue , Mauro Carvalho Chehab Cc: linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Wangao Wang , quic_qiweil@quicinc.com, quic_renjiang@quicinc.com X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1761904292; l=13897; i=wangao.wang@oss.qualcomm.com; s=20251021; h=from:subject:message-id; bh=4j/d/pgw1rmbCsB9i6CZ160Pv6XuxPt6j/us2SNkP9Y=; b=97igKe7GDWK8kaNnR3drUYkQHGk1Y3GA0tnniDb2FzTcSuZGckvCzIuZYipuYVKgWWIec9S3P ctOZGGT7FMJBkO09BS2/DVv9seQNRLdhDaNe+O1Ts58wwS+8CKAUjvJ X-Developer-Key: i=wangao.wang@oss.qualcomm.com; a=ed25519; pk=bUPgYblBUAsoPyGfssbNR7ZXUSGF8v1VF4FJzSO6/aA= X-Authority-Analysis: v=2.4 cv=RL2+3oi+ c=1 sm=1 tr=0 ts=690486b3 cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=x6icFKpwvdMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=XuHcMD-VqflyE-QO6owA:9 a=QEXdDO2ut3YA:10 a=324X-CrmTo6CU4MGRt3R:22 X-Proofpoint-ORIG-GUID: f9wr-AKjNtnGmmjebBoqTrOuWZAuX8Qs X-Proofpoint-GUID: f9wr-AKjNtnGmmjebBoqTrOuWZAuX8Qs X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDMxMDA4OSBTYWx0ZWRfX7s1sDigmpfW7 NBEAn5bLWdPHGJmbjo/f5fl+b3XPXocE/ATw1chVuLHKFr+zhq1kJYmEaOq5602nH1t7BOVz0/m G4SMqAeBkDOvn4x7LG5MuU6+kuUef8DaSkh4NbuhPPy26ikuFchxPrz2Qt3OYppX/ndj2pnwuMz BGUCRPwEQjpGcsA3sff9NKlXTAwSLKRBR3Ig7gc1bwj0iLzhn0eF7YopHdEy1wkBPOKImRy0Xtu pXcD/I6M1Pdm29DFfYhYb56kCNqXLk5AJLKwDkYS92QMlEvRRFsk/Hf02jIN34I4APiFOo4S5P8 f0QJeDukvaksVAnD4q84Tesu5Bo23biVhUgbX06tMnfEEc3olQN9nIK7nYkIO5mPxBm/aiZGxFz Tf+JeL8WzRhHJYePg9f6e7unLyjDYw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-10-31_02,2025-10-29_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 lowpriorityscore=0 malwarescore=0 impostorscore=0 phishscore=0 bulkscore=0 adultscore=0 spamscore=0 clxscore=1015 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2510310089 Add rotation control for encoder, enabling V4L2_CID_ROTATE and handling 90/180/270 degree rotation. Signed-off-by: Wangao Wang Tested-by: Neil Armstrong # on SM8650-HDK --- drivers/media/platform/qcom/iris/iris_ctrls.c | 34 ++++++++++++++++ drivers/media/platform/qcom/iris/iris_ctrls.h | 1 + .../platform/qcom/iris/iris_hfi_gen2_command.c | 41 ++++++++++++++----- .../platform/qcom/iris/iris_hfi_gen2_defines.h | 9 +++++ .../platform/qcom/iris/iris_platform_common.h | 1 + .../media/platform/qcom/iris/iris_platform_gen2.c | 10 +++++ drivers/media/platform/qcom/iris/iris_utils.c | 6 +++ drivers/media/platform/qcom/iris/iris_utils.h | 1 + drivers/media/platform/qcom/iris/iris_vpu_buffer.c | 46 +++++++++++++-----= ---- 9 files changed, 121 insertions(+), 28 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_ctrls.c b/drivers/media/= platform/qcom/iris/iris_ctrls.c index 754a5ad718bc37630bb861012301df7a2e7342a1..00949c207ddb0203e51df359214= bf23c3d8265d0 100644 --- a/drivers/media/platform/qcom/iris/iris_ctrls.c +++ b/drivers/media/platform/qcom/iris/iris_ctrls.c @@ -98,6 +98,8 @@ static enum platform_inst_fw_cap_type iris_get_cap_id(u32= id) return B_FRAME_QP_H264; case V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_QP: return B_FRAME_QP_HEVC; + case V4L2_CID_ROTATE: + return ROTATION; default: return INST_FW_CAP_MAX; } @@ -185,6 +187,8 @@ static u32 iris_get_v4l2_id(enum platform_inst_fw_cap_t= ype cap_id) return V4L2_CID_MPEG_VIDEO_H264_B_FRAME_QP; case B_FRAME_QP_HEVC: return V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_QP; + case ROTATION: + return V4L2_CID_ROTATE; default: return 0; } @@ -883,6 +887,36 @@ int iris_set_qp_range(struct iris_inst *inst, enum pla= tform_inst_fw_cap_type cap &range, sizeof(range)); } =20 +int iris_set_rotation(struct iris_inst *inst, enum platform_inst_fw_cap_ty= pe cap_id) +{ + const struct iris_hfi_command_ops *hfi_ops =3D inst->core->hfi_ops; + u32 hfi_id =3D inst->fw_caps[cap_id].hfi_id; + u32 hfi_val; + + switch (inst->fw_caps[cap_id].value) { + case 0: + hfi_val =3D HFI_ROTATION_NONE; + return 0; + case 90: + hfi_val =3D HFI_ROTATION_90; + break; + case 180: + hfi_val =3D HFI_ROTATION_180; + break; + case 270: + hfi_val =3D HFI_ROTATION_270; + break; + default: + return -EINVAL; + } + + return hfi_ops->session_set_property(inst, hfi_id, + HFI_HOST_FLAGS_NONE, + iris_get_port_info(inst, cap_id), + HFI_PAYLOAD_U32, + &hfi_val, sizeof(u32)); +} + int iris_set_properties(struct iris_inst *inst, u32 plane) { const struct iris_hfi_command_ops *hfi_ops =3D inst->core->hfi_ops; diff --git a/drivers/media/platform/qcom/iris/iris_ctrls.h b/drivers/media/= platform/qcom/iris/iris_ctrls.h index 30af333cc4941e737eb1ae83a6944b4192896e23..3ea0a00c7587a516f19bb7307a0= eb9a60c856ab0 100644 --- a/drivers/media/platform/qcom/iris/iris_ctrls.h +++ b/drivers/media/platform/qcom/iris/iris_ctrls.h @@ -32,6 +32,7 @@ int iris_set_min_qp(struct iris_inst *inst, enum platform= _inst_fw_cap_type cap_i int iris_set_max_qp(struct iris_inst *inst, enum platform_inst_fw_cap_type= cap_id); int iris_set_frame_qp(struct iris_inst *inst, enum platform_inst_fw_cap_ty= pe cap_id); int iris_set_qp_range(struct iris_inst *inst, enum platform_inst_fw_cap_ty= pe cap_id); +int iris_set_rotation(struct iris_inst *inst, enum platform_inst_fw_cap_ty= pe cap_id); int iris_set_properties(struct iris_inst *inst, u32 plane); =20 #endif diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c b/dri= vers/media/platform/qcom/iris/iris_hfi_gen2_command.c index 6ec217268a2bc1f939fa33820c1ae19adaad2e96..4e88239351bb5adf1ed3260ad4d= 3ba2fe1df7555 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c @@ -180,22 +180,36 @@ static int iris_hfi_gen2_set_raw_resolution(struct ir= is_inst *inst, u32 plane) sizeof(u32)); } =20 +static inline u32 iris_hfi_get_aligned_resolution(struct iris_inst *inst, = u32 width, u32 height) +{ + u32 codec_align =3D inst->codec =3D=3D V4L2_PIX_FMT_HEVC ? 32 : 16; + + return (ALIGN(width, codec_align) << 16 | ALIGN(height, codec_align)); +} + static int iris_hfi_gen2_set_bitstream_resolution(struct iris_inst *inst, = u32 plane) { struct iris_inst_hfi_gen2 *inst_hfi_gen2 =3D to_iris_inst_hfi_gen2(inst); u32 port =3D iris_hfi_gen2_get_port(inst, plane); enum hfi_packet_payload_info payload_type; - u32 resolution, codec_align; + u32 width, height; + u32 resolution; =20 if (inst->domain =3D=3D DECODER) { - resolution =3D inst->fmt_src->fmt.pix_mp.width << 16 | - inst->fmt_src->fmt.pix_mp.height; + width =3D inst->fmt_src->fmt.pix_mp.width; + height =3D inst->fmt_src->fmt.pix_mp.height; + resolution =3D iris_hfi_get_aligned_resolution(inst, width, height); inst_hfi_gen2->src_subcr_params.bitstream_resolution =3D resolution; payload_type =3D HFI_PAYLOAD_U32; } else { - codec_align =3D inst->codec =3D=3D V4L2_PIX_FMT_HEVC ? 32 : 16; - resolution =3D ALIGN(inst->enc_scale_width, codec_align) << 16 | - ALIGN(inst->enc_scale_height, codec_align); + if (is_rotation_90_or_270(inst)) { + width =3D inst->enc_scale_height; + height =3D inst->enc_scale_width; + } else { + width =3D inst->enc_scale_width; + height =3D inst->enc_scale_height; + } + resolution =3D iris_hfi_get_aligned_resolution(inst, width, height); inst_hfi_gen2->dst_subcr_params.bitstream_resolution =3D resolution; payload_type =3D HFI_PAYLOAD_32_PACKED; } @@ -234,10 +248,17 @@ static int iris_hfi_gen2_set_crop_offsets(struct iris= _inst *inst, u32 plane) } } else { if (V4L2_TYPE_IS_CAPTURE(plane)) { - bottom_offset =3D (ALIGN(inst->enc_raw_height, codec_align) - - inst->enc_raw_height); - right_offset =3D (ALIGN(inst->enc_raw_width, codec_align) - - inst->enc_raw_width); + if (is_rotation_90_or_270(inst)) { + bottom_offset =3D (ALIGN(inst->enc_scale_width, codec_align) - + inst->enc_scale_width); + right_offset =3D (ALIGN(inst->enc_scale_height, codec_align) - + inst->enc_scale_height); + } else { + bottom_offset =3D (ALIGN(inst->enc_scale_height, codec_align) - + inst->enc_scale_height); + right_offset =3D (ALIGN(inst->enc_scale_width, codec_align) - + inst->enc_scale_width); + } left_offset =3D inst->crop.left; top_offset =3D inst->crop.top; } diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen2_defines.h b/dri= vers/media/platform/qcom/iris/iris_hfi_gen2_defines.h index aa1f795f5626c1f76a32dd650302633877ce67be..4edcce7faf5e2f74bfecfdbf574= 391d5b1c9cca5 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen2_defines.h +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen2_defines.h @@ -83,6 +83,15 @@ enum hfi_seq_header_mode { }; =20 #define HFI_PROP_SEQ_HEADER_MODE 0x03000149 + +enum hfi_rotation { + HFI_ROTATION_NONE =3D 0x00000000, + HFI_ROTATION_90 =3D 0x00000001, + HFI_ROTATION_180 =3D 0x00000002, + HFI_ROTATION_270 =3D 0x00000003, +}; + +#define HFI_PROP_ROTATION 0x0300014b #define HFI_PROP_SIGNAL_COLOR_INFO 0x03000155 #define HFI_PROP_PICTURE_TYPE 0x03000162 #define HFI_PROP_DEC_DEFAULT_HEADER 0x03000168 diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/driv= ers/media/platform/qcom/iris/iris_platform_common.h index 58d05e0a112eed25faea027a34c719c89d6c3897..9a4232b1c64eea6ce909e1e3117= 69dd958b84c6e 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -140,6 +140,7 @@ enum platform_inst_fw_cap_type { P_FRAME_QP_HEVC, B_FRAME_QP_H264, B_FRAME_QP_HEVC, + ROTATION, INST_FW_CAP_MAX, }; =20 diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/driver= s/media/platform/qcom/iris/iris_platform_gen2.c index d3306189d902a1f42666010468c9e4e4316a66e1..c1f83e179d441c45df8d6487dc8= 7e137e482fb63 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c +++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c @@ -588,6 +588,16 @@ static struct platform_inst_fw_cap inst_fw_cap_sm8550_= enc[] =3D { .flags =3D CAP_FLAG_OUTPUT_PORT, .set =3D iris_set_u32, }, + { + .cap_id =3D ROTATION, + .min =3D 0, + .max =3D 270, + .step_or_mask =3D 90, + .value =3D 0, + .hfi_id =3D HFI_PROP_ROTATION, + .flags =3D CAP_FLAG_OUTPUT_PORT, + .set =3D iris_set_rotation, + }, }; =20 static struct platform_inst_caps platform_inst_cap_sm8550 =3D { diff --git a/drivers/media/platform/qcom/iris/iris_utils.c b/drivers/media/= platform/qcom/iris/iris_utils.c index 85c70a62b1fd2c409fc18b28f64771cb0097a7fd..97465dfbdec1497b1111b9069fd= 56dff286b2d0e 100644 --- a/drivers/media/platform/qcom/iris/iris_utils.c +++ b/drivers/media/platform/qcom/iris/iris_utils.c @@ -124,3 +124,9 @@ int iris_check_core_mbps(struct iris_inst *inst) =20 return 0; } + +bool is_rotation_90_or_270(struct iris_inst *inst) +{ + return inst->fw_caps[ROTATION].value =3D=3D 90 || + inst->fw_caps[ROTATION].value =3D=3D 270; +} diff --git a/drivers/media/platform/qcom/iris/iris_utils.h b/drivers/media/= platform/qcom/iris/iris_utils.h index 75740181122f5bdf93d64d3f43b3a26a9fe97919..b5705d156431a5cf59d645ce988= bc3a3c9b9c5e2 100644 --- a/drivers/media/platform/qcom/iris/iris_utils.h +++ b/drivers/media/platform/qcom/iris/iris_utils.h @@ -51,5 +51,6 @@ void iris_helper_buffers_done(struct iris_inst *inst, uns= igned int type, int iris_wait_for_session_response(struct iris_inst *inst, bool is_flush); int iris_check_core_mbpf(struct iris_inst *inst); int iris_check_core_mbps(struct iris_inst *inst); +bool is_rotation_90_or_270(struct iris_inst *inst); =20 #endif diff --git a/drivers/media/platform/qcom/iris/iris_vpu_buffer.c b/drivers/m= edia/platform/qcom/iris/iris_vpu_buffer.c index db5adadd1b39c06bc41ae6f1b3d2f924b3ebf150..be8b8588a39fb02d8dd9f1f1f67= 65ec76dc7d08f 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_buffer.c +++ b/drivers/media/platform/qcom/iris/iris_vpu_buffer.c @@ -556,6 +556,22 @@ static u32 iris_vpu_dec_scratch1_size(struct iris_inst= *inst) iris_vpu_dec_line_size(inst); } =20 +static inline u32 iris_vpu_enc_get_bitstream_width(struct iris_inst *inst) +{ + if (is_rotation_90_or_270(inst)) + return inst->fmt_dst->fmt.pix_mp.height; + else + return inst->fmt_dst->fmt.pix_mp.width; +} + +static inline u32 iris_vpu_enc_get_bitstream_height(struct iris_inst *inst) +{ + if (is_rotation_90_or_270(inst)) + return inst->fmt_dst->fmt.pix_mp.width; + else + return inst->fmt_dst->fmt.pix_mp.height; +} + static inline u32 size_bin_bitstream_enc(u32 width, u32 height, u32 rc_type) { @@ -638,10 +654,9 @@ static inline u32 hfi_buffer_bin_enc(u32 width, u32 he= ight, static u32 iris_vpu_enc_bin_size(struct iris_inst *inst) { u32 num_vpp_pipes =3D inst->core->iris_platform_data->num_vpp_pipe; + u32 height =3D iris_vpu_enc_get_bitstream_height(inst); + u32 width =3D iris_vpu_enc_get_bitstream_width(inst); u32 stage =3D inst->fw_caps[STAGE].value; - struct v4l2_format *f =3D inst->fmt_dst; - u32 height =3D f->fmt.pix_mp.height; - u32 width =3D f->fmt.pix_mp.width; u32 lcu_size; =20 if (inst->codec =3D=3D V4L2_PIX_FMT_HEVC) @@ -676,9 +691,8 @@ u32 hfi_buffer_comv_enc(u32 frame_width, u32 frame_heig= ht, u32 lcu_size, =20 static u32 iris_vpu_enc_comv_size(struct iris_inst *inst) { - struct v4l2_format *f =3D inst->fmt_dst; - u32 height =3D f->fmt.pix_mp.height; - u32 width =3D f->fmt.pix_mp.width; + u32 height =3D iris_vpu_enc_get_bitstream_height(inst); + u32 width =3D iris_vpu_enc_get_bitstream_width(inst); u32 num_recon =3D 1; u32 lcu_size =3D 16; =20 @@ -958,9 +972,8 @@ u32 hfi_buffer_non_comv_enc(u32 frame_width, u32 frame_= height, static u32 iris_vpu_enc_non_comv_size(struct iris_inst *inst) { u32 num_vpp_pipes =3D inst->core->iris_platform_data->num_vpp_pipe; - struct v4l2_format *f =3D inst->fmt_dst; - u32 height =3D f->fmt.pix_mp.height; - u32 width =3D f->fmt.pix_mp.width; + u32 height =3D iris_vpu_enc_get_bitstream_height(inst); + u32 width =3D iris_vpu_enc_get_bitstream_width(inst); u32 lcu_size =3D 16; =20 if (inst->codec =3D=3D V4L2_PIX_FMT_HEVC) { @@ -1051,9 +1064,8 @@ u32 hfi_buffer_line_enc_vpu33(u32 frame_width, u32 fr= ame_height, bool is_ten_bit static u32 iris_vpu_enc_line_size(struct iris_inst *inst) { u32 num_vpp_pipes =3D inst->core->iris_platform_data->num_vpp_pipe; - struct v4l2_format *f =3D inst->fmt_dst; - u32 height =3D f->fmt.pix_mp.height; - u32 width =3D f->fmt.pix_mp.width; + u32 height =3D iris_vpu_enc_get_bitstream_height(inst); + u32 width =3D iris_vpu_enc_get_bitstream_width(inst); u32 lcu_size =3D 16; =20 if (inst->codec =3D=3D V4L2_PIX_FMT_HEVC) { @@ -1292,9 +1304,8 @@ static inline u32 hfi_buffer_scratch1_enc(u32 frame_w= idth, u32 frame_height, static u32 iris_vpu_enc_scratch1_size(struct iris_inst *inst) { u32 num_vpp_pipes =3D inst->core->iris_platform_data->num_vpp_pipe; - struct v4l2_format *f =3D inst->fmt_dst; - u32 frame_height =3D f->fmt.pix_mp.height; - u32 frame_width =3D f->fmt.pix_mp.width; + u32 frame_height =3D iris_vpu_enc_get_bitstream_height(inst); + u32 frame_width =3D iris_vpu_enc_get_bitstream_width(inst); u32 num_ref =3D 1; u32 lcu_size; bool is_h265; @@ -1390,9 +1401,8 @@ static inline u32 hfi_buffer_scratch2_enc(u32 frame_w= idth, u32 frame_height, =20 static u32 iris_vpu_enc_scratch2_size(struct iris_inst *inst) { - struct v4l2_format *f =3D inst->fmt_dst; - u32 frame_width =3D f->fmt.pix_mp.width; - u32 frame_height =3D f->fmt.pix_mp.height; + u32 frame_height =3D iris_vpu_enc_get_bitstream_height(inst); + u32 frame_width =3D iris_vpu_enc_get_bitstream_width(inst); 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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-295268716e4sm17913115ad.9.2025.10.31.02.51.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 31 Oct 2025 02:51:48 -0700 (PDT) From: Wangao Wang Date: Fri, 31 Oct 2025 17:50:42 +0800 Subject: [PATCH v2 4/5] media: qcom: iris: Add flip support for encoder Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251031-iris_encoder_enhancements-v2-4-319cd75cbb45@oss.qualcomm.com> References: <20251031-iris_encoder_enhancements-v2-0-319cd75cbb45@oss.qualcomm.com> In-Reply-To: <20251031-iris_encoder_enhancements-v2-0-319cd75cbb45@oss.qualcomm.com> To: Vikash Garodia , Dikshita Agarwal , Abhinav Kumar , Bryan O'Donoghue , Mauro Carvalho Chehab Cc: linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Wangao Wang , quic_qiweil@quicinc.com, quic_renjiang@quicinc.com X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1761904292; l=5471; i=wangao.wang@oss.qualcomm.com; s=20251021; h=from:subject:message-id; bh=IJkf+YIwrITwSassNOIm3Z8YdfOmrJJE6k+78c9So9k=; b=K35f/ZHVJTu2oQJcWIZut+CcfRQe39O3PZFjqUTVMGrfZhbqbLNHhZhmXkww06vIB17GXEtuj 9Z+aucb82OrBPB8CBUuSMA4FbjpeQ8jHTWgHNoioguzMTJPQ/TcUTmw X-Developer-Key: i=wangao.wang@oss.qualcomm.com; a=ed25519; pk=bUPgYblBUAsoPyGfssbNR7ZXUSGF8v1VF4FJzSO6/aA= X-Authority-Analysis: v=2.4 cv=efswvrEH c=1 sm=1 tr=0 ts=690486b6 cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=x6icFKpwvdMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=uxdc-9wEpbf47THqrzgA:9 a=QEXdDO2ut3YA:10 a=GvdueXVYPmCkWapjIL-Q:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDMxMDA4OSBTYWx0ZWRfX3loSYuIOQPhZ 8trIuBezzclAT7HCLiefT3cy7O91FVFcMsbW//Nsfvv3sr3JjyZmlXLAva0pUJwdJu7XkWZFNmM ndVfyeQr+meFYmDM7E4nobemd9hlTC5aoy9G5XH7S7kx9KK0GE1UaOjhD2TnIP2+7twftckgMQE ImGDKjySaqsUms9dGxAMYywOI6avkcdahC6bubzpyso9VKX4DYWthxY+VixFEws5tCjltto/L8B VcwP8U7MWTS2mFqir9nbq5iHl8fCX9ruBhXaVCADkL2fWHDr1CKL4B4mzkpsL9eMSgS1yB49Rux 6VPuPzuamQ4TxJyPflmDNwEqYDCAXlTb6pNURg+CAMIJjQbVlaiGOmn9ndlK+YicC8bnbmnemHs WsnwLDI3URRRjx8SRIxB9nRcCIZiXw== X-Proofpoint-GUID: wKujo_j2hEh2km6nTU3PLklovwNCpkFU X-Proofpoint-ORIG-GUID: wKujo_j2hEh2km6nTU3PLklovwNCpkFU X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-10-31_02,2025-10-29_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 malwarescore=0 phishscore=0 impostorscore=0 lowpriorityscore=0 priorityscore=1501 spamscore=0 clxscore=1015 adultscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2510310089 Add support for V4L2_CID_HFLIP and V4L2_CID_VFLIP controls in encoder. Signed-off-by: Wangao Wang Tested-by: Neil Armstrong # on SM8650-HDK --- drivers/media/platform/qcom/iris/iris_ctrls.c | 27 ++++++++++++++++++= ++++ drivers/media/platform/qcom/iris/iris_ctrls.h | 1 + .../platform/qcom/iris/iris_hfi_gen2_defines.h | 8 +++++++ .../platform/qcom/iris/iris_platform_common.h | 2 ++ .../media/platform/qcom/iris/iris_platform_gen2.c | 22 ++++++++++++++++++ 5 files changed, 60 insertions(+) diff --git a/drivers/media/platform/qcom/iris/iris_ctrls.c b/drivers/media/= platform/qcom/iris/iris_ctrls.c index 00949c207ddb0203e51df359214bf23c3d8265d0..8f74c12f2f41f23d75424819c70= 7aff61ea61b33 100644 --- a/drivers/media/platform/qcom/iris/iris_ctrls.c +++ b/drivers/media/platform/qcom/iris/iris_ctrls.c @@ -100,6 +100,10 @@ static enum platform_inst_fw_cap_type iris_get_cap_id(= u32 id) return B_FRAME_QP_HEVC; case V4L2_CID_ROTATE: return ROTATION; + case V4L2_CID_HFLIP: + return HFLIP; + case V4L2_CID_VFLIP: + return VFLIP; default: return INST_FW_CAP_MAX; } @@ -189,6 +193,10 @@ static u32 iris_get_v4l2_id(enum platform_inst_fw_cap_= type cap_id) return V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_QP; case ROTATION: return V4L2_CID_ROTATE; + case HFLIP: + return V4L2_CID_HFLIP; + case VFLIP: + return V4L2_CID_VFLIP; default: return 0; } @@ -917,6 +925,25 @@ int iris_set_rotation(struct iris_inst *inst, enum pla= tform_inst_fw_cap_type cap &hfi_val, sizeof(u32)); } =20 +int iris_set_flip(struct iris_inst *inst, enum platform_inst_fw_cap_type c= ap_id) +{ + const struct iris_hfi_command_ops *hfi_ops =3D inst->core->hfi_ops; + u32 hfi_id =3D inst->fw_caps[cap_id].hfi_id; + u32 hfi_val =3D HFI_DISABLE_FLIP; + + if (inst->fw_caps[HFLIP].value) + hfi_val |=3D HFI_HORIZONTAL_FLIP; + + if (inst->fw_caps[VFLIP].value) + hfi_val |=3D HFI_VERTICAL_FLIP; + + return hfi_ops->session_set_property(inst, hfi_id, + HFI_HOST_FLAGS_NONE, + iris_get_port_info(inst, cap_id), + HFI_PAYLOAD_U32_ENUM, + &hfi_val, sizeof(u32)); +} + int iris_set_properties(struct iris_inst *inst, u32 plane) { const struct iris_hfi_command_ops *hfi_ops =3D inst->core->hfi_ops; diff --git a/drivers/media/platform/qcom/iris/iris_ctrls.h b/drivers/media/= platform/qcom/iris/iris_ctrls.h index 3ea0a00c7587a516f19bb7307a0eb9a60c856ab0..355a592049f3fcc715a1b9df44b= 4d1398b052653 100644 --- a/drivers/media/platform/qcom/iris/iris_ctrls.h +++ b/drivers/media/platform/qcom/iris/iris_ctrls.h @@ -33,6 +33,7 @@ int iris_set_max_qp(struct iris_inst *inst, enum platform= _inst_fw_cap_type cap_i int iris_set_frame_qp(struct iris_inst *inst, enum platform_inst_fw_cap_ty= pe cap_id); int iris_set_qp_range(struct iris_inst *inst, enum platform_inst_fw_cap_ty= pe cap_id); int iris_set_rotation(struct iris_inst *inst, enum platform_inst_fw_cap_ty= pe cap_id); +int iris_set_flip(struct iris_inst *inst, enum platform_inst_fw_cap_type c= ap_id); int iris_set_properties(struct iris_inst *inst, u32 plane); =20 #endif diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen2_defines.h b/dri= vers/media/platform/qcom/iris/iris_hfi_gen2_defines.h index 4edcce7faf5e2f74bfecfdbf574391d5b1c9cca5..0f92468dca91cbb2ca9b451ebce= 255180066b3a4 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen2_defines.h +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen2_defines.h @@ -92,6 +92,14 @@ enum hfi_rotation { }; =20 #define HFI_PROP_ROTATION 0x0300014b + +enum hfi_flip { + HFI_DISABLE_FLIP =3D 0x00000000, + HFI_HORIZONTAL_FLIP =3D 0x00000001, + HFI_VERTICAL_FLIP =3D 0x00000002, +}; + +#define HFI_PROP_FLIP 0x0300014c #define HFI_PROP_SIGNAL_COLOR_INFO 0x03000155 #define HFI_PROP_PICTURE_TYPE 0x03000162 #define HFI_PROP_DEC_DEFAULT_HEADER 0x03000168 diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/driv= ers/media/platform/qcom/iris/iris_platform_common.h index 9a4232b1c64eea6ce909e1e311769dd958b84c6e..284d6bde6d6bcdf70016646d1c9= 2e6ae7f067efc 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -141,6 +141,8 @@ enum platform_inst_fw_cap_type { B_FRAME_QP_H264, B_FRAME_QP_HEVC, ROTATION, + HFLIP, + VFLIP, INST_FW_CAP_MAX, }; =20 diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/driver= s/media/platform/qcom/iris/iris_platform_gen2.c index c1f83e179d441c45df8d6487dc87e137e482fb63..e74bdd00a4bb2f457ec9352e0ac= aebc820dae235 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c +++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c @@ -598,6 +598,28 @@ static struct platform_inst_fw_cap inst_fw_cap_sm8550_= enc[] =3D { .flags =3D CAP_FLAG_OUTPUT_PORT, .set =3D iris_set_rotation, }, + { + .cap_id =3D HFLIP, + .min =3D 0, + .max =3D 1, + .step_or_mask =3D 1, + .value =3D 0, + .hfi_id =3D HFI_PROP_FLIP, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED, + .set =3D iris_set_flip, + }, + { + .cap_id =3D VFLIP, + .min =3D 0, + .max =3D 1, + .step_or_mask =3D 1, + .value =3D 0, + .hfi_id =3D HFI_PROP_FLIP, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED, + .set =3D iris_set_flip, + }, }; =20 static struct platform_inst_caps platform_inst_cap_sm8550 =3D { --=20 2.43.0 From nobody Sun Feb 8 11:06:34 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AF24033710D for ; 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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-295268716e4sm17913115ad.9.2025.10.31.02.51.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 31 Oct 2025 02:51:51 -0700 (PDT) From: Wangao Wang Date: Fri, 31 Oct 2025 17:50:43 +0800 Subject: [PATCH v2 5/5] media: qcom: iris: Add intra refresh support for encoder Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251031-iris_encoder_enhancements-v2-5-319cd75cbb45@oss.qualcomm.com> References: <20251031-iris_encoder_enhancements-v2-0-319cd75cbb45@oss.qualcomm.com> In-Reply-To: <20251031-iris_encoder_enhancements-v2-0-319cd75cbb45@oss.qualcomm.com> To: Vikash Garodia , Dikshita Agarwal , Abhinav Kumar , Bryan O'Donoghue , Mauro Carvalho Chehab Cc: linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Wangao Wang , quic_qiweil@quicinc.com, quic_renjiang@quicinc.com X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1761904292; l=6258; i=wangao.wang@oss.qualcomm.com; s=20251021; h=from:subject:message-id; bh=yXQEX8LNu0TsL9VDTKU5gwOSUNtbhNTnq7C28ggjxog=; b=xJS+oQadNRx7R2wufglLZFEq4msH9/kXRJxJPCI0aNVjGHXc6OGbeZe+MIKIEOuHmUvQg1fhA 9JUVktI7blHCQcRUWg7/286uLaFx8Vec9vxVeZL5ocLW/3i4CFCbR+h X-Developer-Key: i=wangao.wang@oss.qualcomm.com; a=ed25519; pk=bUPgYblBUAsoPyGfssbNR7ZXUSGF8v1VF4FJzSO6/aA= X-Authority-Analysis: v=2.4 cv=efswvrEH c=1 sm=1 tr=0 ts=690486b9 cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=x6icFKpwvdMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=-vM60OG-bLC5KXgFrusA:9 a=QEXdDO2ut3YA:10 a=1OuFwYUASf3TG4hYMiVC:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDMxMDA4OSBTYWx0ZWRfXz34u2rsfuZSp StTAy1aDjXjjHEfkPnnBHYdQcOrSaoqrJKmye4+Qr1PK6ot5s0sjlLi1AtGJUdx6qC5Y+eWZuT4 ke/awnRhQiMOi3W3f77iVjdSucXTZCU2i7FfmEL79xUXNI4+cqKdlPHb/aKMA/Ii4DW2JD3KGiB KAlGkPpxFvCOcfVzS2XBH7MVTKDh74KIr1krpg4iicbEAOqolLaJqnlircAuWyRSe6CfpXqqXzR FBpHCZJ0g6x11v/07pMgPuFwfor3KfT/JHukXttB/Dj7BCxKNGZbPEG5P1swKUyAE9wXoO2dmN3 moMwFMi1hw8/uhm2806p5W0Ul+xBzIYVNONhZ+E8sE1gfUE6f7pa8WDxw1Z4SYEiRptjLa+9dF1 YRujM5As7qF5v3T5HX4gnDStlc/6gg== X-Proofpoint-GUID: epmLU3OpDrilHnMaw5Epk69IxXsf5ysf X-Proofpoint-ORIG-GUID: epmLU3OpDrilHnMaw5Epk69IxXsf5ysf X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-10-31_02,2025-10-29_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 malwarescore=0 phishscore=0 impostorscore=0 lowpriorityscore=0 priorityscore=1501 spamscore=0 clxscore=1015 adultscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2510310089 Add support for V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD and V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE controls. Signed-off-by: Wangao Wang --- drivers/media/platform/qcom/iris/iris_ctrls.c | 33 ++++++++++++++++++= ++++ drivers/media/platform/qcom/iris/iris_ctrls.h | 1 + .../platform/qcom/iris/iris_hfi_gen2_defines.h | 2 ++ .../platform/qcom/iris/iris_platform_common.h | 2 ++ .../media/platform/qcom/iris/iris_platform_gen2.c | 19 +++++++++++++ 5 files changed, 57 insertions(+) diff --git a/drivers/media/platform/qcom/iris/iris_ctrls.c b/drivers/media/= platform/qcom/iris/iris_ctrls.c index 8f74c12f2f41f23d75424819c707aff61ea61b33..14891569247318aaa7b2009b737= f077d1cb45095 100644 --- a/drivers/media/platform/qcom/iris/iris_ctrls.c +++ b/drivers/media/platform/qcom/iris/iris_ctrls.c @@ -104,6 +104,10 @@ static enum platform_inst_fw_cap_type iris_get_cap_id(= u32 id) return HFLIP; case V4L2_CID_VFLIP: return VFLIP; + case V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE: + return IR_TYPE; + case V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD: + return IR_PERIOD; default: return INST_FW_CAP_MAX; } @@ -197,6 +201,10 @@ static u32 iris_get_v4l2_id(enum platform_inst_fw_cap_= type cap_id) return V4L2_CID_HFLIP; case VFLIP: return V4L2_CID_VFLIP; + case IR_TYPE: + return V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE; + case IR_PERIOD: + return V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD; default: return 0; } @@ -944,6 +952,31 @@ int iris_set_flip(struct iris_inst *inst, enum platfor= m_inst_fw_cap_type cap_id) &hfi_val, sizeof(u32)); } =20 +int iris_set_ir_period(struct iris_inst *inst, enum platform_inst_fw_cap_t= ype cap_id) +{ + const struct iris_hfi_command_ops *hfi_ops =3D inst->core->hfi_ops; + struct vb2_queue *q =3D v4l2_m2m_get_dst_vq(inst->m2m_ctx); + u32 ir_period =3D inst->fw_caps[cap_id].value; + u32 ir_type =3D 0; + + if (inst->fw_caps[IR_TYPE].value =3D=3D + V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE_RANDOM) { + if (vb2_is_streaming(q)) + return 0; + ir_type =3D HFI_PROP_IR_RANDOM_PERIOD; + } else if (inst->fw_caps[IR_TYPE].value =3D=3D + V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE_CYCLIC) { + ir_type =3D HFI_PROP_IR_CYCLIC_PERIOD; + } else + return -EINVAL; + + return hfi_ops->session_set_property(inst, ir_type, + HFI_HOST_FLAGS_NONE, + iris_get_port_info(inst, cap_id), + HFI_PAYLOAD_U32, + &ir_period, sizeof(u32)); +} + int iris_set_properties(struct iris_inst *inst, u32 plane) { const struct iris_hfi_command_ops *hfi_ops =3D inst->core->hfi_ops; diff --git a/drivers/media/platform/qcom/iris/iris_ctrls.h b/drivers/media/= platform/qcom/iris/iris_ctrls.h index 355a592049f3fcc715a1b9df44b4d1398b052653..9518803577bc39f5c1339a49878= dd0c3e8f510ad 100644 --- a/drivers/media/platform/qcom/iris/iris_ctrls.h +++ b/drivers/media/platform/qcom/iris/iris_ctrls.h @@ -34,6 +34,7 @@ int iris_set_frame_qp(struct iris_inst *inst, enum platfo= rm_inst_fw_cap_type cap int iris_set_qp_range(struct iris_inst *inst, enum platform_inst_fw_cap_ty= pe cap_id); int iris_set_rotation(struct iris_inst *inst, enum platform_inst_fw_cap_ty= pe cap_id); int iris_set_flip(struct iris_inst *inst, enum platform_inst_fw_cap_type c= ap_id); +int iris_set_ir_period(struct iris_inst *inst, enum platform_inst_fw_cap_t= ype cap_id); int iris_set_properties(struct iris_inst *inst, u32 plane); =20 #endif diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen2_defines.h b/dri= vers/media/platform/qcom/iris/iris_hfi_gen2_defines.h index 0f92468dca91cbb2ca9b451ebce255180066b3a4..9e8fdddf2aef439e7f133c9bb2f= afa6d95062b02 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen2_defines.h +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen2_defines.h @@ -70,6 +70,7 @@ enum hfi_rate_control { #define HFI_PROP_QP_PACKED 0x0300012e #define HFI_PROP_MIN_QP_PACKED 0x0300012f #define HFI_PROP_MAX_QP_PACKED 0x03000130 +#define HFI_PROP_IR_RANDOM_PERIOD 0x03000131 #define HFI_PROP_TOTAL_BITRATE 0x0300013b #define HFI_PROP_MAX_GOP_FRAMES 0x03000146 #define HFI_PROP_MAX_B_FRAMES 0x03000147 @@ -108,6 +109,7 @@ enum hfi_flip { #define HFI_PROP_BUFFER_MARK 0x0300016c #define HFI_PROP_RAW_RESOLUTION 0x03000178 #define HFI_PROP_TOTAL_PEAK_BITRATE 0x0300017C +#define HFI_PROP_IR_CYCLIC_PERIOD 0x0300017E #define HFI_PROP_COMV_BUFFER_COUNT 0x03000193 #define HFI_PROP_END 0x03FFFFFF =20 diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/driv= ers/media/platform/qcom/iris/iris_platform_common.h index 284d6bde6d6bcdf70016646d1c92e6ae7f067efc..30b98e769ad34c2b63dd63e7714= bfeaa5b4f162c 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -143,6 +143,8 @@ enum platform_inst_fw_cap_type { ROTATION, HFLIP, VFLIP, + IR_TYPE, + IR_PERIOD, INST_FW_CAP_MAX, }; =20 diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/driver= s/media/platform/qcom/iris/iris_platform_gen2.c index e74bdd00a4bb2f457ec9352e0acaebc820dae235..ce54aac766e2bf76fa2de64c884= 724ca63f05dcb 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c +++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c @@ -620,6 +620,25 @@ static struct platform_inst_fw_cap inst_fw_cap_sm8550_= enc[] =3D { CAP_FLAG_DYNAMIC_ALLOWED, .set =3D iris_set_flip, }, + { + .cap_id =3D IR_TYPE, + .min =3D V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE_RANDOM, + .max =3D V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE_CYCLIC, + .step_or_mask =3D BIT(V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE_RAND= OM) | + BIT(V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE_CYCLIC), + .value =3D V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE_RANDOM, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + }, + { + .cap_id =3D IR_PERIOD, + .min =3D 0, + .max =3D INT_MAX, + .step_or_mask =3D 1, + .value =3D 0, + .flags =3D CAP_FLAG_OUTPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED, + .set =3D iris_set_ir_period, + }, }; =20 static struct platform_inst_caps platform_inst_cap_sm8550 =3D { --=20 2.43.0