From nobody Mon Feb 9 11:34:42 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 968723346B0; Fri, 31 Oct 2025 10:21:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761906075; cv=none; b=LyBD4EsGW7dLWdxTPm7n3tAY9OC2xmGa+Vl/d6X07YqDMezXV/k2wOsOnr3uNOg7VcMyWcMSUUOzhuoHzHXXnXpVeguClpfwiNKOCmYdsY6BBe+90LVd1Uf4iZkaAeMLxdJXMCb4G6Ggop0i3flv/KzGHBIZLEFyLU7qSId8N1s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761906075; c=relaxed/simple; bh=eWgStNZQkKRckliNTzEBfeYbSqjsyecK1f1P6AlnbeI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=MsGeiXvCWPO1BGJx1pRzFwMapsh/7DXEnauPdUCWoFmIX1WhPD77RuCfA9M3PIo156XN01sFMRFa0NsXl0sbgJOCDRzqvi7jMZIZwO2szyzh8qRKFrjZ3/kFFdpAS/2WeufHVlSg77VSTwgceT/ClbbD/zi9Dy6iYLohX7gRocA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=jzW5tepR; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="jzW5tepR" Received: by smtp.kernel.org (Postfix) with ESMTPS id 45DDBC4CEFB; Fri, 31 Oct 2025 10:21:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1761906075; bh=eWgStNZQkKRckliNTzEBfeYbSqjsyecK1f1P6AlnbeI=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=jzW5tepRDri9zBMyQsI47H4Tcikc4dqED8tfXWYePy7oBUJkTjHsrm0JWgOg1bFIW saSV+IPVtFoHuWEBBcEV80z222xJrY3+f3ltEuTEqHqqQUQ2QPp4qeIKBOBHlwAqkC VbyS/QgKtlbAzKKL8LmchdT4MmotRfOOH+yNvE24k8AnZjYXbrU/WTvrIuRdI6h09I +YXnYOr5EvOkklH6kH+9UOVx/VQFVukDPsrmAWUZk4NVHn0WOVD4/n5b6ErzEyvk3c oZvp8g38vC+U41lBTuC+a1IoFhWwmbuNMM+wq2LdyYj8Vm07Sdlb2VuwCIdXDapXt5 /pd900SL+HdeA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 305ABCCF9F8; Fri, 31 Oct 2025 10:21:15 +0000 (UTC) From: Hrishabh Rajput via B4 Relay Date: Fri, 31 Oct 2025 10:18:13 +0000 Subject: [PATCH v4 1/2] soc: qcom: smem: Register gunyah watchdog device Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251031-gunyah_watchdog-v4-1-7abb1ee11315@oss.qualcomm.com> References: <20251031-gunyah_watchdog-v4-0-7abb1ee11315@oss.qualcomm.com> In-Reply-To: <20251031-gunyah_watchdog-v4-0-7abb1ee11315@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Wim Van Sebroeck , Guenter Roeck , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Pavan Kondeti , Neil Armstrong , Dmitry Baryshkov , Hrishabh Rajput X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1761906073; l=2298; i=hrishabh.rajput@oss.qualcomm.com; s=20250903; h=from:subject:message-id; bh=ScMyepfgPdrQal4O/t/gi35G4I+goW0FS6p9YVcPjOI=; b=1qWdIsujLdCX86SfLztCocP3MKWXDMGJ61+zTsF+4d3pVKhPs7YKa2/Vs2YB0neeANKcrpgSO NeAIuM25vKbDor3Hv7CG76ynpZX1CQvn2IW3WHgWs5R4P0+km84l3DH X-Developer-Key: i=hrishabh.rajput@oss.qualcomm.com; a=ed25519; pk=syafMitrjr3b/OYAtA2Im06AUb3fxZY2vJ/t4iCPmgw= X-Endpoint-Received: by B4 Relay for hrishabh.rajput@oss.qualcomm.com/20250903 with auth_id=509 X-Original-From: Hrishabh Rajput Reply-To: hrishabh.rajput@oss.qualcomm.com From: Hrishabh Rajput To restrict gunyah watchdog initialization to Qualcomm platforms, register the watchdog device in the SMEM driver. When Gunyah is not present or Gunyah emulates MMIO-based watchdog, we expect Qualcomm watchdog or ARM SBSA watchdog device to be present in the devicetree. If none of these device nodes are detected, we register the SMC-based Gunyah watchdog device. Signed-off-by: Hrishabh Rajput --- drivers/soc/qcom/smem.c | 37 +++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/drivers/soc/qcom/smem.c b/drivers/soc/qcom/smem.c index cf425930539e..40e4749fab02 100644 --- a/drivers/soc/qcom/smem.c +++ b/drivers/soc/qcom/smem.c @@ -1118,6 +1118,34 @@ static int qcom_smem_resolve_mem(struct qcom_smem *s= mem, const char *name, return 0; } =20 +static int register_gunyah_wdt_device(void) +{ + struct platform_device *gunyah_wdt_dev; + struct device_node *np; + + /* + * When Gunyah is not present or Gunyah is emulating a memory-mapped + * watchdog, either of Qualcomm watchdog or ARM SBSA watchdog will be + * present. Skip initialization of SMC-based Gunyah watchdog if that is + * the case. + */ + np =3D of_find_compatible_node(NULL, NULL, "qcom,kpss-wdt"); + if (np) { + of_node_put(np); + return 0; + } + + np =3D of_find_compatible_node(NULL, NULL, "arm,sbsa-gwdt"); + if (np) { + of_node_put(np); + return 0; + } + + gunyah_wdt_dev =3D platform_device_register_simple("gunyah-wdt", -1, + NULL, 0); + return PTR_ERR_OR_ZERO(gunyah_wdt_dev); +} + static int qcom_smem_probe(struct platform_device *pdev) { struct smem_header *header; @@ -1236,11 +1264,20 @@ static int qcom_smem_probe(struct platform_device *= pdev) if (IS_ERR(smem->socinfo)) dev_dbg(&pdev->dev, "failed to register socinfo device\n"); =20 + ret =3D register_gunyah_wdt_device(); + if (ret) + dev_dbg(&pdev->dev, "failed to register watchdog device\n"); + return 0; } =20 static void qcom_smem_remove(struct platform_device *pdev) { + /* + * Gunyah watchdog is intended to be a persistent module. Hence, the + * watchdog device is not unregistered. + */ + platform_device_unregister(__smem->socinfo); =20 hwspin_lock_free(__smem->hwlock); --=20 2.43.0 From nobody Mon Feb 9 11:34:42 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 79E26334372; Fri, 31 Oct 2025 10:21:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761906075; cv=none; b=s3MnaZ/xLkJFd6JKx4S7gUM+2KvvOSOdidhbb2fIt4A7sApcqP8NmIYTHFwupCVR7kcmi2B8A95PdGKfJwLXmqiUEt+ySb7Cr7kfxb3RnM/jPYAlZTZiezXyWdI5w59teAGsgpPbA9ZfZaBq05h43x381+625kCUCVxlVpJgodA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761906075; c=relaxed/simple; bh=/XaqdWiD71n5xxdhLWfrjmXdj4EctoFhRZOYL5YiB+Y=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=juv/JjgU6vnsEZAGFKqWOJXY2xX+5EVuo2lpF6uxll34lA0HHJPPFTiA0N0A3RfQ///PrEKLvZqW7aCudvrVUtrJjqkt/Sv1zStD95XRUbDG0VRzFr8RutnN1p/mxBsZcLiwCjNTutqgZr/iTwiFoMp7dj3p8+trpgnkuHMFYds= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=PccZYxxf; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="PccZYxxf" Received: by smtp.kernel.org (Postfix) with ESMTPS id 565A4C116D0; Fri, 31 Oct 2025 10:21:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1761906075; bh=/XaqdWiD71n5xxdhLWfrjmXdj4EctoFhRZOYL5YiB+Y=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=PccZYxxf5wIXr5s0ANAf3fKK2uDebN40xuv5E37XepI5JdKAz4K4AteygDINX0hh9 5to3Uh7m2y05UVZJVgxmKANrUisN2S8INLBsJD2p+9Gti+KJIWTeuV901xJv6O4Dbr KoFDWy3GYt2MYqu3McRNW74mr+d3+ndsM2pf8vtPJI7aGBpLdRqTOPpacGhdn9m4Dz 6EBcY+SnxgKX/VbvkEJo0HNXwO+bMXFciuupsn7B+VbjHqomxHmwNnsI96KEUicDYz J/44rZ8RLuP9ubRKmeLgPyt6E36buojB8GA+XPgLLYfgF+HTHfViNS6FLGrjH4+e69 UBvz9iWQvEZgQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4268FCCF9FF; Fri, 31 Oct 2025 10:21:15 +0000 (UTC) From: Hrishabh Rajput via B4 Relay Date: Fri, 31 Oct 2025 10:18:14 +0000 Subject: [PATCH v4 2/2] watchdog: Add driver for Gunyah Watchdog Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251031-gunyah_watchdog-v4-2-7abb1ee11315@oss.qualcomm.com> References: <20251031-gunyah_watchdog-v4-0-7abb1ee11315@oss.qualcomm.com> In-Reply-To: <20251031-gunyah_watchdog-v4-0-7abb1ee11315@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Wim Van Sebroeck , Guenter Roeck , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Pavan Kondeti , Neil Armstrong , Dmitry Baryshkov , Hrishabh Rajput X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1761906073; l=9633; i=hrishabh.rajput@oss.qualcomm.com; s=20250903; h=from:subject:message-id; bh=dgpXhemyNU8fZfy0HYNG8ecCoDLEgtKWX9CLRroJfTs=; b=WZHuEpsab3t10pm18Z9WOY+KoPXqyBINyTayZm51J7TGfhcNQfyOvvgj6mVh981YxHD0wA6Iv iNql3qyUouNCreQeh0bChlTNLQbwODGV9t/qK0tVnFUpx/bqSvA7wJ/ X-Developer-Key: i=hrishabh.rajput@oss.qualcomm.com; a=ed25519; pk=syafMitrjr3b/OYAtA2Im06AUb3fxZY2vJ/t4iCPmgw= X-Endpoint-Received: by B4 Relay for hrishabh.rajput@oss.qualcomm.com/20250903 with auth_id=509 X-Original-From: Hrishabh Rajput Reply-To: hrishabh.rajput@oss.qualcomm.com From: Hrishabh Rajput On Qualcomm SoCs running under the Gunyah hypervisor, access to watchdog through MMIO is not available on all platforms. Depending on the hypervisor configuration, the watchdog is either fully emulated or exposed via ARM's SMC Calling Conventions (SMCCC) through the Vendor Specific Hypervisor Service Calls space. Add driver to support the SMC-based watchdog provided by the Gunyah Hypervisor. Device registration is done in the SMEM driver after checks to restrict the watchdog initialization to Qualcomm devices. module_exit() is intentionally not implemented as this driver is intended to be a persistent module. Signed-off-by: Hrishabh Rajput --- MAINTAINERS | 1 + drivers/watchdog/Kconfig | 14 +++ drivers/watchdog/Makefile | 1 + drivers/watchdog/gunyah_wdt.c | 249 ++++++++++++++++++++++++++++++++++++++= ++++ 4 files changed, 265 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index c0b444e5fd5a..56dbd0d3e31b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3083,6 +3083,7 @@ F: arch/arm64/boot/dts/qcom/ F: drivers/bus/qcom* F: drivers/firmware/qcom/ F: drivers/soc/qcom/ +F: drivers/watchdog/gunyah_wdt.c F: include/dt-bindings/arm/qcom,ids.h F: include/dt-bindings/firmware/qcom,scm.h F: include/dt-bindings/soc/qcom* diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 0c25b2ed44eb..f0dee04b3650 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -2343,4 +2343,18 @@ config KEEMBAY_WATCHDOG To compile this driver as a module, choose M here: the module will be called keembay_wdt. =20 +config GUNYAH_WATCHDOG + tristate "Qualcomm Gunyah Watchdog" + depends on ARCH_QCOM || COMPILE_TEST + depends on HAVE_ARM_SMCCC + depends on OF + select WATCHDOG_CORE + help + Say Y here to include support for watchdog timer provided by the + Gunyah hypervisor. The driver uses ARM SMC Calling Convention (SMCCC) + to interact with Gunyah Watchdog. + + To compile this driver as a module, choose M here: the + module will be called gunyah_wdt. + endif # WATCHDOG diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index bbd4d62d2cc3..308379782bc3 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -102,6 +102,7 @@ obj-$(CONFIG_MSC313E_WATCHDOG) +=3D msc313e_wdt.o obj-$(CONFIG_APPLE_WATCHDOG) +=3D apple_wdt.o obj-$(CONFIG_SUNPLUS_WATCHDOG) +=3D sunplus_wdt.o obj-$(CONFIG_MARVELL_GTI_WDT) +=3D marvell_gti_wdt.o +obj-$(CONFIG_GUNYAH_WATCHDOG) +=3D gunyah_wdt.o =20 # X86 (i386 + ia64 + x86_64) Architecture obj-$(CONFIG_ACQUIRE_WDT) +=3D acquirewdt.o diff --git a/drivers/watchdog/gunyah_wdt.c b/drivers/watchdog/gunyah_wdt.c new file mode 100644 index 000000000000..bfe8b656d674 --- /dev/null +++ b/drivers/watchdog/gunyah_wdt.c @@ -0,0 +1,249 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define GUNYAH_WDT_SMCCC_CALL_VAL(func_id) \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, ARM_SMCCC_SMC_32,\ + ARM_SMCCC_OWNER_VENDOR_HYP, func_id) + +/* SMCCC function IDs for watchdog operations */ +#define GUNYAH_WDT_CONTROL GUNYAH_WDT_SMCCC_CALL_VAL(0x0005) +#define GUNYAH_WDT_STATUS GUNYAH_WDT_SMCCC_CALL_VAL(0x0006) +#define GUNYAH_WDT_PING GUNYAH_WDT_SMCCC_CALL_VAL(0x0007) +#define GUNYAH_WDT_SET_TIME GUNYAH_WDT_SMCCC_CALL_VAL(0x0008) + +/* + * Control values for GUNYAH_WDT_CONTROL. + * Bit 0 is used to enable or disable the watchdog. If this bit is set, + * then the watchdog is enabled and vice versa. + * Bit 1 should always be set to 1 as this bit is reserved in Gunyah and + * it's expected to be 1. + */ +#define WDT_CTRL_ENABLE (BIT(1) | BIT(0)) +#define WDT_CTRL_DISABLE BIT(1) + +enum gunyah_error { + GUNYAH_ERROR_OK =3D 0, + GUNYAH_ERROR_UNIMPLEMENTED =3D -1, + GUNYAH_ERROR_ARG_INVAL =3D 1, +}; + +/** + * gunyah_error_remap() - Remap Gunyah hypervisor errors into a Linux erro= r code + * @gunyah_error: Gunyah hypercall return value + */ +static inline int gunyah_error_remap(enum gunyah_error gunyah_error) +{ + switch (gunyah_error) { + case GUNYAH_ERROR_OK: + return 0; + case GUNYAH_ERROR_UNIMPLEMENTED: + return -EOPNOTSUPP; + default: + return -EINVAL; + } +} + +static int gunyah_wdt_call(unsigned long func_id, unsigned long arg1, + unsigned long arg2, struct arm_smccc_res *res) +{ + arm_smccc_1_1_smc(func_id, arg1, arg2, res); + return gunyah_error_remap(res->a0); +} + +static int gunyah_wdt_start(struct watchdog_device *wdd) +{ + struct arm_smccc_res res; + unsigned int timeout_ms; + struct device *dev =3D wdd->parent; + int ret; + + ret =3D gunyah_wdt_call(GUNYAH_WDT_CONTROL, WDT_CTRL_DISABLE, 0, &res); + if (ret && watchdog_active(wdd)) { + dev_err(dev, "%s: Failed to stop gunyah wdt %d\n", __func__, ret); + return ret; + } + + timeout_ms =3D wdd->timeout * 1000; + ret =3D gunyah_wdt_call(GUNYAH_WDT_SET_TIME, + timeout_ms, timeout_ms, &res); + if (ret) { + dev_err(dev, "%s: Failed to set timeout for gunyah wdt %d\n", + __func__, ret); + return ret; + } + + ret =3D gunyah_wdt_call(GUNYAH_WDT_CONTROL, WDT_CTRL_ENABLE, 0, &res); + if (ret) + dev_err(dev, "%s: Failed to start gunyah wdt %d\n", __func__, ret); + + return ret; +} + +static int gunyah_wdt_stop(struct watchdog_device *wdd) +{ + struct arm_smccc_res res; + + return gunyah_wdt_call(GUNYAH_WDT_CONTROL, WDT_CTRL_DISABLE, 0, &res); +} + +static int gunyah_wdt_ping(struct watchdog_device *wdd) +{ + struct arm_smccc_res res; + + return gunyah_wdt_call(GUNYAH_WDT_PING, 0, 0, &res); +} + +static int gunyah_wdt_set_timeout(struct watchdog_device *wdd, + unsigned int timeout_sec) +{ + wdd->timeout =3D timeout_sec; + + if (watchdog_active(wdd)) + return gunyah_wdt_start(wdd); + + return 0; +} + +static unsigned int gunyah_wdt_get_timeleft(struct watchdog_device *wdd) +{ + struct arm_smccc_res res; + unsigned int seconds_since_last_ping; + int ret; + + ret =3D gunyah_wdt_call(GUNYAH_WDT_STATUS, 0, 0, &res); + if (ret) + return 0; + + seconds_since_last_ping =3D res.a2 / 1000; + if (seconds_since_last_ping > wdd->timeout) + return 0; + + return wdd->timeout - seconds_since_last_ping; +} + +static int gunyah_wdt_restart(struct watchdog_device *wdd, + unsigned long action, void *data) +{ + struct arm_smccc_res res; + + /* Set timeout to 1ms and send a ping */ + gunyah_wdt_call(GUNYAH_WDT_CONTROL, WDT_CTRL_ENABLE, 0, &res); + gunyah_wdt_call(GUNYAH_WDT_SET_TIME, 1, 1, &res); + gunyah_wdt_call(GUNYAH_WDT_PING, 0, 0, &res); + + /* Wait to make sure reset occurs */ + mdelay(100); + + return 0; +} + +static const struct watchdog_info gunyah_wdt_info =3D { + .identity =3D "Gunyah Watchdog", + .firmware_version =3D 0, + .options =3D WDIOF_SETTIMEOUT + | WDIOF_KEEPALIVEPING + | WDIOF_MAGICCLOSE, +}; + +static const struct watchdog_ops gunyah_wdt_ops =3D { + .owner =3D THIS_MODULE, + .start =3D gunyah_wdt_start, + .stop =3D gunyah_wdt_stop, + .ping =3D gunyah_wdt_ping, + .set_timeout =3D gunyah_wdt_set_timeout, + .get_timeleft =3D gunyah_wdt_get_timeleft, + .restart =3D gunyah_wdt_restart +}; + +static int gunyah_wdt_probe(struct platform_device *pdev) +{ + struct arm_smccc_res res; + struct watchdog_device *wdd; + struct device *dev =3D &pdev->dev; + int ret; + + ret =3D gunyah_wdt_call(GUNYAH_WDT_STATUS, 0, 0, &res); + if (ret) { + dev_dbg(dev, "Watchdog interface status check failed with %d\n", ret); + return -ENODEV; + } + + wdd =3D devm_kzalloc(dev, sizeof(*wdd), GFP_KERNEL); + if (!wdd) + return -ENOMEM; + + wdd->info =3D &gunyah_wdt_info; + wdd->ops =3D &gunyah_wdt_ops; + wdd->parent =3D dev; + + /* + * Although Gunyah expects 16-bit unsigned int values as timeout values + * in milliseconds, values above 0x8000 are reserved. This limits the + * max timeout value to 32 seconds. + */ + wdd->max_timeout =3D 32; /* seconds */ + wdd->min_timeout =3D 1; /* seconds */ + wdd->timeout =3D wdd->max_timeout; + + gunyah_wdt_stop(wdd); + platform_set_drvdata(pdev, wdd); + watchdog_set_restart_priority(wdd, 0); + + ret =3D devm_watchdog_register_device(dev, wdd); + if (ret) + return dev_err_probe(dev, ret, "Failed to register watchdog device"); + + dev_dbg(dev, "Gunyah watchdog registered\n"); + return 0; +} + +static int __maybe_unused gunyah_wdt_suspend(struct device *dev) +{ + struct watchdog_device *wdd =3D dev_get_drvdata(dev); + + if (watchdog_active(wdd)) + gunyah_wdt_stop(wdd); + + return 0; +} + +static int __maybe_unused gunyah_wdt_resume(struct device *dev) +{ + struct watchdog_device *wdd =3D dev_get_drvdata(dev); + + if (watchdog_active(wdd)) + gunyah_wdt_start(wdd); + + return 0; +} + +static DEFINE_SIMPLE_DEV_PM_OPS(gunyah_wdt_pm_ops, gunyah_wdt_suspend, gun= yah_wdt_resume); + +static struct platform_driver gunyah_wdt_driver =3D { + .probe =3D gunyah_wdt_probe, + .driver =3D { + .name =3D "gunyah-wdt", + .pm =3D pm_sleep_ptr(&gunyah_wdt_pm_ops), + }, +}; + +static int __init gunyah_wdt_init(void) +{ + return platform_driver_register(&gunyah_wdt_driver); +} + +module_init(gunyah_wdt_init); + +MODULE_DESCRIPTION("Gunyah Watchdog Driver"); +MODULE_LICENSE("GPL"); --=20 2.43.0