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[34.77.53.213]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-47732ff7fdbsm31077535e9.16.2025.10.31.05.45.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 31 Oct 2025 05:45:17 -0700 (PDT) From: Tudor Ambarus Date: Fri, 31 Oct 2025 12:45:09 +0000 Subject: [PATCH 1/5] dt-bindings: nvmem: add google,gs101-otp Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251031-gs101-otp-v1-1-2a54f6c4e7b6@linaro.org> References: <20251031-gs101-otp-v1-0-2a54f6c4e7b6@linaro.org> In-Reply-To: <20251031-gs101-otp-v1-0-2a54f6c4e7b6@linaro.org> To: Srinivas Kandagatla , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krzysztof Kozlowski , Alim Akhtar , Peter Griffin , =?utf-8?q?Andr=C3=A9_Draszik?= Cc: semen.protsenko@linaro.org, willmcvicker@google.com, kernel-team@android.com, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Tudor Ambarus X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1761914716; l=2206; i=tudor.ambarus@linaro.org; s=20241212; h=from:subject:message-id; bh=sdrHsJNK5w1wePKRU9wLpHaRPe0gYufMWkbjaBq2T7Y=; b=AzeBS3xPCS7ipIbmYRwBNmPpWeii/0REg4uHEKIlalF+Nqp39ED1ebruQ20wc/fQ2pKxt0v3Q vvYd2l2dU4uBxwKMIQ2L5J3vjcn7FMvU7YTvXTWg7YNSDkjXjZYV38P X-Developer-Key: i=tudor.ambarus@linaro.org; a=ed25519; pk=uQzE0NXo3dIjeowMTOPCpIiPHEz12IA/MbyzrZVh9WI= Add binding for the OTP controller found on Google GS101. Signed-off-by: Tudor Ambarus --- .../bindings/nvmem/google,gs101-otp.yaml | 68 ++++++++++++++++++= ++++ 1 file changed, 68 insertions(+) diff --git a/Documentation/devicetree/bindings/nvmem/google,gs101-otp.yaml = b/Documentation/devicetree/bindings/nvmem/google,gs101-otp.yaml new file mode 100644 index 0000000000000000000000000000000000000000..2144911297beb89337b0389b30f= e6609db4156ea --- /dev/null +++ b/Documentation/devicetree/bindings/nvmem/google,gs101-otp.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/nvmem/google,gs101-otp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Google GS101 OTP Controller + +maintainers: + - Tudor Ambarus + +description: | + OTP controller drives a NVMEM memory where system or user specific data + can be stored. The OTP controller register space if of interest as well + because it contains dedicated registers where it stores the Product ID + and the Chip ID (apart other things like TMU or ASV info). + +allOf: + - $ref: nvmem.yaml# + - $ref: nvmem-deprecated-cells.yaml + +properties: + compatible: + items: + - const: google,gs101-otp + + clocks: + maxItems: 1 + + clock-names: + const: pclk + + reg: + maxItems: 1 + + power-domains: + maxItems: 1 + +required: + - compatible + - reg + - "#address-cells" + - "#size-cells" + - clock-names + - clocks + +unevaluatedProperties: false + +examples: + - | + #include + + otp: efuse@10000000 { + compatible =3D "google,gs101-otp"; + reg =3D <0x10000000 0xf084>; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&cmu_misc CLK_GOUT_MISC_OTP_CON_TOP_PCLK>; + clock-names =3D "pclk"; + + product_id: product_id@0 { + reg =3D <0x0 0x4>; + }; + + chip_id: chip-id@4 { + reg =3D <0x4 0x10>; + }; + }; --=20 2.51.1.930.gacf6e81ea2-goog