From nobody Sun Feb 8 05:42:15 2026 Received: from mail-pj1-f73.google.com (mail-pj1-f73.google.com [209.85.216.73]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7205133BBD0 for ; Thu, 30 Oct 2025 22:42:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.73 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761864175; cv=none; b=fRsePPo6peSXV7EXoBo9GhMhoicM32ZETZrhWy8BafH+atdlx31FIqCTyXW29kkNo5DKdqVSxyTxOIpQOBnqlpIPiODxTypsKEKbJScPbEjI5YcDTrjG0g6czodRojY5AvyiYKGDofJCA0IQqYWdGZiHv+QcUeNan3rWSOrrGhg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761864175; c=relaxed/simple; bh=04xnJwAcMICbMnebLnR0u9v2H7m/YSJO+W1jRIi4Fmk=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=FjF72VwjeD5CPEqtpW5SnPwRiVqJd9lLswZ+U3WWt3H5ot2VmfUDU7fSBtSq37ew1FCz1Tikn7Wlsolbh1wzcTj67ppY0ru2MmNKoKG5v30xjpVlwssvosvlXAuDOV3USRFGXszVDMF9K5MZNDljbvyipht2Yqs7gHEfWYOjZn0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=AkTAIJUI; arc=none smtp.client-ip=209.85.216.73 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="AkTAIJUI" Received: by mail-pj1-f73.google.com with SMTP id 98e67ed59e1d1-3406aa44a1dso1858782a91.2 for ; Thu, 30 Oct 2025 15:42:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1761864173; x=1762468973; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:from:to:cc:subject:date:message-id:reply-to; bh=KcDGQ+FJrmPj33uuNnd2ahLYzOoCImQQ4AQmI9v7NVo=; b=AkTAIJUIq7/4uIq3vWJf8R+uq27BO8eexJGSDgubATx/eP9hsDmQSZ8UCHs618aaC8 wrblfp9A3Ow4OVM3P4Rmhe3VMIzHwpJfZQSqY82XReQqrm77anUUBrT67ZZvOFxNC2eb pnS1DtAQrI1tRB0MM/J/Gs+JGyY6e9dwYsBVkaJqREaBY5IoXPe4qxbwi+4fP6ii2Esb HW2F9dpQ5l/AOMIIqxRQmLMu0RVU1RMhZAcYf7RBgWnWGGfZRfvKHyjicMlfCxRxoRSq Q2CHbaVSvN9f4nm8gam0XXNTpXxap9CpadnVpxKZ1tyiR4ac7UBRnHQNBAqLy8IB5paj wMOw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1761864173; x=1762468973; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=KcDGQ+FJrmPj33uuNnd2ahLYzOoCImQQ4AQmI9v7NVo=; b=OzMP+zodXXsxm4fgE5DGY5Hc1SrP2F0eLCG+2Za0/viqmTSY0Lp894tTxgEgCf2unH xSQ6IpNqYx1N4+guIYelPm1bJ2EAbXQQYaX52YFtLyKzjFwlSIgsAamBP86NstIx09Yb wDm8XKQv/MzdGcG9v+YAG815naOKKO7xunvXbk0N9s5lTiNF5AXldyJ1xHPHcobmVlP2 np9HF5z8XmZuxEw6HZh9qBN2XpYOrCjOQA68e4or1vHKPas5gnlJsmuU4FrzbngBaUvK y2FGmAUkvTsL0hhXxGw/byegWyrrvgMGMpCnwmxNyMQZDyA1yADWDADiratr2Orqs/fF lBag== X-Forwarded-Encrypted: i=1; AJvYcCWAgw34+rQ2wfyC9EbnPNLbGmfrBroRI1jLbpM2VbnIVZebG57LqL+GHvtVhCDgiZmPAEcz6MEfghWjx6U=@vger.kernel.org X-Gm-Message-State: AOJu0YxouxFTc9OhJS/CHGiTDLmQ8FHLFQ3TOLdhPJUrIadj/Q/FEpAN /BoOYkghJBCLSvaab8FeuSYI1ST2Tgg3GiWFDm50/T0c3Dlm30uqHdLbTHT5eeorUcobOCMW/rk 7X5iADQ== X-Google-Smtp-Source: AGHT+IHx3r5KOxD+Pa4cYbZxXLFPXjy7LS9ZHDQFrKCaQ27ZyUwu5YQC2zgibVU8pjv1FCMn6Ev8njqyhHo= X-Received: from pjuy3.prod.google.com ([2002:a17:90a:d703:b0:33b:51fe:1a91]) (user=seanjc job=prod-delivery.src-stubby-dispatcher) by 2002:a17:90b:2886:b0:33b:8ac4:1ac4 with SMTP id 98e67ed59e1d1-34083089b28mr1743813a91.35.1761864172829; Thu, 30 Oct 2025 15:42:52 -0700 (PDT) Reply-To: Sean Christopherson Date: Thu, 30 Oct 2025 15:42:43 -0700 In-Reply-To: <20251030224246.3456492-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20251030224246.3456492-1-seanjc@google.com> X-Mailer: git-send-email 2.51.1.930.gacf6e81ea2-goog Message-ID: <20251030224246.3456492-2-seanjc@google.com> Subject: [PATCH 1/4] KVM: SVM: Handle #MCs in guest outside of fastpath From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Jon Kohler Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Handle Machine Checks (#MC) that happen in the guest (by forwarding them to the host) outside of KVM's fastpath so that as much host state as possible is re-loaded before invoking the kernel's #MC handler. The only requirement is that KVM invokes the #MC handler before enabling IRQs (and even that could _probably_ be relaxed to handling #MCs before enabling preemption). Waiting to handle #MCs until "more" host state is loaded hardens KVM against flaws in the #MC handler, which has historically been quite brittle. E.g. prior to commit 5567d11c21a1 ("x86/mce: Send #MC singal from task work"), the #MC code could trigger a schedule() with IRQs and preemption disabled. That led to a KVM hack-a-fix in commit 1811d979c716 ("x86/kvm: move kvm_load/put_guest_xcr0 into atomic context"). Note, except for #MCs on VM-Enter, VMX already handles #MCs outside of the fastpath. Signed-off-by: Sean Christopherson Reviewed-By: Jon Kohler Reviewed-by: Rick Edgecombe --- arch/x86/kvm/svm/svm.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index f14709a511aa..e8b158f73c79 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -4335,14 +4335,6 @@ static __no_kcsan fastpath_t svm_vcpu_run(struct kvm= _vcpu *vcpu, u64 run_flags) =20 vcpu->arch.regs_avail &=3D ~SVM_REGS_LAZY_LOAD_SET; =20 - /* - * We need to handle MC intercepts here before the vcpu has a chance to - * change the physical cpu - */ - if (unlikely(svm->vmcb->control.exit_code =3D=3D - SVM_EXIT_EXCP_BASE + MC_VECTOR)) - svm_handle_mce(vcpu); - trace_kvm_exit(vcpu, KVM_ISA_SVM); =20 svm_complete_interrupts(vcpu); @@ -4631,8 +4623,16 @@ static int svm_check_intercept(struct kvm_vcpu *vcpu, =20 static void svm_handle_exit_irqoff(struct kvm_vcpu *vcpu) { - if (to_svm(vcpu)->vmcb->control.exit_code =3D=3D SVM_EXIT_INTR) + switch (to_svm(vcpu)->vmcb->control.exit_code) { + case SVM_EXIT_EXCP_BASE + MC_VECTOR: + svm_handle_mce(vcpu); + break; + case SVM_EXIT_INTR: vcpu->arch.at_instruction_boundary =3D true; + break; + default: + break; + } } =20 static void svm_setup_mce(struct kvm_vcpu *vcpu) --=20 2.51.1.930.gacf6e81ea2-goog From nobody Sun Feb 8 05:42:15 2026 Received: from mail-pj1-f74.google.com (mail-pj1-f74.google.com [209.85.216.74]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6B09833C50B for ; Thu, 30 Oct 2025 22:42:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.74 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761864177; cv=none; b=KyMowIcvrUkVbA8MAs/kqABYhHvYr59c0Qnufpn2wJdLtNgq8vYomHEHMNjyHtgnQyLuhWDm5nrQNkHX0cSAijaF3Imn80r4ca9oXddTmT9zhUZFrWt5tucjLziNlZsB9mcAJwAhU0n1ZJKpPm6O3E6jF+I6zpu9pKdktuuhItw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761864177; c=relaxed/simple; bh=MchINskavBlkrWKmsZW/V/NyWaLoR3Fo1XQuVOdWnzU=; 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AJvYcCVOhVNv/cnUWLgUW7c0Bed5usp8UOXTV8EKYrfDw6m7efEFORSeRIlH3ePZJS99/r8tXvpbiGWwSHaKV/E=@vger.kernel.org X-Gm-Message-State: AOJu0Yy9SqkrMB6hyKsx9E29iV6IB2ssKdzrSWE/suFA2SK9fJZ6nrdk 3je2IkISghRPv8n5Wk+C6BYwonuEXIPqr4312ab8If71pnX8F68V/WUt1l0qvIYD9jF5bd/onpq e+/NSmQ== X-Google-Smtp-Source: AGHT+IGTW7/+BlUHW51xmkfkplp3sSIcQ+cUhORPp1pYopyj5vl7hP44CWO33PujFVasNhIynwLieXXQRjA= X-Received: from pjbms9.prod.google.com ([2002:a17:90b:2349:b0:33d:69cf:1f82]) (user=seanjc job=prod-delivery.src-stubby-dispatcher) by 2002:a17:90b:2f87:b0:33e:30e8:81cb with SMTP id 98e67ed59e1d1-34082fd8a5emr1932559a91.13.1761864174630; Thu, 30 Oct 2025 15:42:54 -0700 (PDT) Reply-To: Sean Christopherson Date: Thu, 30 Oct 2025 15:42:44 -0700 In-Reply-To: <20251030224246.3456492-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20251030224246.3456492-1-seanjc@google.com> X-Mailer: git-send-email 2.51.1.930.gacf6e81ea2-goog Message-ID: <20251030224246.3456492-3-seanjc@google.com> Subject: [PATCH 2/4] KVM: VMX: Handle #MCs on VM-Enter/TD-Enter outside of the fastpath From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Jon Kohler Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Handle Machine Checks (#MC) that happen on VM-Enter (VMX or TDX) outside of KVM's fastpath so that as much host state as possible is re-loaded before invoking the kernel's #MC handler. The only requirement is that KVM invokes the #MC handler before enabling IRQs (and even that could _probably_ be related to handling #MCs before enabling preemption). Waiting to handle #MCs until "more" host state is loaded hardens KVM against flaws in the #MC handler, which has historically been quite brittle. E.g. prior to commit 5567d11c21a1 ("x86/mce: Send #MC singal from task work"), the #MC code could trigger a schedule() with IRQs and preemption disabled. That led to a KVM hack-a-fix in commit 1811d979c716 ("x86/kvm: move kvm_load/put_guest_xcr0 into atomic context"). Signed-off-by: Sean Christopherson Reviewed-By: Jon Kohler Reviewed-by: Rick Edgecombe --- arch/x86/kvm/vmx/main.c | 13 ++++++++++++- arch/x86/kvm/vmx/tdx.c | 3 --- arch/x86/kvm/vmx/vmx.c | 3 --- 3 files changed, 12 insertions(+), 7 deletions(-) diff --git a/arch/x86/kvm/vmx/main.c b/arch/x86/kvm/vmx/main.c index 0eb2773b2ae2..1beaec5b9727 100644 --- a/arch/x86/kvm/vmx/main.c +++ b/arch/x86/kvm/vmx/main.c @@ -608,6 +608,17 @@ static void vt_load_mmu_pgd(struct kvm_vcpu *vcpu, hpa= _t root_hpa, vmx_load_mmu_pgd(vcpu, root_hpa, pgd_level); } =20 +static void vt_handle_exit_irqoff(struct kvm_vcpu *vcpu) +{ + if (unlikely((u16)vmx_get_exit_reason(vcpu).basic =3D=3D EXIT_REASON_MCE_= DURING_VMENTRY)) + kvm_machine_check(); + + if (is_td_vcpu(vcpu)) + return; + + return vmx_handle_exit_irqoff(vcpu); +} + static void vt_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask) { if (is_td_vcpu(vcpu)) @@ -969,7 +980,7 @@ struct kvm_x86_ops vt_x86_ops __initdata =3D { .load_mmu_pgd =3D vt_op(load_mmu_pgd), =20 .check_intercept =3D vmx_check_intercept, - .handle_exit_irqoff =3D vmx_handle_exit_irqoff, + .handle_exit_irqoff =3D vt_op(handle_exit_irqoff), =20 .update_cpu_dirty_logging =3D vt_op(update_cpu_dirty_logging), =20 diff --git a/arch/x86/kvm/vmx/tdx.c b/arch/x86/kvm/vmx/tdx.c index 326db9b9c567..a2f6ba3268d1 100644 --- a/arch/x86/kvm/vmx/tdx.c +++ b/arch/x86/kvm/vmx/tdx.c @@ -1069,9 +1069,6 @@ fastpath_t tdx_vcpu_run(struct kvm_vcpu *vcpu, u64 ru= n_flags) if (unlikely((tdx->vp_enter_ret & TDX_SW_ERROR) =3D=3D TDX_SW_ERROR)) return EXIT_FASTPATH_NONE; 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Thu, 30 Oct 2025 15:42:56 -0700 (PDT) Reply-To: Sean Christopherson Date: Thu, 30 Oct 2025 15:42:45 -0700 In-Reply-To: <20251030224246.3456492-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20251030224246.3456492-1-seanjc@google.com> X-Mailer: git-send-email 2.51.1.930.gacf6e81ea2-goog Message-ID: <20251030224246.3456492-4-seanjc@google.com> Subject: [PATCH 3/4] KVM: x86: Load guest/host XCR0 and XSS outside of the fastpath run loop From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Jon Kohler Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Move KVM's swapping of XFEATURE masks, i.e. XCR0 and XSS, out of the fastpath loop now that the guts of the #MC handler runs in task context, i.e. won't invoke schedule() with preemption disabled and clobber state (or crash the kernel) due to trying to context switch XSTATE with a mix of host and guest state. For all intents and purposes, this reverts commit 1811d979c716 ("x86/kvm: move kvm_load/put_guest_xcr0 into atomic context"), which papered over an egregious bug/flaw in the #MC handler where it would do schedule() even though IRQs are disabled. E.g. the call stack from the commit: kvm_load_guest_xcr0 ... kvm_x86_ops->run(vcpu) vmx_vcpu_run vmx_complete_atomic_exit kvm_machine_check do_machine_check do_memory_failure memory_failure lock_page Commit 1811d979c716 "fixed" the immediate issue of XRSTORS exploding, but completely ignored that scheduling out a vCPU task while IRQs and preemption is wildly broken. Thankfully, commit 5567d11c21a1 ("x86/mce: Send #MC singal from task work") (somewhat incidentally?) fixed that flaw by pushing the meat of the work to the user-return path, i.e. to task context. KVM has also hardened itself against #MC goofs by moving #MC forwarding to kvm_x86_ops.handle_exit_irqoff(), i.e. out of the fastpath. While that's by no means a robust fix, restoring as much state as possible before handling the #MC will hopefully provide some measure of protection in the event that #MC handling goes off the rails again. Note, KVM always intercepts XCR0 writes for vCPUs without protected state, e.g. there's no risk of consuming a stale XCR0 when determining if a PKRU update is needed; kvm_load_host_xfeatures() only reads, and never writes, vcpu->arch.xcr0. Deferring the XCR0 and XSS loads shaves ~300 cycles off the fastpath for Intel, and ~500 cycles for AMD. E.g. using INVD in KVM-Unit-Test's vmexit.c, which an extra hack to enable CR4.OXSAVE, latency numbers for AMD Turin go from ~2000 =3D> 1500, and for Intel Emerald Rapids, go from ~1300 =3D> ~1000. Cc: Jon Kohler Signed-off-by: Sean Christopherson Reviewed-By: Jon Kohler Reviewed-by: Rick Edgecombe --- arch/x86/kvm/x86.c | 39 ++++++++++++++++++++++++++------------- 1 file changed, 26 insertions(+), 13 deletions(-) diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index b4b5d2d09634..b5c2879e3330 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -1203,13 +1203,12 @@ void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long = msw) } EXPORT_SYMBOL_FOR_KVM_INTERNAL(kvm_lmsw); =20 -void kvm_load_guest_xsave_state(struct kvm_vcpu *vcpu) +static void kvm_load_guest_xfeatures(struct kvm_vcpu *vcpu) { if (vcpu->arch.guest_state_protected) return; =20 if (kvm_is_cr4_bit_set(vcpu, X86_CR4_OSXSAVE)) { - if (vcpu->arch.xcr0 !=3D kvm_host.xcr0) xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0); =20 @@ -1217,6 +1216,27 @@ void kvm_load_guest_xsave_state(struct kvm_vcpu *vcp= u) vcpu->arch.ia32_xss !=3D kvm_host.xss) wrmsrq(MSR_IA32_XSS, vcpu->arch.ia32_xss); } +} + +static void kvm_load_host_xfeatures(struct kvm_vcpu *vcpu) +{ + if (vcpu->arch.guest_state_protected) + return; + + if (kvm_is_cr4_bit_set(vcpu, X86_CR4_OSXSAVE)) { + if (vcpu->arch.xcr0 !=3D kvm_host.xcr0) + xsetbv(XCR_XFEATURE_ENABLED_MASK, kvm_host.xcr0); + + if (guest_cpu_cap_has(vcpu, X86_FEATURE_XSAVES) && + vcpu->arch.ia32_xss !=3D kvm_host.xss) + wrmsrq(MSR_IA32_XSS, kvm_host.xss); + } +} + +void kvm_load_guest_xsave_state(struct kvm_vcpu *vcpu) +{ + if (vcpu->arch.guest_state_protected) + return; =20 if (cpu_feature_enabled(X86_FEATURE_PKU) && vcpu->arch.pkru !=3D vcpu->arch.host_pkru && @@ -1238,17 +1258,6 @@ void kvm_load_host_xsave_state(struct kvm_vcpu *vcpu) if (vcpu->arch.pkru !=3D vcpu->arch.host_pkru) wrpkru(vcpu->arch.host_pkru); } - - if (kvm_is_cr4_bit_set(vcpu, X86_CR4_OSXSAVE)) { - - if (vcpu->arch.xcr0 !=3D kvm_host.xcr0) - xsetbv(XCR_XFEATURE_ENABLED_MASK, kvm_host.xcr0); - - if (guest_cpu_cap_has(vcpu, X86_FEATURE_XSAVES) && - vcpu->arch.ia32_xss !=3D kvm_host.xss) - wrmsrq(MSR_IA32_XSS, kvm_host.xss); - } - } EXPORT_SYMBOL_FOR_KVM_INTERNAL(kvm_load_host_xsave_state); =20 @@ -11292,6 +11301,8 @@ static int vcpu_enter_guest(struct kvm_vcpu *vcpu) if (vcpu->arch.guest_fpu.xfd_err) wrmsrq(MSR_IA32_XFD_ERR, vcpu->arch.guest_fpu.xfd_err); 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charset="utf-8" Move KVM's swapping of PKRU outside of the fastpath loop, as there is no KVM code anywhere in the fastpath that accesses guest/userspace memory, i.e. that can consume protection keys. As documented by commit 1be0e61c1f25 ("KVM, pkeys: save/restore PKRU when guest/host switches"), KVM just needs to ensure the host's PKRU is loaded when KVM (or the kernel at-large) may access userspace memory. And at the time of commit 1be0e61c1f25, KVM didn't have a fastpath, and PKU was strictly contained to VMX, i.e. there was no reason to swap PKRU outside of vmx_vcpu_run(). Over time, the "need" to swap PKRU close to VM-Enter was likely falsely solidified by the association with XFEATUREs in commit 37486135d3a7 ("KVM: x86: Fix pkru save/restore when guest CR4.PKE=3D0, move it to x86.c"= ), and XFEATURE swapping was in turn moved close to VM-Enter/VM-Exit as a KVM hack-a-fix ution for an #MC handler bug by commit 1811d979c716 ("x86/kvm: move kvm_load/put_guest_xcr0 into atomic context"). Deferring the PKRU loads shaves ~40 cycles off the fastpath for Intel, and ~60 cycles for AMD. E.g. using INVD in KVM-Unit-Test's vmexit.c, with extra hacks to enable CR4.PKE and PKRU=3D(-1u & ~0x3), latency numbers for AMD Turin go from ~1560 =3D> ~1500, and for Intel Emerald Rapids, go from ~810 =3D> ~770. Signed-off-by: Sean Christopherson Reviewed-By: Jon Kohler Reviewed-by: Rick Edgecombe --- arch/x86/kvm/svm/svm.c | 2 -- arch/x86/kvm/vmx/vmx.c | 4 ---- arch/x86/kvm/x86.c | 14 ++++++++++---- arch/x86/kvm/x86.h | 2 -- 4 files changed, 10 insertions(+), 12 deletions(-) diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index e8b158f73c79..e1fb853c263c 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -4260,7 +4260,6 @@ static __no_kcsan fastpath_t svm_vcpu_run(struct kvm_= vcpu *vcpu, u64 run_flags) svm_set_dr6(vcpu, DR6_ACTIVE_LOW); =20 clgi(); - kvm_load_guest_xsave_state(vcpu); =20 /* * Hardware only context switches DEBUGCTL if LBR virtualization is @@ -4303,7 +4302,6 @@ static __no_kcsan fastpath_t svm_vcpu_run(struct kvm_= vcpu *vcpu, u64 run_flags) vcpu->arch.host_debugctl !=3D svm->vmcb->save.dbgctl) update_debugctlmsr(vcpu->arch.host_debugctl); =20 - kvm_load_host_xsave_state(vcpu); stgi(); =20 /* Any pending NMI will happen here */ diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index 123dae8cf46b..55d637cea84a 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -7465,8 +7465,6 @@ fastpath_t vmx_vcpu_run(struct kvm_vcpu *vcpu, u64 ru= n_flags) if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) vmx_set_interrupt_shadow(vcpu, 0); =20 - kvm_load_guest_xsave_state(vcpu); - pt_guest_enter(vmx); =20 atomic_switch_perf_msrs(vmx); @@ -7510,8 +7508,6 @@ fastpath_t vmx_vcpu_run(struct kvm_vcpu *vcpu, u64 ru= n_flags) =20 pt_guest_exit(vmx); =20 - kvm_load_host_xsave_state(vcpu); - if (is_guest_mode(vcpu)) { /* * Track VMLAUNCH/VMRESUME that have made past guest state diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index b5c2879e3330..6924006f0796 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -1233,7 +1233,7 @@ static void kvm_load_host_xfeatures(struct kvm_vcpu *= vcpu) } } =20 -void kvm_load_guest_xsave_state(struct kvm_vcpu *vcpu) +static void kvm_load_guest_pkru(struct kvm_vcpu *vcpu) { if (vcpu->arch.guest_state_protected) return; @@ -1244,9 +1244,8 @@ void kvm_load_guest_xsave_state(struct kvm_vcpu *vcpu) kvm_is_cr4_bit_set(vcpu, X86_CR4_PKE))) wrpkru(vcpu->arch.pkru); } -EXPORT_SYMBOL_FOR_KVM_INTERNAL(kvm_load_guest_xsave_state); =20 -void kvm_load_host_xsave_state(struct kvm_vcpu *vcpu) +static void kvm_load_host_pkru(struct kvm_vcpu *vcpu) { if (vcpu->arch.guest_state_protected) return; @@ -1259,7 +1258,6 @@ void kvm_load_host_xsave_state(struct kvm_vcpu *vcpu) wrpkru(vcpu->arch.host_pkru); } } -EXPORT_SYMBOL_FOR_KVM_INTERNAL(kvm_load_host_xsave_state); =20 #ifdef CONFIG_X86_64 static inline u64 kvm_guest_supported_xfd(struct kvm_vcpu *vcpu) @@ -11331,6 +11329,12 @@ static int vcpu_enter_guest(struct kvm_vcpu *vcpu) =20 guest_timing_enter_irqoff(); =20 + /* + * Swap PKRU with hardware breakpoints disabled to minimize the number + * of flows where non-KVM code can run with guest state loaded. + */ + kvm_load_guest_pkru(vcpu); + for (;;) { /* * Assert that vCPU vs. VM APICv state is consistent. An APICv @@ -11359,6 +11363,8 @@ static int vcpu_enter_guest(struct kvm_vcpu *vcpu) ++vcpu->stat.exits; } =20 + kvm_load_host_pkru(vcpu); + /* * Do this here before restoring debug registers on the host. And * since we do this before handling the vmexit, a DR access vmexit diff --git a/arch/x86/kvm/x86.h b/arch/x86/kvm/x86.h index f3dc77f006f9..24c754b0db2e 100644 --- a/arch/x86/kvm/x86.h +++ b/arch/x86/kvm/x86.h @@ -622,8 +622,6 @@ static inline void kvm_machine_check(void) #endif } =20 -void kvm_load_guest_xsave_state(struct kvm_vcpu *vcpu); -void kvm_load_host_xsave_state(struct kvm_vcpu *vcpu); int kvm_spec_ctrl_test_value(u64 value); int kvm_handle_memory_failure(struct kvm_vcpu *vcpu, int r, struct x86_exception *e); --=20 2.51.1.930.gacf6e81ea2-goog