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[86.162.200.138]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-429952de5f9sm33384041f8f.38.2025.10.30.10.55.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Oct 2025 10:55:32 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: Greg Kroah-Hartman , Jiri Slaby Cc: Biju Das , Wolfram Sang , Lad Prabhakar , Geert Uytterhoeven , linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, Biju Das , linux-renesas-soc@vger.kernel.org Subject: [PATCH v2 07/13] serial: sh-sci: Add RSCI_PORT_{SCI,SCIF} port IDs Date: Thu, 30 Oct 2025 17:55:11 +0000 Message-ID: <20251030175526.607006-8-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251030175526.607006-1-biju.das.jz@bp.renesas.com> References: <20251030175526.607006-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das RZ/G3E RSCI tx/rx supports both FIFO and non-FIFO mode. It has 32-stage FIFO. Add RSCI_PORT_SCI port ID for non-FIFO mode and RSCI_PORT_SCIF port ID for FIFO mode. Update the rx_trigger for both these modes. Signed-off-by: Biju Das --- v1->v2: * No change. --- drivers/tty/serial/sh-sci-common.h | 2 ++ drivers/tty/serial/sh-sci.c | 3 +++ 2 files changed, 5 insertions(+) diff --git a/drivers/tty/serial/sh-sci-common.h b/drivers/tty/serial/sh-sci= -common.h index bcdb41ddc15d..ef1d94ae8b5c 100644 --- a/drivers/tty/serial/sh-sci-common.h +++ b/drivers/tty/serial/sh-sci-common.h @@ -8,6 +8,8 @@ /* Private port IDs */ enum SCI_PORT_TYPE { SCI_PORT_RSCI =3D BIT(7) | 0, + RSCI_PORT_SCI =3D BIT(7) | 1, + RSCI_PORT_SCIF =3D BIT(7) | 2, }; =20 enum SCI_CLKS { diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c index d07424caeeab..6f396e1151d8 100644 --- a/drivers/tty/serial/sh-sci.c +++ b/drivers/tty/serial/sh-sci.c @@ -3149,6 +3149,9 @@ static int sci_init_single(struct platform_device *de= v, case SCI_PORT_RSCI: sci_port->rx_trigger =3D 15; break; + case RSCI_PORT_SCIF: + sci_port->rx_trigger =3D 32; + break; default: sci_port->rx_trigger =3D 1; break; --=20 2.43.0