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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Oct 2025 15:49:05.5799 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6b4c66a5-5bb5-4231-26d9-08de17cbdb43 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB58.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ5PPF0C60B25BF Content-Type: text/plain; charset="utf-8" Introduce a `ConfigSpace` wrapper in Rust PCI abstraction to provide safe accessors for PCI configuration space. The new type implements the `Io` trait to share offset validation and bound-checking logic with others. Signed-off-by: Zhi Wang --- rust/kernel/pci.rs | 62 +++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 61 insertions(+), 1 deletion(-) diff --git a/rust/kernel/pci.rs b/rust/kernel/pci.rs index 9ebba8e08d2e..80bf0d2420f3 100644 --- a/rust/kernel/pci.rs +++ b/rust/kernel/pci.rs @@ -10,7 +10,8 @@ devres::Devres, driver, error::{from_result, to_result, Result}, - io::{Mmio, MmioRaw}, + io::{define_read, define_write}, + io::{Io, Mmio, MmioRaw}, irq::{self, IrqRequest}, str::CStr, sync::aref::ARef, @@ -305,6 +306,60 @@ pub struct Device( PhantomData, ); =20 +/// Represents the PCI configuration space of a device. +/// +/// Provides typed read and write accessors for configuration registers +/// using the standard `pci_read_config_*` and `pci_write_config_*` helper= s. +/// +/// The generic const parameter `SIZE` can be used to indicate the +/// maximum size of the configuration space (e.g. 256 bytes for legacy, +/// 4096 bytes for extended config space). The actual size is obtained +/// from the underlying `struct pci_dev` via [`Device::cfg_size`]. +pub struct ConfigSpace<'a, const SIZE: usize =3D { ConfigSpaceSize::Extend= ed as usize }> { + pdev: &'a Device, +} + +macro_rules! call_config_read { + (fallible, $c_fn:ident, $self:ident, $ty:ty, $addr:expr) =3D> {{ + let mut val: $ty =3D 0; + let ret =3D unsafe { bindings::$c_fn($self.pdev.as_raw(), $addr as= i32, &mut val) }; + (ret =3D=3D 0) + .then_some(Ok(val)) + .unwrap_or_else(|| Err(Error::from_errno(ret))) + }}; +} + +macro_rules! call_config_write { + (fallible, $c_fn:ident, $self:ident, $ty:ty, $addr:expr, $value:expr) = =3D> {{ + let ret =3D unsafe { bindings::$c_fn($self.pdev.as_raw(), $addr as= i32, $value) }; + (ret =3D=3D 0) + .then_some(Ok(())) + .unwrap_or_else(|| Err(Error::from_errno(ret))) + }}; +} + +impl<'a, const SIZE: usize> Io for ConfigSpace<'a, SIZE> { + /// Returns the base address of this mapping. + #[inline] + fn addr(&self) -> usize { + 0 + } + + /// Returns the maximum size of this mapping. + #[inline] + fn maxsize(&self) -> usize { + self.pdev.cfg_size().map_or(0, |v| v as usize) + } + + define_read!(fallible, try_read8, call_config_read, pci_read_config_by= te -> u8); + define_read!(fallible, try_read16, call_config_read, pci_read_config_w= ord -> u16); + define_read!(fallible, try_read32, call_config_read, pci_read_config_d= word -> u32); + + define_write!(fallible, try_write8, call_config_write, pci_write_confi= g_byte <- u8); + define_write!(fallible, try_write16, call_config_write, pci_write_conf= ig_word <- u16); + define_write!(fallible, try_write32, call_config_write, pci_write_conf= ig_dword <- u32); +} + /// A PCI BAR to perform I/O-Operations on. /// /// # Invariants @@ -615,6 +670,11 @@ pub fn set_master(&self) { // SAFETY: `self.as_raw` is guaranteed to be a pointer to a valid = `struct pci_dev`. unsafe { bindings::pci_set_master(self.as_raw()) }; } + + /// Return an initialized config space object. + pub fn config_space<'a>(&'a self) -> Result> { + Ok(ConfigSpace { pdev: self }) + } } =20 // SAFETY: `Device` is a transparent wrapper of a type that doesn't depend= on `Device`'s generic --=20 2.47.3