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[86.162.200.138]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-429952ca569sm31018677f8f.12.2025.10.30.05.05.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Oct 2025 05:05:09 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: Marc Kleine-Budde , Vincent Mailhol , Geert Uytterhoeven , Magnus Damm Cc: Biju Das , Tranh Ha , Duy Nguyen , linux-can@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das , stable@vger.kernel.org Subject: [PATCH] can: rcar_canfd: Fix controller mode setting for RZ/G2L SoCs Date: Thu, 30 Oct 2025 12:05:04 +0000 Message-ID: <20251030120508.420377-1-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable From: Biju Das The commit 5cff263606a1 ("can: rcar_canfd: Fix controller mode setting") applies to all SoCs except the RZ/G2L family of SoCs. As per RZ/G2L hardware manual "Figure 28.16 CAN Setting Procedure after the MCU is Reset" CAN mode needs to be set before channel reset. Add the mode_before_ch_rst variable to struct rcar_canfd_hw_info to handle this difference. The above commit also breaks CANFD functionality on RZ/G3E. Adapt this change to RZ/G3E, as well=C2=A0as it works ok by following the initialisati= on sequence of RZ/G2L. Fixes: 5cff263606a1 ("can: rcar_canfd: Fix controller mode setting") Cc: stable@vger.kernel.org Signed-off-by: Biju Das --- drivers/net/can/rcar/rcar_canfd.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/net/can/rcar/rcar_canfd.c b/drivers/net/can/rcar/rcar_= canfd.c index 49ab65274b51..1724fa5dace6 100644 --- a/drivers/net/can/rcar/rcar_canfd.c +++ b/drivers/net/can/rcar/rcar_canfd.c @@ -444,6 +444,7 @@ struct rcar_canfd_hw_info { unsigned ch_interface_mode:1; /* Has channel interface mode */ unsigned shared_can_regs:1; /* Has shared classical can registers */ unsigned external_clk:1; /* Has external clock */ + unsigned mode_before_ch_rst:1; /* Has set mode before channel reset */ }; =20 /* Channel priv data */ @@ -615,6 +616,7 @@ static const struct rcar_canfd_hw_info rcar_gen3_hw_inf= o =3D { .ch_interface_mode =3D 0, .shared_can_regs =3D 0, .external_clk =3D 1, + .mode_before_ch_rst =3D 0, }; =20 static const struct rcar_canfd_hw_info rcar_gen4_hw_info =3D { @@ -632,6 +634,7 @@ static const struct rcar_canfd_hw_info rcar_gen4_hw_inf= o =3D { .ch_interface_mode =3D 1, .shared_can_regs =3D 1, .external_clk =3D 1, + .mode_before_ch_rst =3D 0, }; =20 static const struct rcar_canfd_hw_info rzg2l_hw_info =3D { @@ -649,6 +652,7 @@ static const struct rcar_canfd_hw_info rzg2l_hw_info = =3D { .ch_interface_mode =3D 0, .shared_can_regs =3D 0, .external_clk =3D 1, + .mode_before_ch_rst =3D 1, }; =20 static const struct rcar_canfd_hw_info r9a09g047_hw_info =3D { @@ -666,6 +670,7 @@ static const struct rcar_canfd_hw_info r9a09g047_hw_inf= o =3D { .ch_interface_mode =3D 1, .shared_can_regs =3D 1, .external_clk =3D 0, + .mode_before_ch_rst =3D 1, }; =20 /* Helper functions */ @@ -806,6 +811,10 @@ static int rcar_canfd_reset_controller(struct rcar_can= fd_global *gpriv) /* Reset Global error flags */ rcar_canfd_write(gpriv->base, RCANFD_GERFL, 0x0); =20 + /* RZ/G2L SoC needs setting the mode before channel reset */ + if (gpriv->info->mode_before_ch_rst) + rcar_canfd_set_mode(gpriv); + /* Transition all Channels to reset mode */ for_each_set_bit(ch, &gpriv->channels_mask, gpriv->info->max_channels) { rcar_canfd_clear_bit(gpriv->base, @@ -826,7 +835,8 @@ static int rcar_canfd_reset_controller(struct rcar_canf= d_global *gpriv) } =20 /* Set the controller into appropriate mode */ - rcar_canfd_set_mode(gpriv); + if (!gpriv->info->mode_before_ch_rst) + rcar_canfd_set_mode(gpriv); =20 return 0; } --=20 2.43.0