From nobody Mon Feb 9 06:33:02 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7E53218DB26; Thu, 30 Oct 2025 10:23:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761819828; cv=none; b=li8leEfjTmwxTdiz5xblbQ13qVEytpfBaHbAiehYyPJNAi/ZQeBgNYP47Ds5ewkugKzmbkxyuTbDINIp/nxuJlpqeeM/G9zwhyy+MuYkF4kdVqWIwpXSidbIBEsNDs6hzHgN9uMNQZ7cn24nNCAEUOqrlnHJrUK2GFwCErdbg4c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761819828; c=relaxed/simple; bh=3V2aV4nPB0UyjK6VToKg9MDzdV9a8nUWRDj7DNXyej0=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=WErZCcLAPH/hWZ8WjBfb7AMqfLPAwjfa/gtqhFockEUCEUa2h7oJjNdqAX8m9PBREYSXx15qvZ5akj39QnV/+hZsmixUPUVjsUPAk4bZ9cg7dDMpEUzZlIVCejWp9u40PtXfoRCltxamOLCZkYBbG8ep6wS8EIJ2g3TuiqY2klA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=2H0TaDZW; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="2H0TaDZW" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1761819826; x=1793355826; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=3V2aV4nPB0UyjK6VToKg9MDzdV9a8nUWRDj7DNXyej0=; b=2H0TaDZW1d9T9IEm14nwL5WohmwO7GrtoCgWnU6VDQ6E1QcPDAo/lfvb vv3osVPHUHUgxkMsGYXtw9/o9AcTYr1Sp2w2vtO+loTBNEZeUFzMyBFlV DhrkJrbRvIiddTWJw6OtqOJA1GSTM0/kfBxCXK+eDrkOVKAuibQBArVRS qFZmSjtjNzGJN/iiHzwHAEsCeMr++Edf/nLlbBwfPneiLfvIZ6co4+2A8 fX6Ch4W3UbLp7EpfpEF/XizUdlBz4epbM4tQCnLfTbC8HEmxSWzKxRfSp xMB08h6oAYOBOGcTyMoT8lUJ8gcAxY1Tty+d/FYhKMfvsy3c4YAkYCoBZ w==; X-CSE-ConnectionGUID: HzbPEBY6R+miNabt6yV/EA== X-CSE-MsgGUID: ENrRBZ2kSBq4dDskuqF/gw== X-IronPort-AV: E=Sophos;i="6.19,266,1754982000"; d="scan'208";a="215806960" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Oct 2025 03:23:40 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.87.71) by chn-vm-ex4.mchp-main.com (10.10.87.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.2.2562.29; Thu, 30 Oct 2025 03:23:09 -0700 Received: from che-ll-i17164.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Thu, 30 Oct 2025 03:23:05 -0700 From: Parthiban Veerasooran To: , , , , , , , CC: , , "Parthiban Veerasooran" Subject: [PATCH net-next 1/2] net: phy: microchip_t1s: add support for Microchip LAN867X Rev.D0 PHY Date: Thu, 30 Oct 2025 15:52:57 +0530 Message-ID: <20251030102258.180061-2-parthiban.veerasooran@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251030102258.180061-1-parthiban.veerasooran@microchip.com> References: <20251030102258.180061-1-parthiban.veerasooran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Add support for the LAN8670/1/2 Rev.D0 10BASE-T1S PHYs from Microchip. The new Rev.D0 silicon requires a specific set of initialization settings to be configured for optimal performance and compliance with OPEN Alliance specifications, as described in Microchip Application Note AN1699 (Revision G, DS60001699G =E2=80=93 October 2025). https://www.microchip.com/en-us/application-notes/an1699 Signed-off-by: Parthiban Veerasooran Reviewed-by: Andrew Lunn --- drivers/net/phy/Kconfig | 2 +- drivers/net/phy/microchip_t1s.c | 47 ++++++++++++++++++++++++++++++++- 2 files changed, 47 insertions(+), 2 deletions(-) diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index 98700d069191..a7ade7b95a2e 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -308,7 +308,7 @@ config MICREL_PHY config MICROCHIP_T1S_PHY tristate "Microchip 10BASE-T1S Ethernet PHYs" help - Currently supports the LAN8670/1/2 Rev.B1/C1/C2 and + Currently supports the LAN8670/1/2 Rev.B1/C1/C2/D0 and LAN8650/1 Rev.B0/B1 Internal PHYs. =20 config MICROCHIP_PHY diff --git a/drivers/net/phy/microchip_t1s.c b/drivers/net/phy/microchip_t1= s.c index e50a0c102a86..03e3bacb02bd 100644 --- a/drivers/net/phy/microchip_t1s.c +++ b/drivers/net/phy/microchip_t1s.c @@ -3,7 +3,7 @@ * Driver for Microchip 10BASE-T1S PHYs * * Support: Microchip Phys: - * lan8670/1/2 Rev.B1/C1/C2 + * lan8670/1/2 Rev.B1/C1/C2/D0 * lan8650/1 Rev.B0/B1 Internal PHYs */ =20 @@ -14,6 +14,7 @@ #define PHY_ID_LAN867X_REVB1 0x0007C162 #define PHY_ID_LAN867X_REVC1 0x0007C164 #define PHY_ID_LAN867X_REVC2 0x0007C165 +#define PHY_ID_LAN867X_REVD0 0x0007C166 /* Both Rev.B0 and B1 clause 22 PHYID's are same due to B1 chip limitation= */ #define PHY_ID_LAN865X_REVB 0x0007C1B3 =20 @@ -109,6 +110,21 @@ static const u16 lan865x_revb_sqi_fixup_cfg_regs[3] = =3D { 0x00AD, 0x00AE, 0x00AF, }; =20 +/* LAN867x Rev.D0 configuration parameters from AN1699 + * As per the Configuration Application Note AN1699 published in the below= link, + * https://www.microchip.com/en-us/application-notes/an1699 + * Revision G (DS60001699G - October 2025) + */ +static const u16 lan867x_revd0_fixup_regs[8] =3D { + 0x0037, 0x008A, 0x0118, 0x00D6, + 0x0082, 0x00FD, 0x00FD, 0x0091, +}; + +static const u16 lan867x_revd0_fixup_values[8] =3D { + 0x0800, 0xBFC0, 0x029C, 0x1001, + 0x001C, 0x0C0B, 0x8C07, 0x9660, +}; + /* Pulled from AN1760 describing 'indirect read' * * write_register(0x4, 0x00D8, addr) @@ -407,6 +423,25 @@ static int lan86xx_plca_set_cfg(struct phy_device *phy= dev, COL_DET_CTRL0_ENABLE_BIT_MASK, COL_DET_ENABLE); } =20 +static int lan867x_revd0_config_init(struct phy_device *phydev) +{ + int ret; + + ret =3D lan867x_check_reset_complete(phydev); + if (ret) + return ret; + + for (int i =3D 0; i < ARRAY_SIZE(lan867x_revd0_fixup_regs); i++) { + ret =3D phy_write_mmd(phydev, MDIO_MMD_VEND2, + lan867x_revd0_fixup_regs[i], + lan867x_revd0_fixup_values[i]); + if (ret) + return ret; + } + + return 0; +} + static int lan86xx_read_status(struct phy_device *phydev) { /* The phy has some limitations, namely: @@ -481,6 +516,15 @@ static struct phy_driver microchip_t1s_driver[] =3D { .set_plca_cfg =3D lan86xx_plca_set_cfg, .get_plca_status =3D genphy_c45_plca_get_status, }, + { + PHY_ID_MATCH_EXACT(PHY_ID_LAN867X_REVD0), + .name =3D "LAN867X Rev.D0", + .features =3D PHY_BASIC_T1S_P2MP_FEATURES, + .config_init =3D lan867x_revd0_config_init, + .get_plca_cfg =3D genphy_c45_plca_get_cfg, + .set_plca_cfg =3D lan86xx_plca_set_cfg, + .get_plca_status =3D genphy_c45_plca_get_status, + }, { PHY_ID_MATCH_EXACT(PHY_ID_LAN865X_REVB), .name =3D "LAN865X Rev.B0/B1 Internal Phy", @@ -501,6 +545,7 @@ static const struct mdio_device_id __maybe_unused tbl[]= =3D { { PHY_ID_MATCH_EXACT(PHY_ID_LAN867X_REVB1) }, { PHY_ID_MATCH_EXACT(PHY_ID_LAN867X_REVC1) }, { PHY_ID_MATCH_EXACT(PHY_ID_LAN867X_REVC2) }, + { PHY_ID_MATCH_EXACT(PHY_ID_LAN867X_REVD0) }, { PHY_ID_MATCH_EXACT(PHY_ID_LAN865X_REVB) }, { } }; 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charset="utf-8" Configure the link status in the Link Status Control register for LAN8670/1/2 Rev.D0 PHYs, depending on whether PLCA or CSMA/CD mode is enabled. When PLCA is enabled, the link status reflects the PLCA status. When PLCA is disabled (CSMA/CD mode), the PHY does not support autonegotiation, so the link status is forced active by setting the LINK_STATUS_SEMAPHORE bit. The link status control is configured: - During PHY initialization, for default CSMA/CD mode. - Whenever PLCA configuration is updated. This ensures correct link reporting and consistent behavior for LAN867x Rev.D0 devices. Signed-off-by: Parthiban Veerasooran Reviewed-by: Andrew Lunn --- drivers/net/phy/microchip_t1s.c | 51 ++++++++++++++++++++++++++++++++- 1 file changed, 50 insertions(+), 1 deletion(-) diff --git a/drivers/net/phy/microchip_t1s.c b/drivers/net/phy/microchip_t1= s.c index 03e3bacb02bd..bce5cf087b19 100644 --- a/drivers/net/phy/microchip_t1s.c +++ b/drivers/net/phy/microchip_t1s.c @@ -33,6 +33,17 @@ #define COL_DET_ENABLE BIT(15) #define COL_DET_DISABLE 0x0000 =20 +/* LAN8670/1/2 Rev.D0 Link Status Selection Register */ +#define LAN867X_REG_LINK_STATUS_CTRL 0x0012 +#define LINK_STATUS_CONFIGURATION GENMASK(12, 11) +#define LINK_STATUS_SEMAPHORE BIT(0) + +/* Link Status Configuration */ +#define LINK_STATUS_CONFIG_PLCA_STATUS 0x1 +#define LINK_STATUS_CONFIG_SEMAPHORE 0x2 + +#define LINK_STATUS_SEMAPHORE_SET 0x1 + #define LAN865X_CFGPARAM_READ_ENABLE BIT(1) =20 /* The arrays below are pulled from the following table from AN1699 @@ -393,6 +404,32 @@ static int lan867x_revb1_config_init(struct phy_device= *phydev) return 0; } =20 +static int lan867x_revd0_link_active_selection(struct phy_device *phydev, + bool plca_enabled) +{ + u16 value; + + if (plca_enabled) { + /* 0x1 - When PLCA is enabled: link status reflects plca_status. + */ + value =3D FIELD_PREP(LINK_STATUS_CONFIGURATION, + LINK_STATUS_CONFIG_PLCA_STATUS); + } else { + /* 0x2 - Link status is controlled by the value written into the + * LINK_STATUS_SEMAPHORE bit written. Here the link semaphore + * bit is written with 0x1 to set the link always active in + * CSMA/CD mode as it doesn't support autoneg. + */ + value =3D FIELD_PREP(LINK_STATUS_CONFIGURATION, + LINK_STATUS_CONFIG_SEMAPHORE) | + FIELD_PREP(LINK_STATUS_SEMAPHORE, + LINK_STATUS_SEMAPHORE_SET); + } + + return phy_write_mmd(phydev, MDIO_MMD_VEND2, + LAN867X_REG_LINK_STATUS_CTRL, value); +} + /* As per LAN8650/1 Rev.B0/B1 AN1760 (Revision F (DS60001760G - June 2024)= ) and * LAN8670/1/2 Rev.C1/C2 AN1699 (Revision E (DS60001699F - June 2024)), un= der * normal operation, the device should be operated in PLCA mode. Disabling @@ -409,6 +446,14 @@ static int lan86xx_plca_set_cfg(struct phy_device *phy= dev, { int ret; =20 + /* Link status selection must be configured for LAN8670/1/2 Rev.D0 */ + if (phydev->phy_id =3D=3D PHY_ID_LAN867X_REVD0) { + ret =3D lan867x_revd0_link_active_selection(phydev, + plca_cfg->enabled); + if (ret) + return ret; + } + ret =3D genphy_c45_plca_set_cfg(phydev, plca_cfg); if (ret) return ret; @@ -439,7 +484,11 @@ static int lan867x_revd0_config_init(struct phy_device= *phydev) return ret; } =20 - return 0; + /* Initially the PHY will be in CSMA/CD mode by default. So it is + * required to set the link always active as it doesn't support + * autoneg. + */ + return lan867x_revd0_link_active_selection(phydev, false); } =20 static int lan86xx_read_status(struct phy_device *phydev) --=20 2.34.1