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charset="utf-8" This update enables PCIe5 support by adding necessary sideband signals (PERST#, WAKE#, CLKREQ#) and required regulators to the PCIe3 controller and PHY device tree nodes. These changes ensure correct link initialization and power sequencing for devices connected via PCIe5. Signed-off-by: Ziyue Zhang Reviewed-by: Krishna Chaitanya Chundru --- arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi | 40 +++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi b/arch/arm64/boot/= dts/qcom/hamoa-iot-som.dtsi index 4de7c0abb25a..8ea5d0cebe6e 100644 --- a/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi +++ b/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi @@ -407,6 +407,23 @@ &pcie4_phy { status =3D "okay"; }; =20 +&pcie5 { + perst-gpios =3D <&tlmm 149 GPIO_ACTIVE_LOW>; + wake-gpios =3D <&tlmm 151 GPIO_ACTIVE_LOW>; + + pinctrl-0 =3D <&pcie5_default>; + pinctrl-names =3D "default"; + + status =3D "okay"; +}; + +&pcie5_phy { + vdda-phy-supply =3D <&vreg_l3i_0p8>; + vdda-pll-supply =3D <&vreg_l3e_1p2>; + + status =3D "okay"; +}; + &pcie6a { perst-gpios =3D <&tlmm 152 GPIO_ACTIVE_LOW>; wake-gpios =3D <&tlmm 154 GPIO_ACTIVE_LOW>; @@ -477,6 +494,29 @@ wake-n-pins { }; }; =20 + pcie5_default: pcie5-default-state { + clkreq-n-pins { + pins =3D "gpio150"; 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charset="utf-8" Specify the vddpe-3v3-supply regulator for PCIe5 using &vreg_wwan to ensure proper power configuration. Signed-off-by: Ziyue Zhang Reviewed-by: Krishna Chaitanya Chundru --- arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts b/arch/arm64/boot/d= ts/qcom/hamoa-iot-evk.dts index 36dd6599402b..24c2dcef0ba8 100644 --- a/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts +++ b/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts @@ -844,6 +844,10 @@ &mdss_dp3_phy { status =3D "okay"; }; =20 +&pcie5 { + vddpe-3v3-supply =3D <&vreg_wwan>; +}; + &pcie6a { vddpe-3v3-supply =3D <&vreg_nvme>; }; --=20 2.34.1 From nobody Mon Feb 9 05:43:12 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7EF763396F4; Thu, 30 Oct 2025 08:48:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; 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charset="utf-8" This update enables PCIe3 support by adding necessary sideband signals (PERST#, WAKE#, CLKREQ#) and required regulators to the PCIe3 controller and PHY device tree nodes. These changes ensure correct link initialization and power sequencing for devices connected via PCIe3. Signed-off-by: Ziyue Zhang --- arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi | 39 +++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi b/arch/arm64/boot/= dts/qcom/hamoa-iot-som.dtsi index 8ea5d0cebe6e..14033d030425 100644 --- a/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi +++ b/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi @@ -390,6 +390,22 @@ &gpu_zap_shader { firmware-name =3D "qcom/x1e80100/gen70500_zap.mbn"; }; =20 +&pcie3 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pcie3_default>; + perst-gpios =3D <&tlmm 143 GPIO_ACTIVE_LOW>; + wake-gpios =3D <&tlmm 145 GPIO_ACTIVE_LOW>; + + status =3D "okay"; +}; + +&pcie3_phy { + vdda-phy-supply =3D <&vreg_l3c_0p8>; + vdda-pll-supply =3D <&vreg_l3e_1p2>; + + status =3D "okay"; +}; + &pcie4 { perst-gpios =3D <&tlmm 146 GPIO_ACTIVE_LOW>; wake-gpios =3D <&tlmm 148 GPIO_ACTIVE_LOW>; @@ -471,6 +487,29 @@ &tlmm { gpio-reserved-ranges =3D <34 2>, /* TPM LP & INT */ <44 4>; /* SPI (TPM) */ =20 + pcie3_default: pcie3-default-state { + clkreq-n-pins { + pins =3D "gpio144"; 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charset="utf-8" HAMOA-IOT-EVK board includes a PCIe3 controller and x8 slot that require proper power rail and control signal configuration. This update adds `vddpe-3v3-supply` and `regulator-pcie-12v` to provide 3.3V to the PHY and 12V to the slot for external devices. It also introduces PM GPIOs to manage power enable and reset signals, ensuring stable power sequencing and reliable PCIe3 operation. Signed-off-by: Ziyue Zhang --- arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts | 79 ++++++++++++++++++++++ 1 file changed, 79 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts b/arch/arm64/boot/d= ts/qcom/hamoa-iot-evk.dts index 24c2dcef0ba8..0984a6eed226 100644 --- a/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts +++ b/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts @@ -414,6 +414,48 @@ vreg_wwan: regulator-wwan { regulator-boot-on; }; =20 + vreg_pcie_12v: regulator-pcie-12v { + compatible =3D "regulator-fixed"; + + regulator-name =3D "VREG_PCIE_12V"; + regulator-min-microvolt =3D <12000000>; + regulator-max-microvolt =3D <12000000>; + + gpio =3D <&pm8550ve_8_gpios 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 =3D <&pcie_x8_12v>; + pinctrl-names =3D "default"; + }; + + vreg_pcie_3v3_aux: regulator-pcie-3v3-aux { + compatible =3D "regulator-fixed"; + + regulator-name =3D "VREG_PCIE_3P3_AUX"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + + gpio =3D <&pmc8380_3_gpios 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 =3D <&pm_sde7_aux_3p3_en>; + pinctrl-names =3D "default"; + }; + + vreg_pcie_3v3: regulator-pcie-3v3 { + compatible =3D "regulator-fixed"; + + regulator-name =3D "VREG_PCIE_3P3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + + gpio =3D <&pmc8380_3_gpios 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 =3D <&pm_sde7_main_3p3_en>; + pinctrl-names =3D "default"; +}; + sound { compatible =3D "qcom,x1e80100-sndcard"; model =3D "X1E80100-EVK"; @@ -844,6 +886,12 @@ &mdss_dp3_phy { status =3D "okay"; }; =20 +&pcie3_port { + vpcie12v-supply =3D <&vreg_pcie_12v>; + vpcie3v3-supply =3D <&vreg_pcie_3v3>; + vpcie3v3aux-supply =3D <&vreg_pcie_3v3_aux>; +}; + &pcie5 { vddpe-3v3-supply =3D <&vreg_wwan>; }; @@ -872,6 +920,17 @@ usb0_3p3_reg_en: usb0-3p3-reg-en-state { }; }; =20 +&pm8550ve_8_gpios { + pcie_x8_12v: pcie-12v-default-state { + pins =3D "gpio8"; + function =3D "normal"; + output-enable; + output-high; + bias-pull-down; + power-source =3D <0>; + }; +}; + &pm8550ve_9_gpios { usb0_1p8_reg_en: usb0-1p8-reg-en-state { pins =3D "gpio8"; @@ -883,6 +942,26 @@ usb0_1p8_reg_en: usb0-1p8-reg-en-state { }; }; =20 +&pmc8380_3_gpios { + pm_sde7_aux_3p3_en: pcie-aux-3p3-default-state { + pins =3D "gpio8"; + function =3D "normal"; + output-enable; + output-high; + bias-pull-down; + power-source =3D <0>; + }; + + pm_sde7_main_3p3_en: pcie-main-3p3-default-state { + pins =3D "gpio6"; + function =3D "normal"; + output-enable; + output-high; + bias-pull-down; + power-source =3D <0>; + }; +}; + &pmc8380_5_gpios { usb0_pwr_1p15_reg_en: usb0-pwr-1p15-reg-en-state { pins =3D "gpio8"; --=20 2.34.1