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[176.247.57.96]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b6d85398439sm1682670866b.36.2025.10.30.00.27.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Oct 2025 00:27:57 -0700 (PDT) From: Francesco Lavra To: Lorenzo Bianconi , Jonathan Cameron , David Lechner , =?UTF-8?q?Nuno=20S=C3=A1?= , Andy Shevchenko , linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 3/9] iio: imu: st_lsm6dsx: move wakeup event enable mask to event_src Date: Thu, 30 Oct 2025 08:27:46 +0100 Message-Id: <20251030072752.349633-4-flavra@baylibre.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20251030072752.349633-1-flavra@baylibre.com> References: <20251030072752.349633-1-flavra@baylibre.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=7477; i=flavra@baylibre.com; h=from:subject; bh=5udrDdlPMpudCr1yZSepm0qaGnwL+JdHE+fbHDma8IU=; b=owEB7QES/pANAwAKAe3xO3POlDZfAcsmYgBpAxNJUqwdeZd2hE7bzBsdS7ZsaGVJIXj6S1gwW zjdQ38hhwaJAbMEAAEKAB0WIQSGV4VPlTvcox7DFObt8TtzzpQ2XwUCaQMTSQAKCRDt8TtzzpQ2 X4seC/0YTo0aLdkslaQoGRrOIQuzRI+uwzb2ayKLfNeD6SWwEZtlcTvAVmMwFsk4TYnU6DrKrcF yrPe/XiYDq+NYjgM43qBOxdUoIrdyd6lRmc7kpw3YuVdbi0MlFYtn1nb+eF8q4c8EKIxaywxi+d kE/349O5UhcRji18ZQvhdChVDR2DoqXKhHMek2ro7JxGxu5azF9Pk+Fnq6Gqtw/IGB+4R9lNj3F /PI88/j9Gl80stNv8Z2fKavy5ISg36zevNUAgEQU+j8+0EfscDUnNHKtx5PKfuSmbavb9lGfize 8kOTPAH92QSLdI2yLUJri+VdQ2Hd8TRUJfpuSqGZotZWrBLWPLoVUMnwbURcjaXtC7hS8VC9vyS zVyWSvl84WgtAIhFbgt+/zVezCWEN3LWLZDoBULPWqpMMfelgmkeSg+dEdCDYXXKSpLy65OjF9r qG10M91YleUlgyNRJzL2M2qVBtO8syciMVNF5v2CgRYBOG2eQqMucAGdWjLFTqZPKxha4= X-Developer-Key: i=flavra@baylibre.com; a=openpgp; fpr=8657854F953BDCA31EC314E6EDF13B73CE94365F Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The mask value being assigned to the irq1_func and irq2_func fields of the irq_config struct is specific to a single event source (i.e. the wakeup event), and as such it should be separate from the definition of the interrupt function registers, which cover multiple event sources. In preparation for adding support for more event types, change the irq1_func and irq2_func type from an {address, mask} pair to an address, and move the mask value to a new field of struct st_lsm6dsx_event_src. No functional changes. Signed-off-by: Francesco Lavra --- drivers/iio/imu/st_lsm6dsx/st_lsm6dsx.h | 7 +- drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c | 80 +++++++------------- 2 files changed, 30 insertions(+), 57 deletions(-) diff --git a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx.h b/drivers/iio/imu/st_l= sm6dsx/st_lsm6dsx.h index 05689887f7ec..5c73156b714a 100644 --- a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx.h +++ b/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx.h @@ -228,6 +228,7 @@ enum st_lsm6dsx_event_id { =20 struct st_lsm6dsx_event_src { struct st_lsm6dsx_reg value; + u8 enable_mask; u8 status_reg; u8 status_mask; u8 status_x_mask; @@ -320,8 +321,8 @@ struct st_lsm6dsx_settings { struct { struct st_lsm6dsx_reg irq1; struct st_lsm6dsx_reg irq2; - struct st_lsm6dsx_reg irq1_func; - struct st_lsm6dsx_reg irq2_func; + u8 irq1_func; + u8 irq2_func; struct st_lsm6dsx_reg lir; struct st_lsm6dsx_reg clear_on_read; struct st_lsm6dsx_reg hla; @@ -420,7 +421,7 @@ struct st_lsm6dsx_hw { u8 ts_sip; u8 sip; =20 - const struct st_lsm6dsx_reg *irq_routing; + u8 irq_routing; u8 event_threshold; u8 enable_event; =20 diff --git a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c b/drivers/iio/imu= /st_lsm6dsx/st_lsm6dsx_core.c index bb4c4c531128..4bae5da8910e 100644 --- a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c +++ b/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c @@ -290,14 +290,8 @@ static const struct st_lsm6dsx_settings st_lsm6dsx_sen= sor_settings[] =3D { .addr =3D 0x58, .mask =3D BIT(0), }, - .irq1_func =3D { - .addr =3D 0x5e, - .mask =3D BIT(5), - }, - .irq2_func =3D { - .addr =3D 0x5f, - .mask =3D BIT(5), - }, + .irq1_func =3D 0x5e, + .irq2_func =3D 0x5f, .hla =3D { .addr =3D 0x12, .mask =3D BIT(5), @@ -356,6 +350,7 @@ static const struct st_lsm6dsx_settings st_lsm6dsx_sens= or_settings[] =3D { .addr =3D 0x5b, .mask =3D GENMASK(5, 0), }, + .enable_mask =3D BIT(5), .status_reg =3D 0x1b, .status_mask =3D BIT(3), .status_z_mask =3D BIT(0), @@ -454,14 +449,8 @@ static const struct st_lsm6dsx_settings st_lsm6dsx_sen= sor_settings[] =3D { .addr =3D 0x58, .mask =3D BIT(0), }, - .irq1_func =3D { - .addr =3D 0x5e, - .mask =3D BIT(5), - }, - .irq2_func =3D { - .addr =3D 0x5f, - .mask =3D BIT(5), - }, + .irq1_func =3D 0x5e, + .irq2_func =3D 0x5f, .hla =3D { .addr =3D 0x12, .mask =3D BIT(5), @@ -520,6 +509,7 @@ static const struct st_lsm6dsx_settings st_lsm6dsx_sens= or_settings[] =3D { .addr =3D 0x5b, .mask =3D GENMASK(5, 0), }, + .enable_mask =3D BIT(5), .status_reg =3D 0x1b, .status_mask =3D BIT(3), .status_z_mask =3D BIT(0), @@ -648,14 +638,8 @@ static const struct st_lsm6dsx_settings st_lsm6dsx_sen= sor_settings[] =3D { .addr =3D 0x58, .mask =3D BIT(0), }, - .irq1_func =3D { - .addr =3D 0x5e, - .mask =3D BIT(5), - }, - .irq2_func =3D { - .addr =3D 0x5f, - .mask =3D BIT(5), - }, + .irq1_func =3D 0x5e, + .irq2_func =3D 0x5f, .hla =3D { .addr =3D 0x12, .mask =3D BIT(5), @@ -755,6 +739,7 @@ static const struct st_lsm6dsx_settings st_lsm6dsx_sens= or_settings[] =3D { .addr =3D 0x5b, .mask =3D GENMASK(5, 0), }, + .enable_mask =3D BIT(5), .status_reg =3D 0x1b, .status_mask =3D BIT(3), .status_z_mask =3D BIT(0), @@ -895,14 +880,8 @@ static const struct st_lsm6dsx_settings st_lsm6dsx_sen= sor_settings[] =3D { .addr =3D 0x56, .mask =3D BIT(6), }, - .irq1_func =3D { - .addr =3D 0x5e, - .mask =3D BIT(5), - }, - .irq2_func =3D { - .addr =3D 0x5f, - .mask =3D BIT(5), - }, + .irq1_func =3D 0x5e, + .irq2_func =3D 0x5f, .hla =3D { .addr =3D 0x12, .mask =3D BIT(5), @@ -990,6 +969,7 @@ static const struct st_lsm6dsx_settings st_lsm6dsx_sens= or_settings[] =3D { .addr =3D 0x5b, .mask =3D GENMASK(5, 0), }, + .enable_mask =3D BIT(5), .status_reg =3D 0x1b, .status_mask =3D BIT(3), .status_z_mask =3D BIT(0), @@ -1106,14 +1086,8 @@ static const struct st_lsm6dsx_settings st_lsm6dsx_s= ensor_settings[] =3D { .addr =3D 0x56, .mask =3D BIT(6), }, - .irq1_func =3D { - .addr =3D 0x5e, - .mask =3D BIT(5), - }, - .irq2_func =3D { - .addr =3D 0x5f, - .mask =3D BIT(5), - }, + .irq1_func =3D 0x5e, + .irq2_func =3D 0x5f, .hla =3D { .addr =3D 0x12, .mask =3D BIT(5), @@ -1169,6 +1143,7 @@ static const struct st_lsm6dsx_settings st_lsm6dsx_se= nsor_settings[] =3D { .addr =3D 0x5b, .mask =3D GENMASK(5, 0), }, + .enable_mask =3D BIT(5), .status_reg =3D 0x1b, .status_mask =3D BIT(3), .status_z_mask =3D BIT(0), @@ -1279,14 +1254,8 @@ static const struct st_lsm6dsx_settings st_lsm6dsx_s= ensor_settings[] =3D { .addr =3D 0x56, .mask =3D BIT(0), }, - .irq1_func =3D { - .addr =3D 0x5e, - .mask =3D BIT(5), - }, - .irq2_func =3D { - .addr =3D 0x5f, - .mask =3D BIT(5), - }, + .irq1_func =3D 0x5e, + .irq2_func =3D 0x5f, .hla =3D { .addr =3D 0x03, .mask =3D BIT(4), @@ -1373,6 +1342,7 @@ static const struct st_lsm6dsx_settings st_lsm6dsx_se= nsor_settings[] =3D { .addr =3D 0x5b, .mask =3D GENMASK(5, 0), }, + .enable_mask =3D BIT(5), .status_reg =3D 0x45, .status_mask =3D BIT(3), .status_z_mask =3D BIT(0), @@ -1825,10 +1795,11 @@ static int st_lsm6dsx_write_raw(struct iio_dev *iio= _dev, static int st_lsm6dsx_event_setup(struct st_lsm6dsx_hw *hw, bool state) { const struct st_lsm6dsx_reg *reg; + u8 enable_mask; unsigned int data; int err; =20 - if (!hw->settings->irq_config.irq1_func.addr) + if (!hw->irq_routing) return -ENOTSUPP; =20 reg =3D &hw->settings->event_settings.enable_reg; @@ -1841,9 +1812,10 @@ static int st_lsm6dsx_event_setup(struct st_lsm6dsx_= hw *hw, bool state) } =20 /* Enable wakeup interrupt */ - data =3D ST_LSM6DSX_SHIFT_VAL(state, hw->irq_routing->mask); - return st_lsm6dsx_update_bits_locked(hw, hw->irq_routing->addr, - hw->irq_routing->mask, data); + enable_mask =3D hw->settings->event_settings.sources[ST_LSM6DSX_EVENT_WAK= EUP].enable_mask; + data =3D ST_LSM6DSX_SHIFT_VAL(state, enable_mask); + return st_lsm6dsx_update_bits_locked(hw, hw->irq_routing, + enable_mask, data); } =20 static int st_lsm6dsx_read_event(struct iio_dev *iio_dev, @@ -2097,11 +2069,11 @@ st_lsm6dsx_get_drdy_reg(struct st_lsm6dsx_hw *hw, =20 switch (drdy_pin) { case 1: - hw->irq_routing =3D &hw->settings->irq_config.irq1_func; + hw->irq_routing =3D hw->settings->irq_config.irq1_func; *drdy_reg =3D &hw->settings->irq_config.irq1; break; case 2: - hw->irq_routing =3D &hw->settings->irq_config.irq2_func; + hw->irq_routing =3D hw->settings->irq_config.irq2_func; *drdy_reg =3D &hw->settings->irq_config.irq2; break; default: --=20 2.39.5