From nobody Sun Dec 14 05:53:24 2025 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B18D53148DB; Thu, 30 Oct 2025 06:02:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761804127; cv=none; b=iZTN5RmHMi5QEJI8mujLL5pSTfyqj8MjQL8sLxm6P8m0YGg0ngYqLzGVz2PDqx4Opjxn1gq/T/A/ELx/wy5ecwZPY8Fvcij9Wx8V4alHeQw2N2JGu0B24nfAfC6vYsguOUTUS4f9EOiGMgY23+Gsepbs4kyt+SQQgjT0cLLpxUk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761804127; c=relaxed/simple; bh=qPIsxmkLKEGcwd+vT7xjUk/aYe0vjQsnPgFlfMj9/MM=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=M/Jmorn/XWzx49Kr8kEP6mfiNouEikG7xHJp7fVWsMyUK/gb1aTKW1S1ioq0s8y1mmm/wUK6NDQZPiP2biNNlvwW0AUPamVxE8emuxI+8uI6yM9GaGp+wc5q4hXchCOqla09ZAQxn+4ru63AfICNk8JPilMEbhSAQoF7zNxX9Pg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Thu, 30 Oct 2025 14:01:55 +0800 Received: from twmbx02.aspeed.com (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Thu, 30 Oct 2025 14:01:55 +0800 From: Ryan Chen To: ryan_chen , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery , , Kevin Chen , , , , Subject: [PATCH v6 1/1] dt-bindings: interrupt-controller: aspeed,ast2700: correct #interrupt-cells and interrupts count Date: Thu, 30 Oct 2025 14:01:55 +0800 Message-ID: <20251030060155.2342604-2-ryan_chen@aspeedtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251030060155.2342604-1-ryan_chen@aspeedtech.com> References: <20251030060155.2342604-1-ryan_chen@aspeedtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Update the AST2700 interrupt controller binding to match the actual hardware and the irq-aspeed-intc driver behavior. - Interrupts: First-level INTC banks request multiple interrupt lines to the root GIC, with a maximum of 10 per bank. Second-level INTC banks request only one interrupt line to their parent INTC-IC. Therefore, set the interrupts property to allow a minimum of 1 and a maximum of 10 entries. - #interrupt-cells: Set '#interrupt-cells' to <1> since the irq-aspeed-intc.c driver does not support specifying a trigger type; only the interrupt index is used. Signed-off-by: Ryan Chen Acked-by: Krzysztof Kozlowski --- .../interrupt-controller/aspeed,ast2700-intc.yaml | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/aspeed,= ast2700-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/= aspeed,ast2700-intc.yaml index 55636d06a674..999df5b905c5 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700= -intc.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700= -intc.yaml @@ -25,13 +25,14 @@ properties: interrupt-controller: true =20 '#interrupt-cells': - const: 2 + const: 1 description: The first cell is the IRQ number, the second cell is the trigger type as defined in interrupt.txt in this directory. =20 interrupts: - maxItems: 6 + minItems: 1 + maxItems: 10 description: | Depend to which INTC0 or INTC1 used. INTC0 and INTC1 are two kinds of interrupt controller with enable an= d raw @@ -74,13 +75,17 @@ examples: interrupt-controller@12101b00 { compatible =3D "aspeed,ast2700-intc-ic"; reg =3D <0 0x12101b00 0 0x10>; - #interrupt-cells =3D <2>; + #interrupt-cells =3D <1>; interrupt-controller; interrupts =3D , , , , , - ; + , + , + , + , + ; }; }; --=20 2.34.1