From nobody Sun Feb 8 17:13:32 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3D4D019E99F; Thu, 30 Oct 2025 07:24:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761809075; cv=none; b=GgserRE91kpFL+MKO9kQ1bk0ppWCLvct/vr7+zXfo8yVnzyTNwNZIJXSpSfzbhQeD8sTu04ha0mn7nOUcqDnPtQa23gf1attZBp5nrBqKYLtYCaQlCf9I0cGl07UAp+RH2DhJ/l76w3SqlRlH1LK/+EMQK8qnh0tRvrhqFjZImg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761809075; c=relaxed/simple; bh=8aOZFPFTflbkscTIWZBhClsCIM9o4GWwmg9TXIcb2zo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=p4ZaPpkHiBHhJefQ1nOgVRMRgs7zNyRuXVEWgbTm0OEiD8hP/G8FF319tDt5AKQlbQvsbFomEXivSKhH5acVVnW7SYxZdaZGOVpwEq1U1P6oxj0GYGLrbEeVBwtdrRnoUP+sAHJaIP81QQCnyNtOovlRkGH9v1Z0N/cUn33BulQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Bv5q+2pm; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Bv5q+2pm" Received: by smtp.kernel.org (Postfix) with ESMTPS id D51EEC4CEFB; Thu, 30 Oct 2025 07:24:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1761809074; bh=8aOZFPFTflbkscTIWZBhClsCIM9o4GWwmg9TXIcb2zo=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=Bv5q+2pmPcsi3F2BCg2gHy2HIOVw4b9FKgXsNcJKyJrS2ib1onF9Jd3Vs8SaNvI72 dMikeWhYcPZ6KS585ztnmaKN+TZGopb5DTtjwLiMdjAzwVv4NAmgcHj5umpEmBSc4X cr8FtAFDjUMavoEWNWGTAe3uYHrbEKiPtYydt/ReOmRQb2JLJNiNOQiK4yaLkM1+TA gCxDwsGmgYif8Wbj3cNzTGB6b2za30rzR/O0Xp3rI3bsCoHLrIPm5de5+PGMQeyeIp /aDvvsOqK4XOWAf/LjSIS67R5Boc9YLOlYVD5EGEW7K/HUPbhvEVoze6qGMXx+3Ufp PDMFL8RxAPztQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id C800BCCF9FA; Thu, 30 Oct 2025 07:24:34 +0000 (UTC) From: David Heidelberg via B4 Relay Date: Thu, 30 Oct 2025 08:24:29 +0100 Subject: [PATCH v2 1/2] Documentation: dt-bindings: arm: qcom: Add Pixel 3 and 3 XL Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251030-pixel-3-v2-1-8caddbe072c9@ixit.cz> References: <20251030-pixel-3-v2-0-8caddbe072c9@ixit.cz> In-Reply-To: <20251030-pixel-3-v2-0-8caddbe072c9@ixit.cz> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: phodina@protonmail.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, phone-devel@vger.kernel.org, David Heidelberg X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=716; i=david@ixit.cz; h=from:subject:message-id; bh=DlXm2VUp7Ijt8uTzaBaBxliSbXJ4DoxMqfa5a4LztB0=; b=owEBbQKS/ZANAwAIAWACP8TTSSByAcsmYgBpAxKxVrFT1VwZwJfehm2IryQgQOjZpqH+tViW1 WYBJWhGs2KJAjMEAAEIAB0WIQTXegnP7twrvVOnBHRgAj/E00kgcgUCaQMSsQAKCRBgAj/E00kg cs4YD/9qzawViIzkeuR6ctXUpYb+EpmYU5qpFlWeAUVuEnPSB7NgEML7I6C2/ZbSqteCao63Uf9 KzddLsDWszBcyO7Yz6FxU21ZsDGEmGa8WQChHUGx2mexka5q+yYkK4m89T28PRKafIy2BGTD64N B8anhGaNFhItMQNfKGdrkHQ1oZ7MDK6u2Z5N3FRSMDaNGDTxhvdIJaCNw86jfdb5GlNwmTkISh7 YZyA7KKePdnWkhrPJd6K8LMGEKsvxHbCoPCVndKnzmNqR9f11OxlYRVL5uM6HssybKy2u/XzQvK 6iwLUeeU3irxdLJsXOME8cbTOsAmyhT3SX9oh5sGidkN88oQsAYKGPjqRbWICnqopKyYCpH1WMt zEB6TlYjEVi/hZPTmf0zTMI7hbLpSx0+xFO6hUcPYx7EqChU/TVmyTvSAZtznW40ugDMoZd7xuX UkIiTG0dd5EzA5VaExF+jKx6Y93N4jNzfHPCcb8x8bEZc0PFeYC+bh7fhx/nMccjMZ9ZI5PInPM 65+0Lc+kzKK+gQsg0bOrZTtm43EKdT/3a6cW1LShmAoMSQ7GvAOTKUPCCMZLTU1BZdOnNzV3FQl e3Lvtre7KF6Awzd07ZhF4QeB7037yT6AvMQPwX7EnMIqEXL43nhBGcfa35QxDQZrvhaNpjNhtQW xTAGnjPYz02nFcA== X-Developer-Key: i=david@ixit.cz; a=openpgp; fpr=D77A09CFEEDC2BBD53A7047460023FC4D3492072 X-Endpoint-Received: by B4 Relay for david@ixit.cz/default with auth_id=355 X-Original-From: David Heidelberg Reply-To: david@ixit.cz From: David Heidelberg Document the bindings for the Pixel 3 and 3 XL. Signed-off-by: David Heidelberg --- Documentation/devicetree/bindings/arm/qcom.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentatio= n/devicetree/bindings/arm/qcom.yaml index d84bd3bca2010..760b6633b7a55 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -900,6 +900,8 @@ properties: =20 - items: - enum: + - google,blueline + - google,crosshatch - huawei,planck - lenovo,yoga-c630 - lg,judyln --=20 2.51.0 From nobody Sun Feb 8 17:13:32 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 68F4A335BB6; Thu, 30 Oct 2025 07:24:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251030-pixel-3-v2-2-8caddbe072c9@ixit.cz> References: <20251030-pixel-3-v2-0-8caddbe072c9@ixit.cz> In-Reply-To: <20251030-pixel-3-v2-0-8caddbe072c9@ixit.cz> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: phodina@protonmail.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, phone-devel@vger.kernel.org, David Heidelberg , Amit Pundir , Casey Connolly , Joel Selvaraj , Sumit Semwal , Vinod Koul , Bjorn Andersson X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=17933; i=david@ixit.cz; h=from:subject:message-id; bh=HmTGvIkZJVszYl69muqXkTZ71K7P8TAe6fLxFfawBBY=; b=owEBbQKS/ZANAwAIAWACP8TTSSByAcsmYgBpAxKxCz1M71uoprPgFfPL1Bjs8xoOgYddF7jvC T1nkflcrMSJAjMEAAEIAB0WIQTXegnP7twrvVOnBHRgAj/E00kgcgUCaQMSsQAKCRBgAj/E00kg chBKD/9EjeaNWk4bj54NZLu1jk/fYxvsVYYHEypcxGQ4IlUzqusDyMPeGKGBzQFU5YsavC1ghIO JK9OPtARhX02W2LJD9dx1WBA0+9bHjaaANQUcZOJiej+Rwwgk79PTrQ/aPmLi74pS0UqCfdz+Yl 3742R5Z8vebLxW3Gg1CiUMH1PSiUXOwa1w9+u3fhO7wAeW7mcTKAMhl1eqh01Qs24UFpKdS9RES CKdB9BB3VNb0MNaPZ1GaJgt68Dl4V5cKPCJixHxlF3gtCMPduEI+kbsAawL8G6IPeLdKvFefNXC XRZKhSkSzu4ZF0TJzcMNEoyGt8GYpGIf4DJe8CR5G4Z24W0dGSqtEpPFYEzcbS8sY71SM2p2GwO iNyKnCVPH8S7O+23eVdl4Ubs9/aMSD8phRUXxox4DKwkpPwrrZdhyGLx9kGPhgoBXQPQlpFh8hA L2DcPMWNFikBJxUE9IL7IcL4kgZTFluqkI3L5crf1lDRYClhovroCZPDUci4dya4kb65o+Czr7A 20JJ+S+sHCTURFpW9vLP3LzB4KOr8Z45YiEHzzxz6Li2CokhYSHrooYHU0Q+LifmFuHfgWliorg +xmqcZ92uD0MiBnb6vfn04OGHbieYUIrd+HaY8tc8MolZCRvw6yp026BCru/YjyuGhQSQRsxVEa ynv2AOXdum0fFIw== X-Developer-Key: i=david@ixit.cz; a=openpgp; fpr=D77A09CFEEDC2BBD53A7047460023FC4D3492072 X-Endpoint-Received: by B4 Relay for david@ixit.cz/default with auth_id=355 X-Original-From: David Heidelberg Reply-To: david@ixit.cz From: David Heidelberg This adds initial device tree support for the following phones: - Google Pixel 3 (blueline) - Google Pixel 3 XL (crosshatch) Both phone boards use the same identifiers and differ only slightly in their connected peripherals. Supported functionality includes: - Debug UART - UFS - USB-C (peripheral mode) - Display (Pixel 3 only, and the driver needs improvements) - GPU - Bluetooth - Wi-Fi GPIOs 0=E2=80=933 and 81=E2=80=9384 are not accessible from the application= CPUs, so they are marked as reserved to allow the Pixel 3 to boot. The rmtfs region is allocated using UIO, making it technically "dynamic." Its address and size can be read from sysfs: $ cat /sys/class/uio/uio0/name /sys/class/uio/uio0/maps/map0/addr 0x00000000f2701000 $ cat /sys/class/uio/uio0/maps/map0/size 0x0000000000200000 Like the OnePlus 6, the Pixel 3 requires 1 kB of reserved memory on either side of the rmtfs region to work around an XPU bug that would otherwise cause erroneous violations when accessing the rmtfs_mem region. Co-developed-by: Amit Pundir Signed-off-by: Amit Pundir Co-developed-by: Bjorn Andersson Signed-off-by: Bjorn Andersson Co-developed-by: Casey Connolly Signed-off-by: Casey Connolly Co-developed-by: Joel Selvaraj Signed-off-by: Joel Selvaraj Co-developed-by: Sumit Semwal Signed-off-by: Sumit Semwal Co-developed-by: Vinod Koul Signed-off-by: Vinod Koul Signed-off-by: David Heidelberg --- arch/arm64/boot/dts/qcom/Makefile | 2 + .../arm64/boot/dts/qcom/sdm845-google-blueline.dts | 94 ++++ arch/arm64/boot/dts/qcom/sdm845-google-common.dtsi | 522 +++++++++++++++++= ++++ .../boot/dts/qcom/sdm845-google-crosshatch.dts | 39 ++ 4 files changed, 657 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index 6f34d5ed331c4..c853b28b3b198 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -250,6 +250,8 @@ dtb-$(CONFIG_ARCH_QCOM) +=3D sdm845-db845c.dtb sdm845-db845c-navigation-mezzanine-dtbs :=3D sdm845-db845c.dtb sdm845-db84= 5c-navigation-mezzanine.dtbo =20 dtb-$(CONFIG_ARCH_QCOM) +=3D sdm845-db845c-navigation-mezzanine.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D sdm845-google-crosshatch.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D sdm845-google-blueline.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sdm845-lg-judyln.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sdm845-lg-judyp.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sdm845-mtp.dtb diff --git a/arch/arm64/boot/dts/qcom/sdm845-google-blueline.dts b/arch/arm= 64/boot/dts/qcom/sdm845-google-blueline.dts new file mode 100644 index 0000000000000..a3e95c47947e2 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sdm845-google-blueline.dts @@ -0,0 +1,94 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/dts-v1/; + +#include "sdm845-google-common.dtsi" + +/ { + model =3D "Google Pixel 3"; + compatible =3D "google,blueline", "qcom,sdm845"; +}; + +&battery { + charge-full-design-microamp-hours =3D <2970000>; + voltage-min-design-microvolt =3D <3600000>; + voltage-max-design-microvolt =3D <4400000>; + + status =3D "okay"; +}; + +&cont_splash_mem { + reg =3D <0 0x9d400000 0 0x02400000>; + + status =3D "okay"; +}; + +&framebuffer0 { + width =3D <1080>; + height =3D <2160>; + stride =3D <(1080 * 4)>; + format =3D "a8r8g8b8"; + + status =3D "okay"; +}; + +&mdss_dsi0 { + vdda-supply =3D <&vdda_mipi_dsi0_1p2>; + + status =3D "okay"; + + panel@0 { + compatible =3D "lg,sw43408"; + reg =3D <0>; + + vddi-supply =3D <&vreg_l14a_1p88>; + vpnl-supply =3D <&vreg_l28a_3p0>; + + reset-gpios =3D <&tlmm 6 GPIO_ACTIVE_LOW>; + + pinctrl-0 =3D <&panel_reset_pins &panel_te_pin>; + pinctrl-names =3D "default"; + + port { + panel_in: endpoint { + remote-endpoint =3D <&mdss_dsi0_out>; + }; + }; + }; +}; + +&mdss_dsi0_out { + data-lanes =3D <0 1 2 3>; + remote-endpoint =3D <&panel_in>; + qcom,te-source =3D "mdp_vsync_e"; +}; + +&mdss_dsi0_phy { + vdds-supply =3D <&vdda_mipi_dsi0_pll>; + + status =3D "okay"; +}; + +&tlmm { + panel_te_pin: panel-te-state { + pins =3D "gpio12"; + function =3D "mdp_vsync"; + drive-strength =3D <2>; + bias-pull-down; + }; + + panel_reset_pins: panel-active-state { + pins =3D "gpio6"; + function =3D "gpio"; + drive-strength =3D <8>; + bias-disable; + }; + + panel_suspend: panel-suspend-state { + pins =3D "gpio6"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-down; + }; + +}; diff --git a/arch/arm64/boot/dts/qcom/sdm845-google-common.dtsi b/arch/arm6= 4/boot/dts/qcom/sdm845-google-common.dtsi new file mode 100644 index 0000000000000..226f1d9004915 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sdm845-google-common.dtsi @@ -0,0 +1,522 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/dts-v1/; + +#include +#include +#include +#include +#include + +#include "sdm845.dtsi" +#include "pm8998.dtsi" +#include "pmi8998.dtsi" + +/delete-node/ &mpss_region; +/delete-node/ &venus_mem; +/delete-node/ &cdsp_mem; +/delete-node/ &mba_region; +/delete-node/ &slpi_mem; +/delete-node/ &spss_mem; +/delete-node/ &rmtfs_mem; + +/ { + chassis-type =3D "handset"; + qcom,board-id =3D <0x00021505 0>; + qcom,msm-id =3D ; + + aliases { + serial0 =3D &uart9; + serial1 =3D &uart6; + }; + + battery: battery { + compatible =3D "simple-battery"; + + status =3D "disabled"; + }; + + chosen { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + stdout-path =3D "serial0:115200n8"; + + /* Use display framebuffer as setup by bootloader */ + framebuffer0: framebuffer-0 { + compatible =3D "simple-framebuffer"; + memory-region =3D <&cont_splash_mem>; + + status =3D "disabled"; + }; + }; + + reserved-memory { + cont_splash_mem: splash@9d400000 { + /* size to be updated by actual board */ + reg =3D <0x0 0x9d400000 0x0>; + no-map; + + status =3D "disabled"; + }; + + mpss_region: memory@8e000000 { + reg =3D <0 0x8e000000 0 0x9800000>; + no-map; + }; + + venus_mem: venus@97800000 { + reg =3D <0 0x97800000 0 0x500000>; + no-map; + }; + + cdsp_mem: cdsp-mem@97D00000 { + reg =3D <0 0x97D00000 0 0x800000>; + no-map; + }; + + mba_region: mba@98500000 { + reg =3D <0 0x98500000 0 0x200000>; + no-map; + }; + + slpi_mem: slpi@98700000 { + reg =3D <0 0x98700000 0 0x1400000>; + no-map; + }; + + spss_mem: spss@99B00000 { + reg =3D <0 0x99B00000 0 0x100000>; + no-map; + }; + + rmtfs_mem: rmtfs-region@f2700000 { + compatible =3D "qcom,rmtfs-mem"; + reg =3D <0 0xf2700000 0 0x202000>; + qcom,use-guard-pages; + no-map; + + qcom,client-id =3D <1>; + qcom,vmid =3D ; + }; + }; + + gpio-keys { + compatible =3D "gpio-keys"; + label =3D "Volume keys"; + autorepeat; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&volume_up_gpio>; + + key-vol-up { + label =3D "Volume Up"; + linux,code =3D ; + gpios =3D <&pm8998_gpios 6 GPIO_ACTIVE_LOW>; + debounce-interval =3D <15>; + }; + }; + + vph_pwr: regulator-vph-pwr { + compatible =3D "regulator-fixed"; + regulator-name =3D "vph_pwr"; + regulator-min-microvolt =3D <3700000>; + regulator-max-microvolt =3D <3700000>; + }; + + vreg_s4a_1p8: regulator-vreg-s4a-1p8 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vreg_s4a_1p8"; + + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-always-on; + regulator-boot-on; + + vin-supply =3D <&vph_pwr>; + }; +}; + +&adsp_pas { + firmware-name =3D "qcom/sdm845/Google/blueline/adsp.mbn"; + + status =3D "okay"; +}; + +&apps_rsc { + regulators-0 { + compatible =3D "qcom,pm8998-rpmh-regulators"; + qcom,pmic-id =3D "a"; + + vdd-s1-supply =3D <&vph_pwr>; + vdd-s2-supply =3D <&vph_pwr>; + vdd-s3-supply =3D <&vph_pwr>; + vdd-s4-supply =3D <&vph_pwr>; + vdd-s5-supply =3D <&vph_pwr>; + vdd-s6-supply =3D <&vph_pwr>; + vdd-s7-supply =3D <&vph_pwr>; + vdd-s8-supply =3D <&vph_pwr>; + vdd-s9-supply =3D <&vph_pwr>; + vdd-s10-supply =3D <&vph_pwr>; + vdd-s11-supply =3D <&vph_pwr>; + vdd-s12-supply =3D <&vph_pwr>; + vdd-s13-supply =3D <&vph_pwr>; + vdd-l1-l27-supply =3D <&vreg_s7a_1p025>; + vdd-l2-l8-l17-supply =3D <&vreg_s3a_1p35>; + vdd-l3-l11-supply =3D <&vreg_s7a_1p025>; + vdd-l4-l5-supply =3D <&vreg_s7a_1p025>; + vdd-l6-supply =3D <&vph_pwr>; + vdd-l7-l12-l14-l15-supply =3D <&vreg_s5a_2p04>; + vdd-l9-supply =3D <&vreg_bob>; + vdd-l10-l23-l25-supply =3D <&vreg_bob>; + vdd-l13-l19-l21-supply =3D <&vreg_bob>; + vdd-l16-l28-supply =3D <&vreg_bob>; + vdd-l18-l22-supply =3D <&vreg_bob>; + vdd-l20-l24-supply =3D <&vreg_bob>; + vdd-l26-supply =3D <&vreg_s3a_1p35>; + vin-lvs-1-2-supply =3D <&vreg_s4a_1p8>; + + vreg_s3a_1p35: smps3 { + regulator-min-microvolt =3D <1352000>; + regulator-max-microvolt =3D <1352000>; + }; + + vreg_s5a_2p04: smps5 { + regulator-min-microvolt =3D <1904000>; + regulator-max-microvolt =3D <2040000>; + }; + + vreg_s7a_1p025: smps7 { + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <1028000>; + }; + + vdda_mipi_dsi0_pll: + vreg_l1a_0p875: ldo1 { + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <880000>; + regulator-initial-mode =3D ; + regulator-boot-on; + }; + + vreg_l5a_0p8: ldo5 { + regulator-min-microvolt =3D <800000>; + regulator-max-microvolt =3D <800000>; + regulator-initial-mode =3D ; + }; + + vreg_l12a_1p8: ldo12 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + }; + + vreg_l7a_1p8: ldo7 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + }; + + vreg_l13a_2p95: ldo13 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <2960000>; + regulator-initial-mode =3D ; + }; + + vreg_l14a_1p88: ldo14 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + regulator-boot-on; + /* + * We can't properly bring the panel back if it gets turned off + * so keep it's regulators always on for now. + */ + regulator-always-on; + }; + + vreg_l17a_1p3: ldo17 { + regulator-min-microvolt =3D <1304000>; + regulator-max-microvolt =3D <1304000>; + regulator-initial-mode =3D ; + }; + + vreg_l19a_3p3: ldo19 { + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3312000>; + regulator-initial-mode =3D ; + /* + * The touchscreen needs this to be 3.3v, which is apparently + * quite close to the hardware limit for this LDO (3.312v) + * It must be kept in high power mode to prevent TS brownouts + */ + regulator-allowed-modes =3D ; + }; + + vreg_l20a_2p95: ldo20 { + regulator-min-microvolt =3D <2960000>; + regulator-max-microvolt =3D <2968000>; + regulator-initial-mode =3D ; + }; + + vreg_l21a_2p95: ldo21 { + regulator-min-microvolt =3D <2960000>; + regulator-max-microvolt =3D <2968000>; + regulator-initial-mode =3D ; + }; + + vreg_l24a_3p075: ldo24 { + regulator-min-microvolt =3D <3088000>; + regulator-max-microvolt =3D <3088000>; + regulator-initial-mode =3D ; + }; + + vreg_l25a_3p3: ldo25 { + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3312000>; + regulator-initial-mode =3D ; + }; + + vdda_mipi_dsi0_1p2: + vreg_l26a_1p2: ldo26 { + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + regulator-boot-on; + }; + + vreg_l28a_3p0: ldo28 { + regulator-min-microvolt =3D <2856000>; + regulator-max-microvolt =3D <3008000>; + regulator-initial-mode =3D ; + regulator-boot-on; + /* + * We can't properly bring the panel back if it gets turned off + * so keep it's regulators always on for now. + */ + regulator-always-on; + }; + }; + + regulators-1 { + compatible =3D "qcom,pmi8998-rpmh-regulators"; + qcom,pmic-id =3D "b"; + + vdd-bob-supply =3D <&vph_pwr>; + + vreg_bob: bob { + regulator-min-microvolt =3D <3312000>; + regulator-max-microvolt =3D <3600000>; + regulator-initial-mode =3D ; + regulator-allow-bypass; + }; + }; + + regulators-2 { + compatible =3D "qcom,pm8005-rpmh-regulators"; + qcom,pmic-id =3D "c"; + + vdd-s1-supply =3D <&vph_pwr>; + vdd-s2-supply =3D <&vph_pwr>; + vdd-s3-supply =3D <&vph_pwr>; + vdd-s4-supply =3D <&vph_pwr>; + + vreg_s3c_0p6: smps3 { + regulator-min-microvolt =3D <600000>; + regulator-max-microvolt =3D <600000>; + }; + }; +}; + +&cdsp_pas { + firmware-name =3D "qcom/sdm845/Google/blueline/cdsp.mbn"; + + status =3D "okay"; +}; + +&gcc { + protected-clocks =3D , + , + ; +}; + +&gpi_dma0 { + status =3D "okay"; +}; + +&gpi_dma1 { + status =3D "okay"; +}; + +&gpu { + status =3D "okay"; +}; + +&gpu_zap_shader { + firmware-name =3D "qcom/sdm845/Google/blueline/a630_zap.mbn"; +}; + +&ipa { + firmware-name =3D "qcom/sdm845/Google/blueline/ipa_fws.mbn"; + memory-region =3D <&ipa_fw_mem>; + + status =3D "okay"; +}; + +&mdss { + status =3D "okay"; +}; + +&mss_pil { + firmware-name =3D "qcom/sdm845/Google/blueline/mba.mbn", + "qcom/sdm845/Google/blueline/modem.mbn"; + + status =3D "okay"; +}; + +&pm8998_gpios { + volume_up_gpio: vol-up-active-state { + pins =3D "gpio6"; + function =3D "normal"; + input-enable; + bias-pull-up; + qcom,drive-strength =3D <0>; + }; +}; + +&pm8998_resin { + linux,code =3D ; + + status =3D "okay"; +}; + +&pmi8998_charger { + monitored-battery =3D <&battery>; + + status =3D "okay"; +}; + +&qupv3_id_0 { + status =3D "okay"; +}; + +&qupv3_id_1 { + status =3D "okay"; +}; + +&qup_uart9_rx { + drive-strength =3D <2>; + bias-pull-up; +}; + +&qup_uart9_tx { + drive-strength =3D <2>; + bias-disable; +}; + +&tlmm { + gpio-reserved-ranges =3D <0 4>, <81 4>; + + touchscreen_reset: ts-reset-state { + pins =3D "gpio99"; + function =3D "gpio"; + drive-strength =3D <8>; + bias-pull-up; + }; + + touchscreen_pins: ts-pins-gpio-state { + pins =3D "gpio125"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + touchscreen_i2c_pins: qup-i2c2-gpio-state { + pins =3D "gpio27", "gpio28"; + function =3D "gpio"; + + drive-strength =3D <2>; + bias-disable; + }; +}; + +&uart6 { + pinctrl-0 =3D <&qup_uart6_4pin>; + + status =3D "okay"; + bluetooth { + compatible =3D "qcom,wcn3990-bt"; + + vddio-supply =3D <&vreg_s4a_1p8>; + vddxo-supply =3D <&vreg_l7a_1p8>; + vddrf-supply =3D <&vreg_l17a_1p3>; + vddch0-supply =3D <&vreg_l25a_3p3>; + max-speed =3D <3200000>; + }; +}; + +&uart9 { + status =3D "okay"; +}; + +&ufs_mem_hc { + reset-gpios =3D <&tlmm 150 GPIO_ACTIVE_LOW>; + + vcc-supply =3D <&vreg_l20a_2p95>; + vcc-max-microamp =3D <800000>; + + status =3D "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply =3D <&vreg_l1a_0p875>; + vdda-pll-supply =3D <&vreg_l26a_1p2>; + + status =3D "okay"; +}; + +&usb_1 { + status =3D "okay"; +}; + +&usb_1_dwc3 { + dr_mode =3D "peripheral"; +}; + +&usb_1_hsphy { + vdd-supply =3D <&vreg_l1a_0p875>; + vdda-pll-supply =3D <&vreg_l12a_1p8>; + vdda-phy-dpdm-supply =3D <&vreg_l24a_3p075>; + + qcom,imp-res-offset-value =3D <8>; + qcom,hstx-trim-value =3D ; + qcom,preemphasis-level =3D ; + qcom,preemphasis-width =3D ; + + status =3D "okay"; +}; + +&usb_1_qmpphy { + vdda-phy-supply =3D <&vreg_l26a_1p2>; + vdda-pll-supply =3D <&vreg_l1a_0p875>; + + status =3D "okay"; +}; + +&venus { + firmware-name =3D "qcom/sdm845/Google/blueline/venus.mbn"; + + status =3D "okay"; +}; + +&wifi { + vdd-0.8-cx-mx-supply =3D <&vreg_l5a_0p8>; + vdd-1.8-xo-supply =3D <&vreg_l7a_1p8>; + vdd-1.3-rfa-supply =3D <&vreg_l17a_1p3>; + vdd-3.3-ch0-supply =3D <&vreg_l25a_3p3>; + + qcom,snoc-host-cap-8bit-quirk; + + status =3D "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/sdm845-google-crosshatch.dts b/arch/a= rm64/boot/dts/qcom/sdm845-google-crosshatch.dts new file mode 100644 index 0000000000000..ef5b6817958fe --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sdm845-google-crosshatch.dts @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/dts-v1/; + +#include "sdm845-google-common.dtsi" + +/ { + model =3D "Google Pixel 3 XL"; + compatible =3D "google,crosshatch", "qcom,sdm845"; +}; + +&battery { + charge-full-design-microamp-hours =3D <3480000>; + voltage-min-design-microvolt =3D <3600000>; + voltage-max-design-microvolt =3D <4400000>; + + status =3D "okay"; +}; + +&cont_splash_mem { + reg =3D <0 0x9d400000 0 0x02400000>; + + status =3D "okay"; +}; + +&framebuffer0 { + width =3D <1440>; + height =3D <2960>; + stride =3D <(1440 * 4)>; + format =3D "a8r8g8b8"; + + status =3D "okay"; +}; + +&mdss { + /* until the panel is prepared */ + status =3D "disabled"; +}; + --=20 2.51.0