From nobody Sun Dec 14 05:56:54 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2843932C94A; Thu, 30 Oct 2025 05:24:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761801858; cv=none; b=htGg8+DVB873HcSQ7F+pd8GM9Lwkr4OWYuWFX7M+Of7tSA1Gxoa27eSlDAv8q2sIP2byH8qgCcEQH848xGAcp/8gjfFpWypEfZHODAc1wI9ICPLGs9kpuTAGy7g0AO2cvkE5CZXXbwRgNH9q/osxAoTCJ4tWPtpX9C7dX89/e7k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761801858; c=relaxed/simple; bh=5tLSRE6BInQejsiPR/fc5RiDlVZ9iOn8Or4TkaTc/g4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=httRM+SjbE9pMKNf5waiFPZ55C6F0jQj8sO4QhiWMBJabg8axvmpXCwC1RMrT05JrsEPZKHRqeNPg6vYEDtoL96uv0Wh74zEIyrAYJGXUV/Zyl3QjkaUKQmboX+6cMDlHqwcEYIg+v+EouHD31MqSPJ16VCkGiBvTlyZ3uvVMQQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=d91xdU3D; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="d91xdU3D" Received: by smtp.kernel.org (Postfix) with ESMTPS id B4D78C4CEFF; Thu, 30 Oct 2025 05:24:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1761801857; bh=5tLSRE6BInQejsiPR/fc5RiDlVZ9iOn8Or4TkaTc/g4=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=d91xdU3DbJl+qQa6lgSQtM7avaR4NNy5V/BBKTRM7wJ+HAfoxiT8FRJTX63UPixo1 AJFPG8ySkx0ZyRFxWRRXEbyG1SbzTXHnG+eRluzSORyzg/u/MN4tousMEBE1uNEIGO fsWmpwSrtd4YoejlXGH5+fGOPz42aara+mOHhVrTFrMT2m5yhlVevAPQFW53tHWriK S/DSuVjw1oDxtzGp0BiREnjg9KKiV78RRYc9KYGbcvdDhdBBl89GuHNoCMWsAOw7B0 OrTDqQo3r6XJPKOvys5HzBP5VjGlBbAqPMhYGZVKMhiERNLgFa4V58oqDQa3cbVOIR oaazgjXuWGsTw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9EE23CCF9EA; Thu, 30 Oct 2025 05:24:17 +0000 (UTC) From: Chuan Liu via B4 Relay Date: Thu, 30 Oct 2025 13:24:11 +0800 Subject: [PATCH v2 1/5] clk: amlogic: Fix out-of-range PLL frequency setting Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251030-optimize_pll_driver-v2-1-37273f5b25ab@amlogic.com> References: <20251030-optimize_pll_driver-v2-0-37273f5b25ab@amlogic.com> In-Reply-To: <20251030-optimize_pll_driver-v2-0-37273f5b25ab@amlogic.com> To: Neil Armstrong , Jerome Brunet , Michael Turquette , Stephen Boyd , Kevin Hilman , Martin Blumenstingl Cc: linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Chuan Liu , da@libre.computer X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1761801855; l=991; i=chuan.liu@amlogic.com; s=20240902; h=from:subject:message-id; bh=6onhzW3ODDG4bFoHZLKVZ14BJkN4o2IaabjNVGrsFP0=; b=1KGZg2CEt0fhJufxEmdvITvTntwRDyum3Rdl62EXQsiDSKUog/TKBEitbhD1QajWng+8BLt18 T+rrPWVi0uQBAvwQMD9AjZ6uyKVd2rP99mLY1neIEaParGQ9LNvQWUW X-Developer-Key: i=chuan.liu@amlogic.com; a=ed25519; pk=fnKDB+81SoWGKW2GJNFkKy/ULvsDmJZRGBE7pR5Xcpo= X-Endpoint-Received: by B4 Relay for chuan.liu@amlogic.com/20240902 with auth_id=203 X-Original-From: Chuan Liu Reply-To: chuan.liu@amlogic.com From: Chuan Liu If the calculated 'm' falls into the range: pll->range->max < m < (1 << pll->m.width) Here an incorrect 'm' value could be obtained, so an additional condition is added to ensure that the calculated 'm' stays within a valid range. Fixes: 8eed1db1adec6 ("clk: meson: pll: update driver for the g12a") Signed-off-by: Chuan Liu --- drivers/clk/meson/clk-pll.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/meson/clk-pll.c b/drivers/clk/meson/clk-pll.c index 1ea6579a760f..629f6af18ea1 100644 --- a/drivers/clk/meson/clk-pll.c +++ b/drivers/clk/meson/clk-pll.c @@ -191,7 +191,7 @@ static int meson_clk_get_pll_range_index(unsigned long = rate, *m =3D meson_clk_get_pll_range_m(rate, parent_rate, *n, pll); =20 /* the pre-divider gives a multiplier too big - stop */ - if (*m >=3D (1 << pll->m.width)) + if (*m > pll->range->max || *m >=3D (1 << pll->m.width)) return -EINVAL; =20 return 0; --=20 2.42.0 From nobody Sun Dec 14 05:56:54 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2CCC332C94F; Thu, 30 Oct 2025 05:24:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761801858; cv=none; b=XNZAzvD1pKAYZNS5GJ5rrwn29hfTvpQMGo+96Uu7RtDXI0VRkiWB0WDUnELBblDYS9RJPAjG4Xe2C3rzhwdsZzUGmsjYUY6VQGTcX1BIjt0O3H1BemycGrffMDGZX4Qy9K8S0F3u84PkZGcSRuiL5kt4QDr+99cy6f7DsdXERjc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761801858; c=relaxed/simple; bh=2jU1k23psQLoti835WJhUi8hPO5zOMCVn1KLTW6Gx7o=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=JiX9FsGKRMkKxs0LdIvimyXrjIblczOLq3rgWyuopzu/ulx7BB+m0Zx4c1PXDD2bHIEjcKBg88uZN7T9FBYF0szi7y3jHeMfQnFRJKSNu1TwAlmsMzSCyPp7o/SCffVrPHJPFg8LSuv6zFy2lTYkLFq35WMAdTzc9oozfStqAQA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Fqct62np; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Fqct62np" Received: by smtp.kernel.org (Postfix) with ESMTPS id C27FCC4CEFB; Thu, 30 Oct 2025 05:24:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1761801857; bh=2jU1k23psQLoti835WJhUi8hPO5zOMCVn1KLTW6Gx7o=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=Fqct62npqZNU+7aZwsQZWh1JWHKkBg0YVUWAGL+i6XEbL232ekVUazCOU0HaAR0BD fYn8Zp9ku2mPyqXsQ7ga1lJPG1sQuWmBb7U5Ct0cRa7lq8pf7w5swmYJE/k5gNz/BM YhO9IS/JzLvmVvjE6VVBiAzz1RrbYlWudw4yeIC9+YEUWq8n4DegFGe5cMjCMb/fqh 8f4VYoV9BU/WxYmvCQOLj1dnLobZJ/Aim7AueiiF2q+D4+O9FqFQ/dCKKwFslC43uD /rl+FO5cWp/+8hT9quRlpMAj3Sbb74Ip7NZIz4bD3zWIByIxmdW4pEFuRWoqznm8nm ybfwXVyuNfiEg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id AE968CCF9F6; Thu, 30 Oct 2025 05:24:17 +0000 (UTC) From: Chuan Liu via B4 Relay Date: Thu, 30 Oct 2025 13:24:12 +0800 Subject: [PATCH v2 2/5] clk: amlogic: Improve the issue of PLL lock failures Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251030-optimize_pll_driver-v2-2-37273f5b25ab@amlogic.com> References: <20251030-optimize_pll_driver-v2-0-37273f5b25ab@amlogic.com> In-Reply-To: <20251030-optimize_pll_driver-v2-0-37273f5b25ab@amlogic.com> To: Neil Armstrong , Jerome Brunet , Michael Turquette , Stephen Boyd , Kevin Hilman , Martin Blumenstingl Cc: linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Chuan Liu , da@libre.computer X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1761801855; l=1329; i=chuan.liu@amlogic.com; s=20240902; h=from:subject:message-id; bh=By36+5Xc3F4ZCx2+oODMEZ/7arVOVHo8uzE39j79UAI=; b=uZ6pe/g6+Kcpzahmm37OY/aCUYb8QAGsQ9XhgLK57CE/ZIYOWn0w0solOn5GWD1DFWNqs20OZ DbfMN8DGCptAdPPnCDKIoA1yjDdyQRO7hVdZKe6PPNqGayQVvll6NrY X-Developer-Key: i=chuan.liu@amlogic.com; a=ed25519; pk=fnKDB+81SoWGKW2GJNFkKy/ULvsDmJZRGBE7pR5Xcpo= X-Endpoint-Received: by B4 Relay for chuan.liu@amlogic.com/20240902 with auth_id=203 X-Original-From: Chuan Liu Reply-To: chuan.liu@amlogic.com From: Chuan Liu Due to factors such as temperature and process variations, the internal circuits of the PLL may require a longer time to reach a steady state, which can result in occasional lock failures on some SoCs under low-temperature conditions. After enabling the PLL and releasing its reset, a 20 us delay is added at each step to provide enough time for the internal PLL circuit to stabilize, thus reducing the probability of PLL lock failure. Signed-off-by: Chuan Liu --- drivers/clk/meson/clk-pll.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/clk/meson/clk-pll.c b/drivers/clk/meson/clk-pll.c index 629f6af18ea1..f81ebf6cc981 100644 --- a/drivers/clk/meson/clk-pll.c +++ b/drivers/clk/meson/clk-pll.c @@ -368,11 +368,16 @@ static int meson_clk_pll_enable(struct clk_hw *hw) =20 /* Enable the pll */ meson_parm_write(clk->map, &pll->en, 1); + /* Wait for Bandgap and LDO to power up and stabilize */ + udelay(20); =20 /* Take the pll out reset */ if (MESON_PARM_APPLICABLE(&pll->rst)) meson_parm_write(clk->map, &pll->rst, 0); =20 + /* Wait for PLL loop stabilization */ + udelay(20); + /* * Compared with the previous SoCs, self-adaption current module * is newly added for A1, keep the new power-on sequence to enable the --=20 2.42.0 From nobody Sun Dec 14 05:56:54 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 283412D063D; Thu, 30 Oct 2025 05:24:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761801858; cv=none; b=Pdxm1phoufvKryhexvnZ8pjqddx165lpMyrp2N11j7nWSeFZCvtoeAh1RC3K/coclEpKclzIyTJr6+xccAvFIYn72PfMhoAlSz9EysOoGQL2O58Z8ECqLKk7NeiEZOOMqk/FDCNQy5s1ybFnRE8H5yuqMiZC75h+d3oFbEYjvtc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761801858; c=relaxed/simple; bh=7PrPtqlO+xwMN6puDCOh8Tf+yRQi8msCbeKY70lBqSA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Ja56smi5MWd4WdUfKcEmZanPTXK39/ij/HAbcZk2ijYisFZuKlm4ZmKc23VbMqA4/wF7kD4w0JA+bVQOuTsuAnHEVV1ERlQ7GUb77knW0qhKJs2iAJ9OJzM7O+0rLTP6WlipFhR3MZkQP+fI4Sc8/lLmU5iNuHUbCOJtIaK6mt0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ba0sn1gg; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ba0sn1gg" Received: by smtp.kernel.org (Postfix) with ESMTPS id CB1EEC113D0; Thu, 30 Oct 2025 05:24:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1761801857; bh=7PrPtqlO+xwMN6puDCOh8Tf+yRQi8msCbeKY70lBqSA=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=ba0sn1ggI/79H0CiA2KfZtb+PuJZfu0J6FUZhhW/kSpdorEYmTY5veZhUeycILUuB UcL7ghxSH9Epb5IloiBr/MklFdp5Dc12GnK0/7bAuhm7ZjGczYrhWeO3Xt/HPxnmfd OgqV7y8PG06UoOYdxabsXtfDTJ+3sVexvebrS0LyC3okbCUlt7QT9tBMnnwKMhBPgH hE88iu134EiV5UPHwVQiuTnjwRp1aOhS06jv5WhohA2F/ci+hHzUIxB47PqwG4H1Xi HIWxyzvEr1R9PtSWJQ7D5Rl3DHPqx7ta/BSd0yRBHWyY8UR2dFcGeaGlCPtvfTIhMK EWe7v5WzMD0kg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id BE853CCF9F8; Thu, 30 Oct 2025 05:24:17 +0000 (UTC) From: Chuan Liu via B4 Relay Date: Thu, 30 Oct 2025 13:24:13 +0800 Subject: [PATCH v2 3/5] clk: amlogic: Add handling for PLL lock failure Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251030-optimize_pll_driver-v2-3-37273f5b25ab@amlogic.com> References: <20251030-optimize_pll_driver-v2-0-37273f5b25ab@amlogic.com> In-Reply-To: <20251030-optimize_pll_driver-v2-0-37273f5b25ab@amlogic.com> To: Neil Armstrong , Jerome Brunet , Michael Turquette , Stephen Boyd , Kevin Hilman , Martin Blumenstingl Cc: linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Chuan Liu , da@libre.computer X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1761801855; l=2331; i=chuan.liu@amlogic.com; s=20240902; h=from:subject:message-id; bh=vrUlJ1HmRnCEyEkq2xDw1ggVFh4RddetWLmGLf94sV4=; b=cSkp9cTFFGr5sg6ASQ8L33zSJKDZR942ZJ8M8anl9qJse6qqWwezMYBS2WJrFMSpurm2Vpguh xbNHhPo/ZlBCEu/7QDJNyKvbgOsc82743NVagBbUZHSXjb5k+QBmYDc X-Developer-Key: i=chuan.liu@amlogic.com; a=ed25519; pk=fnKDB+81SoWGKW2GJNFkKy/ULvsDmJZRGBE7pR5Xcpo= X-Endpoint-Received: by B4 Relay for chuan.liu@amlogic.com/20240902 with auth_id=203 X-Original-From: Chuan Liu Reply-To: chuan.liu@amlogic.com From: Chuan Liu If the PLL fails to lock, it should be disabled, This makes the logic more complete, and also helps save unnecessary power consumption when the PLL is malfunctioning. Signed-off-by: Chuan Liu --- drivers/clk/meson/clk-pll.c | 41 +++++++++++++++++++++++------------------ 1 file changed, 23 insertions(+), 18 deletions(-) diff --git a/drivers/clk/meson/clk-pll.c b/drivers/clk/meson/clk-pll.c index f81ebf6cc981..6c794adb8ccd 100644 --- a/drivers/clk/meson/clk-pll.c +++ b/drivers/clk/meson/clk-pll.c @@ -353,6 +353,23 @@ static int meson_clk_pcie_pll_enable(struct clk_hw *hw) return -EIO; } =20 +static void meson_clk_pll_disable(struct clk_hw *hw) +{ + struct clk_regmap *clk =3D to_clk_regmap(hw); + struct meson_clk_pll_data *pll =3D meson_clk_pll_data(clk); + + /* Put the pll is in reset */ + if (MESON_PARM_APPLICABLE(&pll->rst)) + meson_parm_write(clk->map, &pll->rst, 1); + + /* Disable the pll */ + meson_parm_write(clk->map, &pll->en, 0); + + /* Disable PLL internal self-adaption current module */ + if (MESON_PARM_APPLICABLE(&pll->current_en)) + meson_parm_write(clk->map, &pll->current_en, 0); +} + static int meson_clk_pll_enable(struct clk_hw *hw) { struct clk_regmap *clk =3D to_clk_regmap(hw); @@ -397,29 +414,17 @@ static int meson_clk_pll_enable(struct clk_hw *hw) meson_parm_write(clk->map, &pll->l_detect, 0); } =20 - if (meson_clk_pll_wait_lock(hw)) + if (meson_clk_pll_wait_lock(hw)) { + /* disable PLL when PLL lock failed. */ + meson_clk_pll_disable(hw); + pr_warn("%s: PLL lock failed!!!\n", clk_hw_get_name(hw)); + return -EIO; + } =20 return 0; } =20 -static void meson_clk_pll_disable(struct clk_hw *hw) -{ - struct clk_regmap *clk =3D to_clk_regmap(hw); - struct meson_clk_pll_data *pll =3D meson_clk_pll_data(clk); - - /* Put the pll is in reset */ - if (MESON_PARM_APPLICABLE(&pll->rst)) - meson_parm_write(clk->map, &pll->rst, 1); - - /* Disable the pll */ - meson_parm_write(clk->map, &pll->en, 0); - - /* Disable PLL internal self-adaption current module */ - if (MESON_PARM_APPLICABLE(&pll->current_en)) - meson_parm_write(clk->map, &pll->current_en, 0); -} - static int meson_clk_pll_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { --=20 2.42.0 From nobody Sun Dec 14 05:56:54 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2CD3C32C950; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251030-optimize_pll_driver-v2-4-37273f5b25ab@amlogic.com> References: <20251030-optimize_pll_driver-v2-0-37273f5b25ab@amlogic.com> In-Reply-To: <20251030-optimize_pll_driver-v2-0-37273f5b25ab@amlogic.com> To: Neil Armstrong , Jerome Brunet , Michael Turquette , Stephen Boyd , Kevin Hilman , Martin Blumenstingl Cc: linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Chuan Liu , da@libre.computer X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1761801855; l=2564; i=chuan.liu@amlogic.com; s=20240902; h=from:subject:message-id; bh=DjnEanujLZY4RuGc42rl8hj7g33ffwSvffDuoLJcxso=; b=sTga/WVc91PpMaP5RpP+aJzcq1fHbdkptD2tzxJ/anIj6LHmeSDy9p2tUGqkohJmzO2ldf8Bk OsA0vBqz2nqDsOLShEcZFUKNQw3jhmY3tuftag8o15yNCYsVdSJ+jvT X-Developer-Key: i=chuan.liu@amlogic.com; a=ed25519; pk=fnKDB+81SoWGKW2GJNFkKy/ULvsDmJZRGBE7pR5Xcpo= X-Endpoint-Received: by B4 Relay for chuan.liu@amlogic.com/20240902 with auth_id=203 X-Original-From: Chuan Liu Reply-To: chuan.liu@amlogic.com From: Chuan Liu l_detect controls the enablement of the PLL lock detection module. It should remain disabled while the internal PLL circuits are reaching a steady state; otherwise, the lock signal may be falsely triggered high. Before enabling the internal power supply of the PLL, l_detect should be disabled. After the PLL=E2=80=99s internal circuits have stabilized, l_detect should be enabled to prevent false lock signal triggers. Currently, only A1 supports both l_detect and current_en, so this patch will only affect A1. Signed-off-by: Chuan Liu --- drivers/clk/meson/clk-pll.c | 28 +++++++++++++++------------- 1 file changed, 15 insertions(+), 13 deletions(-) diff --git a/drivers/clk/meson/clk-pll.c b/drivers/clk/meson/clk-pll.c index 6c794adb8ccd..c6eebde1f516 100644 --- a/drivers/clk/meson/clk-pll.c +++ b/drivers/clk/meson/clk-pll.c @@ -383,36 +383,38 @@ static int meson_clk_pll_enable(struct clk_hw *hw) if (MESON_PARM_APPLICABLE(&pll->rst)) meson_parm_write(clk->map, &pll->rst, 1); =20 + /* Disable the PLL lock-detect module */ + if (MESON_PARM_APPLICABLE(&pll->l_detect)) + meson_parm_write(clk->map, &pll->l_detect, 1); + /* Enable the pll */ meson_parm_write(clk->map, &pll->en, 1); /* Wait for Bandgap and LDO to power up and stabilize */ udelay(20); =20 - /* Take the pll out reset */ - if (MESON_PARM_APPLICABLE(&pll->rst)) - meson_parm_write(clk->map, &pll->rst, 0); - - /* Wait for PLL loop stabilization */ - udelay(20); - /* * Compared with the previous SoCs, self-adaption current module * is newly added for A1, keep the new power-on sequence to enable the * PLL. The sequence is: - * 1. enable the pll, delay for 10us + * 1. enable the pll, delay for 20us * 2. enable the pll self-adaption current module, delay for 40us * 3. enable the lock detect module */ if (MESON_PARM_APPLICABLE(&pll->current_en)) { - udelay(10); meson_parm_write(clk->map, &pll->current_en, 1); - udelay(40); + udelay(20); } =20 - if (MESON_PARM_APPLICABLE(&pll->l_detect)) { - meson_parm_write(clk->map, &pll->l_detect, 1); + /* Take the pll out reset */ + if (MESON_PARM_APPLICABLE(&pll->rst)) + meson_parm_write(clk->map, &pll->rst, 0); + + /* Wait for PLL loop stabilization */ + udelay(20); + + /* Enable the lock-detect module */ + if (MESON_PARM_APPLICABLE(&pll->l_detect)) meson_parm_write(clk->map, &pll->l_detect, 0); - } =20 if (meson_clk_pll_wait_lock(hw)) { /* disable PLL when PLL lock failed. */ --=20 2.42.0 From nobody Sun Dec 14 05:56:54 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8BFB132D44A; Thu, 30 Oct 2025 05:24:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761801858; cv=none; b=Hj8+Dxqwgya1+bHyO4nY8nSBebDESEPDnXMByn9VVEapoFumGdE/InYz+7Io3U6mqaIplULnVkifXTGacSlGjl9xicxezPWFKbc1mcNXyvYQ+DGPg4zUpJxX6b7K3vpah5Q1HxYDGRlN2tDRFFq1tioXefoHsFQdA6FgHJp7ju4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761801858; c=relaxed/simple; bh=zzksamsMZJOf1VT2cpshTei0QB7OGy3UaCYmRF0l4+I=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=i10stj/ylXsYAywOcobpKqKojGZPqzjXuDtHs25Iy8z6rJP05hr/8+VWbInSFaKRWG1uhyZlXIya3iAtrQ7uBlZsG20awelRxu1gerp/3V7nl60vDOkhBj+y5ZIzze6sbeDcRntp5zbsnBBIUrtYfTgl+L2muGxbs4pH4x29YV8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Re3PalxX; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Re3PalxX" Received: by smtp.kernel.org (Postfix) with ESMTPS id EEB10C19422; Thu, 30 Oct 2025 05:24:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1761801858; bh=zzksamsMZJOf1VT2cpshTei0QB7OGy3UaCYmRF0l4+I=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=Re3PalxXppg+X4cVfexljdnK7Rq7OkfLbTIsQpYACW5uPSmp9dwiuqRk/owTZwAz/ ZvZNS1V714JLYIR2jWFh6W++HPwQcTGIgNhxt8aAwcrOFpt8tVnCDxAtO6JSEWcy0T wbEecwKaAoepL3qNOJG7A9aslcpoKnUsY+wOemOxm3Jz1O9/s3TxMBxFLQ7lkOR1iD pRg2/Jx+oVmMTtIrbWYjDqe8C7TjVKhi7Dvavzbu8k59p96SgLyOrGx76cZAIQhhvb jtesJy/LMawdLz/d0VXxknKYgCW7gc8GH+A6P4ZyhQQM8dkXe0oG4N4FQyPeFC6Ilb p2hIcnSa4h5gA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id E7B6FCCF9F6; Thu, 30 Oct 2025 05:24:17 +0000 (UTC) From: Chuan Liu via B4 Relay Date: Thu, 30 Oct 2025 13:24:15 +0800 Subject: [PATCH v2 5/5] clk: amlogic: Change the active level of l_detect Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251030-optimize_pll_driver-v2-5-37273f5b25ab@amlogic.com> References: <20251030-optimize_pll_driver-v2-0-37273f5b25ab@amlogic.com> In-Reply-To: <20251030-optimize_pll_driver-v2-0-37273f5b25ab@amlogic.com> To: Neil Armstrong , Jerome Brunet , Michael Turquette , Stephen Boyd , Kevin Hilman , Martin Blumenstingl Cc: linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Chuan Liu , da@libre.computer X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1761801855; l=2920; i=chuan.liu@amlogic.com; s=20240902; h=from:subject:message-id; bh=EZQlp+ntQWH8wulP13OMEjecr2IO8R7gTLRrdJNlJqE=; b=tkTJCiK33Lo/TFJ+LelyksSbZKnetVKLe70d7ctvoJhRiAucDH840dF3/2GnHDeDNQika1syG p2IuaWbAkHsB2RTAIEHlBjlOt/J8081nbUxgd6kHxUu9KBv1e/jPZwI X-Developer-Key: i=chuan.liu@amlogic.com; a=ed25519; pk=fnKDB+81SoWGKW2GJNFkKy/ULvsDmJZRGBE7pR5Xcpo= X-Endpoint-Received: by B4 Relay for chuan.liu@amlogic.com/20240902 with auth_id=203 X-Original-From: Chuan Liu Reply-To: chuan.liu@amlogic.com From: Chuan Liu l_detect controls the enable/disable of the PLL lock-detect module. The enable signal is normally active-high. This design ensures that the module remains disabled during the power-on process, preventing power fluctuations from affecting its operating state. For A1, the l_detect signal is active-low: 0 -> Enable lock-detect module; 1 -> Disable lock-detect module. Here, a flag CLK_MESON_PLL_L_DETECT_N is added to handle cases like A1, where the signal is active-low. Signed-off-by: Chuan Liu --- drivers/clk/meson/a1-pll.c | 1 + drivers/clk/meson/clk-pll.c | 16 ++++++++++++---- drivers/clk/meson/clk-pll.h | 2 ++ 3 files changed, 15 insertions(+), 4 deletions(-) diff --git a/drivers/clk/meson/a1-pll.c b/drivers/clk/meson/a1-pll.c index 1f82e9c7c14e..bfe559c71402 100644 --- a/drivers/clk/meson/a1-pll.c +++ b/drivers/clk/meson/a1-pll.c @@ -137,6 +137,7 @@ static struct clk_regmap a1_hifi_pll =3D { .range =3D &a1_hifi_pll_range, .init_regs =3D a1_hifi_pll_init_regs, .init_count =3D ARRAY_SIZE(a1_hifi_pll_init_regs), + .flags =3D CLK_MESON_PLL_L_DETECT_N }, .hw.init =3D &(struct clk_init_data){ .name =3D "hifi_pll", diff --git a/drivers/clk/meson/clk-pll.c b/drivers/clk/meson/clk-pll.c index c6eebde1f516..d729e933aa1c 100644 --- a/drivers/clk/meson/clk-pll.c +++ b/drivers/clk/meson/clk-pll.c @@ -384,8 +384,12 @@ static int meson_clk_pll_enable(struct clk_hw *hw) meson_parm_write(clk->map, &pll->rst, 1); =20 /* Disable the PLL lock-detect module */ - if (MESON_PARM_APPLICABLE(&pll->l_detect)) - meson_parm_write(clk->map, &pll->l_detect, 1); + if (MESON_PARM_APPLICABLE(&pll->l_detect)) { + if (pll->flags & CLK_MESON_PLL_L_DETECT_N) + meson_parm_write(clk->map, &pll->l_detect, 1); + else + meson_parm_write(clk->map, &pll->l_detect, 0); + } =20 /* Enable the pll */ meson_parm_write(clk->map, &pll->en, 1); @@ -413,8 +417,12 @@ static int meson_clk_pll_enable(struct clk_hw *hw) udelay(20); =20 /* Enable the lock-detect module */ - if (MESON_PARM_APPLICABLE(&pll->l_detect)) - meson_parm_write(clk->map, &pll->l_detect, 0); + if (MESON_PARM_APPLICABLE(&pll->l_detect)) { + if (pll->flags & CLK_MESON_PLL_L_DETECT_N) + meson_parm_write(clk->map, &pll->l_detect, 0); + else + meson_parm_write(clk->map, &pll->l_detect, 1); + } =20 if (meson_clk_pll_wait_lock(hw)) { /* disable PLL when PLL lock failed. */ diff --git a/drivers/clk/meson/clk-pll.h b/drivers/clk/meson/clk-pll.h index 949157fb7bf5..83295a24721f 100644 --- a/drivers/clk/meson/clk-pll.h +++ b/drivers/clk/meson/clk-pll.h @@ -29,6 +29,8 @@ struct pll_mult_range { =20 #define CLK_MESON_PLL_ROUND_CLOSEST BIT(0) #define CLK_MESON_PLL_NOINIT_ENABLED BIT(1) +/* l_detect signal is active-low */ +#define CLK_MESON_PLL_L_DETECT_N BIT(2) =20 struct meson_clk_pll_data { struct parm en; --=20 2.42.0