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Thu, 30 Oct 2025 11:50:20 -0700 (PDT) Received: from Black-Pearl.localdomain ([27.7.191.116]) by smtp.googlemail.com with ESMTPSA id 98e67ed59e1d1-340509a3001sm3386203a91.10.2025.10.30.11.50.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Oct 2025 11:50:19 -0700 (PDT) From: Charan Pedumuru Date: Thu, 30 Oct 2025 18:47:25 +0000 Subject: [PATCH] dt-bindings: mtd: nvidia,tegra20-nand: convert to DT schema Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251030-nvidia-nand-v1-1-7614e1428292@gmail.com> X-B4-Tracking: v=1; b=H4sIALyyA2kC/x3MMQqAMAxA0auUzAbaoiheRRxiGzVLlBaKULy7x fEN/1fInIQzzKZC4iJZLm1wnYFwkh6MEpvBWz846xxqkSiEShrR+j6EkXjaLEEr7sS7PP9tWd/ 3A73CBlpdAAAA X-Change-ID: 20251011-nvidia-nand-024cc7ae8b0a To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding , Jonathan Hunter , Stefan Agner , Lucas Stach Cc: linux-mtd@lists.infradead.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, Charan Pedumuru X-Mailer: b4 0.14.3 Convert NVIDIA Tegra NAND Flash Controller binding to YAML format. Changes during Conversion: - Define new properties `power-domains` and `operating-points-v2` to resolve errors generated by `dtb_check`. - Add the `#address-cells` and `#size-cells` properties to the parent node to fix errors reported by `dt_check`, and include these properties in the `required` section, as they are not mentioned in the text binding. Signed-off-by: Charan Pedumuru --- .../bindings/mtd/nvidia,tegra20-nand.yaml | 157 +++++++++++++++++= ++++ .../bindings/mtd/nvidia-tegra20-nand.txt | 64 --------- 2 files changed, 157 insertions(+), 64 deletions(-) diff --git a/Documentation/devicetree/bindings/mtd/nvidia,tegra20-nand.yaml= b/Documentation/devicetree/bindings/mtd/nvidia,tegra20-nand.yaml new file mode 100644 index 000000000000..67b3c45566db --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/nvidia,tegra20-nand.yaml @@ -0,0 +1,157 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mtd/nvidia,tegra20-nand.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra NAND Flash Controller + +maintainers: + - Jonathan Hunter + +description: + Device tree bindings for the NVIDIA Tegra NAND Flash Controller (NFC). + The controller supports a single NAND chip with specific properties. + +properties: + compatible: + const: nvidia,tegra20-nand + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: nand + + resets: + maxItems: 1 + + reset-names: + items: + - const: nand + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + power-domains: + maxItems: 1 + + operating-points-v2: + maxItems: 1 + +patternProperties: + "^nand@[0-5]$": + type: object + description: Individual NAND chip connected to the NAND controller + properties: + reg: + maxItems: 1 + + nand-ecc-mode: + description: + Operation mode of the NAND ECC, currently only hardware + mode supported + const: hw + + nand-ecc-algo: + description: Algorithm for NAND ECC when using hw ECC mode + enum: + - rs + - bch + + nand-bus-width: + description: Width of the NAND flash bus in bits + enum: [8, 16] + default: 8 + + nand-on-flash-bbt: + description: Use an on-flash bad block table to track bad blocks + type: boolean + + nand-ecc-maximize: + description: + Maximize ECC strength for the NAND chip, overriding + default strength selection + type: boolean + + nand-ecc-strength: + description: Number of bits to correct per ECC step (512 bytes) + enum: [4, 6, 8, 14, 16] + + nand-is-boot-medium: + description: Ensures ECC strengths are compatible with the boot ROM + type: boolean + + wp-gpios: + description: GPIO specifier for the write protect pin + maxItems: 1 + + '#address-cells': + const: 1 + + '#size-cells': + const: 1 + + patternProperties: + "^partition@[0-9a-f]+$": + $ref: /schemas/mtd/mtd.yaml# + description: + Optional MTD partitions for the NAND chip, as defined in mtd.yaml + + required: + - reg + + unevaluatedProperties: false + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - resets + - reset-names + - '#address-cells' + - '#size-cells' + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + + nand-controller@70008000 { + compatible =3D "nvidia,tegra20-nand"; + reg =3D <0x70008000 0x100>; + interrupts =3D ; + clocks =3D <&tegra_car TEGRA20_CLK_NDFLASH>; + clock-names =3D "nand"; + resets =3D <&tegra_car 13>; + reset-names =3D "nand"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + nand@0 { + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <1>; + nand-bus-width =3D <8>; + nand-on-flash-bbt; + nand-ecc-algo =3D "bch"; + nand-ecc-strength =3D <8>; + wp-gpios =3D <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_LOW>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/mtd/nvidia-tegra20-nand.txt = b/Documentation/devicetree/bindings/mtd/nvidia-tegra20-nand.txt deleted file mode 100644 index 4a00ec2b2540..000000000000 --- a/Documentation/devicetree/bindings/mtd/nvidia-tegra20-nand.txt +++ /dev/null @@ -1,64 +0,0 @@ -NVIDIA Tegra NAND Flash controller - -Required properties: -- compatible: Must be one of: - - "nvidia,tegra20-nand" -- reg: MMIO address range -- interrupts: interrupt output of the NFC controller -- clocks: Must contain an entry for each entry in clock-names. - See ../clocks/clock-bindings.txt for details. -- clock-names: Must include the following entries: - - nand -- resets: Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. -- reset-names: Must include the following entries: - - nand - -Optional children nodes: -Individual NAND chips are children of the NAND controller node. Currently -only one NAND chip supported. - -Required children node properties: -- reg: An integer ranging from 1 to 6 representing the CS line to use. - -Optional children node properties: -- nand-ecc-mode: String, operation mode of the NAND ecc mode. Currently on= ly - "hw" is supported. -- nand-ecc-algo: string, algorithm of NAND ECC. - Supported values with "hw" ECC mode are: "rs", "bch". -- nand-bus-width : See nand-controller.yaml -- nand-on-flash-bbt: See nand-controller.yaml -- nand-ecc-strength: integer representing the number of bits to correct - per ECC step (always 512). Supported strength using HW ECC - modes are: - - RS: 4, 6, 8 - - BCH: 4, 8, 14, 16 -- nand-ecc-maximize: See nand-controller.yaml -- nand-is-boot-medium: Makes sure only ECC strengths supported by the boot= ROM - are chosen. -- wp-gpios: GPIO specifier for the write protect pin. - -Optional child node of NAND chip nodes: -Partitions: see mtd.yaml - - Example: - nand-controller@70008000 { - compatible =3D "nvidia,tegra20-nand"; - reg =3D <0x70008000 0x100>; - interrupts =3D ; - clocks =3D <&tegra_car TEGRA20_CLK_NDFLASH>; - clock-names =3D "nand"; - resets =3D <&tegra_car 13>; - reset-names =3D "nand"; - - nand@0 { - reg =3D <0>; - #address-cells =3D <1>; - #size-cells =3D <1>; - nand-bus-width =3D <8>; - nand-on-flash-bbt; - nand-ecc-algo =3D "bch"; - nand-ecc-strength =3D <8>; - wp-gpios =3D <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_LOW>; - }; - }; --- base-commit: 43edce71d70c603d3f3f1b1c886f65cd02d80c24 change-id: 20251011-nvidia-nand-024cc7ae8b0a Best regards, --=20 Charan Pedumuru