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This format is intended for AV1 bitstreams in stateful decoding/encoding workflows. The fourcc code 'AV10' is used to distinguish this format from the existing V4L2_PIX_FMT_AV1_FRAME, which is used for stateless AV1 decoder implementation. Signed-off-by: Deepa Guthyappa Madivalara Reviewed-by: Bryan O'Donoghue --- Documentation/userspace-api/media/v4l/pixfmt-compressed.rst | 8 ++++++++ include/uapi/linux/videodev2.h | 1 + 2 files changed, 9 insertions(+) diff --git a/Documentation/userspace-api/media/v4l/pixfmt-compressed.rst b/= Documentation/userspace-api/media/v4l/pixfmt-compressed.rst index c7efb0465db6480fe35be8557728c196e0e530f4..0c70410ffd4d58e0719d3cf13ad= 336c97b454ae9 100644 --- a/Documentation/userspace-api/media/v4l/pixfmt-compressed.rst +++ b/Documentation/userspace-api/media/v4l/pixfmt-compressed.rst @@ -275,6 +275,14 @@ Compressed Formats of macroblocks to decode a full corresponding frame to the matching capture buffer. =20 + * .. _V4L2-PIX-FMT-AV1: + + - ``V4L2_PIX_FMT_AV1`` + - 'AV01' + - AV1 compressed video frame. This format is adapted for implementin= g AV1 + pipeline. The decoder implements stateful video decoder and expect= s one + Temporal Unit per buffer from OBU-stream or AnnexB. + The encoder generates one Temporal Unit per buffer. .. raw:: latex =20 \normalsize diff --git a/include/uapi/linux/videodev2.h b/include/uapi/linux/videodev2.h index becd08fdbddb857f8f2bf205d2164dc6e20e80b2..cf0b71bbe0f9d397e1e6c88433a= 0fc3ba11fb947 100644 --- a/include/uapi/linux/videodev2.h +++ b/include/uapi/linux/videodev2.h @@ -775,6 +775,7 @@ struct v4l2_pix_format { #define V4L2_PIX_FMT_H264_SLICE v4l2_fourcc('S', '2', '6', '4') /* H264 pa= rsed slices */ #define V4L2_PIX_FMT_HEVC_SLICE v4l2_fourcc('S', '2', '6', '5') /* HEVC pa= rsed slices */ #define V4L2_PIX_FMT_AV1_FRAME v4l2_fourcc('A', 'V', '1', 'F') /* AV1 pars= ed frame */ +#define V4L2_PIX_FMT_AV1 v4l2_fourcc('A', 'V', '0', '1') /* AV1 */ #define V4L2_PIX_FMT_SPK v4l2_fourcc('S', 'P', 'K', '0') /* Sorenson = Spark */ #define V4L2_PIX_FMT_RV30 v4l2_fourcc('R', 'V', '3', '0') /* RealVideo= 8 */ #define V4L2_PIX_FMT_RV40 v4l2_fourcc('R', 'V', '4', '0') /* RealVideo= 9 & 10 */ --=20 2.34.1 From nobody Sun Dec 14 05:53:37 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ABFA53081C2 for ; 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Signed-off-by: Deepa Guthyappa Madivalara Reviewed-by: Bryan O'Donoghue --- drivers/media/v4l2-core/v4l2-ioctl.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/media/v4l2-core/v4l2-ioctl.c b/drivers/media/v4l2-core= /v4l2-ioctl.c index 01cf52c3ea33e1a01e1b306036ba4e57ef5c95d0..bdfdf45c5de2f2ce885f2190077= 18a54b5c86251 100644 --- a/drivers/media/v4l2-core/v4l2-ioctl.c +++ b/drivers/media/v4l2-core/v4l2-ioctl.c @@ -1542,6 +1542,7 @@ static void v4l_fill_fmtdesc(struct v4l2_fmtdesc *fmt) case V4L2_PIX_FMT_QC10C: descr =3D "QCOM Compressed 10-bit Format"; brea= k; case V4L2_PIX_FMT_AJPG: descr =3D "Aspeed JPEG"; break; case V4L2_PIX_FMT_AV1_FRAME: descr =3D "AV1 Frame"; break; + case V4L2_PIX_FMT_AV1: descr =3D "AV1 OBU stream"; break; case V4L2_PIX_FMT_MT2110T: descr =3D "Mediatek 10bit Tile Mode"; break; case V4L2_PIX_FMT_MT2110R: descr =3D "Mediatek 10bit Raster Mode"; break; case V4L2_PIX_FMT_HEXTILE: descr =3D "Hextile Compressed Format"; break; --=20 2.34.1 From nobody Sun Dec 14 05:53:37 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 67AD52F7446 for ; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-29498d40a73sm177671325ad.74.2025.10.30.00.00.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Oct 2025 00:00:26 -0700 (PDT) From: Deepa Guthyappa Madivalara Date: Thu, 30 Oct 2025 00:00:08 -0700 Subject: [PATCH v3 3/5] media: iris: Add support for AV1 format in iris decoder Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251030-av1d_stateful_v3-v3-3-a1184de52fc4@oss.qualcomm.com> References: <20251030-av1d_stateful_v3-v3-0-a1184de52fc4@oss.qualcomm.com> In-Reply-To: <20251030-av1d_stateful_v3-v3-0-a1184de52fc4@oss.qualcomm.com> To: Mauro Carvalho Chehab , Vikash Garodia , Dikshita Agarwal , Abhinav Kumar , Bryan O'Donoghue Cc: linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, kernel test robot , Deepa Guthyappa Madivalara , Bryan O'Donoghue X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1761807623; l=7589; i=deepa.madivalara@oss.qualcomm.com; s=20250814; h=from:subject:message-id; bh=Omy9/5Kj5+LGcB63VdSV5IrNWZc52iR3S5f9i+4vMDk=; b=gDYAUoskczFHkGZqeuOQ4tyXSmb6fwaFM2Mbwpp2OzyoLoobd/7JEwOCX0eMkkZlYL5jfgAc/ i7pmO/TQSIPDAtAE7SGm7RW+DLEOn0M9ouB+Y6h0XBo4w2zh+NQHY+4 X-Developer-Key: i=deepa.madivalara@oss.qualcomm.com; a=ed25519; pk=MOEXgyokievn+bgpHdS6Ixh/KQYyS90z2mqIbQ822FQ= X-Proofpoint-ORIG-GUID: ASMANArRG2GB8MxNOdQHonl_wUqVXDIn X-Proofpoint-GUID: ASMANArRG2GB8MxNOdQHonl_wUqVXDIn X-Authority-Analysis: v=2.4 cv=Cf4FJbrl c=1 sm=1 tr=0 ts=69030d0c cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=x6icFKpwvdMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=KKAkSRfTAAAA:8 a=EUspDBNiAAAA:8 a=Dfn2-qcXI_AzomQv4o8A:9 a=QEXdDO2ut3YA:10 a=1OuFwYUASf3TG4hYMiVC:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDMwMDA1NSBTYWx0ZWRfX7uw2ebn1+/QL 0NUIKUnlE8ooCUlJMoGfXSYJOn/hVLV1iw2sOTUmx58U+61c7ESMvcA6hmnHIIuONq/N34OSclk fTi56C40WnJsAA1R9iYTXQzW4uugbQ4DgicSBdkFph0Gvd8T8QMcNoD15UfGZac1XhQOq+FY294 9hqzBROYBh9THdvgLrbdp2wWMDhofGrfUJ1uY+kLkti9k+if6FUJGdzklVqeSmBIDOtfm/wzWAl ghtwla95Zw4X/r5RQSUc7lzVSiuoWX1mLzde6gV3rU3F2U8z/Fza4DSXUDE8nnChVM0XgzBf5pk HIhnwNHyVWgIBg1bhUaxCXr8w4sG8xI5wvVv/+DZYxYOh2qlOiP4Fv/wC9X5wBNEtxxO63+BH+Z pj2Bz2lBm0Xf4K8iPuySHl+W0wMOCQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-10-30_01,2025-10-29_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 suspectscore=0 phishscore=0 malwarescore=0 impostorscore=0 clxscore=1015 priorityscore=1501 lowpriorityscore=0 spamscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2510300055 Extend iris decoder driver to support format V4L2_PIX_FMT_AV1. This change updates the format enumeration (VIDIOC_ENUM_FMT) and allows setting AV1 format via VIDIOC_S_FMT for gen2 and beyond. Gen1 iris hardware decoder does not support AV1 format. Reviewed-by: Bryan O'Donoghue Signed-off-by: Deepa Guthyappa Madivalara Reviewed-by: Dikshita Agarwal --- .../platform/qcom/iris/iris_hfi_gen2_defines.h | 1 + drivers/media/platform/qcom/iris/iris_instance.h | 1 + .../platform/qcom/iris/iris_platform_common.h | 2 ++ .../media/platform/qcom/iris/iris_platform_gen2.c | 23 ++++++++++++++++++= ++++ .../platform/qcom/iris/iris_platform_sm8250.c | 17 ++++++++++++++++ drivers/media/platform/qcom/iris/iris_vdec.c | 23 ++++--------------= ---- 6 files changed, 48 insertions(+), 19 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen2_defines.h b/dri= vers/media/platform/qcom/iris/iris_hfi_gen2_defines.h index 1b6a4dbac828ffea53c1be0d3624a033c283c972..3d56f257bc5620aacec2bb7e112= 53dc7c83b7db9 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen2_defines.h +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen2_defines.h @@ -139,6 +139,7 @@ enum hfi_codec_type { HFI_CODEC_DECODE_HEVC =3D 3, HFI_CODEC_ENCODE_HEVC =3D 4, HFI_CODEC_DECODE_VP9 =3D 5, + HFI_CODEC_DECODE_AV1 =3D 7, }; =20 enum hfi_picture_type { diff --git a/drivers/media/platform/qcom/iris/iris_instance.h b/drivers/med= ia/platform/qcom/iris/iris_instance.h index 62fbb30691ff967212022308fa53ff221fa24ce9..7e4f5f1dd8921c57db039fbd4bc= 2f321891348db 100644 --- a/drivers/media/platform/qcom/iris/iris_instance.h +++ b/drivers/media/platform/qcom/iris/iris_instance.h @@ -19,6 +19,7 @@ enum iris_fmt_type_out { IRIS_FMT_H264, IRIS_FMT_HEVC, IRIS_FMT_VP9, + IRIS_FMT_AV1, }; =20 enum iris_fmt_type_cap { diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/driv= ers/media/platform/qcom/iris/iris_platform_common.h index 58d05e0a112eed25faea027a34c719c89d6c3897..9aca70b4c0690f0d8d799e2a997= 6bd20d6bb8c94 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -214,6 +214,8 @@ struct iris_platform_data { u64 dma_mask; const char *fwname; u32 pas_id; + struct iris_fmt *inst_iris_fmts; + u32 inst_iris_fmts_size; struct platform_inst_caps *inst_caps; struct platform_inst_fw_cap *inst_fw_caps_dec; u32 inst_fw_caps_dec_size; diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/driver= s/media/platform/qcom/iris/iris_platform_gen2.c index 69c952c68e939f305f25511e2e4763487ec8e0de..3b61723dbf27e9ba8d427686e44= cf048a0ab7c5b 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c +++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c @@ -19,6 +19,25 @@ #define VIDEO_ARCH_LX 1 #define BITRATE_MAX 245000000 =20 +static struct iris_fmt platform_fmts_sm8550_dec[] =3D { + [IRIS_FMT_H264] =3D { + .pixfmt =3D V4L2_PIX_FMT_H264, + .type =3D V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, + }, + [IRIS_FMT_HEVC] =3D { + .pixfmt =3D V4L2_PIX_FMT_HEVC, + .type =3D V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, + }, + [IRIS_FMT_VP9] =3D { + .pixfmt =3D V4L2_PIX_FMT_VP9, + .type =3D V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, + }, + [IRIS_FMT_AV1] =3D { + .pixfmt =3D V4L2_PIX_FMT_AV1, + .type =3D V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, + }, +}; + static struct platform_inst_fw_cap inst_fw_cap_sm8550_dec[] =3D { { .cap_id =3D PROFILE_H264, @@ -761,6 +780,8 @@ struct iris_platform_data sm8550_data =3D { .dma_mask =3D 0xe0000000 - 1, .fwname =3D "qcom/vpu/vpu30_p4.mbn", .pas_id =3D IRIS_PAS_ID, + .inst_iris_fmts =3D platform_fmts_sm8550_dec, + .inst_iris_fmts_size =3D ARRAY_SIZE(platform_fmts_sm8550_dec), .inst_caps =3D &platform_inst_cap_sm8550, .inst_fw_caps_dec =3D inst_fw_cap_sm8550_dec, .inst_fw_caps_dec_size =3D ARRAY_SIZE(inst_fw_cap_sm8550_dec), @@ -853,6 +874,8 @@ struct iris_platform_data sm8650_data =3D { .dma_mask =3D 0xe0000000 - 1, .fwname =3D "qcom/vpu/vpu33_p4.mbn", .pas_id =3D IRIS_PAS_ID, + .inst_iris_fmts =3D platform_fmts_sm8550_dec, + .inst_iris_fmts_size =3D ARRAY_SIZE(platform_fmts_sm8550_dec), .inst_caps =3D &platform_inst_cap_sm8550, .inst_fw_caps_dec =3D inst_fw_cap_sm8550_dec, .inst_fw_caps_dec_size =3D ARRAY_SIZE(inst_fw_cap_sm8550_dec), diff --git a/drivers/media/platform/qcom/iris/iris_platform_sm8250.c b/driv= ers/media/platform/qcom/iris/iris_platform_sm8250.c index 16486284f8acccf6a95a27f6003e885226e28f4d..8342a0b6f825b385192baedfc67= c50bba7661470 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_sm8250.c +++ b/drivers/media/platform/qcom/iris/iris_platform_sm8250.c @@ -17,6 +17,21 @@ #define BITRATE_PEAK_DEFAULT (BITRATE_DEFAULT * 2) #define BITRATE_STEP 100 =20 +static struct iris_fmt platform_fmts_sm8250_dec[] =3D { + [IRIS_FMT_H264] =3D { + .pixfmt =3D V4L2_PIX_FMT_H264, + .type =3D V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, + }, + [IRIS_FMT_HEVC] =3D { + .pixfmt =3D V4L2_PIX_FMT_HEVC, + .type =3D V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, + }, + [IRIS_FMT_VP9] =3D { + .pixfmt =3D V4L2_PIX_FMT_VP9, + .type =3D V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, + }, +}; + static struct platform_inst_fw_cap inst_fw_cap_sm8250_dec[] =3D { { .cap_id =3D PIPE, @@ -337,6 +352,8 @@ struct iris_platform_data sm8250_data =3D { .dma_mask =3D 0xe0000000 - 1, .fwname =3D "qcom/vpu-1.0/venus.mbn", .pas_id =3D IRIS_PAS_ID, + .inst_iris_fmts =3D platform_fmts_sm8250_dec, + .inst_iris_fmts_size =3D ARRAY_SIZE(platform_fmts_sm8250_dec), .inst_caps =3D &platform_inst_cap_sm8250, .inst_fw_caps_dec =3D inst_fw_cap_sm8250_dec, .inst_fw_caps_dec_size =3D ARRAY_SIZE(inst_fw_cap_sm8250_dec), diff --git a/drivers/media/platform/qcom/iris/iris_vdec.c b/drivers/media/p= latform/qcom/iris/iris_vdec.c index 69ffe52590d3acf8d595f856fb1dbd81f3073721..bf7b9c621cb7255367c06f144c0= 3c3faa69372e0 100644 --- a/drivers/media/platform/qcom/iris/iris_vdec.c +++ b/drivers/media/platform/qcom/iris/iris_vdec.c @@ -67,21 +67,6 @@ void iris_vdec_inst_deinit(struct iris_inst *inst) kfree(inst->fmt_src); } =20 -static const struct iris_fmt iris_vdec_formats_out[] =3D { - [IRIS_FMT_H264] =3D { - .pixfmt =3D V4L2_PIX_FMT_H264, - .type =3D V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, - }, - [IRIS_FMT_HEVC] =3D { - .pixfmt =3D V4L2_PIX_FMT_HEVC, - .type =3D V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, - }, - [IRIS_FMT_VP9] =3D { - .pixfmt =3D V4L2_PIX_FMT_VP9, - .type =3D V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, - }, -}; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-29498d40a73sm177671325ad.74.2025.10.30.00.00.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Oct 2025 00:00:27 -0700 (PDT) From: Deepa Guthyappa Madivalara Date: Thu, 30 Oct 2025 00:00:09 -0700 Subject: [PATCH v3 4/5] media: iris: Define AV1-specific platform capabilities and properties Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251030-av1d_stateful_v3-v3-4-a1184de52fc4@oss.qualcomm.com> References: <20251030-av1d_stateful_v3-v3-0-a1184de52fc4@oss.qualcomm.com> In-Reply-To: <20251030-av1d_stateful_v3-v3-0-a1184de52fc4@oss.qualcomm.com> To: Mauro Carvalho Chehab , Vikash Garodia , Dikshita Agarwal , Abhinav Kumar , Bryan O'Donoghue Cc: linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, kernel test robot , Deepa Guthyappa Madivalara , Bryan O'Donoghue X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1761807623; l=24496; i=deepa.madivalara@oss.qualcomm.com; s=20250814; h=from:subject:message-id; bh=ZL2Ztvm7JxlK0TBsmXbngLxQ37MSEJilZTNKWVvh2MQ=; b=Prki8vUvzJPt/Fq0A3iksfNlssLWXt9UK4WixZ5Tp2L19S0KqQhaguPKYiW9939x0R+4kSOkv ncC8AiLdtI0D0ot7u66/ws8V7jPai9ycQ8McigkuOUZ9564xaMjN9re X-Developer-Key: i=deepa.madivalara@oss.qualcomm.com; a=ed25519; pk=MOEXgyokievn+bgpHdS6Ixh/KQYyS90z2mqIbQ822FQ= X-Proofpoint-GUID: R_QO7xagXAbr1wMRqgkAq5eJhxx_jPe6 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDMwMDA1NSBTYWx0ZWRfX64WryULcwZKD mHWoCyeJ51cgqFJcAr3FStjR4Ho3qjFqlExlzG60db7ZyTopDxhuxrfEynk/18he+7YaKrxZS+d Wa+lO+uOFJ2PJIvUxc5D8yG/pO8Tz79SadWR5A2iNTChjGNKm8ODCJtt1+NHWJUd6UvXCGmhUgz MocmDuIgp4KjzgFEl58AWnnUGMlFlxAW0aFLLM2DZsoIhYO5JljjtRV1AbyfKKJt8XkFc9qGd5q odUw1cQEXrK6GN5ZKZLP2FvRpzZQHnGh0DRZfb+s42aVWaCkUDiVx6nGvk9jWZNqYvfBBW7gyhy Tr/0sUYhWad4kfg3hNktiXod9HQ4yCeidMkr60afsHEWX2ks/UM1yKs9xGgXGMUKP7B6o4ZBjQH nnJgTHne7qaClLkg1zXqFDtRw3Gm1g== X-Authority-Analysis: v=2.4 cv=a/Q9NESF c=1 sm=1 tr=0 ts=69030d0f cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=x6icFKpwvdMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=KKAkSRfTAAAA:8 a=EUspDBNiAAAA:8 a=AP-cJNIzh2fI31YzWqcA:9 a=QEXdDO2ut3YA:10 a=324X-CrmTo6CU4MGRt3R:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-ORIG-GUID: R_QO7xagXAbr1wMRqgkAq5eJhxx_jPe6 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-10-30_01,2025-10-29_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 priorityscore=1501 lowpriorityscore=0 malwarescore=0 suspectscore=0 phishscore=0 spamscore=0 adultscore=0 clxscore=1015 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2510300055 Defining platform specific capabilities specific to AV1 decoder. Set and subscribe to manadatory properties to firmware for AV1. Reviewed-by: Bryan O'Donoghue Signed-off-by: Deepa Guthyappa Madivalara --- drivers/media/platform/qcom/iris/iris_buffer.h | 1 + drivers/media/platform/qcom/iris/iris_ctrls.c | 8 ++ drivers/media/platform/qcom/iris/iris_hfi_common.h | 3 + .../platform/qcom/iris/iris_hfi_gen2_command.c | 94 ++++++++++++++- .../platform/qcom/iris/iris_hfi_gen2_defines.h | 10 +- .../platform/qcom/iris/iris_hfi_gen2_response.c | 22 ++++ .../platform/qcom/iris/iris_platform_common.h | 13 ++ .../media/platform/qcom/iris/iris_platform_gen2.c | 133 +++++++++++++++++= +++- drivers/media/platform/qcom/iris/iris_vidc.c | 1 + 9 files changed, 279 insertions(+), 6 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_buffer.h b/drivers/media= /platform/qcom/iris/iris_buffer.h index 325d30fce5c99185b61ff989fbfd4de9a56762b2..5ef365d9236c7cbdee24a461478= 9b3191881968b 100644 --- a/drivers/media/platform/qcom/iris/iris_buffer.h +++ b/drivers/media/platform/qcom/iris/iris_buffer.h @@ -42,6 +42,7 @@ enum iris_buffer_type { BUF_SCRATCH_1, BUF_SCRATCH_2, BUF_VPSS, + BUF_PARTIAL, BUF_TYPE_MAX, }; =20 diff --git a/drivers/media/platform/qcom/iris/iris_ctrls.c b/drivers/media/= platform/qcom/iris/iris_ctrls.c index 754a5ad718bc37630bb861012301df7a2e7342a1..620c7e1bd273e25febd8ca70dd1= dcfb0b862692b 100644 --- a/drivers/media/platform/qcom/iris/iris_ctrls.c +++ b/drivers/media/platform/qcom/iris/iris_ctrls.c @@ -98,6 +98,10 @@ static enum platform_inst_fw_cap_type iris_get_cap_id(u3= 2 id) return B_FRAME_QP_H264; case V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_QP: return B_FRAME_QP_HEVC; + case V4L2_CID_MPEG_VIDEO_AV1_PROFILE: + return PROFILE_AV1; + case V4L2_CID_MPEG_VIDEO_AV1_LEVEL: + return LEVEL_AV1; default: return INST_FW_CAP_MAX; } @@ -185,6 +189,10 @@ static u32 iris_get_v4l2_id(enum platform_inst_fw_cap_= type cap_id) return V4L2_CID_MPEG_VIDEO_H264_B_FRAME_QP; case B_FRAME_QP_HEVC: return V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_QP; + case PROFILE_AV1: + return V4L2_CID_MPEG_VIDEO_AV1_PROFILE; + case LEVEL_AV1: + return V4L2_CID_MPEG_VIDEO_AV1_LEVEL; default: return 0; } diff --git a/drivers/media/platform/qcom/iris/iris_hfi_common.h b/drivers/m= edia/platform/qcom/iris/iris_hfi_common.h index b51471fb32c70acee44c37f8e9dce0c6bc0b6ccc..3edb5ae582b49bea2e2408c4a5c= fc0a742adc05f 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_common.h +++ b/drivers/media/platform/qcom/iris/iris_hfi_common.h @@ -141,6 +141,9 @@ struct hfi_subscription_params { u32 profile; u32 level; u32 tier; + u32 drap; + u32 film_grain; + u32 super_block; }; =20 u32 iris_hfi_get_v4l2_color_primaries(u32 hfi_primaries); diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c b/dri= vers/media/platform/qcom/iris/iris_hfi_gen2_command.c index 6a772db2ec33fb002d8884753a41dc98b3a8439d..ee99ba206b64bb3367d0a1cdd76= 34e3241f9ed83 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c @@ -10,6 +10,7 @@ =20 #define UNSPECIFIED_COLOR_FORMAT 5 #define NUM_SYS_INIT_PACKETS 8 +#define NUM_COMV_AV1 18 =20 #define SYS_INIT_PKT_SIZE (sizeof(struct iris_hfi_header) + \ NUM_SYS_INIT_PACKETS * (sizeof(struct iris_hfi_packet) + sizeof(u32))) @@ -121,6 +122,7 @@ static u32 iris_hfi_gen2_get_port_from_buf_type(struct = iris_inst *inst, case BUF_COMV: case BUF_NON_COMV: case BUF_LINE: + case BUF_PARTIAL: return HFI_PORT_BITSTREAM; case BUF_OUTPUT: case BUF_DPB: @@ -380,6 +382,9 @@ static int iris_hfi_gen2_set_profile(struct iris_inst *= inst, u32 plane) case V4L2_PIX_FMT_H264: profile =3D inst->fw_caps[PROFILE_H264].value; break; + case V4L2_PIX_FMT_AV1: + profile =3D inst->fw_caps[PROFILE_AV1].value; + break; } =20 inst_hfi_gen2->src_subcr_params.profile =3D profile; @@ -409,6 +414,9 @@ static int iris_hfi_gen2_set_level(struct iris_inst *in= st, u32 plane) case V4L2_PIX_FMT_H264: level =3D inst->fw_caps[LEVEL_H264].value; break; + case V4L2_PIX_FMT_AV1: + level =3D inst->fw_caps[LEVEL_AV1].value; + break; } =20 inst_hfi_gen2->src_subcr_params.level =3D level; @@ -496,10 +504,12 @@ static int iris_hfi_gen2_set_linear_stride_scanline(s= truct iris_inst *inst, u32 =20 static int iris_hfi_gen2_set_tier(struct iris_inst *inst, u32 plane) { - struct iris_inst_hfi_gen2 *inst_hfi_gen2 =3D to_iris_inst_hfi_gen2(inst); u32 port =3D iris_hfi_gen2_get_port(inst, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLA= NE); + struct iris_inst_hfi_gen2 *inst_hfi_gen2 =3D to_iris_inst_hfi_gen2(inst); u32 tier =3D inst->fw_caps[TIER].value; =20 + tier =3D (inst->codec =3D=3D V4L2_PIX_FMT_AV1) ? inst->fw_caps[TIER_AV1].= value : + inst->fw_caps[TIER].value; inst_hfi_gen2->src_subcr_params.tier =3D tier; =20 return iris_hfi_gen2_session_set_property(inst, @@ -525,6 +535,40 @@ static int iris_hfi_gen2_set_frame_rate(struct iris_in= st *inst, u32 plane) sizeof(u32)); } =20 +static int iris_hfi_gen2_set_film_grain(struct iris_inst *inst, u32 plane) +{ + u32 port =3D iris_hfi_gen2_get_port(inst, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLA= NE); + struct iris_inst_hfi_gen2 *inst_hfi_gen2 =3D to_iris_inst_hfi_gen2(inst); + u32 film_grain =3D inst->fw_caps[FILM_GRAIN].value; + + inst_hfi_gen2->src_subcr_params.film_grain =3D film_grain; + + return iris_hfi_gen2_session_set_property(inst, + HFI_PROP_AV1_FILM_GRAIN_PRESENT, + HFI_HOST_FLAGS_NONE, + port, + HFI_PAYLOAD_U32_ENUM, + &film_grain, + sizeof(u32)); +} + +static int iris_hfi_gen2_set_super_block(struct iris_inst *inst, u32 plane) +{ + u32 port =3D iris_hfi_gen2_get_port(inst, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLA= NE); + struct iris_inst_hfi_gen2 *inst_hfi_gen2 =3D to_iris_inst_hfi_gen2(inst); + u32 super_block =3D inst->fw_caps[SUPER_BLOCK].value; + + inst_hfi_gen2->src_subcr_params.super_block =3D super_block; + + return iris_hfi_gen2_session_set_property(inst, + HFI_PROP_AV1_SUPER_BLOCK_ENABLED, + HFI_HOST_FLAGS_NONE, + port, + HFI_PAYLOAD_U32_ENUM, + &super_block, + sizeof(u32)); +} + static int iris_hfi_gen2_session_set_config_params(struct iris_inst *inst,= u32 plane) { const struct iris_platform_data *pdata =3D inst->core->iris_platform_data; @@ -548,6 +592,9 @@ static int iris_hfi_gen2_session_set_config_params(stru= ct iris_inst *inst, u32 p {HFI_PROP_LINEAR_STRIDE_SCANLINE, iris_hfi_gen2_set_linear_stride_sc= anline }, {HFI_PROP_TIER, iris_hfi_gen2_set_tier = }, {HFI_PROP_FRAME_RATE, iris_hfi_gen2_set_frame_rate = }, + {HFI_PROP_AV1_FILM_GRAIN_PRESENT, iris_hfi_gen2_set_film_grain = }, + {HFI_PROP_AV1_SUPER_BLOCK_ENABLED, iris_hfi_gen2_set_super_block = }, + {HFI_PROP_OPB_ENABLE, iris_hfi_gen2_set_opb_enable = }, }; =20 if (inst->domain =3D=3D DECODER) { @@ -561,12 +608,20 @@ static int iris_hfi_gen2_session_set_config_params(st= ruct iris_inst *inst, u32 p } else if (inst->codec =3D=3D V4L2_PIX_FMT_VP9) { config_params =3D pdata->dec_input_config_params_vp9; config_params_size =3D pdata->dec_input_config_params_vp9_size; + } else if (inst->codec =3D=3D V4L2_PIX_FMT_AV1) { + config_params =3D pdata->dec_input_config_params_av1; + config_params_size =3D pdata->dec_input_config_params_av1_size; } else { return -EINVAL; } } else { - config_params =3D pdata->dec_output_config_params; - config_params_size =3D pdata->dec_output_config_params_size; + if (inst->codec =3D=3D V4L2_PIX_FMT_AV1) { + config_params =3D pdata->dec_output_config_params_av1; + config_params_size =3D pdata->dec_output_config_params_av1_size; + } else { + config_params =3D pdata->dec_output_config_params; + config_params_size =3D pdata->dec_output_config_params_size; + } } } else { if (V4L2_TYPE_IS_OUTPUT(plane)) { @@ -615,6 +670,9 @@ static int iris_hfi_gen2_session_set_codec(struct iris_= inst *inst) break; case V4L2_PIX_FMT_VP9: codec =3D HFI_CODEC_DECODE_VP9; + break; + case V4L2_PIX_FMT_AV1: + codec =3D HFI_CODEC_DECODE_AV1; } =20 iris_hfi_gen2_packet_session_property(inst, @@ -780,6 +838,11 @@ static int iris_hfi_gen2_subscribe_change_param(struct= iris_inst *inst, u32 plan change_param_size =3D core->iris_platform_data->dec_input_config_params_vp9_size; break; + case V4L2_PIX_FMT_AV1: + change_param =3D core->iris_platform_data->dec_input_config_params_av1; + change_param_size =3D + core->iris_platform_data->dec_input_config_params_av1_size; + break; } =20 payload[0] =3D HFI_MODE_PORT_SETTINGS_CHANGE; @@ -862,6 +925,16 @@ static int iris_hfi_gen2_subscribe_change_param(struct= iris_inst *inst, u32 plan payload_size =3D sizeof(u32); payload_type =3D HFI_PAYLOAD_U32; break; + case HFI_PROP_AV1_FILM_GRAIN_PRESENT: + payload[0] =3D subsc_params.film_grain; + payload_size =3D sizeof(u32); + payload_type =3D HFI_PAYLOAD_U32; + break; + case HFI_PROP_AV1_SUPER_BLOCK_ENABLED: + payload[0] =3D subsc_params.super_block; + payload_size =3D sizeof(u32); + payload_type =3D HFI_PAYLOAD_U32; + break; default: prop_type =3D 0; ret =3D -EINVAL; @@ -917,6 +990,11 @@ static int iris_hfi_gen2_subscribe_property(struct iri= s_inst *inst, u32 plane) subscribe_prop_size =3D core->iris_platform_data->dec_output_prop_vp9_size; break; + case V4L2_PIX_FMT_AV1: + subcribe_prop =3D core->iris_platform_data->dec_output_prop_av1; + subscribe_prop_size =3D + core->iris_platform_data->dec_output_prop_av1_size; + break; } } =20 @@ -1092,6 +1170,8 @@ static u32 iris_hfi_gen2_buf_type_from_driver(u32 dom= ain, enum iris_buffer_type return HFI_BUFFER_ARP; case BUF_VPSS: return HFI_BUFFER_VPSS; + case BUF_PARTIAL: + return HFI_BUFFER_PARTIAL_DATA; default: return 0; } @@ -1104,7 +1184,13 @@ static int iris_set_num_comv(struct iris_inst *inst) u32 num_comv; =20 caps =3D core->iris_platform_data->inst_caps; - num_comv =3D caps->num_comv; + + /* + * AV1 needs more comv buffers than other codecs. + * Update accordingly. + */ + num_comv =3D (inst->codec =3D=3D V4L2_PIX_FMT_AV1) ? + NUM_COMV_AV1 : caps->num_comv; =20 return core->hfi_ops->session_set_property(inst, HFI_PROP_COMV_BUFFER_COUNT, diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen2_defines.h b/dri= vers/media/platform/qcom/iris/iris_hfi_gen2_defines.h index 3d56f257bc5620aacec2bb7e11253dc7c83b7db9..12b4c6517bf094e3e98332a1b2b= 70ac5a349b863 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen2_defines.h +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen2_defines.h @@ -89,10 +89,18 @@ enum hfi_seq_header_mode { #define HFI_PROP_DEC_START_FROM_RAP_FRAME 0x03000169 #define HFI_PROP_NO_OUTPUT 0x0300016a #define HFI_PROP_BUFFER_MARK 0x0300016c +#define HFI_PROP_WORST_COMPRESSION_RATIO 0x03000174 +#define HFI_PROP_WORST_COMPLEXITY_FACTOR 0x03000175 #define HFI_PROP_RAW_RESOLUTION 0x03000178 #define HFI_PROP_TOTAL_PEAK_BITRATE 0x0300017C -#define HFI_PROP_OPB_ENABLE 0x03000184 +#define HFI_PROP_AV1_FILM_GRAIN_PRESENT 0x03000180 +#define HFI_PROP_AV1_SUPER_BLOCK_ENABLED 0x03000181 +#define HFI_PROP_AV1_OP_POINT 0x03000182 +#define HFI_PROP_OPB_ENABLE 0x03000184 +#define HFI_PROP_AV1_TILE_ROWS_COLUMNS 0x03000187 +#define HFI_PROP_AV1_DRAP_CONFIG 0x03000189 #define HFI_PROP_COMV_BUFFER_COUNT 0x03000193 +#define HFI_PROP_AV1_UNIFORM_TILE_SPACING 0x03000197 #define HFI_PROP_END 0x03FFFFFF =20 #define HFI_SESSION_ERROR_BEGIN 0x04000000 diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c b/dr= ivers/media/platform/qcom/iris/iris_hfi_gen2_response.c index 2f1f118eae4f6462ab1aa1d16844b34e6e699f1e..eb3373f0ad4a1b26fb847db0244= 9ec8d8cb3bdbb 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c @@ -54,6 +54,8 @@ static u32 iris_hfi_gen2_buf_type_to_driver(struct iris_i= nst *inst, return BUF_SCRATCH_2; case HFI_BUFFER_PERSIST: return BUF_PERSIST; + case HFI_BUFFER_PARTIAL_DATA: + return BUF_PARTIAL; default: return 0; } @@ -72,6 +74,7 @@ static bool iris_hfi_gen2_is_valid_hfi_buffer_type(u32 bu= ffer_type) case HFI_BUFFER_DPB: case HFI_BUFFER_PERSIST: case HFI_BUFFER_VPSS: + case HFI_BUFFER_PARTIAL_DATA: return true; default: return false; @@ -596,6 +599,10 @@ static void iris_hfi_gen2_read_input_subcr_params(stru= ct iris_inst *inst) inst->fw_caps[PROFILE_H264].value =3D subsc_params.profile; inst->fw_caps[LEVEL_H264].value =3D subsc_params.level; break; + case V4L2_PIX_FMT_AV1: + inst->fw_caps[PROFILE_AV1].value =3D subsc_params.profile; + inst->fw_caps[LEVEL_AV1].value =3D subsc_params.level; + break; } =20 inst->fw_caps[POC].value =3D subsc_params.pic_order_cnt; @@ -608,6 +615,11 @@ static void iris_hfi_gen2_read_input_subcr_params(stru= ct iris_inst *inst) iris_inst_change_state(inst, IRIS_INST_ERROR); } =20 + if (inst->codec =3D=3D V4L2_PIX_FMT_AV1) { + inst->fw_caps[FILM_GRAIN].value =3D subsc_params.film_grain; + inst->fw_caps[SUPER_BLOCK].value =3D subsc_params.super_block; + } + inst->fw_min_count =3D subsc_params.fw_min_count; inst->buffers[BUF_OUTPUT].min_count =3D iris_vpu_buf_count(inst, BUF_OUTP= UT); inst->buffers[BUF_OUTPUT].size =3D pixmp_op->plane_fmt[0].sizeimage; @@ -711,6 +723,12 @@ static int iris_hfi_gen2_handle_session_property(struc= t iris_inst *inst, case HFI_PROP_NO_OUTPUT: inst_hfi_gen2->hfi_frame_info.no_output =3D 1; break; + case HFI_PROP_AV1_FILM_GRAIN_PRESENT: + inst_hfi_gen2->src_subcr_params.film_grain =3D pkt->payload[0]; + break; + case HFI_PROP_AV1_SUPER_BLOCK_ENABLED: + inst_hfi_gen2->src_subcr_params.super_block =3D pkt->payload[0]; + break; case HFI_PROP_QUALITY_MODE: case HFI_PROP_STAGE: case HFI_PROP_PIPE: @@ -841,6 +859,10 @@ static void iris_hfi_gen2_init_src_change_param(struct= iris_inst *inst) subsc_params->profile =3D inst->fw_caps[PROFILE_H264].value; subsc_params->level =3D inst->fw_caps[LEVEL_H264].value; break; + case V4L2_PIX_FMT_AV1: + subsc_params->profile =3D inst->fw_caps[PROFILE_AV1].value; + subsc_params->level =3D inst->fw_caps[LEVEL_AV1].value; + break; } =20 subsc_params->pic_order_cnt =3D inst->fw_caps[POC].value; diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/driv= ers/media/platform/qcom/iris/iris_platform_common.h index 9aca70b4c0690f0d8d799e2a9976bd20d6bb8c94..19f0660f0388499ab71a1413b2c= 05f891bd5d511 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -100,6 +100,13 @@ enum platform_inst_fw_cap_type { LEVEL_H264, LEVEL_HEVC, LEVEL_VP9, + PROFILE_AV1, + LEVEL_AV1, + TIER_AV1, + DRAP, + FILM_GRAIN, + SUPER_BLOCK, + ENH_LAYER_COUNT, INPUT_BUF_HOST_MAX_COUNT, OUTPUT_BUF_HOST_MAX_COUNT, STAGE, @@ -237,8 +244,12 @@ struct iris_platform_data { unsigned int dec_input_config_params_hevc_size; const u32 *dec_input_config_params_vp9; unsigned int dec_input_config_params_vp9_size; + const u32 *dec_input_config_params_av1; + unsigned int dec_input_config_params_av1_size; const u32 *dec_output_config_params; unsigned int dec_output_config_params_size; + const u32 *dec_output_config_params_av1; + unsigned int dec_output_config_params_av1_size; const u32 *enc_input_config_params; unsigned int enc_input_config_params_size; const u32 *enc_output_config_params; @@ -251,6 +262,8 @@ struct iris_platform_data { unsigned int dec_output_prop_hevc_size; const u32 *dec_output_prop_vp9; unsigned int dec_output_prop_vp9_size; + const u32 *dec_output_prop_av1; + unsigned int dec_output_prop_av1_size; const u32 *dec_ip_int_buf_tbl; unsigned int dec_ip_int_buf_tbl_size; const u32 *dec_op_int_buf_tbl; diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/driver= s/media/platform/qcom/iris/iris_platform_gen2.c index 3b61723dbf27e9ba8d427686e44cf048a0ab7c5b..9ac5541f528741e45b31634230d= a44d53012e659 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c +++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c @@ -64,6 +64,16 @@ static struct platform_inst_fw_cap inst_fw_cap_sm8550_de= c[] =3D { .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, .set =3D iris_set_u32_enum, }, + { + .cap_id =3D PROFILE_AV1, + .min =3D V4L2_MPEG_VIDEO_AV1_PROFILE_MAIN, + .max =3D V4L2_MPEG_VIDEO_AV1_PROFILE_MAIN, + .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_AV1_PROFILE_MAIN), + .value =3D V4L2_MPEG_VIDEO_AV1_PROFILE_MAIN, + .hfi_id =3D HFI_PROP_PROFILE, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + .set =3D iris_set_u32_enum, + }, { .cap_id =3D PROFILE_VP9, .min =3D V4L2_MPEG_VIDEO_VP9_PROFILE_0, @@ -147,6 +157,33 @@ static struct platform_inst_fw_cap inst_fw_cap_sm8550_= dec[] =3D { .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, .set =3D iris_set_u32_enum, }, + { + .cap_id =3D LEVEL_AV1, + .min =3D V4L2_MPEG_VIDEO_AV1_LEVEL_2_0, + .max =3D V4L2_MPEG_VIDEO_AV1_LEVEL_6_1, + .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_AV1_LEVEL_2_0) | + BIT(V4L2_MPEG_VIDEO_AV1_LEVEL_2_1) | + BIT(V4L2_MPEG_VIDEO_AV1_LEVEL_2_2) | + BIT(V4L2_MPEG_VIDEO_AV1_LEVEL_2_3) | + BIT(V4L2_MPEG_VIDEO_AV1_LEVEL_3_0) | + BIT(V4L2_MPEG_VIDEO_AV1_LEVEL_3_1) | + BIT(V4L2_MPEG_VIDEO_AV1_LEVEL_3_2) | + BIT(V4L2_MPEG_VIDEO_AV1_LEVEL_3_3) | + BIT(V4L2_MPEG_VIDEO_AV1_LEVEL_4_0) | + BIT(V4L2_MPEG_VIDEO_AV1_LEVEL_4_1) | + BIT(V4L2_MPEG_VIDEO_AV1_LEVEL_4_2) | + BIT(V4L2_MPEG_VIDEO_AV1_LEVEL_4_3) | + BIT(V4L2_MPEG_VIDEO_AV1_LEVEL_5_0) | + BIT(V4L2_MPEG_VIDEO_AV1_LEVEL_5_1) | + BIT(V4L2_MPEG_VIDEO_AV1_LEVEL_5_2) | + BIT(V4L2_MPEG_VIDEO_AV1_LEVEL_5_3) | + BIT(V4L2_MPEG_VIDEO_AV1_LEVEL_6_0) | + BIT(V4L2_MPEG_VIDEO_AV1_LEVEL_6_1), + .value =3D V4L2_MPEG_VIDEO_AV1_LEVEL_6_1, + .hfi_id =3D HFI_PROP_LEVEL, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + .set =3D iris_set_u32_enum, + }, { .cap_id =3D TIER, .min =3D V4L2_MPEG_VIDEO_HEVC_TIER_MAIN, @@ -158,6 +195,53 @@ static struct platform_inst_fw_cap inst_fw_cap_sm8550_= dec[] =3D { .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, .set =3D iris_set_u32_enum, }, + { + .cap_id =3D TIER_AV1, + .min =3D 0, + .max =3D 1, + .step_or_mask =3D 1, + .value =3D 0, + .hfi_id =3D HFI_PROP_TIER, + .flags =3D CAP_FLAG_INPUT_PORT, + .set =3D iris_set_u32, + }, + { + .cap_id =3D DRAP, + .min =3D 0, + .max =3D 1, + .step_or_mask =3D 1, + .value =3D 0, + .hfi_id =3D HFI_PROP_AV1_DRAP_CONFIG, + .flags =3D CAP_FLAG_INPUT_PORT, + .set =3D iris_set_u32, + }, + { + .cap_id =3D FILM_GRAIN, + .min =3D 0, + .max =3D 1, + .step_or_mask =3D 1, + .value =3D 0, + .hfi_id =3D HFI_PROP_AV1_FILM_GRAIN_PRESENT, + .flags =3D CAP_FLAG_VOLATILE, + }, + { + .cap_id =3D SUPER_BLOCK, + .min =3D 0, + .max =3D 1, + .step_or_mask =3D 1, + .value =3D 0, + .hfi_id =3D HFI_PROP_AV1_SUPER_BLOCK_ENABLED, + }, + { + .cap_id =3D ENH_LAYER_COUNT, + .min =3D 0, + .max =3D 1, + .step_or_mask =3D 1, + .value =3D 0, + .hfi_id =3D HFI_PROP_AV1_OP_POINT, + .flags =3D CAP_FLAG_INPUT_PORT, + .set =3D iris_set_u32, + }, { .cap_id =3D INPUT_BUF_HOST_MAX_COUNT, .min =3D DEFAULT_MAX_HOST_BUF_COUNT, @@ -701,6 +785,19 @@ static const u32 sm8550_vdec_input_config_param_vp9[] = =3D { HFI_PROP_LEVEL, }; =20 +static const u32 sm8550_vdec_input_config_param_av1[] =3D { + HFI_PROP_BITSTREAM_RESOLUTION, + HFI_PROP_CROP_OFFSETS, + HFI_PROP_LUMA_CHROMA_BIT_DEPTH, + HFI_PROP_BUFFER_FW_MIN_OUTPUT_COUNT, + HFI_PROP_PROFILE, + HFI_PROP_LEVEL, + HFI_PROP_TIER, + HFI_PROP_AV1_FILM_GRAIN_PRESENT, + HFI_PROP_AV1_SUPER_BLOCK_ENABLED, + HFI_PROP_SIGNAL_COLOR_INFO, +}; + static const u32 sm8550_venc_input_config_params[] =3D { HFI_PROP_COLOR_FORMAT, HFI_PROP_RAW_RESOLUTION, @@ -715,6 +812,12 @@ static const u32 sm8550_vdec_output_config_params[] = =3D { HFI_PROP_LINEAR_STRIDE_SCANLINE, }; =20 +static const u32 sm8550_vdec_output_config_param_av1[] =3D { + HFI_PROP_OPB_ENABLE, + HFI_PROP_COLOR_FORMAT, + HFI_PROP_LINEAR_STRIDE_SCANLINE, +}; + static const u32 sm8550_venc_output_config_params[] =3D { HFI_PROP_BITSTREAM_RESOLUTION, HFI_PROP_CROP_OFFSETS, @@ -738,11 +841,18 @@ static const u32 sm8550_vdec_subscribe_output_propert= ies_vp9[] =3D { HFI_PROP_PICTURE_TYPE, }; =20 +static const u32 sm8550_vdec_subscribe_output_properties_av1[] =3D { + HFI_PROP_PICTURE_TYPE, + HFI_PROP_WORST_COMPRESSION_RATIO, + HFI_PROP_WORST_COMPLEXITY_FACTOR, +}; + static const u32 sm8550_dec_ip_int_buf_tbl[] =3D { BUF_BIN, BUF_COMV, BUF_NON_COMV, BUF_LINE, + BUF_PARTIAL, }; =20 static const u32 sm8550_dec_op_int_buf_tbl[] =3D { @@ -807,11 +917,18 @@ struct iris_platform_data sm8550_data =3D { sm8550_vdec_input_config_param_vp9, .dec_input_config_params_vp9_size =3D ARRAY_SIZE(sm8550_vdec_input_config_param_vp9), + .dec_input_config_params_av1 =3D + sm8550_vdec_input_config_param_av1, + .dec_input_config_params_av1_size =3D + ARRAY_SIZE(sm8550_vdec_input_config_param_av1), .dec_output_config_params =3D sm8550_vdec_output_config_params, .dec_output_config_params_size =3D ARRAY_SIZE(sm8550_vdec_output_config_params), - + .dec_output_config_params_av1 =3D + sm8550_vdec_output_config_param_av1, + .dec_output_config_params_av1_size =3D + ARRAY_SIZE(sm8550_vdec_output_config_param_av1), .enc_input_config_params =3D sm8550_venc_input_config_params, .enc_input_config_params_size =3D @@ -832,6 +949,9 @@ struct iris_platform_data sm8550_data =3D { .dec_output_prop_vp9 =3D sm8550_vdec_subscribe_output_properties_vp9, .dec_output_prop_vp9_size =3D ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_vp9), + .dec_output_prop_av1 =3D sm8550_vdec_subscribe_output_properties_av1, + .dec_output_prop_av1_size =3D + ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_av1), =20 .dec_ip_int_buf_tbl =3D sm8550_dec_ip_int_buf_tbl, .dec_ip_int_buf_tbl_size =3D ARRAY_SIZE(sm8550_dec_ip_int_buf_tbl), @@ -901,10 +1021,18 @@ struct iris_platform_data sm8650_data =3D { sm8550_vdec_input_config_param_vp9, .dec_input_config_params_vp9_size =3D ARRAY_SIZE(sm8550_vdec_input_config_param_vp9), + .dec_input_config_params_av1 =3D + sm8550_vdec_input_config_param_av1, + .dec_input_config_params_av1_size =3D + ARRAY_SIZE(sm8550_vdec_input_config_param_av1), .dec_output_config_params =3D sm8550_vdec_output_config_params, .dec_output_config_params_size =3D ARRAY_SIZE(sm8550_vdec_output_config_params), + .dec_output_config_params_av1 =3D + sm8550_vdec_output_config_param_av1, + .dec_output_config_params_av1_size =3D + ARRAY_SIZE(sm8550_vdec_output_config_param_av1), =20 .enc_input_config_params =3D sm8550_venc_input_config_params, @@ -926,6 +1054,9 @@ struct iris_platform_data sm8650_data =3D { .dec_output_prop_vp9 =3D sm8550_vdec_subscribe_output_properties_vp9, .dec_output_prop_vp9_size =3D ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_vp9), + .dec_output_prop_av1 =3D sm8550_vdec_subscribe_output_properties_av1, + .dec_output_prop_av1_size =3D + ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_av1), =20 .dec_ip_int_buf_tbl =3D sm8550_dec_ip_int_buf_tbl, .dec_ip_int_buf_tbl_size =3D ARRAY_SIZE(sm8550_dec_ip_int_buf_tbl), diff --git a/drivers/media/platform/qcom/iris/iris_vidc.c b/drivers/media/p= latform/qcom/iris/iris_vidc.c index d38d0f6961cd5cb9929e2aecbec7353dcc2d4a7d..05eec18f937a51d3c081d0f98a8= ffa6bbd30d166 100644 --- a/drivers/media/platform/qcom/iris/iris_vidc.c +++ b/drivers/media/platform/qcom/iris/iris_vidc.c @@ -178,6 +178,7 @@ int iris_open(struct file *filp) INIT_LIST_HEAD(&inst->buffers[BUF_SCRATCH_1].list); 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This ensures the hardware decoder has properly allocated memory for AV1 decoding operations, enabling correct AV1 video playback. Signed-off-by: Deepa Guthyappa Madivalara Reviewed-by: Dikshita Agarwal --- drivers/media/platform/qcom/iris/iris_buffer.h | 1 + drivers/media/platform/qcom/iris/iris_vpu_buffer.c | 297 +++++++++++++++++= +++- drivers/media/platform/qcom/iris/iris_vpu_buffer.h | 116 ++++++++ 3 files changed, 411 insertions(+), 3 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_buffer.h b/drivers/media= /platform/qcom/iris/iris_buffer.h index 5ef365d9236c7cbdee24a4614789b3191881968b..75bb767761824c4c02e0df9b765= 896cc093be333 100644 --- a/drivers/media/platform/qcom/iris/iris_buffer.h +++ b/drivers/media/platform/qcom/iris/iris_buffer.h @@ -27,6 +27,7 @@ struct iris_inst; * @BUF_SCRATCH_1: buffer to store decoding/encoding context data for HW * @BUF_SCRATCH_2: buffer to store encoding context data for HW * @BUF_VPSS: buffer to store VPSS context data for HW + * @BUF_PARTIAL: buffer for AV1 IBC data * @BUF_TYPE_MAX: max buffer types */ enum iris_buffer_type { diff --git a/drivers/media/platform/qcom/iris/iris_vpu_buffer.c b/drivers/m= edia/platform/qcom/iris/iris_vpu_buffer.c index 4463be05ce165adef6b152eb0c155d2e6a7b3c36..694f431cca98af945ac8afee41a= 0c2de6edac3ef 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_buffer.c +++ b/drivers/media/platform/qcom/iris/iris_vpu_buffer.c @@ -9,6 +9,17 @@ #include "iris_hfi_gen2_defines.h" =20 #define HFI_MAX_COL_FRAME 6 +#define HFI_COLOR_FORMAT_YUV420_NV12_UBWC_Y_TILE_HEIGHT (8) +#define HFI_COLOR_FORMAT_YUV420_NV12_UBWC_Y_TILE_WIDTH (32) +#define HFI_COLOR_FORMAT_YUV420_NV12_UBWC_UV_TILE_HEIGHT (8) +#define HFI_COLOR_FORMAT_YUV420_NV12_UBWC_UV_TILE_WIDTH (16) +#define HFI_COLOR_FORMAT_YUV420_TP10_UBWC_Y_TILE_HEIGHT (4) +#define HFI_COLOR_FORMAT_YUV420_TP10_UBWC_Y_TILE_WIDTH (48) +#define HFI_COLOR_FORMAT_YUV420_TP10_UBWC_UV_TILE_HEIGHT (4) +#define HFI_COLOR_FORMAT_YUV420_TP10_UBWC_UV_TILE_WIDTH (24) +#define AV1D_SIZE_BSE_COL_MV_64x64 512 +#define AV1D_SIZE_BSE_COL_MV_128x128 2816 + =20 #ifndef SYSTEM_LAL_TILE10 #define SYSTEM_LAL_TILE10 192 @@ -39,6 +50,31 @@ static u32 hfi_buffer_bin_h264d(u32 frame_width, u32 fra= me_height, u32 num_vpp_p return size_h264d_hw_bin_buffer(n_aligned_w, n_aligned_h, num_vpp_pipes); } =20 +static u32 size_av1d_hw_bin_buffer(u32 frame_width, u32 frame_height, u32 = num_vpp_pipes) +{ + u32 size_yuv, size_bin_hdr, size_bin_res; + + size_yuv =3D ((frame_width * frame_height) <=3D BIN_BUFFER_THRESHOLD) ? + ((BIN_BUFFER_THRESHOLD * 3) >> 1) : + ((frame_width * frame_height * 3) >> 1); + size_bin_hdr =3D size_yuv * AV1_CABAC_HDR_RATIO_HD_TOT; + size_bin_res =3D size_yuv * AV1_CABAC_RES_RATIO_HD_TOT; + size_bin_hdr =3D ALIGN(size_bin_hdr / num_vpp_pipes, + DMA_ALIGNMENT) * num_vpp_pipes; + size_bin_res =3D ALIGN(size_bin_res / num_vpp_pipes, + DMA_ALIGNMENT) * num_vpp_pipes; + + return size_bin_hdr + size_bin_res; +} + +static u32 hfi_buffer_bin_av1d(u32 frame_width, u32 frame_height, u32 num_= vpp_pipes) +{ + u32 n_aligned_h =3D ALIGN(frame_height, 16); + u32 n_aligned_w =3D ALIGN(frame_width, 16); + + return size_av1d_hw_bin_buffer(n_aligned_w, n_aligned_h, num_vpp_pipes); +} + static u32 size_h265d_hw_bin_buffer(u32 frame_width, u32 frame_height, u32= num_vpp_pipes) { u32 product =3D frame_width * frame_height; @@ -110,6 +146,26 @@ static u32 hfi_buffer_comv_h265d(u32 frame_width, u32 = frame_height, u32 _comv_bu return (_size * (_comv_bufcount)) + 512; } =20 +static u32 num_lcu(u32 frame_width, u32 frame_height, u32 lcu_size) +{ + return ((frame_width + lcu_size - 1) / lcu_size) * + ((frame_height + lcu_size - 1) / lcu_size); +} + +static u32 hfi_buffer_comv_av1d(u32 frame_width, u32 frame_height, u32 com= v_bufcount) +{ + u32 size; + + size =3D 2 * ALIGN(max(num_lcu(frame_width, frame_height, 64) * + AV1D_SIZE_BSE_COL_MV_64x64, + num_lcu(frame_width, frame_height, 128) * + AV1D_SIZE_BSE_COL_MV_128x128), + DMA_ALIGNMENT); + size *=3D comv_bufcount; + + return size; +} + static u32 size_h264d_bse_cmd_buf(u32 frame_height) { u32 height =3D ALIGN(frame_height, 32); @@ -174,6 +230,20 @@ static u32 hfi_buffer_persist_h264d(void) DMA_ALIGNMENT); } =20 +static u32 hfi_buffer_persist_av1d(u32 max_width, u32 max_height, u32 tota= l_ref_count) +{ + u32 comv_size, size; + + comv_size =3D hfi_buffer_comv_av1d(max_width, max_height, total_ref_coun= t); + size =3D ALIGN((SIZE_AV1D_SEQUENCE_HEADER * 2 + SIZE_AV1D_METADATA + + AV1D_NUM_HW_PIC_BUF * (SIZE_AV1D_TILE_OFFSET + SIZE_AV1D_QM) + + AV1D_NUM_FRAME_HEADERS * (SIZE_AV1D_FRAME_HEADER + + 2 * SIZE_AV1D_PROB_TABLE) + comv_size + HDR10_HIST_EXTRADATA_SIZE + + SIZE_AV1D_METADATA * AV1D_NUM_HW_PIC_BUF), DMA_ALIGNMENT); + + return ALIGN(size, DMA_ALIGNMENT); +} + static u32 hfi_buffer_non_comv_h264d(u32 frame_width, u32 frame_height, u3= 2 num_vpp_pipes) { u32 size_bse =3D size_h264d_bse_cmd_buf(frame_height); @@ -459,6 +529,182 @@ static u32 hfi_buffer_line_h264d(u32 frame_width, u32= frame_height, return ALIGN((size + vpss_lb_size), DMA_ALIGNMENT); } =20 +static u32 size_av1d_lb_opb_wr1_nv12_ubwc(u32 frame_width, u32 frame_heigh= t) +{ + u32 size, y_width, y_width_a =3D 128; + + y_width =3D ALIGN(frame_width, y_width_a); + + size =3D ((y_width + HFI_COLOR_FORMAT_YUV420_NV12_UBWC_Y_TILE_WIDTH - 1) / + HFI_COLOR_FORMAT_YUV420_NV12_UBWC_Y_TILE_WIDTH + + (AV1D_MAX_TILE_COLS - 1)); + return size * 256; +} + +static u32 size_av1d_lb_opb_wr1_tp10_ubwc(u32 frame_width, u32 frame_heigh= t) +{ + u32 size, y_width, y_width_a =3D 256; + + y_width =3D ALIGN(frame_width, y_width_a); + + size =3D ((y_width + HFI_COLOR_FORMAT_YUV420_TP10_UBWC_Y_TILE_WIDTH - 1) / + HFI_COLOR_FORMAT_YUV420_TP10_UBWC_Y_TILE_WIDTH + + (AV1D_MAX_TILE_COLS - 1)); + + return size * 256; +} + +static u32 hfi_buffer_line_av1d(u32 frame_width, u32 frame_height, + bool is_opb, u32 num_vpp_pipes) +{ + u32 size, vpss_lb_size, opbwrbufsize, opbwr8, opbwr10; + + size =3D ALIGN(size_av1d_lb_fe_top_data(frame_width, frame_height), + DMA_ALIGNMENT) + + ALIGN(size_av1d_lb_fe_top_ctrl(frame_width, frame_height), + DMA_ALIGNMENT) + + ALIGN(size_av1d_lb_fe_left_data(frame_width, frame_height), + DMA_ALIGNMENT) * num_vpp_pipes + + ALIGN(size_av1d_lb_fe_left_ctrl(frame_width, frame_height), + DMA_ALIGNMENT) * num_vpp_pipes + + ALIGN(size_av1d_lb_se_left_ctrl(frame_width, frame_height), + DMA_ALIGNMENT) * num_vpp_pipes + + ALIGN(size_av1d_lb_se_top_ctrl(frame_width, frame_height), + DMA_ALIGNMENT) + + ALIGN(size_av1d_lb_pe_top_data(frame_width, frame_height), + DMA_ALIGNMENT) + + ALIGN(size_av1d_lb_vsp_top(frame_width, frame_height), + DMA_ALIGNMENT) + + ALIGN(size_av1d_lb_recon_dma_metadata_wr + (frame_width, frame_height), DMA_ALIGNMENT) * 2 + + ALIGN(size_av1d_qp(frame_width, frame_height), DMA_ALIGNMENT); + opbwr8 =3D size_av1d_lb_opb_wr1_nv12_ubwc(frame_width, frame_height); + opbwr10 =3D size_av1d_lb_opb_wr1_tp10_ubwc(frame_width, frame_height); + opbwrbufsize =3D opbwr8 >=3D opbwr10 ? opbwr8 : opbwr10; + size =3D ALIGN((size + opbwrbufsize), DMA_ALIGNMENT); + if (is_opb) { + vpss_lb_size =3D size_vpss_lb(frame_width, frame_height); + size =3D ALIGN((size + vpss_lb_size) * 2, DMA_ALIGNMENT); + } + + return size; +} + +static u32 size_av1d_ibc_nv12_ubwc(u32 frame_width, u32 frame_height) +{ + u32 size; + u32 y_width_a =3D 128, y_height_a =3D 32; + u32 uv_width_a =3D 128, uv_height_a =3D 32; + u32 ybufsize, uvbufsize, y_width, y_height, uv_width, uv_height; + u32 y_meta_width_a =3D 64, y_meta_height_a =3D 16; + u32 uv_meta_width_a =3D 64, uv_meta_height_a =3D 16; + u32 meta_height, meta_stride, meta_size; + u32 tile_width_y =3D HFI_COLOR_FORMAT_YUV420_NV12_UBWC_Y_TILE_WIDTH; + u32 tile_height_y =3D HFI_COLOR_FORMAT_YUV420_NV12_UBWC_Y_TILE_HEIGHT; + u32 tile_width_uv =3D HFI_COLOR_FORMAT_YUV420_NV12_UBWC_UV_TILE_WIDTH; + u32 tile_height_uv =3D HFI_COLOR_FORMAT_YUV420_NV12_UBWC_UV_TILE_HEIGHT; + + y_width =3D ALIGN(frame_width, y_width_a); + y_height =3D ALIGN(frame_height, y_height_a); + uv_width =3D ALIGN(frame_width, uv_width_a); + uv_height =3D ALIGN(((frame_height + 1) >> 1), uv_height_a); + ybufsize =3D ALIGN((y_width * y_height), HFI_ALIGNMENT_4096); + uvbufsize =3D ALIGN(uv_width * uv_height, HFI_ALIGNMENT_4096); + size =3D ybufsize + uvbufsize; + meta_stride =3D ALIGN(((frame_width + (tile_width_y - 1)) / tile_width_y), + y_meta_width_a); + meta_height =3D ALIGN(((frame_height + (tile_height_y - 1)) / tile_height= _y), + y_meta_height_a); + meta_size =3D ALIGN(meta_stride * meta_height, HFI_ALIGNMENT_4096); + size +=3D meta_size; + meta_stride =3D ALIGN(((((frame_width + 1) >> 1) + (tile_width_uv - 1)) / + tile_width_uv), uv_meta_width_a); + meta_height =3D ALIGN(((((frame_height + 1) >> 1) + (tile_height_uv - 1))= / + tile_height_uv), uv_meta_height_a); + meta_size =3D ALIGN(meta_stride * meta_height, HFI_ALIGNMENT_4096); + size +=3D meta_size; + + return size; +} + +static u32 hfi_yuv420_tp10_calc_y_stride(u32 frame_width, u32 stride_multi= ple) +{ + u32 stride; + + stride =3D ALIGN(frame_width, 192); + stride =3D ALIGN(stride * 4 / 3, stride_multiple); + + return stride; +} + +static u32 hfi_yuv420_tp10_calc_y_bufheight(u32 frame_height, u32 min_buf_= height_multiple) +{ + return ALIGN(frame_height, min_buf_height_multiple); +} + +static u32 hfi_yuv420_tp10_calc_uv_stride(u32 frame_width, u32 stride_mult= iple) +{ + u32 stride; + + stride =3D ALIGN(frame_width, 192); + stride =3D ALIGN(stride * 4 / 3, stride_multiple); + + return stride; +} + +static u32 hfi_yuv420_tp10_calc_uv_bufheight(u32 frame_height, u32 min_buf= _height_multiple) +{ + return ALIGN(((frame_height + 1) >> 1), min_buf_height_multiple); +} + +static u32 size_av1d_ibc_tp10_ubwc(u32 frame_width, u32 frame_height) +{ + u32 size; + u32 y_width_a =3D 256, y_height_a =3D 16, + uv_width_a =3D 256, uv_height_a =3D 16; + u32 ybufsize, uvbufsize, y_width, y_height, uv_width, uv_height; + u32 y_meta_width_a =3D 64, y_meta_height_a =3D 16, + uv_meta_width_a =3D 64, uv_meta_height_a =3D 16; + u32 meta_height, meta_stride, meta_size; + u32 tile_width_y =3D HFI_COLOR_FORMAT_YUV420_TP10_UBWC_Y_TILE_WIDTH; + u32 tile_height_y =3D HFI_COLOR_FORMAT_YUV420_TP10_UBWC_Y_TILE_HEIGHT; + u32 tile_width_uv =3D HFI_COLOR_FORMAT_YUV420_TP10_UBWC_UV_TILE_WIDTH; + u32 tile_height_uv =3D HFI_COLOR_FORMAT_YUV420_TP10_UBWC_UV_TILE_HEIGHT; + + y_width =3D hfi_yuv420_tp10_calc_y_stride(frame_width, y_width_a); + y_height =3D hfi_yuv420_tp10_calc_y_bufheight(frame_height, y_height_a); + uv_width =3D hfi_yuv420_tp10_calc_uv_stride(frame_width, uv_width_a); + uv_height =3D hfi_yuv420_tp10_calc_uv_bufheight(frame_height, uv_height_a= ); + ybufsize =3D ALIGN(y_width * y_height, HFI_ALIGNMENT_4096); + uvbufsize =3D ALIGN(uv_width * uv_height, HFI_ALIGNMENT_4096); + size =3D ybufsize + uvbufsize; + meta_stride =3D ALIGN(((frame_width + (tile_width_y - 1)) / tile_width_y), + y_meta_width_a); + meta_height =3D ALIGN(((frame_height + (tile_height_y - 1)) / tile_height= _y), + y_meta_height_a); + meta_size =3D ALIGN(meta_stride * meta_height, HFI_ALIGNMENT_4096); + size +=3D meta_size; + meta_stride =3D ALIGN(((((frame_width + 1) >> 1) + (tile_width_uv - 1)) / + tile_width_uv), uv_meta_width_a); + meta_height =3D ALIGN(((((frame_height + 1) >> 1) + (tile_height_uv - 1))= / + tile_height_uv), uv_meta_height_a); + meta_size =3D ALIGN(meta_stride * meta_height, HFI_ALIGNMENT_4096); + size +=3D meta_size; + + return size; +} + +static u32 hfi_buffer_ibc_av1d(u32 frame_width, u32 frame_height) +{ + u32 size, ibc8, ibc10; + + ibc8 =3D size_av1d_ibc_nv12_ubwc(frame_width, frame_height); + ibc10 =3D size_av1d_ibc_tp10_ubwc(frame_width, frame_height); + size =3D ibc8 >=3D ibc10 ? ibc8 : ibc10; + + return ALIGN(size, DMA_ALIGNMENT); +} + static u32 iris_vpu_dec_bin_size(struct iris_inst *inst) { u32 num_vpp_pipes =3D inst->core->iris_platform_data->num_vpp_pipe; @@ -472,6 +718,8 @@ static u32 iris_vpu_dec_bin_size(struct iris_inst *inst) return hfi_buffer_bin_h265d(width, height, num_vpp_pipes); else if (inst->codec =3D=3D V4L2_PIX_FMT_VP9) return hfi_buffer_bin_vp9d(width, height, num_vpp_pipes); + else if (inst->codec =3D=3D V4L2_PIX_FMT_AV1) + return hfi_buffer_bin_av1d(width, height, num_vpp_pipes); =20 return 0; } @@ -487,18 +735,34 @@ static u32 iris_vpu_dec_comv_size(struct iris_inst *i= nst) return hfi_buffer_comv_h264d(width, height, num_comv); else if (inst->codec =3D=3D V4L2_PIX_FMT_HEVC) return hfi_buffer_comv_h265d(width, height, num_comv); + else if (inst->codec =3D=3D V4L2_PIX_FMT_AV1) { + if (inst->fw_caps[DRAP].value) + return 0; + else + return hfi_buffer_comv_av1d(width, height, num_comv); + } =20 return 0; } =20 static u32 iris_vpu_dec_persist_size(struct iris_inst *inst) { + struct platform_inst_caps *caps; + if (inst->codec =3D=3D V4L2_PIX_FMT_H264) return hfi_buffer_persist_h264d(); else if (inst->codec =3D=3D V4L2_PIX_FMT_HEVC) return hfi_buffer_persist_h265d(0); else if (inst->codec =3D=3D V4L2_PIX_FMT_VP9) return hfi_buffer_persist_vp9d(); + else if (inst->codec =3D=3D V4L2_PIX_FMT_AV1) { + caps =3D inst->core->iris_platform_data->inst_caps; + if (inst->fw_caps[DRAP].value) + return hfi_buffer_persist_av1d(caps->max_frame_width, + caps->max_frame_height, 16); + else + return hfi_buffer_persist_av1d(0, 0, 0); + } =20 return 0; } @@ -545,6 +809,8 @@ static u32 iris_vpu_dec_line_size(struct iris_inst *ins= t) else if (inst->codec =3D=3D V4L2_PIX_FMT_VP9) return hfi_buffer_line_vp9d(width, height, out_min_count, is_opb, num_vpp_pipes); + else if (inst->codec =3D=3D V4L2_PIX_FMT_AV1) + return hfi_buffer_line_av1d(width, height, is_opb, num_vpp_pipes); =20 return 0; } @@ -653,6 +919,15 @@ static u32 iris_vpu_enc_bin_size(struct iris_inst *ins= t) num_vpp_pipes, inst->hfi_rc_type); } =20 +static u32 iris_vpu_dec_partial_size(struct iris_inst *inst) +{ + struct v4l2_format *f =3D inst->fmt_src; + u32 height =3D f->fmt.pix_mp.height; + u32 width =3D f->fmt.pix_mp.width; + + return hfi_buffer_ibc_av1d(width, height); +} + static inline u32 hfi_buffer_comv_enc(u32 frame_width, u32 frame_height, u32 lcu_size, u32 num_recon, u32 standard) @@ -1414,7 +1689,9 @@ static int output_min_count(struct iris_inst *inst) =20 /* fw_min_count > 0 indicates reconfig event has already arrived */ if (inst->fw_min_count) { - if (iris_split_mode_enabled(inst) && inst->codec =3D=3D V4L2_PIX_FMT_VP9) + if (iris_split_mode_enabled(inst) && + (inst->codec =3D=3D V4L2_PIX_FMT_VP9 || + inst->codec =3D=3D V4L2_PIX_FMT_AV1)) return min_t(u32, 4, inst->fw_min_count); else return inst->fw_min_count; @@ -1422,6 +1699,8 @@ static int output_min_count(struct iris_inst *inst) =20 if (inst->codec =3D=3D V4L2_PIX_FMT_VP9) output_min_count =3D 9; + else if (inst->codec =3D=3D V4L2_PIX_FMT_AV1) + output_min_count =3D 11; =20 return output_min_count; } @@ -1444,6 +1723,7 @@ u32 iris_vpu_buf_size(struct iris_inst *inst, enum ir= is_buffer_type buffer_type) {BUF_PERSIST, iris_vpu_dec_persist_size }, {BUF_DPB, iris_vpu_dec_dpb_size }, {BUF_SCRATCH_1, iris_vpu_dec_scratch1_size }, + {BUF_PARTIAL, iris_vpu_dec_partial_size }, }; =20 static const struct iris_vpu_buf_type_handle enc_internal_buf_type_handle= [] =3D { @@ -1510,14 +1790,20 @@ static u32 internal_buffer_count(struct iris_inst *= inst, buffer_type =3D=3D BUF_PERSIST) { return 1; } else if (buffer_type =3D=3D BUF_COMV || buffer_type =3D=3D BUF_NON_COMV= ) { - if (inst->codec =3D=3D V4L2_PIX_FMT_H264 || inst->codec =3D=3D V4L2_PIX_= FMT_HEVC) + if (inst->codec =3D=3D V4L2_PIX_FMT_H264 || + inst->codec =3D=3D V4L2_PIX_FMT_HEVC || + inst->codec =3D=3D V4L2_PIX_FMT_AV1) return 1; } + return 0; } =20 static inline int iris_vpu_dpb_count(struct iris_inst *inst) { + if (inst->codec =3D=3D V4L2_PIX_FMT_AV1) + return 11; + if (iris_split_mode_enabled(inst)) { return inst->fw_min_count ? inst->fw_min_count : inst->buffers[BUF_OUTPUT].min_count; @@ -1536,9 +1822,13 @@ int iris_vpu_buf_count(struct iris_inst *inst, enum = iris_buffer_type buffer_type return MIN_BUFFERS; else return output_min_count(inst); + case BUF_NON_COMV: + if (inst->codec =3D=3D V4L2_PIX_FMT_AV1) + return 0; + else + return 1; case BUF_BIN: case BUF_COMV: - case BUF_NON_COMV: case BUF_LINE: case BUF_PERSIST: return internal_buffer_count(inst, buffer_type); @@ -1546,6 +1836,7 @@ int iris_vpu_buf_count(struct iris_inst *inst, enum i= ris_buffer_type buffer_type case BUF_SCRATCH_2: case BUF_VPSS: case BUF_ARP: + case BUF_PARTIAL: return 1; /* internal buffer count needed by firmware is 1 */ case BUF_DPB: return iris_vpu_dpb_count(inst); diff --git a/drivers/media/platform/qcom/iris/iris_vpu_buffer.h b/drivers/m= edia/platform/qcom/iris/iris_vpu_buffer.h index 04f0b7400a1e4e1d274d690a2761b9e57778e8b7..a8ffc1286260bddbf49df18fba0= a23f78056a484 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_buffer.h +++ b/drivers/media/platform/qcom/iris/iris_vpu_buffer.h @@ -11,6 +11,7 @@ struct iris_inst; #define MIN_BUFFERS 4 =20 #define DMA_ALIGNMENT 256 +#define HFI_ALIGNMENT_4096 4096 =20 #define NUM_HW_PIC_BUF 32 #define LCU_MAX_SIZE_PELS 64 @@ -81,6 +82,22 @@ struct iris_inst; #define MAX_PE_NBR_DATA_LCU64_LINE_BUFFER_SIZE 384 #define MAX_FE_NBR_DATA_LUMA_LINE_BUFFER_SIZE 640 =20 +#define AV1_CABAC_HDR_RATIO_HD_TOT 2 +#define AV1_CABAC_RES_RATIO_HD_TOT 2 +#define AV1D_LCU_MAX_SIZE_PELS 128 +#define AV1D_LCU_MIN_SIZE_PELS 64 +#define AV1D_MAX_TILE_COLS 64 +#define MAX_PE_NBR_DATA_LCU32_LINE_BUFFER_SIZE 192 +#define MAX_PE_NBR_DATA_LCU16_LINE_BUFFER_SIZE 96 +#define AV1D_NUM_HW_PIC_BUF 16 +#define AV1D_NUM_FRAME_HEADERS 16 +#define SIZE_AV1D_SEQUENCE_HEADER 768 +#define SIZE_AV1D_METADATA 512 +#define SIZE_AV1D_FRAME_HEADER 1280 +#define SIZE_AV1D_TILE_OFFSET 65536 +#define SIZE_AV1D_QM 3328 +#define SIZE_AV1D_PROB_TABLE 22784 + #define SIZE_SLICE_CMD_BUFFER (ALIGN(20480, 256)) #define SIZE_SPS_PPS_SLICE_HDR (2048 + 4096) #define SIZE_BSE_SLICE_CMD_BUF ((((8192 << 2) + 7) & (~7)) * 3) @@ -101,6 +118,15 @@ struct iris_inst; #define NUM_MBS_4K (DIV_ROUND_UP(MAX_WIDTH, 16) * DIV_ROUND_UP(MAX_HEIGHT,= 16)) #define NUM_MBS_720P (((ALIGN(1280, 16)) >> 4) * ((ALIGN(736, 16)) >> 4)) =20 +#define BITS_PER_PIX 16 +#define NUM_LINES_LUMA 10 +#define NUM_LINES_CHROMA 6 +#define AV1D_LCU_MAX_SIZE_PELS 128 +#define AV1D_LCU_MIN_SIZE_PELS 64 +#define AV1D_MAX_TILE_COLS 64 +#define BITS_PER_CTRL_PACK 128 +#define NUM_CTRL_PACK_LCU 10 + static inline u32 size_h264d_lb_fe_top_data(u32 frame_width) { return MAX_FE_NBR_DATA_LUMA_LINE_BUFFER_SIZE * ALIGN(frame_width, 16) * 3; @@ -146,6 +172,96 @@ static inline u32 size_h264d_qp(u32 frame_width, u32 f= rame_height) return DIV_ROUND_UP(frame_width, 64) * DIV_ROUND_UP(frame_height, 64) * 1= 28; } =20 +static inline u32 size_av1d_lb_fe_top_data(u32 frame_width, u32 frame_heig= ht) +{ + return (ALIGN(frame_width, AV1D_LCU_MAX_SIZE_PELS) * + ((BITS_PER_PIX * NUM_LINES_LUMA) >> 3) + + ALIGN(frame_width, AV1D_LCU_MAX_SIZE_PELS) / 2 * + ((BITS_PER_PIX * NUM_LINES_CHROMA) >> 3) * 2); +} + +static inline u32 size_av1d_lb_fe_left_data(u32 frame_width, u32 frame_hei= ght) +{ + return (32 * (ALIGN(frame_height, AV1D_LCU_MAX_SIZE_PELS) + + ALIGN(frame_height, AV1D_LCU_MAX_SIZE_PELS) / + AV1D_LCU_MIN_SIZE_PELS * 16) + + 16 * (ALIGN(frame_height, AV1D_LCU_MAX_SIZE_PELS) / 2 + + ALIGN(frame_height, AV1D_LCU_MAX_SIZE_PELS) / + AV1D_LCU_MIN_SIZE_PELS * 8) * 2 + + 24 * (ALIGN(frame_height, AV1D_LCU_MAX_SIZE_PELS) + + ALIGN(frame_height, AV1D_LCU_MAX_SIZE_PELS) / + AV1D_LCU_MIN_SIZE_PELS * 16) + + 24 * (ALIGN(frame_height, AV1D_LCU_MAX_SIZE_PELS) / 2 + + ALIGN(frame_height, AV1D_LCU_MAX_SIZE_PELS) / + AV1D_LCU_MIN_SIZE_PELS * 12) * 2 + + 24 * (ALIGN(frame_height, AV1D_LCU_MAX_SIZE_PELS) + + ALIGN(frame_height, AV1D_LCU_MAX_SIZE_PELS) / + AV1D_LCU_MIN_SIZE_PELS * 16) + + 16 * (ALIGN(frame_height, AV1D_LCU_MAX_SIZE_PELS) + + ALIGN(frame_height, AV1D_LCU_MAX_SIZE_PELS) / + AV1D_LCU_MIN_SIZE_PELS * 16) + + 16 * (ALIGN(frame_height, AV1D_LCU_MAX_SIZE_PELS) / 2 + + ALIGN(frame_height, AV1D_LCU_MAX_SIZE_PELS) / + AV1D_LCU_MIN_SIZE_PELS * 12) * 2); +} + +static inline u32 size_av1d_lb_fe_top_ctrl(u32 frame_width, u32 frame_heig= ht) +{ + return (NUM_CTRL_PACK_LCU * ((frame_width + AV1D_LCU_MIN_SIZE_PELS - 1) / + AV1D_LCU_MIN_SIZE_PELS) * BITS_PER_CTRL_PACK / 8); +} + +static inline u32 size_av1d_lb_fe_left_ctrl(u32 frame_width, u32 frame_hei= ght) +{ + return (16 * ((ALIGN(frame_height, AV1D_LCU_MAX_SIZE_PELS) / 16) + + (ALIGN(frame_height, AV1D_LCU_MAX_SIZE_PELS) / + AV1D_LCU_MIN_SIZE_PELS)) + + 3 * 16 * (ALIGN(frame_height, AV1D_LCU_MAX_SIZE_PELS) / + AV1D_LCU_MIN_SIZE_PELS)); +} + +static inline u32 size_av1d_lb_se_top_ctrl(u32 frame_width, u32 frame_heig= ht) +{ + return (((frame_width + 7) / 8) * MAX_SE_NBR_CTRL_LCU16_LINE_BUFFER_SIZE); +} + +static inline u32 size_av1d_lb_se_left_ctrl(u32 frame_width, u32 frame_hei= ght) +{ + return (max(((frame_height + 15) / 16) * + MAX_SE_NBR_CTRL_LCU16_LINE_BUFFER_SIZE, + max(((frame_height + 31) / 32) * + MAX_SE_NBR_CTRL_LCU32_LINE_BUFFER_SIZE, + ((frame_height + 63) / 64) * + MAX_SE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE))); +} + +static inline u32 size_av1d_lb_pe_top_data(u32 frame_width, u32 frame_heig= ht) +{ + return (max(((frame_width + 15) / 16) * + MAX_PE_NBR_DATA_LCU16_LINE_BUFFER_SIZE, + max(((frame_width + 31) / 32) * + MAX_PE_NBR_DATA_LCU32_LINE_BUFFER_SIZE, + ((frame_width + 63) / 64) * + MAX_PE_NBR_DATA_LCU64_LINE_BUFFER_SIZE))); +} + +static inline u32 size_av1d_lb_vsp_top(u32 frame_width, u32 frame_height) +{ + return (max(((frame_width + 63) / 64) * 1280, + ((frame_width + 127) / 128) * 2304)); +} + +static inline u32 size_av1d_lb_recon_dma_metadata_wr(u32 frame_width, + u32 frame_height) +{ + return ((ALIGN(frame_height, 8) / (4 / 2)) * 64); +} + +static inline u32 size_av1d_qp(u32 frame_width, u32 frame_height) +{ + return size_h264d_qp(frame_width, frame_height); +} + u32 iris_vpu_buf_size(struct iris_inst *inst, enum iris_buffer_type buffer= _type); u32 iris_vpu33_buf_size(struct iris_inst *inst, enum iris_buffer_type buff= er_type); int iris_vpu_buf_count(struct iris_inst *inst, enum iris_buffer_type buffe= r_type); --=20 2.34.1