From nobody Sun Dec 14 11:16:13 2025 Received: from mail-pj1-f74.google.com (mail-pj1-f74.google.com [209.85.216.74]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 46BDD31B11D for ; Wed, 29 Oct 2025 21:41:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.74 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761774064; cv=none; b=An1wv6c7KYIwNep+xuDtpPlYP7APXnvLb2SOHAdmP5+tdXzrELT+JccD9CRj7QQy13CrnthIFoJD8/CRH+fVIr77Pas/COsABh7UizhWNK84In/n+BN3Mj2S6N0qNyV7F1W9C0PKGGuXrCWYhEPnOuH/7g2CtqErrTHpzImf51U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761774064; c=relaxed/simple; bh=neF3Fi0sXnJm1U9OAdPuiEM1w+TSdwNCf78x0u+9EMM=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=GcR3x2pzAblb0x6IYSM5RA8sMToZmW6wa24Owdk+N1jRnYN375gk8AmUkYXD08s0ok0Gfw18AIGwqIiU6rSYkCmYVVi10dMFcA2vbHH4HXizrzTaSPx5DUYtWRVjs/mRbbvIacShYA4CfGoY/JLHfdof0yjbD3JMHfLpdIDsEKc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--royluo.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=pUS0jZZh; arc=none smtp.client-ip=209.85.216.74 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--royluo.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="pUS0jZZh" Received: by mail-pj1-f74.google.com with SMTP id 98e67ed59e1d1-3324538ceb0so564502a91.1 for ; Wed, 29 Oct 2025 14:41:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1761774061; x=1762378861; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=PsD+60KDxRA63pKuk3kGCvoA2vQ4JCKP7PSH6fRAYgs=; b=pUS0jZZh9+wSFK+Qv456MvdTe8eN0ld9sEJqcsLqW/RQydW+pghU3UMDz6hDXxDPs+ glUA9cBJSqbtgs+ky6FxP14u82h54c7FjIqU/6EMmfISu9e5BTB4oSg2Jhnr+IT7D4E2 41iy5m+q9eE4tqz5q6SBggMjnPO8WhvHb0Y8BRupAjHaRMWRZhYACV3NVwEtr6lu86IO BARZjO+0qmlNKFz5awpOJyQD7ivJW/6i/nG1QdvRHAAiming2OQ6446B62bJTKhZXduj mHkdMrCapwZQL35mTTmD6KVhgSqWdY9q/txpHUpQf+bv5llhKDbBQIGLGGdylx82pZTK QJnQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1761774062; x=1762378862; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=PsD+60KDxRA63pKuk3kGCvoA2vQ4JCKP7PSH6fRAYgs=; b=Nbhap8Rg33VgLhTshjxpPYcTOkmj3zR2DcHdtPjdumctQvhwDoGf3Ylm5qw0n19XCg FK2G93s0s8yquK7pUsFSXnzm8wmisv9yKSI3qLIuDoTwtm1nNZKx09FPLrULU5a8zdzC CGCWexFBT9VbI/MMg+5AfAK3ZmOhB3EvyQa2Tb06aOORVmkD7ACPuxlDV+ENc42QAI4s Bag8JaHwAzr7j9PljOpkLlaHKyoD9Odp7SseUEwsaAmSVPvssBXcCWc/7h1f57EGJJLY Vns9nG1RNJueb3U1kWDJZC12gQO8qq6F4ndbH3uCb1BaMSYx3OVXlXF/3toMYJzDbft+ ArhA== X-Forwarded-Encrypted: i=1; AJvYcCVsY74VczSuZppLMdqK3poLOs4V5Rsi1ZXec5VWixB1OaXaAcTPZpN9ytBgD0FrkGc9+Rpgy/aG6wonPPM=@vger.kernel.org X-Gm-Message-State: AOJu0YwteaFrXoqSbUqLwlaJjVTAgqHnVTYvs8diKFAeLE/gTPd7txzg 6KxBcXL/d6cTmU8TwgkxRhfRYLrJNsRwBKmMEzB1zFOdT3foDR3mpqezgiEZD8Usz4opas7FHfC Xk0FJGQ== X-Google-Smtp-Source: AGHT+IEMfFp8ZCC0xNU0mSbhzy5iC7snXPJKFHRF56WugTXlGgarRnyuyK6BjOFtMaCJF60s6FLDD+G3tTU= X-Received: from plbli15.prod.google.com ([2002:a17:903:294f:b0:267:fa7d:b637]) (user=royluo job=prod-delivery.src-stubby-dispatcher) by 2002:a17:902:ec8d:b0:269:87a3:43b8 with SMTP id d9443c01a7336-294ee217833mr7098535ad.4.1761774061567; Wed, 29 Oct 2025 14:41:01 -0700 (PDT) Date: Wed, 29 Oct 2025 21:40:32 +0000 In-Reply-To: <20251029214032.3175261-1-royluo@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20251029214032.3175261-1-royluo@google.com> X-Mailer: git-send-email 2.51.1.851.g4ebd6896fd-goog Message-ID: <20251029214032.3175261-3-royluo@google.com> Subject: [PATCH v5 2/2] phy: Add Google Tensor SoC USB PHY driver From: Roy Luo To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Peter Griffin , "=?UTF-8?q?Andr=C3=A9=20Draszik?=" , Tudor Ambarus Cc: Doug Anderson , Joy Chakraborty , Naveen Kumar , Roy Luo , Badhri Jagan Sridharan , linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Support the USB PHY found on Google Tensor G5. This particular USB PHY supports both high-speed and super-speed operations, and is integrated with the SNPS DWC3 controller that's also on the SoC. This initial patch specifically adds functionality for high-speed. Co-developed-by: Joy Chakraborty Signed-off-by: Joy Chakraborty Co-developed-by: Naveen Kumar Signed-off-by: Naveen Kumar Signed-off-by: Roy Luo --- drivers/phy/Kconfig | 13 ++ drivers/phy/Makefile | 1 + drivers/phy/phy-google-usb.c | 271 +++++++++++++++++++++++++++++++++++ 3 files changed, 285 insertions(+) create mode 100644 drivers/phy/phy-google-usb.c diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index 58c911e1b2d2..be237847efed 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -101,6 +101,19 @@ config PHY_NXP_PTN3222 schemes. It supports all three USB 2.0 data rates: Low Speed, Full Speed and High Speed. =20 +config PHY_GOOGLE_USB + tristate "Google Tensor SoC USB PHY driver" + depends on HAS_IOMEM + depends on OF + depends on TYPEC + select GENERIC_PHY + help + Enable support for the USB PHY on Google Tensor SoCs, starting with + the G5 generation. This driver provides the PHY interfaces to + interact with the SNPS eUSB2 and USB 3.2/DisplayPort Combo PHY, both + of which are integrated with the DWC3 USB DRD controller. + This driver currently supports USB high-speed. + source "drivers/phy/allwinner/Kconfig" source "drivers/phy/amlogic/Kconfig" source "drivers/phy/broadcom/Kconfig" diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index c670a8dac468..1d7a1331bd19 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -13,6 +13,7 @@ obj-$(CONFIG_PHY_SNPS_EUSB2) +=3D phy-snps-eusb2.o obj-$(CONFIG_USB_LGM_PHY) +=3D phy-lgm-usb.o obj-$(CONFIG_PHY_AIROHA_PCIE) +=3D phy-airoha-pcie.o obj-$(CONFIG_PHY_NXP_PTN3222) +=3D phy-nxp-ptn3222.o +obj-$(CONFIG_PHY_GOOGLE_USB) +=3D phy-google-usb.o obj-y +=3D allwinner/ \ amlogic/ \ broadcom/ \ diff --git a/drivers/phy/phy-google-usb.c b/drivers/phy/phy-google-usb.c new file mode 100644 index 000000000000..02c6e9f2912e --- /dev/null +++ b/drivers/phy/phy-google-usb.c @@ -0,0 +1,271 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * phy-google-usb.c - Google USB PHY driver + * + * Copyright (C) 2025, Google LLC + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define USBCS_USB2PHY_CFG19_OFFSET 0x0 +#define USBCS_USB2PHY_CFG19_PHY_CFG_PLL_FB_DIV GENMASK(19, 8) + +#define USBCS_USB2PHY_CFG21_OFFSET 0x8 +#define USBCS_USB2PHY_CFG21_PHY_ENABLE BIT(12) +#define USBCS_USB2PHY_CFG21_REF_FREQ_SEL GENMASK(15, 13) +#define USBCS_USB2PHY_CFG21_PHY_TX_DIG_BYPASS_SEL BIT(19) + +#define USBCS_PHY_CFG1_OFFSET 0x28 +#define USBCS_PHY_CFG1_SYS_VBUSVALID BIT(17) + +enum google_usb_phy_id { + GOOGLE_USB2_PHY, + GOOGLE_USB_PHY_NUM, +}; + +struct google_usb_phy_instance { + int index; + struct phy *phy; + int num_clks; + struct clk_bulk_data *clks; + struct reset_control *rsts; +}; + +struct google_usb_phy { + struct device *dev; + void __iomem *usb2_cfg_base; + void __iomem *usb3_top_base; + struct google_usb_phy_instance insts[GOOGLE_USB_PHY_NUM]; + /* serialize phy access */ + struct mutex phy_mutex; + struct typec_switch_dev *sw; + enum typec_orientation orientation; +}; + +static inline struct google_usb_phy *to_google_usb_phy(struct google_usb_p= hy_instance *inst) +{ + return container_of(inst, struct google_usb_phy, insts[inst->index]); +} + +static void set_vbus_valid(struct google_usb_phy *gphy) +{ + u32 reg; + + if (gphy->orientation =3D=3D TYPEC_ORIENTATION_NONE) { + reg =3D readl(gphy->usb3_top_base + USBCS_PHY_CFG1_OFFSET); + reg &=3D ~USBCS_PHY_CFG1_SYS_VBUSVALID; + writel(reg, gphy->usb3_top_base + USBCS_PHY_CFG1_OFFSET); + } else { + reg =3D readl(gphy->usb3_top_base + USBCS_PHY_CFG1_OFFSET); + reg |=3D USBCS_PHY_CFG1_SYS_VBUSVALID; + writel(reg, gphy->usb3_top_base + USBCS_PHY_CFG1_OFFSET); + } +} + +static int google_usb_set_orientation(struct typec_switch_dev *sw, + enum typec_orientation orientation) +{ + struct google_usb_phy *gphy =3D typec_switch_get_drvdata(sw); + + dev_dbg(gphy->dev, "set orientation %d\n", orientation); + + gphy->orientation =3D orientation; + + if (pm_runtime_suspended(gphy->dev)) + return 0; + + guard(mutex)(&gphy->phy_mutex); + + set_vbus_valid(gphy); + + return 0; +} + +static int google_usb2_phy_init(struct phy *_phy) +{ + struct google_usb_phy_instance *inst =3D phy_get_drvdata(_phy); + struct google_usb_phy *gphy =3D to_google_usb_phy(inst); + u32 reg; + int ret =3D 0; + + dev_dbg(gphy->dev, "initializing usb2 phy\n"); + + guard(mutex)(&gphy->phy_mutex); + + reg =3D readl(gphy->usb2_cfg_base + USBCS_USB2PHY_CFG21_OFFSET); + reg &=3D ~USBCS_USB2PHY_CFG21_PHY_TX_DIG_BYPASS_SEL; + reg &=3D ~USBCS_USB2PHY_CFG21_REF_FREQ_SEL; + reg |=3D FIELD_PREP(USBCS_USB2PHY_CFG21_REF_FREQ_SEL, 0); + writel(reg, gphy->usb2_cfg_base + USBCS_USB2PHY_CFG21_OFFSET); + + reg =3D readl(gphy->usb2_cfg_base + USBCS_USB2PHY_CFG19_OFFSET); + reg &=3D ~USBCS_USB2PHY_CFG19_PHY_CFG_PLL_FB_DIV; + reg |=3D FIELD_PREP(USBCS_USB2PHY_CFG19_PHY_CFG_PLL_FB_DIV, 368); + writel(reg, gphy->usb2_cfg_base + USBCS_USB2PHY_CFG19_OFFSET); + + set_vbus_valid(gphy); + + ret =3D clk_bulk_prepare_enable(inst->num_clks, inst->clks); + if (ret) + return ret; + + ret =3D reset_control_deassert(inst->rsts); + if (ret) { + clk_bulk_disable_unprepare(inst->num_clks, inst->clks); + return ret; + } + + reg =3D readl(gphy->usb2_cfg_base + USBCS_USB2PHY_CFG21_OFFSET); + reg |=3D USBCS_USB2PHY_CFG21_PHY_ENABLE; + writel(reg, gphy->usb2_cfg_base + USBCS_USB2PHY_CFG21_OFFSET); + + return ret; +} + +static int google_usb2_phy_exit(struct phy *_phy) +{ + struct google_usb_phy_instance *inst =3D phy_get_drvdata(_phy); + struct google_usb_phy *gphy =3D to_google_usb_phy(inst); + u32 reg; + + dev_dbg(gphy->dev, "exiting usb2 phy\n"); + + guard(mutex)(&gphy->phy_mutex); + + reg =3D readl(gphy->usb2_cfg_base + USBCS_USB2PHY_CFG21_OFFSET); + reg &=3D ~USBCS_USB2PHY_CFG21_PHY_ENABLE; + writel(reg, gphy->usb2_cfg_base + USBCS_USB2PHY_CFG21_OFFSET); + + reset_control_assert(inst->rsts); + clk_bulk_disable_unprepare(inst->num_clks, inst->clks); + + return 0; +} + +static const struct phy_ops google_usb2_phy_ops =3D { + .init =3D google_usb2_phy_init, + .exit =3D google_usb2_phy_exit, +}; + +static struct phy *google_usb_phy_xlate(struct device *dev, + const struct of_phandle_args *args) +{ + struct google_usb_phy *gphy =3D dev_get_drvdata(dev); + + if (args->args[0] >=3D GOOGLE_USB_PHY_NUM) { + dev_err(dev, "invalid PHY index requested from DT\n"); + return ERR_PTR(-ENODEV); + } + return gphy->insts[args->args[0]].phy; +} + +static int google_usb_phy_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct google_usb_phy *gphy; + struct phy *phy; + struct google_usb_phy_instance *inst; + struct phy_provider *phy_provider; + struct typec_switch_desc sw_desc =3D { }; + int ret; + + gphy =3D devm_kzalloc(dev, sizeof(*gphy), GFP_KERNEL); + if (!gphy) + return -ENOMEM; + + dev_set_drvdata(dev, gphy); + gphy->dev =3D dev; + + ret =3D devm_mutex_init(dev, &gphy->phy_mutex); + if (ret) + return ret; + + gphy->usb2_cfg_base =3D devm_platform_ioremap_resource_byname(pdev, + "usb2_cfg"); + if (IS_ERR(gphy->usb2_cfg_base)) + return dev_err_probe(dev, PTR_ERR(gphy->usb2_cfg_base), + "invalid usb2 cfg\n"); + + gphy->usb3_top_base =3D devm_platform_ioremap_resource_byname(pdev, + "usb3_top"); + if (IS_ERR(gphy->usb3_top_base)) + return dev_err_probe(dev, PTR_ERR(gphy->usb3_top_base), + "invalid usb3 top\n"); + + inst =3D &gphy->insts[GOOGLE_USB2_PHY]; + inst->index =3D GOOGLE_USB2_PHY; + phy =3D devm_phy_create(dev, NULL, &google_usb2_phy_ops); + if (IS_ERR(phy)) + return dev_err_probe(dev, PTR_ERR(phy), + "failed to create usb2 phy instance\n"); + inst->phy =3D phy; + phy_set_drvdata(phy, inst); + ret =3D devm_clk_bulk_get_all_enabled(dev, &inst->clks); + if (ret < 0) + return dev_err_probe(dev, ret, "failed to get u2 phy clks\n"); + inst->num_clks =3D ret; + + inst->rsts =3D devm_reset_control_array_get_exclusive(dev); + if (IS_ERR(inst->rsts)) + return dev_err_probe(dev, PTR_ERR(inst->rsts), + "failed to get u2 phy resets\n"); + + phy_provider =3D devm_of_phy_provider_register(dev, google_usb_phy_xlate); + if (IS_ERR(phy_provider)) + return dev_err_probe(dev, PTR_ERR(phy_provider), + "failed to register phy provider\n"); + + pm_runtime_enable(dev); + + sw_desc.fwnode =3D dev_fwnode(dev); + sw_desc.drvdata =3D gphy; + sw_desc.name =3D fwnode_get_name(dev_fwnode(dev)); + sw_desc.set =3D google_usb_set_orientation; + + gphy->sw =3D typec_switch_register(dev, &sw_desc); + if (IS_ERR(gphy->sw)) + return dev_err_probe(dev, PTR_ERR(gphy->sw), + "failed to register typec switch\n"); + + return 0; +} + +static void google_usb_phy_remove(struct platform_device *pdev) +{ + struct google_usb_phy *gphy =3D dev_get_drvdata(&pdev->dev); + + typec_switch_unregister(gphy->sw); + pm_runtime_disable(&pdev->dev); +} + +static const struct of_device_id google_usb_phy_of_match[] =3D { + { + .compatible =3D "google,gs5-usb-phy", + }, + { } +}; +MODULE_DEVICE_TABLE(of, google_usb_phy_of_match); + +static struct platform_driver google_usb_phy =3D { + .probe =3D google_usb_phy_probe, + .remove =3D google_usb_phy_remove, + .driver =3D { + .name =3D "google-usb-phy", + .of_match_table =3D google_usb_phy_of_match, + } +}; + +module_platform_driver(google_usb_phy); +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Google USB phy driver"); --=20 2.51.1.851.g4ebd6896fd-goog