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AJvYcCUAuC4ypHhpc3Zs21Q2cN1HyWK6AkCwvJUJvEzY/dBRdic8TX9BOirYxqBKdjOMp8c1stSmyKixRR1Ux2c=@vger.kernel.org X-Gm-Message-State: AOJu0YwcnjAC28perq4aYgRgwnKh79mucMwP/B8NYU6yyoFMWWZD6c1O JcHUKUJ2J6L+jfoWHzaCnc9CB7z09NvD3DpK5iGQsj9E3aHZgGpzTpUiGGnRr2KkF7uqJa45vuP afKFvWA== X-Google-Smtp-Source: AGHT+IHjZCapQlgh36DZaiJIbU3mEEeF0xr5npuEpjzvxQ1RgmrSJTd3OvlwYm13zuS1GDPmiCuLj+1oRUQ= X-Received: from plbla5.prod.google.com ([2002:a17:902:fa05:b0:27e:eb0e:15aa]) (user=royluo job=prod-delivery.src-stubby-dispatcher) by 2002:a17:902:ea03:b0:292:fe19:8896 with SMTP id d9443c01a7336-294def36a78mr46266815ad.52.1761774058892; Wed, 29 Oct 2025 14:40:58 -0700 (PDT) Date: Wed, 29 Oct 2025 21:40:31 +0000 In-Reply-To: <20251029214032.3175261-1-royluo@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20251029214032.3175261-1-royluo@google.com> X-Mailer: git-send-email 2.51.1.851.g4ebd6896fd-goog Message-ID: <20251029214032.3175261-2-royluo@google.com> Subject: [PATCH v5 1/2] dt-bindings: phy: google: Add Google Tensor G5 USB PHY From: Roy Luo To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Peter Griffin , "=?UTF-8?q?Andr=C3=A9=20Draszik?=" , Tudor Ambarus Cc: Doug Anderson , Joy Chakraborty , Naveen Kumar , Roy Luo , Badhri Jagan Sridharan , linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Document the device tree bindings for the USB PHY interfaces integrated with the DWC3 controller on Google Tensor SoCs, starting with G5 generation. The USB PHY on Tensor G5 includes two integrated Synopsys PHY IPs: the eUSB 2.0 PHY IP and the USB 3.2/DisplayPort combo PHY IP. Due to a complete architectural overhaul in the Google Tensor G5, the existing Samsung/Exynos USB PHY binding for older generations of Google silicons such as gs101 are no longer compatible, necessitating this new device tree binding. Signed-off-by: Roy Luo --- .../bindings/phy/google,gs5-usb-phy.yaml | 127 ++++++++++++++++++ 1 file changed, 127 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/google,gs5-usb-ph= y.yaml diff --git a/Documentation/devicetree/bindings/phy/google,gs5-usb-phy.yaml = b/Documentation/devicetree/bindings/phy/google,gs5-usb-phy.yaml new file mode 100644 index 000000000000..8a590036fbac --- /dev/null +++ b/Documentation/devicetree/bindings/phy/google,gs5-usb-phy.yaml @@ -0,0 +1,127 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2025, Google LLC +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/google,gs5-usb-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Google Tensor Series (G5+) USB PHY + +maintainers: + - Roy Luo + +description: | + Describes the USB PHY interfaces integrated with the DWC3 USB controller= on + Google Tensor SoCs, starting with the G5 generation. + Two specific PHY IPs from Synopsys are integrated, including eUSB 2.0 PH= Y IP + and USB 3.2/DisplayPort combo PHY IP. + +properties: + compatible: + const: google,gs5-usb-phy + + reg: + items: + - description: USB3.2/DisplayPort combo PHY core registers. + - description: USB3.2/DisplayPort combo PHY Type-C Assist registers. + - description: USB2 PHY configuration registers. + - description: USB3.2/DisplayPort combo PHY top-level registers. + + reg-names: + items: + - const: usb3_core + - const: usb3_tca + - const: usb2_cfg + - const: usb3_top + + "#phy-cells": + description: | + The phandle's argument in the PHY specifier selects one of the three + following PHY interfaces. + - 0 for USB high-speed. + - 1 for USB super-speed. + - 2 for DisplayPort. + const: 1 + + clocks: + minItems: 2 + items: + - description: USB2 PHY clock. + - description: USB2 PHY APB clock. + - description: USB3.2/DisplayPort combo PHY clock. + - description: USB3.2/DisplayPort combo PHY firmware clock. + description: + USB3 clocks are optional if the device is intended for USB2-only + operation. + + clock-names: + minItems: 2 + items: + - const: usb2 + - const: usb2_apb + - const: usb3 + - const: usb3_fw + + resets: + minItems: 2 + items: + - description: USB2 PHY reset. + - description: USB2 PHY APB reset. + - description: USB3.2/DisplayPort combo PHY reset. + description: + USB3 clocks are optional if the device is intended for USB2-only + operation. + + reset-names: + minItems: 2 + items: + - const: usb2 + - const: usb2_apb + - const: usb3 + + power-domains: + maxItems: 1 + + orientation-switch: + type: boolean + description: + Indicates the PHY as a handler of USB Type-C orientation changes + +required: + - compatible + - reg + - reg-names + - "#phy-cells" + - clocks + - clock-names + - resets + - reset-names + - power-domains + - orientation-switch + +additionalProperties: false + +examples: + - | + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + usb_phy: usb_phy@c410000 { + compatible =3D "google,gs5-usb-phy"; + reg =3D <0 0x0c410000 0 0x20000>, + <0 0x0c430000 0 0x1000>, + <0 0x0c450014 0 0xc>, + <0 0x0c637000 0 0xa0>; + reg-names =3D "usb3_core", "usb3_tca", "usb2_cfg", "usb3_top"; + #phy-cells =3D <1>; + clocks =3D <&hsion_usb2_phy_clk>, <&hsion_u2phy_apb_clk>; + clock-names =3D "usb2", "usb2_apb"; + resets =3D <&hsion_resets_usb2_phy>, + <&hsion_resets_u2phy_apb>; + reset-names =3D "usb2", "usb2_apb"; + power-domains =3D <&hsio_n_usb_pd>; + orientation-switch; + }; + }; +... --=20 2.51.1.851.g4ebd6896fd-goog