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[93.34.90.37]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-429952d9e80sm27493844f8f.28.2025.10.29.10.37.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Oct 2025 10:37:24 -0700 (PDT) From: Christian Marangi To: Christian Marangi , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lorenzo Bianconi , linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 1/4] dt-bindings: soc: Add bindings for Airoha SCU Serdes lines Date: Wed, 29 Oct 2025 18:37:09 +0100 Message-ID: <20251029173713.7670-2-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251029173713.7670-1-ansuelsmth@gmail.com> References: <20251029173713.7670-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Airoha AN7581 SoC can configure the SCU serdes lines for multiple purpose. For example the Serdes for the USB1 port can be both used for USB 3.0 operation or for Ethernet. Or the USB2 serdes can both used for USB 3.0 operation or for PCIe. The PCIe Serdes can be both used for PCIe operation or for Ethernet. Add bindings to permit correct reference of the different ports in DT, mostly to differentiate the different supported modes internally to the drivers. Signed-off-by: Christian Marangi --- include/dt-bindings/soc/airoha,scu-ssr.h | 11 +++++++++++ 1 file changed, 11 insertions(+) create mode 100644 include/dt-bindings/soc/airoha,scu-ssr.h diff --git a/include/dt-bindings/soc/airoha,scu-ssr.h b/include/dt-bindings= /soc/airoha,scu-ssr.h new file mode 100644 index 000000000000..33c64844ada3 --- /dev/null +++ b/include/dt-bindings/soc/airoha,scu-ssr.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef __DT_BINDINGS_AIROHA_SCU_SSR_H +#define __DT_BINDINGS_AIROHA_SCU_SSR_H + +#define AIROHA_SCU_SERDES_PCIE1 0 +#define AIROHA_SCU_SERDES_PCIE2 1 +#define AIROHA_SCU_SERDES_USB1 2 +#define AIROHA_SCU_SERDES_USB2 3 + +#endif /* __DT_BINDINGS_AIROHA_SCU_SSR_H */ --=20 2.51.0