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[2003:e4:1f27:4600:f22f:74ff:fe1f:3a53]) by smtp.gmail.com with UTF8SMTPSA id a640c23a62f3a-b6d853e5138sm1485764866b.44.2025.10.29.09.33.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Oct 2025 09:33:46 -0700 (PDT) From: Thierry Reding To: Greg Kroah-Hartman , "Rafael J. Wysocki" Cc: x86@kernel.org, linux-arm-kernel@lists.infradead.org, linux-riscv@lists.infradead.org, linux-mips@vger.kernel.org, loongarch@lists.linux.dev, linuxppc-dev@lists.ozlabs.org, linux-sh@vger.kernel.org, linux-pci@vger.kernel.org, linux-acpi@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 2/7] MIPS: PCI: Use contextual data instead of global variable Date: Wed, 29 Oct 2025 17:33:31 +0100 Message-ID: <20251029163336.2785270-3-thierry.reding@gmail.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251029163336.2785270-1-thierry.reding@gmail.com> References: <20251029163336.2785270-1-thierry.reding@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Thierry Reding Pass the driver-specific data via the syscore struct and use it in the syscore ops. Signed-off-by: Thierry Reding --- Changes in v3: - adjust for API changes and update commit message Changes in v2: - remove unused global variable arch/mips/pci/pci-alchemy.c | 24 ++++++------------------ 1 file changed, 6 insertions(+), 18 deletions(-) diff --git a/arch/mips/pci/pci-alchemy.c b/arch/mips/pci/pci-alchemy.c index 6bfee0f71803..f73bf60bd069 100644 --- a/arch/mips/pci/pci-alchemy.c +++ b/arch/mips/pci/pci-alchemy.c @@ -33,6 +33,7 @@ =20 struct alchemy_pci_context { struct pci_controller alchemy_pci_ctrl; /* leave as first member! */ + struct syscore syscore; void __iomem *regs; /* ctrl base */ /* tools for wired entry for config space access */ unsigned long last_elo0; @@ -46,12 +47,6 @@ struct alchemy_pci_context { int (*board_pci_idsel)(unsigned int devsel, int assert); }; =20 -/* for syscore_ops. There's only one PCI controller on Alchemy chips, so t= his - * should suffice for now. - */ -static struct alchemy_pci_context *__alchemy_pci_ctx; - - /* IO/MEM resources for PCI. Keep the memres in sync with fixup_bigphys_ad= dr * in arch/mips/alchemy/common/setup.c */ @@ -306,9 +301,7 @@ static int alchemy_pci_def_idsel(unsigned int devsel, i= nt assert) /* save PCI controller register contents. */ static int alchemy_pci_suspend(void *data) { - struct alchemy_pci_context *ctx =3D __alchemy_pci_ctx; - if (!ctx) - return 0; + struct alchemy_pci_context *ctx =3D data; =20 ctx->pm[0] =3D __raw_readl(ctx->regs + PCI_REG_CMEM); ctx->pm[1] =3D __raw_readl(ctx->regs + PCI_REG_CONFIG) & 0x0009ffff; @@ -328,9 +321,7 @@ static int alchemy_pci_suspend(void *data) =20 static void alchemy_pci_resume(void *data) { - struct alchemy_pci_context *ctx =3D __alchemy_pci_ctx; - if (!ctx) - return; + struct alchemy_pci_context *ctx =3D data; =20 __raw_writel(ctx->pm[0], ctx->regs + PCI_REG_CMEM); __raw_writel(ctx->pm[2], ctx->regs + PCI_REG_B2BMASK_CCH); @@ -359,10 +350,6 @@ static const struct syscore_ops alchemy_pci_syscore_op= s =3D { .resume =3D alchemy_pci_resume, }; =20 -static struct syscore alchemy_pci_syscore =3D { - .ops =3D &alchemy_pci_syscore_ops, -}; - static int alchemy_pci_probe(struct platform_device *pdev) { struct alchemy_pci_platdata *pd =3D pdev->dev.platform_data; @@ -480,9 +467,10 @@ static int alchemy_pci_probe(struct platform_device *p= dev) __raw_writel(val, ctx->regs + PCI_REG_CONFIG); wmb(); =20 - __alchemy_pci_ctx =3D ctx; platform_set_drvdata(pdev, ctx); - register_syscore(&alchemy_pci_syscore); + ctx->syscore.ops =3D &alchemy_pci_syscore_ops; + ctx->syscore.data =3D ctx; + register_syscore(&ctx->syscore); register_pci_controller(&ctx->alchemy_pci_ctrl); =20 dev_info(&pdev->dev, "PCI controller at %ld MHz\n", --=20 2.51.0