From nobody Sun Feb 8 17:36:55 2026 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A651D34A77E; Wed, 29 Oct 2025 14:47:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.171.202.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761749239; cv=none; b=c+VNfUL2xZuJIR/UmpRs2g3fiMfLZMqngszlwshEYBkU/5ZES90DJl8Y0xjN8tZCaHLU2fSA9WvomKGrqhSgIrhXU2Mdl2RRu0JuxzsVW713uGFWONI2lhDnNJ1Kvol9zH8AJn2kmxwhViL2ltKmfQAaHbrH40BbtH0k1JFK284= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761749239; c=relaxed/simple; bh=Iq9TOV4FcGWhqql6PtEpR26BCz7j6f4oU9hSvDKk5F4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=hswAplYu+Xq0pjd6YG26r7zu7HfBv0XD4CEwYGwERM5/m1L4c144yLo17AeJcR3exG+oOxsp1YXWXGu7Kv8hlYT5ZOEzdcNWdXZfEhDcC0mUP6JMWyrAQ1Bv1NL1ccW40bymwELxBNWyx39xZGRbXU4kClZL9TWxLjkmr4MTRv4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=u4f+gfDT; arc=none smtp.client-ip=185.171.202.116 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="u4f+gfDT" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-04.galae.net (Postfix) with ESMTPS id E5FF0C0DA83; Wed, 29 Oct 2025 14:46:55 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 4976B606E8; Wed, 29 Oct 2025 14:47:16 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id DE80F102F24F9; Wed, 29 Oct 2025 15:47:13 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1761749235; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=32YjyCAMTifsZOSn5l7Q5VxrAGZMoiALl3BPu6raayM=; b=u4f+gfDTXduqu9W7spUIVYKchETYLNw5B2oR8VBj90ITnXSO1Y16cEBeONKQZrDZnfuwqC Xv4qm9pYmTJ9OWEoedNtYUhXC+DtjqvhoHc21uqJlxqiLs1DYETffMGNB31fQfVjUMlxMz 01hHuByXGZu4RlNaEw12qLrg5jx3RdHVswTpVM09T4Kx39xQiMlMxlnib0wiBzREG6kH7E t6cnsgah5vuLOjJZNoggroLarmHEc5wJAyMTNwPNmCeWV4IIRIi+feUo5ZNl0gfOQsOaXY Y3ivh2xfYVVoThuWA+v7WoguQD8PrbV9vCFSxnGdcfxhjYSG4rsC4PUC7z/wGA== From: "Herve Codina (Schneider Electric)" To: Wolfram Sang , Herve Codina , Jonathan Cameron , David Lechner , =?UTF-8?q?Nuno=20S=C3=A1?= , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Liam Girdwood , Mark Brown Cc: linux-iio@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Pascal Eberhard , Miquel Raynal , Thomas Petazzoni Subject: [PATCH v2 3/4] ARM: dts: renesas: r9a06g032: Add the ADC device Date: Wed, 29 Oct 2025 15:46:43 +0100 Message-ID: <20251029144644.667561-4-herve.codina@bootlin.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251029144644.667561-1-herve.codina@bootlin.com> References: <20251029144644.667561-1-herve.codina@bootlin.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" The ADC available in the r9a06g032 SoC can use up to two internal ADC cores (ADC1 and ADC2) those internal cores are handled through ADC controller virtual channels. Describe this device. Signed-off-by: Herve Codina (Schneider Electric) Reviewed-by: Wolfram Sang --- arch/arm/boot/dts/renesas/r9a06g032.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/renesas/r9a06g032.dtsi b/arch/arm/boot/dts/r= enesas/r9a06g032.dtsi index 13a60656b044..2c1577923223 100644 --- a/arch/arm/boot/dts/renesas/r9a06g032.dtsi +++ b/arch/arm/boot/dts/renesas/r9a06g032.dtsi @@ -290,6 +290,16 @@ i2c2: i2c@40064000 { status =3D "disabled"; }; =20 + adc: adc@40065000 { + compatible =3D "renesas,r9a06g032-adc", "renesas,rzn1-adc"; + reg =3D <0x40065000 0x200>; + clocks =3D <&sysctrl R9A06G032_HCLK_ADC>, <&sysctrl R9A06G032_CLK_ADC>; + clock-names =3D "pclk", "adc"; + power-domains =3D <&sysctrl>; + #io-channel-cells =3D <1>; + status =3D "disabled"; + }; + pinctrl: pinctrl@40067000 { compatible =3D "renesas,r9a06g032-pinctrl", "renesas,rzn1-pinctrl"; reg =3D <0x40067000 0x1000>, <0x51000000 0x480>; --=20 2.51.0