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Wed, 29 Oct 2025 06:56:00 -0700 (PDT) From: Laurentiu Mihalcea To: Abel Vesa , Peng Fan , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Fabio Estevam , Philipp Zabel , Daniel Baluta , Shengjiu Wang Cc: linux-clk@vger.kernel.org, imx@lists.linux.dev, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Pengutronix Kernel Team Subject: [PATCH v3 1/8] reset: imx8mp-audiomix: Fix bad mask values Date: Wed, 29 Oct 2025 06:52:22 -0700 Message-ID: <20251029135229.890-2-laurentiumihalcea111@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251029135229.890-1-laurentiumihalcea111@gmail.com> References: <20251029135229.890-1-laurentiumihalcea111@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Laurentiu Mihalcea As per the i.MX8MP TRM, section 14.2 "AUDIO_BLK_CTRL", table 14.2.3.1.1 "memory map", the definition of the EARC control register shows that the EARC controller software reset is controlled via bit 0, while the EARC PHY software reset is controlled via bit 1. This means that the current definitions of IMX8MP_AUDIOMIX_EARC_RESET_MASK and IMX8MP_AUDIOMIX_EARC_PHY_RESET_MASK are wrong since their values would imply that the EARC controller software reset is controlled via bit 1 and the EARC PHY software reset is controlled via bit 2. Fix them. Fixes: a83bc87cd30a ("reset: imx8mp-audiomix: Prepare the code for more res= et bits") Cc: stable@vger.kernel.org Reviewed-by: Shengjiu Wang Reviewed-by: Frank Li Reviewed-by: Daniel Baluta Signed-off-by: Laurentiu Mihalcea --- drivers/reset/reset-imx8mp-audiomix.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/reset/reset-imx8mp-audiomix.c b/drivers/reset/reset-im= x8mp-audiomix.c index 6b357adfe646..eceb37ff5dc5 100644 --- a/drivers/reset/reset-imx8mp-audiomix.c +++ b/drivers/reset/reset-imx8mp-audiomix.c @@ -14,8 +14,8 @@ #include =20 #define IMX8MP_AUDIOMIX_EARC_RESET_OFFSET 0x200 -#define IMX8MP_AUDIOMIX_EARC_RESET_MASK BIT(1) -#define IMX8MP_AUDIOMIX_EARC_PHY_RESET_MASK BIT(2) +#define IMX8MP_AUDIOMIX_EARC_RESET_MASK BIT(0) +#define IMX8MP_AUDIOMIX_EARC_PHY_RESET_MASK BIT(1) =20 #define IMX8MP_AUDIOMIX_DSP_RUNSTALL_OFFSET 0x108 #define IMX8MP_AUDIOMIX_DSP_RUNSTALL_MASK BIT(5) --=20 2.43.0 From nobody Sun Feb 8 13:53:07 2026 Received: from mail-ej1-f53.google.com (mail-ej1-f53.google.com [209.85.218.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B9810277818 for ; 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charset="utf-8" From: Laurentiu Mihalcea Add documentation for i.MX8ULP's SIM LPAV module. Reviewed-by: Krzysztof Kozlowski Reviewed-by: Daniel Baluta Signed-off-by: Laurentiu Mihalcea --- .../bindings/clock/fsl,imx8ulp-sim-lpav.yaml | 72 +++++++++++++++++++ include/dt-bindings/clock/imx8ulp-clock.h | 5 ++ .../dt-bindings/reset/fsl,imx8ulp-sim-lpav.h | 16 +++++ 3 files changed, 93 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/fsl,imx8ulp-sim= -lpav.yaml create mode 100644 include/dt-bindings/reset/fsl,imx8ulp-sim-lpav.h diff --git a/Documentation/devicetree/bindings/clock/fsl,imx8ulp-sim-lpav.y= aml b/Documentation/devicetree/bindings/clock/fsl,imx8ulp-sim-lpav.yaml new file mode 100644 index 000000000000..662e07528d76 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/fsl,imx8ulp-sim-lpav.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/fsl,imx8ulp-sim-lpav.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP i.MX8ULP LPAV System Integration Module (SIM) + +maintainers: + - Laurentiu Mihalcea + +description: + The i.MX8ULP LPAV subsystem contains a block control module known as + SIM LPAV, which offers functionalities such as clock gating or reset + line assertion/de-assertion. + +properties: + compatible: + const: fsl,imx8ulp-sim-lpav + + reg: + maxItems: 1 + + clocks: + maxItems: 3 + + clock-names: + items: + - const: bus + - const: core + - const: plat + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + mux-controller: + $ref: /schemas/mux/reg-mux.yaml# + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#reset-cells' + - mux-controller + +additionalProperties: false + +examples: + - | + #include + + clock-controller@2da50000 { + compatible =3D "fsl,imx8ulp-sim-lpav"; + reg =3D <0x2da50000 0x10000>; + clocks =3D <&cgc2 IMX8ULP_CLK_LPAV_BUS_DIV>, + <&cgc2 IMX8ULP_CLK_HIFI_DIVCORE>, + <&cgc2 IMX8ULP_CLK_HIFI_DIVPLAT>; + clock-names =3D "bus", "core", "plat"; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + + mux-controller { + compatible =3D "reg-mux"; + #mux-control-cells =3D <1>; + mux-reg-masks =3D <0x8 0x00000200>; + }; + }; diff --git a/include/dt-bindings/clock/imx8ulp-clock.h b/include/dt-binding= s/clock/imx8ulp-clock.h index 827404fadf5c..c62d84d093a9 100644 --- a/include/dt-bindings/clock/imx8ulp-clock.h +++ b/include/dt-bindings/clock/imx8ulp-clock.h @@ -255,4 +255,9 @@ =20 #define IMX8ULP_CLK_PCC5_END 56 =20 +/* LPAV SIM */ +#define IMX8ULP_CLK_SIM_LPAV_HIFI_CORE 0 +#define IMX8ULP_CLK_SIM_LPAV_HIFI_PBCLK 1 +#define IMX8ULP_CLK_SIM_LPAV_HIFI_PLAT 2 + #endif diff --git a/include/dt-bindings/reset/fsl,imx8ulp-sim-lpav.h b/include/dt-= bindings/reset/fsl,imx8ulp-sim-lpav.h new file mode 100644 index 000000000000..adf95bb26d21 --- /dev/null +++ b/include/dt-bindings/reset/fsl,imx8ulp-sim-lpav.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright 2025 NXP + */ + +#ifndef DT_BINDING_RESET_IMX8ULP_SIM_LPAV_H +#define DT_BINDING_RESET_IMX8ULP_SIM_LPAV_H + +#define IMX8ULP_SIM_LPAV_HIFI4_DSP_DBG_RST 0 +#define IMX8ULP_SIM_LPAV_HIFI4_DSP_RST 1 +#define IMX8ULP_SIM_LPAV_HIFI4_DSP_STALL 2 +#define IMX8ULP_SIM_LPAV_DSI_RST_BYTE_N 3 +#define IMX8ULP_SIM_LPAV_DSI_RST_ESC_N 4 +#define IMX8ULP_SIM_LPAV_DSI_RST_DPI_N 5 + +#endif /* DT_BINDING_RESET_IMX8ULP_SIM_LPAV_H */ --=20 2.43.0 From nobody Sun Feb 8 13:53:07 2026 Received: from mail-ej1-f47.google.com (mail-ej1-f47.google.com [209.85.218.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0D4143559C1 for ; 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Wed, 29 Oct 2025 06:56:07 -0700 (PDT) Received: from SMW024614.wbi.nxp.com ([128.77.115.157]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b6d8534d99dsm1444960766b.21.2025.10.29.06.56.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Oct 2025 06:56:06 -0700 (PDT) From: Laurentiu Mihalcea To: Abel Vesa , Peng Fan , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Fabio Estevam , Philipp Zabel , Daniel Baluta , Shengjiu Wang Cc: linux-clk@vger.kernel.org, imx@lists.linux.dev, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Pengutronix Kernel Team Subject: [PATCH v3 3/8] clk: imx: add driver for imx8ulp's sim lpav Date: Wed, 29 Oct 2025 06:52:24 -0700 Message-ID: <20251029135229.890-4-laurentiumihalcea111@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251029135229.890-1-laurentiumihalcea111@gmail.com> References: <20251029135229.890-1-laurentiumihalcea111@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Laurentiu Mihalcea The i.MX8ULP System Integration Module (SIM) LPAV module is a block control module found inside the LPAV subsystem, which offers some clock gating options and reset line assertion/de-assertion capabilities. Therefore, the clock gate management is supported by registering the module's driver as a clock provider, while the reset capabilities are managed via the auxiliary device API to allow the DT node to act as a reset and clock provider. Signed-off-by: Laurentiu Mihalcea Reviewed-by: Peng Fan --- drivers/clk/imx/Makefile | 1 + drivers/clk/imx/clk-imx8ulp-sim-lpav.c | 160 +++++++++++++++++++++++++ 2 files changed, 161 insertions(+) create mode 100644 drivers/clk/imx/clk-imx8ulp-sim-lpav.c diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile index 03f2b2a1ab63..208b46873a18 100644 --- a/drivers/clk/imx/Makefile +++ b/drivers/clk/imx/Makefile @@ -41,6 +41,7 @@ clk-imx-lpcg-scu-$(CONFIG_CLK_IMX8QXP) +=3D clk-lpcg-scu.= o clk-imx8qxp-lpcg.o clk-imx-acm-$(CONFIG_CLK_IMX8QXP) =3D clk-imx8-acm.o =20 obj-$(CONFIG_CLK_IMX8ULP) +=3D clk-imx8ulp.o +obj-$(CONFIG_CLK_IMX8ULP) +=3D clk-imx8ulp-sim-lpav.o =20 obj-$(CONFIG_CLK_IMX1) +=3D clk-imx1.o obj-$(CONFIG_CLK_IMX25) +=3D clk-imx25.o diff --git a/drivers/clk/imx/clk-imx8ulp-sim-lpav.c b/drivers/clk/imx/clk-i= mx8ulp-sim-lpav.c new file mode 100644 index 000000000000..1614d9209734 --- /dev/null +++ b/drivers/clk/imx/clk-imx8ulp-sim-lpav.c @@ -0,0 +1,160 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2025 NXP + */ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#define SYSCTRL0 0x8 + +#define IMX8ULP_HIFI_CLK_GATE(gname, cname, pname, bidx) \ + { \ + .name =3D gname "_cg", \ + .id =3D IMX8ULP_CLK_SIM_LPAV_HIFI_##cname, \ + .parent =3D { .fw_name =3D pname }, \ + .bit =3D bidx, \ + } + +struct clk_imx8ulp_sim_lpav_data { + void __iomem *base; + struct regmap *regmap; + spinlock_t lock; /* shared by MUX, clock gate and reset */ + unsigned long flags; /* for spinlock usage */ + struct clk_hw_onecell_data clk_data; /* keep last */ +}; + +struct clk_imx8ulp_sim_lpav_gate { + const char *name; + int id; + const struct clk_parent_data parent; + u8 bit; +}; + +static struct clk_imx8ulp_sim_lpav_gate gates[] =3D { + IMX8ULP_HIFI_CLK_GATE("hifi_core", CORE, "core", 17), + IMX8ULP_HIFI_CLK_GATE("hifi_pbclk", PBCLK, "bus", 18), + IMX8ULP_HIFI_CLK_GATE("hifi_plat", PLAT, "plat", 19) +}; + +static void clk_imx8ulp_sim_lpav_lock(void *arg) __acquires(&data->lock) +{ + struct clk_imx8ulp_sim_lpav_data *data =3D dev_get_drvdata(arg); + + spin_lock_irqsave(&data->lock, data->flags); +} + +static void clk_imx8ulp_sim_lpav_unlock(void *arg) __releases(&data->lock) +{ + struct clk_imx8ulp_sim_lpav_data *data =3D dev_get_drvdata(arg); + + spin_unlock_irqrestore(&data->lock, data->flags); +} + +static const struct regmap_config clk_imx8ulp_sim_lpav_regmap_cfg =3D { + .reg_bits =3D 32, + .val_bits =3D 32, + .reg_stride =3D 4, + .lock =3D clk_imx8ulp_sim_lpav_lock, + .unlock =3D clk_imx8ulp_sim_lpav_unlock, +}; + +static int clk_imx8ulp_sim_lpav_probe(struct platform_device *pdev) +{ + struct clk_imx8ulp_sim_lpav_data *data; + struct regmap_config regmap_config; + struct auxiliary_device *adev; + struct clk_hw *hw; + int i, ret; + + data =3D devm_kzalloc(&pdev->dev, + struct_size(data, clk_data.hws, ARRAY_SIZE(gates)), + GFP_KERNEL); + if (!data) + return -ENOMEM; + + dev_set_drvdata(&pdev->dev, data); + + memcpy(®map_config, &clk_imx8ulp_sim_lpav_regmap_cfg, sizeof(regmap_co= nfig)); + regmap_config.lock_arg =3D &pdev->dev; + + /* + * this lock is used directly by the clock gate and indirectly + * by the reset and mux controller via the regmap API + */ + spin_lock_init(&data->lock); + + data->base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(data->base)) + return dev_err_probe(&pdev->dev, PTR_ERR(data->base), + "failed to ioremap base\n"); + /* + * although the clock gate doesn't use the regmap API to modify the + * registers, we still need the regmap because of the reset auxiliary + * driver and the MUX drivers, which use the parent device's regmap + */ + data->regmap =3D devm_regmap_init_mmio(&pdev->dev, data->base, ®map_co= nfig); + if (IS_ERR(data->regmap)) + return dev_err_probe(&pdev->dev, PTR_ERR(data->regmap), + "failed to initialize regmap\n"); + + data->clk_data.num =3D ARRAY_SIZE(gates); + + for (i =3D 0; i < ARRAY_SIZE(gates); i++) { + hw =3D devm_clk_hw_register_gate_parent_data(&pdev->dev, + gates[i].name, + &gates[i].parent, + CLK_SET_RATE_PARENT, + data->base + SYSCTRL0, + gates[i].bit, + 0x0, &data->lock); + if (IS_ERR(hw)) + return dev_err_probe(&pdev->dev, PTR_ERR(hw), + "failed to register %s gate\n", + gates[i].name); + + data->clk_data.hws[i] =3D hw; + } + + adev =3D devm_auxiliary_device_create(&pdev->dev, "reset", NULL); + if (!adev) + return dev_err_probe(&pdev->dev, -ENODEV, + "failed to register aux reset\n"); + + ret =3D devm_of_clk_add_hw_provider(&pdev->dev, + of_clk_hw_onecell_get, + &data->clk_data); + if (ret) + return dev_err_probe(&pdev->dev, ret, + "failed to register clk hw provider\n"); + + /* used to probe MUX child device */ + return devm_of_platform_populate(&pdev->dev); +} + +static const struct of_device_id clk_imx8ulp_sim_lpav_of_match[] =3D { + { .compatible =3D "fsl,imx8ulp-sim-lpav" }, + { } +}; +MODULE_DEVICE_TABLE(of, clk_imx8ulp_sim_lpav_of_match); + +static struct platform_driver clk_imx8ulp_sim_lpav_driver =3D { + .probe =3D clk_imx8ulp_sim_lpav_probe, + .driver =3D { + .name =3D "clk-imx8ulp-sim-lpav", + .of_match_table =3D clk_imx8ulp_sim_lpav_of_match, + }, +}; +module_platform_driver(clk_imx8ulp_sim_lpav_driver); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("i.MX8ULP LPAV System Integration Module (SIM) clock dr= iver"); +MODULE_AUTHOR("Laurentiu Mihalcea "); --=20 2.43.0 From nobody Sun Feb 8 13:53:07 2026 Received: from mail-ej1-f41.google.com (mail-ej1-f41.google.com [209.85.218.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 03E6F3559DA for ; Wed, 29 Oct 2025 13:56:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.41 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761746174; cv=none; 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charset="utf-8" From: Laurentiu Mihalcea The macros defining the mask values for the EARC, EARC PHY resets, and the DSP RUN_STALL signal can be dropped as they are not and will not be used anywhere else except to set the value of the "mask" field from "struct imx8mp_reset_map". In this particular case, based on the name of the "mask" field, you can already deduce what these values are for, which is why defining macros for them doesn't offer any new information, nor does it help with the code readability. Reviewed-by: Daniel Baluta Signed-off-by: Laurentiu Mihalcea Reviewed-by: Frank Li --- drivers/reset/reset-imx8mp-audiomix.c | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) diff --git a/drivers/reset/reset-imx8mp-audiomix.c b/drivers/reset/reset-im= x8mp-audiomix.c index eceb37ff5dc5..e9643365a62c 100644 --- a/drivers/reset/reset-imx8mp-audiomix.c +++ b/drivers/reset/reset-imx8mp-audiomix.c @@ -14,11 +14,7 @@ #include =20 #define IMX8MP_AUDIOMIX_EARC_RESET_OFFSET 0x200 -#define IMX8MP_AUDIOMIX_EARC_RESET_MASK BIT(0) -#define IMX8MP_AUDIOMIX_EARC_PHY_RESET_MASK BIT(1) - #define IMX8MP_AUDIOMIX_DSP_RUNSTALL_OFFSET 0x108 -#define IMX8MP_AUDIOMIX_DSP_RUNSTALL_MASK BIT(5) =20 struct imx8mp_reset_map { unsigned int offset; @@ -29,17 +25,17 @@ struct imx8mp_reset_map { static const struct imx8mp_reset_map reset_map[] =3D { [IMX8MP_AUDIOMIX_EARC_RESET] =3D { .offset =3D IMX8MP_AUDIOMIX_EARC_RESET_OFFSET, - .mask =3D IMX8MP_AUDIOMIX_EARC_RESET_MASK, + .mask =3D BIT(0), .active_low =3D true, }, [IMX8MP_AUDIOMIX_EARC_PHY_RESET] =3D { .offset =3D IMX8MP_AUDIOMIX_EARC_RESET_OFFSET, - .mask =3D IMX8MP_AUDIOMIX_EARC_PHY_RESET_MASK, + .mask =3D BIT(1), .active_low =3D true, }, [IMX8MP_AUDIOMIX_DSP_RUNSTALL] =3D { .offset =3D IMX8MP_AUDIOMIX_DSP_RUNSTALL_OFFSET, - .mask =3D IMX8MP_AUDIOMIX_DSP_RUNSTALL_MASK, + .mask =3D BIT(5), .active_low =3D false, }, }; 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Wed, 29 Oct 2025 06:56:12 -0700 (PDT) From: Laurentiu Mihalcea To: Abel Vesa , Peng Fan , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Fabio Estevam , Philipp Zabel , Daniel Baluta , Shengjiu Wang Cc: linux-clk@vger.kernel.org, imx@lists.linux.dev, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Pengutronix Kernel Team Subject: [PATCH v3 5/8] reset: imx8mp-audiomix: Switch to using regmap API Date: Wed, 29 Oct 2025 06:52:26 -0700 Message-ID: <20251029135229.890-6-laurentiumihalcea111@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251029135229.890-1-laurentiumihalcea111@gmail.com> References: <20251029135229.890-1-laurentiumihalcea111@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Laurentiu Mihalcea As far as the Linux kernel is concerned, block devices such as i.MX8MP's AUDIOMIX block control or i.MX8ULP's SIM LPAV can simultaneously act as clock controllers, reset controllers or mux controllers. Since these IPs offer different functionalities through different subsystem APIs, it's important to make sure that the register R-M-W cycles are performed under the same lock across all subsystem APIs. This will ensure that registers will not end up with the wrong values because of race conditions (e.g. clock consumer tries to update block control register A, while, at the same time, reset consumer tries to update the same block control register). However, the aforementioned race conditions will only impact block control IPs which use the same register for multiple functionalities. For example, i.MX8MP's AUDIOMIX block control IP provides clock gating functionalities and reset control functionalities through different registers. This is why the current approach (i.e. clock control and reset control work using different locks) has worked well so far. Since we want to extend this driver to be usable for i.MX8ULP's SIM LPAV block control IP, we need to make sure that clock control, reset control, and mux control APIs use the same lock since all of these functionalities are performed using the SYSCTRL0 register. To do so, we need to switch to the regmap API and, if possible, use the parent device's regmap, which, in the case of i.MX8ULP, will be the clock controller. This way, we can make sure that the clock gates and the reset controller will use the same lock to perform the register R-M-W cycles. This change will also work fine for cases where we don't really need to share the lock across multiple APIs (e.g. i.MX8MP's AUDIOMIX block control) since regmap will take care of the locking we were previously explicitly performing in the driver. The transition to the regmap API also involves some cleanup. Specifically, we can make use of devres to unmap the device's memory and get rid of the memory mapping-related error paths and the remove() function altogether. Signed-off-by: Laurentiu Mihalcea --- drivers/reset/reset-imx8mp-audiomix.c | 91 +++++++++++++++++---------- 1 file changed, 57 insertions(+), 34 deletions(-) diff --git a/drivers/reset/reset-imx8mp-audiomix.c b/drivers/reset/reset-im= x8mp-audiomix.c index e9643365a62c..3f6d11270918 100644 --- a/drivers/reset/reset-imx8mp-audiomix.c +++ b/drivers/reset/reset-imx8mp-audiomix.c @@ -11,6 +11,7 @@ #include #include #include +#include #include =20 #define IMX8MP_AUDIOMIX_EARC_RESET_OFFSET 0x200 @@ -42,8 +43,8 @@ static const struct imx8mp_reset_map reset_map[] =3D { =20 struct imx8mp_audiomix_reset { struct reset_controller_dev rcdev; - spinlock_t lock; /* protect register read-modify-write cycle */ void __iomem *base; + struct regmap *regmap; }; =20 static struct imx8mp_audiomix_reset *to_imx8mp_audiomix_reset(struct reset= _controller_dev *rcdev) @@ -55,26 +56,15 @@ static int imx8mp_audiomix_update(struct reset_controll= er_dev *rcdev, unsigned long id, bool assert) { struct imx8mp_audiomix_reset *priv =3D to_imx8mp_audiomix_reset(rcdev); - void __iomem *reg_addr =3D priv->base; - unsigned int mask, offset, active_low; - unsigned long reg, flags; + unsigned int mask, offset, active_low, shift, val; =20 mask =3D reset_map[id].mask; offset =3D reset_map[id].offset; active_low =3D reset_map[id].active_low; + shift =3D ffs(mask) - 1; + val =3D (active_low ^ assert) << shift; =20 - spin_lock_irqsave(&priv->lock, flags); - - reg =3D readl(reg_addr + offset); - if (active_low ^ assert) - reg |=3D mask; - else - reg &=3D ~mask; - writel(reg, reg_addr + offset); - - spin_unlock_irqrestore(&priv->lock, flags); - - return 0; + return regmap_update_bits(priv->regmap, offset, mask, val); } =20 static int imx8mp_audiomix_reset_assert(struct reset_controller_dev *rcdev, @@ -94,6 +84,50 @@ static const struct reset_control_ops imx8mp_audiomix_re= set_ops =3D { .deassert =3D imx8mp_audiomix_reset_deassert, }; =20 +static const struct regmap_config regmap_config =3D { + .reg_bits =3D 32, + .val_bits =3D 32, + .reg_stride =3D 4, +}; + +/* assumption: registered only if not using parent regmap */ +static void imx8mp_audiomix_reset_iounmap(void *data) +{ + struct imx8mp_audiomix_reset *priv =3D dev_get_drvdata(data); + + iounmap(priv->base); +} + +/* assumption: dev_set_drvdata() is called before this */ +static int imx8mp_audiomix_reset_get_regmap(struct device *dev) +{ + struct imx8mp_audiomix_reset *priv; + int ret; + + priv =3D dev_get_drvdata(dev); + + /* try to use the parent's regmap */ + priv->regmap =3D dev_get_regmap(dev->parent, NULL); + if (priv->regmap) + return 0; + + /* ... if that's not possible then initialize the regmap right now */ + priv->base =3D of_iomap(dev->parent->of_node, 0); + if (!priv->base) + return dev_err_probe(dev, -ENOMEM, "failed to iomap address space\n"); + + ret =3D devm_add_action_or_reset(dev, imx8mp_audiomix_reset_iounmap, dev); + if (ret) + return dev_err_probe(dev, ret, "failed to register action\n"); + + priv->regmap =3D devm_regmap_init_mmio(dev, priv->base, ®map_config); + if (IS_ERR(priv->regmap)) + return dev_err_probe(dev, PTR_ERR(priv->regmap), + "failed to initialize regmap\n"); + + return 0; +} + static int imx8mp_audiomix_reset_probe(struct auxiliary_device *adev, const struct auxiliary_device_id *id) { @@ -105,36 +139,26 @@ static int imx8mp_audiomix_reset_probe(struct auxilia= ry_device *adev, if (!priv) return -ENOMEM; =20 - spin_lock_init(&priv->lock); - priv->rcdev.owner =3D THIS_MODULE; priv->rcdev.nr_resets =3D ARRAY_SIZE(reset_map); priv->rcdev.ops =3D &imx8mp_audiomix_reset_ops; priv->rcdev.of_node =3D dev->parent->of_node; priv->rcdev.dev =3D dev; priv->rcdev.of_reset_n_cells =3D 1; - priv->base =3D of_iomap(dev->parent->of_node, 0); - if (!priv->base) - return -ENOMEM; =20 + /* keep before call to imx8mp_audiomix_reset_init_regmap() */ dev_set_drvdata(dev, priv); =20 + ret =3D imx8mp_audiomix_reset_get_regmap(dev); + if (ret) + return dev_err_probe(dev, ret, "failed to get regmap\n"); + ret =3D devm_reset_controller_register(dev, &priv->rcdev); if (ret) - goto out_unmap; + return dev_err_probe(dev, ret, + "failed to register reset controller\n"); =20 return 0; - -out_unmap: - iounmap(priv->base); - return ret; -} - -static void imx8mp_audiomix_reset_remove(struct auxiliary_device *adev) -{ - struct imx8mp_audiomix_reset *priv =3D dev_get_drvdata(&adev->dev); - - iounmap(priv->base); } =20 static const struct auxiliary_device_id imx8mp_audiomix_reset_ids[] =3D { @@ -147,7 +171,6 @@ MODULE_DEVICE_TABLE(auxiliary, imx8mp_audiomix_reset_id= s); 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Wed, 29 Oct 2025 06:56:14 -0700 (PDT) From: Laurentiu Mihalcea To: Abel Vesa , Peng Fan , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Fabio Estevam , Philipp Zabel , Daniel Baluta , Shengjiu Wang Cc: linux-clk@vger.kernel.org, imx@lists.linux.dev, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Pengutronix Kernel Team Subject: [PATCH v3 6/8] reset: imx8mp-audiomix: Extend the driver usage Date: Wed, 29 Oct 2025 06:52:27 -0700 Message-ID: <20251029135229.890-7-laurentiumihalcea111@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251029135229.890-1-laurentiumihalcea111@gmail.com> References: <20251029135229.890-1-laurentiumihalcea111@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Laurentiu Mihalcea Replace the previous approach, in which a single reset map is used, by a per-driver approach, in which each auxiliary device driver holds a reference to a certain reset map. This change is needed to allow the driver to be reused for other NXP block control IPs such as i.MX8ULP's SIM LPAV. Reviewed-by: Daniel Baluta Signed-off-by: Laurentiu Mihalcea --- drivers/reset/reset-imx8mp-audiomix.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/drivers/reset/reset-imx8mp-audiomix.c b/drivers/reset/reset-im= x8mp-audiomix.c index 3f6d11270918..5ee5a32c6950 100644 --- a/drivers/reset/reset-imx8mp-audiomix.c +++ b/drivers/reset/reset-imx8mp-audiomix.c @@ -23,7 +23,12 @@ struct imx8mp_reset_map { bool active_low; }; =20 -static const struct imx8mp_reset_map reset_map[] =3D { +struct imx8mp_reset_info { + const struct imx8mp_reset_map *map; + int num_lines; +}; + +static const struct imx8mp_reset_map imx8mp_reset_map[] =3D { [IMX8MP_AUDIOMIX_EARC_RESET] =3D { .offset =3D IMX8MP_AUDIOMIX_EARC_RESET_OFFSET, .mask =3D BIT(0), @@ -41,10 +46,16 @@ static const struct imx8mp_reset_map reset_map[] =3D { }, }; =20 +static const struct imx8mp_reset_info imx8mp_reset_info =3D { + .map =3D imx8mp_reset_map, + .num_lines =3D ARRAY_SIZE(imx8mp_reset_map), +}; + struct imx8mp_audiomix_reset { struct reset_controller_dev rcdev; void __iomem *base; struct regmap *regmap; + const struct imx8mp_reset_info *rinfo; }; =20 static struct imx8mp_audiomix_reset *to_imx8mp_audiomix_reset(struct reset= _controller_dev *rcdev) @@ -56,6 +67,7 @@ static int imx8mp_audiomix_update(struct reset_controller= _dev *rcdev, unsigned long id, bool assert) { struct imx8mp_audiomix_reset *priv =3D to_imx8mp_audiomix_reset(rcdev); + const struct imx8mp_reset_map *reset_map =3D priv->rinfo->map; unsigned int mask, offset, active_low, shift, val; =20 mask =3D reset_map[id].mask; @@ -140,7 +152,8 @@ static int imx8mp_audiomix_reset_probe(struct auxiliary= _device *adev, return -ENOMEM; =20 priv->rcdev.owner =3D THIS_MODULE; - priv->rcdev.nr_resets =3D ARRAY_SIZE(reset_map); + priv->rinfo =3D (void *)id->driver_data; + priv->rcdev.nr_resets =3D priv->rinfo->num_lines; priv->rcdev.ops =3D &imx8mp_audiomix_reset_ops; priv->rcdev.of_node =3D dev->parent->of_node; priv->rcdev.dev =3D dev; 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charset="utf-8" From: Laurentiu Mihalcea Support i.MX8ULP's SIM LPAV by adding its reset map definition. Reviewed-by: Daniel Baluta Signed-off-by: Laurentiu Mihalcea Reviewed-by: Frank Li --- drivers/reset/reset-imx8mp-audiomix.c | 45 +++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/drivers/reset/reset-imx8mp-audiomix.c b/drivers/reset/reset-im= x8mp-audiomix.c index 5ee5a32c6950..4e420c6b8fdc 100644 --- a/drivers/reset/reset-imx8mp-audiomix.c +++ b/drivers/reset/reset-imx8mp-audiomix.c @@ -3,6 +3,7 @@ * Copyright 2024 NXP */ =20 +#include #include =20 #include @@ -17,6 +18,8 @@ #define IMX8MP_AUDIOMIX_EARC_RESET_OFFSET 0x200 #define IMX8MP_AUDIOMIX_DSP_RUNSTALL_OFFSET 0x108 =20 +#define IMX8ULP_SIM_LPAV_SYSCTRL0_OFFSET 0x8 + struct imx8mp_reset_map { unsigned int offset; unsigned int mask; @@ -51,6 +54,44 @@ static const struct imx8mp_reset_info imx8mp_reset_info = =3D { .num_lines =3D ARRAY_SIZE(imx8mp_reset_map), }; =20 +static const struct imx8mp_reset_map imx8ulp_reset_map[] =3D { + [IMX8ULP_SIM_LPAV_HIFI4_DSP_DBG_RST] =3D { + .offset =3D IMX8ULP_SIM_LPAV_SYSCTRL0_OFFSET, + .mask =3D BIT(25), + .active_low =3D false, + }, + [IMX8ULP_SIM_LPAV_HIFI4_DSP_RST] =3D { + .offset =3D IMX8ULP_SIM_LPAV_SYSCTRL0_OFFSET, + .mask =3D BIT(16), + .active_low =3D false, + }, + [IMX8ULP_SIM_LPAV_HIFI4_DSP_STALL] =3D { + .offset =3D IMX8ULP_SIM_LPAV_SYSCTRL0_OFFSET, + .mask =3D BIT(13), + .active_low =3D false, + }, + [IMX8ULP_SIM_LPAV_DSI_RST_BYTE_N] =3D { + .offset =3D IMX8ULP_SIM_LPAV_SYSCTRL0_OFFSET, + .mask =3D BIT(5), + .active_low =3D true, + }, + [IMX8ULP_SIM_LPAV_DSI_RST_ESC_N] =3D { + .offset =3D IMX8ULP_SIM_LPAV_SYSCTRL0_OFFSET, + .mask =3D BIT(4), + .active_low =3D true, + }, + [IMX8ULP_SIM_LPAV_DSI_RST_DPI_N] =3D { + .offset =3D IMX8ULP_SIM_LPAV_SYSCTRL0_OFFSET, + .mask =3D BIT(3), + .active_low =3D true, + }, +}; + +static const struct imx8mp_reset_info imx8ulp_reset_info =3D { + .map =3D imx8ulp_reset_map, + .num_lines =3D ARRAY_SIZE(imx8ulp_reset_map), +}; + struct imx8mp_audiomix_reset { struct reset_controller_dev rcdev; void __iomem *base; @@ -179,6 +220,10 @@ static const struct auxiliary_device_id imx8mp_audiomi= x_reset_ids[] =3D { .name =3D "clk_imx8mp_audiomix.reset", .driver_data =3D (kernel_ulong_t)&imx8mp_reset_info, }, + { + .name =3D "clk_imx8ulp_sim_lpav.reset", + .driver_data =3D (kernel_ulong_t)&imx8ulp_reset_info, + }, { } }; MODULE_DEVICE_TABLE(auxiliary, imx8mp_audiomix_reset_ids); --=20 2.43.0 From nobody Sun Feb 8 13:53:07 2026 Received: from mail-ej1-f43.google.com (mail-ej1-f43.google.com [209.85.218.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 26A143570BF for ; Wed, 29 Oct 2025 13:56:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.43 ARC-Seal: i=1; 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Wed, 29 Oct 2025 06:56:18 -0700 (PDT) Received: from SMW024614.wbi.nxp.com ([128.77.115.157]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b6d8534d99dsm1444960766b.21.2025.10.29.06.56.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Oct 2025 06:56:18 -0700 (PDT) From: Laurentiu Mihalcea To: Abel Vesa , Peng Fan , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Fabio Estevam , Philipp Zabel , Daniel Baluta , Shengjiu Wang Cc: linux-clk@vger.kernel.org, imx@lists.linux.dev, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Pengutronix Kernel Team Subject: [PATCH v3 8/8] arm64: dts: imx8ulp: add sim lpav node Date: Wed, 29 Oct 2025 06:52:29 -0700 Message-ID: <20251029135229.890-9-laurentiumihalcea111@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251029135229.890-1-laurentiumihalcea111@gmail.com> References: <20251029135229.890-1-laurentiumihalcea111@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Laurentiu Mihalcea Add DT node for the SIM LPAV module. Reviewed-by: Daniel Baluta Signed-off-by: Laurentiu Mihalcea Reviewed-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8ulp.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/d= ts/freescale/imx8ulp.dtsi index 13b01f3aa2a4..9b5d98766512 100644 --- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi @@ -776,6 +776,23 @@ edma2: dma-controller@2d800000 { "ch28", "ch29", "ch30", "ch31"; }; =20 + sim_lpav: clock-controller@2da50000 { + compatible =3D "fsl,imx8ulp-sim-lpav"; + reg =3D <0x2da50000 0x10000>; + clocks =3D <&cgc2 IMX8ULP_CLK_LPAV_BUS_DIV>, + <&cgc2 IMX8ULP_CLK_HIFI_DIVCORE>, + <&cgc2 IMX8ULP_CLK_HIFI_DIVPLAT>; + clock-names =3D "bus", "core", "plat"; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + + sim_lpav_mux: mux-controller { + compatible =3D "reg-mux"; + #mux-control-cells =3D <1>; + mux-reg-masks =3D <0x8 0x00000200>; + }; + }; + cgc2: clock-controller@2da60000 { compatible =3D "fsl,imx8ulp-cgc2"; reg =3D <0x2da60000 0x10000>; --=20 2.43.0