From nobody Mon Dec 15 18:59:06 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AF38735772A; Wed, 29 Oct 2025 10:24:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761733484; cv=none; b=SOZH4+jRVMgEUordc3cANgfsAE4aSmbRTTDWMeZJseIza0cPRpFVjdQZXd/kh3b5iLe2/p66/yayL5kJDl4xep+mSFptfZ74KXnOrOcneEmFc4gBzvsG67tNTLq4IzUmCh2cLBOxFDfQKOnkcfwGj9nM5EGy6MjvIMsFPuFBs90= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761733484; c=relaxed/simple; bh=Qm7l75fLYHiaD83aDzkCWhIeMDwrt1uFx2Kg948JfHk=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=NQxiXOh/hc5iew2w2GXfCO92wt3CB2refqf9KVaiJ8aJG8lZaEGtPmcbhTS6Qwur0i1rVDSUWVyx2AXcmxu9bcmOMAzkxe/4WraNEeVEbY3AjiCqk5rNcp5Ljb0kdc256gnZ2xD3ztyJkwANhXY5BqQTuUsXxhkAM/+WvCAl80E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=jz05lH4P; arc=none smtp.client-ip=192.198.163.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="jz05lH4P" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1761733483; x=1793269483; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Qm7l75fLYHiaD83aDzkCWhIeMDwrt1uFx2Kg948JfHk=; b=jz05lH4PPZXs30uXtZqd0MUBxFllN/rB6nqCsbxUzeNNfv2tp7Xv3Amf 46NR1gGdhdyeB5cXw2+8Ym9Y6XvJc3nzeps96QdzZBvSr54L86IIilKZk gKb6A4fceqA+b+Fa3SPEeAdWkAQA2FG1YebJdp/kpgUnpH6dulhyRtydy 7Fncb3R703yw+zVF882UBnso2tlynuUDD83SOIdlhvwfeynHeCyAEJons T1DW0zl0BVQ6B2I/nKMCNGiYjWVVuo4sP6el8QDe/6LCyPhxHtuRuxeO1 VRixgUKawovX8S+jmuofmlJD1XyxtwjoaII3mmpErkOv97wTtDRB3eaxd Q==; X-CSE-ConnectionGUID: zMm0bhE+RqKRFOySfs82Ng== X-CSE-MsgGUID: u4hc9l+8SqKx/kmRARcsCg== X-IronPort-AV: E=McAfee;i="6800,10657,11596"; a="63885973" X-IronPort-AV: E=Sophos;i="6.19,263,1754982000"; d="scan'208";a="63885973" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Oct 2025 03:24:42 -0700 X-CSE-ConnectionGUID: 7gHIH15USTKf4dIBI6PMUg== X-CSE-MsgGUID: Htu9QqY1SJWRTHpo5PCzow== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.19,263,1754982000"; d="scan'208";a="185963382" Received: from spr.sh.intel.com ([10.112.229.196]) by fmviesa008.fm.intel.com with ESMTP; 29 Oct 2025 03:24:38 -0700 From: Dapeng Mi To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , Adrian Hunter , Alexander Shishkin , Andi Kleen , Eranian Stephane Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Dapeng Mi , Zide Chen , Falcon Thomas , Xudong Hao , Dapeng Mi , Kan Liang Subject: [Patch v9 06/12] perf/x86/intel/ds: Factor out PEBS record processing code to functions Date: Wed, 29 Oct 2025 18:21:30 +0800 Message-Id: <20251029102136.61364-7-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251029102136.61364-1-dapeng1.mi@linux.intel.com> References: <20251029102136.61364-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Beside some PEBS record layout difference, arch-PEBS can share most of PEBS record processing code with adaptive PEBS. Thus, factor out these common processing code to independent inline functions, so they can be reused by subsequent arch-PEBS handler. Suggested-by: Kan Liang Signed-off-by: Dapeng Mi --- arch/x86/events/intel/ds.c | 83 ++++++++++++++++++++++++++------------ 1 file changed, 58 insertions(+), 25 deletions(-) diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c index 26e485eca0a0..c8aa72db86d9 100644 --- a/arch/x86/events/intel/ds.c +++ b/arch/x86/events/intel/ds.c @@ -2614,6 +2614,57 @@ static void intel_pmu_drain_pebs_nhm(struct pt_regs = *iregs, struct perf_sample_d } } =20 +static __always_inline void +__intel_pmu_handle_pebs_record(struct pt_regs *iregs, + struct pt_regs *regs, + struct perf_sample_data *data, + void *at, u64 pebs_status, + short *counts, void **last, + setup_fn setup_sample) +{ + struct cpu_hw_events *cpuc =3D this_cpu_ptr(&cpu_hw_events); + struct perf_event *event; + int bit; + + for_each_set_bit(bit, (unsigned long *)&pebs_status, X86_PMC_IDX_MAX) { + event =3D cpuc->events[bit]; + + if (WARN_ON_ONCE(!event) || + WARN_ON_ONCE(!event->attr.precise_ip)) + continue; + + if (counts[bit]++) { + __intel_pmu_pebs_event(event, iregs, regs, data, + last[bit], setup_sample); + } + + last[bit] =3D at; + } +} + +static __always_inline void +__intel_pmu_handle_last_pebs_record(struct pt_regs *iregs, + struct pt_regs *regs, + struct perf_sample_data *data, + u64 mask, short *counts, void **last, + setup_fn setup_sample) +{ + struct cpu_hw_events *cpuc =3D this_cpu_ptr(&cpu_hw_events); + struct perf_event *event; + int bit; + + for_each_set_bit(bit, (unsigned long *)&mask, X86_PMC_IDX_MAX) { + if (!counts[bit]) + continue; + + event =3D cpuc->events[bit]; + + __intel_pmu_pebs_last_event(event, iregs, regs, data, last[bit], + counts[bit], setup_sample); + } + +} + static void intel_pmu_drain_pebs_icl(struct pt_regs *iregs, struct perf_sa= mple_data *data) { short counts[INTEL_PMC_IDX_FIXED + MAX_FIXED_PEBS_EVENTS] =3D {}; @@ -2623,9 +2674,7 @@ static void intel_pmu_drain_pebs_icl(struct pt_regs *= iregs, struct perf_sample_d struct x86_perf_regs perf_regs; struct pt_regs *regs =3D &perf_regs.regs; struct pebs_basic *basic; - struct perf_event *event; void *base, *at, *top; - int bit; u64 mask; =20 if (!x86_pmu.pebs_active) @@ -2638,6 +2687,7 @@ static void intel_pmu_drain_pebs_icl(struct pt_regs *= iregs, struct perf_sample_d =20 mask =3D hybrid(cpuc->pmu, pebs_events_mask) | (hybrid(cpuc->pmu, fixed_cntr_mask64) << INTEL_PMC_IDX_FIXED); + mask &=3D cpuc->pebs_enabled; =20 if (unlikely(base >=3D top)) { intel_pmu_pebs_event_update_no_drain(cpuc, mask); @@ -2655,31 +2705,14 @@ static void intel_pmu_drain_pebs_icl(struct pt_regs= *iregs, struct perf_sample_d if (basic->format_size !=3D cpuc->pebs_record_size) continue; =20 - pebs_status =3D basic->applicable_counters & cpuc->pebs_enabled & mask; - for_each_set_bit(bit, (unsigned long *)&pebs_status, X86_PMC_IDX_MAX) { - event =3D cpuc->events[bit]; - - if (WARN_ON_ONCE(!event) || - WARN_ON_ONCE(!event->attr.precise_ip)) - continue; - - if (counts[bit]++) { - __intel_pmu_pebs_event(event, iregs, regs, data, last[bit], - setup_pebs_adaptive_sample_data); - } - last[bit] =3D at; - } + pebs_status =3D mask & basic->applicable_counters; + __intel_pmu_handle_pebs_record(iregs, regs, data, at, + pebs_status, counts, last, + setup_pebs_adaptive_sample_data); } =20 - for_each_set_bit(bit, (unsigned long *)&mask, X86_PMC_IDX_MAX) { - if (!counts[bit]) - continue; - - event =3D cpuc->events[bit]; - - __intel_pmu_pebs_last_event(event, iregs, regs, data, last[bit], - counts[bit], setup_pebs_adaptive_sample_data); - } + __intel_pmu_handle_last_pebs_record(iregs, regs, data, mask, counts, last, + setup_pebs_adaptive_sample_data); } =20 static void __init intel_arch_pebs_init(void) --=20 2.34.1