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[86.162.200.138]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4771e196a22sm35191915e9.5.2025.10.29.01.21.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Oct 2025 01:21:03 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: Greg Kroah-Hartman , Jiri Slaby , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm Cc: Biju Das , Lad Prabhakar , linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Biju Das , stable@kernel.org, Conor Dooley Subject: [PATCH v2 1/2] dt-bindings: serial: rsci: Drop "uart-has-rtscts: false" Date: Wed, 29 Oct 2025 08:20:56 +0000 Message-ID: <20251029082101.92156-2-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251029082101.92156-1-biju.das.jz@bp.renesas.com> References: <20251029082101.92156-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Drop "uart-has-rtscts: false" from binding as the IP supports hardware flow control on all SoCs. Cc: stable@kernel.org Fixes: 25422e8f46c1 ("dt-bindings: serial: Add compatible for Renesas RZ/T2= H SoC in sci") Acked-by: Conor Dooley Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven --- v1->v2: * Updated commit message to make it clear that hardware flow control supported on all SoC * Added Ack from Conor * Added fixes tag --- Documentation/devicetree/bindings/serial/renesas,rsci.yaml | 2 -- 1 file changed, 2 deletions(-) diff --git a/Documentation/devicetree/bindings/serial/renesas,rsci.yaml b/D= ocumentation/devicetree/bindings/serial/renesas,rsci.yaml index f50d8e02f476..6b1f827a335b 100644 --- a/Documentation/devicetree/bindings/serial/renesas,rsci.yaml +++ b/Documentation/devicetree/bindings/serial/renesas,rsci.yaml @@ -54,8 +54,6 @@ properties: power-domains: maxItems: 1 =20 - uart-has-rtscts: false - required: - compatible - reg --=20 2.43.0 From nobody Mon Dec 15 18:56:42 2025 Received: from mail-wr1-f43.google.com (mail-wr1-f43.google.com [209.85.221.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8E0A4313263 for ; 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[86.162.200.138]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4771e196a22sm35191915e9.5.2025.10.29.01.21.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Oct 2025 01:21:04 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: Greg Kroah-Hartman , Jiri Slaby Cc: Biju Das , Geert Uytterhoeven , Wolfram Sang , Lad Prabhakar , Claudiu Beznea , Nam Cao , linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, Biju Das , linux-renesas-soc@vger.kernel.org, stable@kernel.org Subject: [PATCH v2 2/2] serial: sh-sci: Fix deadlock during RSCI FIFO overrun error Date: Wed, 29 Oct 2025 08:20:57 +0000 Message-ID: <20251029082101.92156-3-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251029082101.92156-1-biju.das.jz@bp.renesas.com> References: <20251029082101.92156-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das On RSCI IP, a deadlock occurs during a FIFO overrun error, as it uses a different register to clear the FIFO overrun error status. Cc: stable@kernel.org Fixes: 0666e3fe95ab ("serial: sh-sci: Add support for RZ/T2H SCI") Signed-off-by: Biju Das --- v1->v2: * Split the fixes patches from original series. --- drivers/tty/serial/rsci.c | 1 + drivers/tty/serial/sh-sci-common.h | 1 + drivers/tty/serial/sh-sci.c | 8 ++++++-- 3 files changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/tty/serial/rsci.c b/drivers/tty/serial/rsci.c index b3c48dc1e07d..3e1f4b3c4e59 100644 --- a/drivers/tty/serial/rsci.c +++ b/drivers/tty/serial/rsci.c @@ -414,6 +414,7 @@ static const struct sci_port_params_bits rsci_port_para= m_bits =3D { .rxtx_enable =3D CCR0_RE | CCR0_TE, .te_clear =3D CCR0_TE | CCR0_TEIE, .poll_sent_bits =3D CSR_TDRE | CSR_TEND, + .overrun_clr =3D CFCLR_ORERC, }; =20 static const struct sci_port_params rsci_port_params =3D { diff --git a/drivers/tty/serial/sh-sci-common.h b/drivers/tty/serial/sh-sci= -common.h index e3c028df14f1..bcdb41ddc15d 100644 --- a/drivers/tty/serial/sh-sci-common.h +++ b/drivers/tty/serial/sh-sci-common.h @@ -51,6 +51,7 @@ struct sci_port_params_bits { unsigned int rxtx_enable; unsigned int te_clear; unsigned int poll_sent_bits; + unsigned int overrun_clr; }; =20 struct sci_common_regs { diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c index 62bb62b82cbe..b33894d0273b 100644 --- a/drivers/tty/serial/sh-sci.c +++ b/drivers/tty/serial/sh-sci.c @@ -1024,8 +1024,12 @@ static int sci_handle_fifo_overrun(struct uart_port = *port) =20 status =3D s->ops->read_reg(port, s->params->overrun_reg); if (status & s->params->overrun_mask) { - status &=3D ~s->params->overrun_mask; - s->ops->write_reg(port, s->params->overrun_reg, status); + if (s->type =3D=3D SCI_PORT_RSCI) { + s->ops->clear_SCxSR(port, s->params->param_bits->overrun_clr); + } else { + status &=3D ~s->params->overrun_mask; + s->ops->write_reg(port, s->params->overrun_reg, status); + } =20 port->icount.overrun++; =20 --=20 2.43.0