From nobody Tue Feb 10 03:57:37 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7CD5F3043DC; Wed, 29 Oct 2025 06:21:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.13 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761718917; cv=none; b=m/r6PrPPt6ZoGCuGOIUQgnuI87D/znwIV81ORx7lTQjCoOJU7I2CyiL11ixsvlnIHJ0dDiA0dt2LuWv9FatLJZrsEa5xBh0qBxrzuAmHhnEORbmhRzQI56g9IOC875TDdvB2Zcw7XjibSCA3hVZqpw/1woUDCT5xmPXPSl/IXtk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761718917; c=relaxed/simple; bh=HDcnGGbcbmRoo8z5vK+lo3rzFRrgRcR30x3ZIFXlv60=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=q3QeWC8mZhcbWMQ59+IiUvwTwEFNVRXkwQterXwnrApYbMZE2bWdcTlc/SqXlSjBHPcNVdVqFLXhnefW0792e2zx/A4JxJWtGqQH4tiNQPMVXHXrR0brTR3zmPTRQmd1pI3He+5ShjEi4BvtMmPxw6GyuiaKievB4eI8umfEUkw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=HGL8CN9X; arc=none smtp.client-ip=192.198.163.13 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="HGL8CN9X" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1761718915; x=1793254915; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=HDcnGGbcbmRoo8z5vK+lo3rzFRrgRcR30x3ZIFXlv60=; b=HGL8CN9XQyOK6PYO75QC9imFBOXmyZl9UQQlTIlYoG/aAMMqKWiQuG+p mV4HOEw9eC7uMzwuRsCIXND9Cvgf/+YQxKTw5t281oRpu33VLsTiOzZoN q/S1H+XcwvQZtI8NuihBsZhhXfXagR6UYqWaqO6I3lLBZhohSHkIwG0ke bTT0QrB8gNTd5c7aDpdEq9Dej64yTIchqceXKjFjpa8BfytVEeMuGAtF/ WvMoEUhUiI5Ny8J37tgmp9fUZzxpEXoLjri9n89siwfkMHeND6WY9AnxS cvz2QuXqI0fmg+16IyCmrEC0wP14+vhJpH54SArvAbXryautX5L9uGyq0 g==; X-CSE-ConnectionGUID: HBMxvmJYTraLeQ+lUZqWoQ== X-CSE-MsgGUID: HrXVrQkASYuEi2n+GgY0cg== X-IronPort-AV: E=McAfee;i="6800,10657,11586"; a="66446274" X-IronPort-AV: E=Sophos;i="6.19,263,1754982000"; d="scan'208";a="66446274" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by fmvoesa107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Oct 2025 23:21:55 -0700 X-CSE-ConnectionGUID: IONHn38ORpWqOpoI6KeePA== X-CSE-MsgGUID: 4MfqJQuGQxK0dtzVJ9tHNA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.19,263,1754982000"; d="scan'208";a="185201102" Received: from jraag-z790m-itx-wifi.iind.intel.com ([10.190.239.23]) by orviesa009.jf.intel.com with ESMTP; 28 Oct 2025 23:21:52 -0700 From: Raag Jadav To: hansg@kernel.org, ilpo.jarvinen@linux.intel.com, andriy.shevchenko@linux.intel.com, linus.walleij@linaro.org, brgl@bgdev.pl Cc: platform-driver-x86@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Raag Jadav Subject: [PATCH v1 1/2] platform/x86/intel: Introduce Intel Elkhart Lake PSE I/O Date: Wed, 29 Oct 2025 11:50:49 +0530 Message-Id: <20251029062050.4160517-2-raag.jadav@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251029062050.4160517-1-raag.jadav@intel.com> References: <20251029062050.4160517-1-raag.jadav@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Intel Elkhart Lake Programmable Service Engine (PSE) includes two PCI devices that expose two different capabilities of GPIO and Timed I/O as a single PCI function through shared MMIO with below layout. GPIO: 0x0000 - 0x1000 TIO: 0x1000 - 0x2000 This driver enumerates the PCI parent device and creates auxiliary child devices for these capabilities. The actual functionalities are provided by their respective auxiliary drivers. Signed-off-by: Raag Jadav --- MAINTAINERS | 7 ++ drivers/platform/x86/intel/Kconfig | 13 +++ drivers/platform/x86/intel/Makefile | 1 + drivers/platform/x86/intel/ehl_pse_io.c | 128 ++++++++++++++++++++++++ include/linux/ehl_pse_io_aux.h | 30 ++++++ 5 files changed, 179 insertions(+) create mode 100644 drivers/platform/x86/intel/ehl_pse_io.c create mode 100644 include/linux/ehl_pse_io_aux.h diff --git a/MAINTAINERS b/MAINTAINERS index 46126ce2f968..bd2a009d73c6 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -12499,6 +12499,13 @@ F: drivers/gpu/drm/xe/ F: include/drm/intel/ F: include/uapi/drm/xe_drm.h =20 +INTEL ELKHART LAKE PSE I/O DRIVER +M: Raag Jadav +L: platform-driver-x86@vger.kernel.org +S: Supported +F: drivers/platform/x86/intel/ehl_pse_io.c +F: include/linux/ehl_pse_io_aux.h + INTEL ETHERNET DRIVERS M: Tony Nguyen M: Przemek Kitszel diff --git a/drivers/platform/x86/intel/Kconfig b/drivers/platform/x86/inte= l/Kconfig index 19a2246f2770..2900407d6095 100644 --- a/drivers/platform/x86/intel/Kconfig +++ b/drivers/platform/x86/intel/Kconfig @@ -41,6 +41,19 @@ config INTEL_VBTN To compile this driver as a module, choose M here: the module will be called intel_vbtn. =20 +config INTEL_EHL_PSE_IO + tristate "Intel Elkhart Lake PSE I/O driver" + depends on PCI + select AUXILIARY_BUS + help + Select this option to enable Intel Elkhart Lake PSE GPIO and Timed + I/O support. This driver enumerates the PCI parent device and + creates auxiliary child devices for these capabilities. The actual + functionalities are provided by their respective auxiliary drivers. + + To compile this driver as a module, choose M here: the module will + be called intel_ehl_pse_io. + config INTEL_INT0002_VGPIO tristate "Intel ACPI INT0002 Virtual GPIO driver" depends on GPIOLIB && ACPI && PM_SLEEP diff --git a/drivers/platform/x86/intel/Makefile b/drivers/platform/x86/int= el/Makefile index 78acb414e154..138b13756158 100644 --- a/drivers/platform/x86/intel/Makefile +++ b/drivers/platform/x86/intel/Makefile @@ -21,6 +21,7 @@ intel-target-$(CONFIG_INTEL_HID_EVENT) +=3D hid.o intel-target-$(CONFIG_INTEL_VBTN) +=3D vbtn.o =20 # Intel miscellaneous drivers +intel-target-$(CONFIG_INTEL_EHL_PSE_IO) +=3D ehl_pse_io.o intel-target-$(CONFIG_INTEL_INT0002_VGPIO) +=3D int0002_vgpio.o intel-target-$(CONFIG_INTEL_ISHTP_ECLITE) +=3D ishtp_eclite.o intel-target-$(CONFIG_INTEL_OAKTRAIL) +=3D oaktrail.o diff --git a/drivers/platform/x86/intel/ehl_pse_io.c b/drivers/platform/x86= /intel/ehl_pse_io.c new file mode 100644 index 000000000000..f1cad102f856 --- /dev/null +++ b/drivers/platform/x86/intel/ehl_pse_io.c @@ -0,0 +1,128 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Intel Elkhart Lake Programmable Service Engine (PSE) I/O + * + * Copyright (c) 2025 Intel Corporation. + * + * Author: Raag Jadav + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define EHL_PSE_IO_DEV_OFFSET SZ_4K +#define EHL_PSE_IO_DEV_SIZE SZ_4K + +static void ehl_pse_io_dev_release(struct device *dev) +{ + struct auxiliary_device *aux_dev =3D to_auxiliary_dev(dev); + struct ehl_pse_io_dev *io_dev =3D auxiliary_dev_to_ehl_pse_io_dev(aux_dev= ); + + kfree(io_dev); +} + +static int ehl_pse_io_dev_add(struct pci_dev *pci, const char *name, int i= dx) +{ + struct auxiliary_device *aux_dev; + struct device *dev =3D &pci->dev; + struct ehl_pse_io_dev *io_dev; + resource_size_t start; + int ret; + + io_dev =3D kzalloc(sizeof(*io_dev), GFP_KERNEL); + if (!io_dev) + return -ENOMEM; + + start =3D pci_resource_start(pci, 0); + io_dev->irq =3D pci_irq_vector(pci, idx); + io_dev->mem =3D DEFINE_RES_MEM(start + (EHL_PSE_IO_DEV_OFFSET * idx), EHL= _PSE_IO_DEV_SIZE); + + aux_dev =3D &io_dev->aux_dev; + aux_dev->name =3D name; + aux_dev->id =3D (pci_domain_nr(pci->bus) << 16) | pci_dev_id(pci); + aux_dev->dev.parent =3D dev; + aux_dev->dev.release =3D ehl_pse_io_dev_release; + + ret =3D auxiliary_device_init(aux_dev); + if (ret) + goto free_io_dev; + + ret =3D __auxiliary_device_add(aux_dev, dev->driver->name); + if (ret) + goto uninit_aux_dev; + + return 0; + +uninit_aux_dev: + /* io_dev will be freed with the put_device() and .release sequence */ + auxiliary_device_uninit(aux_dev); +free_io_dev: + kfree(io_dev); + return ret; +} + +static int ehl_pse_io_probe(struct pci_dev *pci, const struct pci_device_i= d *id) +{ + int ret; + + ret =3D pcim_enable_device(pci); + if (ret) + return ret; + + pci_set_master(pci); + + ret =3D pci_alloc_irq_vectors(pci, 2, 2, PCI_IRQ_MSI); + if (ret < 0) + return ret; + + ret =3D ehl_pse_io_dev_add(pci, EHL_PSE_GPIO_NAME, 0); + if (ret) + return ret; + + return ehl_pse_io_dev_add(pci, EHL_PSE_TIO_NAME, 1); +} + +static int ehl_pse_io_dev_destroy(struct device *dev, void *data) +{ + auxiliary_device_destroy(to_auxiliary_dev(dev)); + + return 0; +} + +static void ehl_pse_io_remove(struct pci_dev *pci) +{ + struct device *dev =3D &pci->dev; + + device_for_each_child_reverse(dev, NULL, ehl_pse_io_dev_destroy); +} + +static const struct pci_device_id ehl_pse_io_ids[] =3D { + { PCI_VDEVICE(INTEL, 0x4b88) }, + { PCI_VDEVICE(INTEL, 0x4b89) }, + { } +}; +MODULE_DEVICE_TABLE(pci, ehl_pse_io_ids); + +static struct pci_driver ehl_pse_io_driver =3D { + .name =3D EHL_PSE_IO_NAME, + .id_table =3D ehl_pse_io_ids, + .probe =3D ehl_pse_io_probe, + .remove =3D ehl_pse_io_remove, +}; +module_pci_driver(ehl_pse_io_driver); + +MODULE_AUTHOR("Raag Jadav "); +MODULE_DESCRIPTION("Intel Elkhart Lake PSE I/O driver"); +MODULE_LICENSE("GPL"); diff --git a/include/linux/ehl_pse_io_aux.h b/include/linux/ehl_pse_io_aux.h new file mode 100644 index 000000000000..33eb5a86ce36 --- /dev/null +++ b/include/linux/ehl_pse_io_aux.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Intel Elkhart Lake PSE I/O Auxiliary Device + * + * Copyright (c) 2025 Intel Corporation. + * + * Author: Raag Jadav + */ + +#ifndef _EHL_PSE_IO_AUX_H_ +#define _EHL_PSE_IO_AUX_H_ + +#include +#include +#include + +#define EHL_PSE_IO_NAME "ehl-pse-io" +#define EHL_PSE_GPIO_NAME "gpio-elkhartlake" +#define EHL_PSE_TIO_NAME "pps-tio" + +struct ehl_pse_io_dev { + struct auxiliary_device aux_dev; + struct resource mem; + int irq; +}; + +#define auxiliary_dev_to_ehl_pse_io_dev(auxiliary_dev) \ + container_of(auxiliary_dev, struct ehl_pse_io_dev, aux_dev) + +#endif /* _EHL_PSE_IO_AUX_H_ */ --=20 2.34.1