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Wed, 29 Oct 2025 08:44:25 -0700 From: Edward Srouji To: Leon Romanovsky , Saeed Mahameed , Tariq Toukan , Mark Bloch , Andrew Lunn , "David S . Miller" , "Eric Dumazet" , Jakub Kicinski , Paolo Abeni , Jason Gunthorpe CC: , , , Patrisious Haddad , "Leon Romanovsky" , Edward Srouji Subject: [PATCH rdma-next 4/7] RDMA/mlx5: Change default device for LAG slaves in RDMA TRANSPORT namespaces Date: Wed, 29 Oct 2025 17:42:56 +0200 Message-ID: <20251029-support-other-eswitch-v1-4-98bb707b5d57@nvidia.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20251029-support-other-eswitch-v1-0-98bb707b5d57@nvidia.com> References: <20251029-support-other-eswitch-v1-0-98bb707b5d57@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF0000467F:EE_|BL1PR12MB5802:EE_ X-MS-Office365-Filtering-Correlation-Id: 3d8efe46-a8e1-4321-2feb-08de1702183f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|82310400026|7416014|376014|921020; X-Microsoft-Antispam-Message-Info: =?utf-8?B?T1RXRnNUSHJDMnd6ZG1tNWdhb1pXSkZSUWZZN1FTbFJqN1B0bFdsL0FIUHBG?= =?utf-8?B?eEhQNTh1aml2b0RJK2xzaDZocEhWS3lZU3U2QnVjSXJOOGs5K2FGaHlWeE9R?= =?utf-8?B?dTJRYm1HZHlvcy8vQkt2cU5LWmRQK0IrWmZxZ21lU0tTYnZUZDZTK2xuUjJt?= =?utf-8?B?MEhBK1VySm9WQ2R6TEQ2OVFyMkhPb2EvWldFU3hwRXd5R0NtM3VZZGwvTGFy?= =?utf-8?B?TTVlTkJKdnZ6ZTRjRmJyaGV3SGQ4Qzl6UFJCNkM0K3NOTVBBQ09LUHh3T0Yr?= =?utf-8?B?MnA5dnhPUzR0T0Z1OXpSQnlXUUM2SnBlcXhpRGtDa1ZEaThUYUlDR1ZTcHE4?= =?utf-8?B?TlYrNUFDcVI0ZVJETFVOaUZJSHFYK2xra0wwY3ZvRHVCZUxIdTY2bnpCWmEv?= =?utf-8?B?d0F6TWl5MzlJVkdSb1I0ODZwVTRsN3FEZS9vRDk2aGc3cTdhUnZ3dHRTbHNh?= =?utf-8?B?aEpsTFRzNWNSckYyc3hGS1hNVzd3cWtzcFRHYldYV0FMckp0ZGtFSzdWWngw?= =?utf-8?B?b2g2d2g5K1JHazE4Q2VpdDVPQmpVSjhPWnQwS2dJOHdmRFVvL0tYU2xCbHdh?= =?utf-8?B?WWY2OGJhVFcxMGFVbGczMFpScTVuWXlkRWNnSEN0UVpjY1RmTGt5SUJIUzRN?= =?utf-8?B?bWVaYzJwVUFxUk0zbVE1Q29RTlFoRFlJb3AxWmIrSGY0TDg2bWw4aEdCajNq?= =?utf-8?B?OWZYYVo0WlJDL3FQRmhRZHV0WHBuei9Zb3h5RWh0SmF2bzJWSXZXSy9HQnZa?= =?utf-8?B?ZzBqTnZ5SENSTGpWekduT0EwaGU4TVN0WVVwNCtqd3lPbUtncnVUTkFFVG4z?= =?utf-8?B?UmdMRVdSUlZYdEdjbHl0bTNTTThrV0dubFIra3FuWitTUWw3R2Y3MzlWbXBa?= =?utf-8?B?RWgrRmZ6VHZ0UXgvQ2V4eWl2MUhqTkZUM1JHWFluNlVsdGR2QzZIU01sc2xa?= =?utf-8?B?V0d2K2d4VFkreEp6Ym1rWG9XUHR0UGlhd25OWkpuVWVoa3lQZEVJVU01ZEVy?= =?utf-8?B?TmFYa3ZDQzFuQ2tCL2EwK3BRblhtSzRxUW9OSHFDbnJYSnRlbEJrVWhVanAv?= =?utf-8?B?aFYrYVhUc1BUVm1LRmdlTkx1RzlXL0NzbThKcEZPWlcxZ2kvNjl3L1FGZXox?= =?utf-8?B?UjcxdUZRY3BPRXR1cDFLVDIyUlVMSkdPODZrb0RMdTFKdDFWYmRVTGo2Umpy?= =?utf-8?B?bWMxc2ZTem5KVG9YYk53bDNiYVlZeWZob3JlUjVjRHVSRHlLVEVIL2RjMUc5?= =?utf-8?B?Q3p6b1c5QldzQTdsUEhXSmVLKzcrUUpjdXhsR2NnNkd6VFZNSFlYeFRnWDBU?= =?utf-8?B?MnVXbjhpZ1JoY2RUdmZPYWRlQ0pLbFp1SUNqWXFKKzJPRmZKT2tTZkZmbS8z?= =?utf-8?B?MTlyd21aZEpqWXZJZkRyc203ZDNzd2hNdUZrb2ExVHNURzFlOFFKUjlmSDg4?= =?utf-8?B?V0EydmlGQi9JUnVybmtlVzkzM3JxbUxYMVNDZGJ1bk8xMWZ6RGttQXFESmZO?= =?utf-8?B?SGM2NllEOTl6QjBkWFNnRDVUWFRMakw2ekdLL0lWY05rQU8vazdPeTcvV2xR?= =?utf-8?B?cExBL2NwbmpNMTVrcWtSWTRkNCtGZnRsZlNqM21GNzVpbFNLKy9YZm5YVUFD?= =?utf-8?B?MVRpMzRja3Q1bUhMdFZHWjUvVnp6cFNxcE55YktQLy9KWUc2cTZkUFhCOWJ2?= =?utf-8?B?NnJUVHNLNnBLclgrM2pUT2FYUFQ1L3VaM2NnYlhaMXN6N3EwckpaSEVWLzB2?= =?utf-8?B?UDVwTldvbXBacDJab0ozOGg0c1hiUWliODdhMHpOTFRCRlZSUlV6ak5WSkpU?= =?utf-8?B?VWl5SFE3cTZXclBSdFI3SzNIVVRwaEpQaFJoTUo0ZmVEd21DRzVaRkxFUnM0?= =?utf-8?B?S0dwOUFKZlVKM2dtNFR5TWQ5ZDBVQzhvRjZ1TGw4VlZuMzQ3WEZQbnYwVEpi?= =?utf-8?B?NmZCbGlaamlHektQUFFxaFN5ekhWQStKczQvWXY3OGZlWUNMaXVUMHpKY3Nm?= =?utf-8?B?UFVYVHRYMXdiekdjM1M5blhsZXd2cUhuVmltQTk5SGdMN1l5NERMbWR0UEpx?= =?utf-8?B?bjdxWjZhcDBuc0xudzEyVVRrSENZcDFGRUo2ejhzZTBiTzZObEI4bXBJMkJy?= =?utf-8?Q?c0h4WqX9Xyhu/LQDGUbMhj9ux?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(1800799024)(82310400026)(7416014)(376014)(921020);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Oct 2025 15:44:49.5587 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3d8efe46-a8e1-4321-2feb-08de1702183f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF0000467F.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5802 From: Patrisious Haddad In case of a LAG configuration change the root namespace core device for all of the LAG slaves to be the core device of the master device for RDMA_TRANSPORT namespaces, in order to ensure all tables are created through the master device. Once the LAG is disabled revert back to the native core device. Signed-off-by: Patrisious Haddad Signed-off-by: Leon Romanovsky Signed-off-by: Edward Srouji --- drivers/infiniband/hw/mlx5/ib_rep.c | 74 +++++++++++++++++++++++++++++++++= +++- 1 file changed, 72 insertions(+), 2 deletions(-) diff --git a/drivers/infiniband/hw/mlx5/ib_rep.c b/drivers/infiniband/hw/ml= x5/ib_rep.c index cc8859d3c2f5..bbecca405171 100644 --- a/drivers/infiniband/hw/mlx5/ib_rep.c +++ b/drivers/infiniband/hw/mlx5/ib_rep.c @@ -44,6 +44,63 @@ static void mlx5_ib_num_ports_update(struct mlx5_core_de= v *dev, u32 *num_ports) } } =20 +static int mlx5_ib_set_owner_transport(struct mlx5_core_dev *cur_owner, + struct mlx5_core_dev *new_owner) +{ + int ret; + + if (!MLX5_CAP_FLOWTABLE_RDMA_TRANSPORT_TX(cur_owner, ft_support) || + !MLX5_CAP_FLOWTABLE_RDMA_TRANSPORT_RX(cur_owner, ft_support)) + return 0; + + if (!MLX5_CAP_ADV_RDMA(new_owner, rdma_transport_manager) || + !MLX5_CAP_ADV_RDMA(new_owner, rdma_transport_manager_other_eswitch)) + return 0; + + ret =3D mlx5_fs_set_root_dev(cur_owner, new_owner, + FS_FT_RDMA_TRANSPORT_TX); + if (ret) + return ret; + + ret =3D mlx5_fs_set_root_dev(cur_owner, new_owner, + FS_FT_RDMA_TRANSPORT_RX); + if (ret) { + mlx5_fs_set_root_dev(cur_owner, cur_owner, + FS_FT_RDMA_TRANSPORT_TX); + return ret; + } + + return 0; +} + +static void mlx5_ib_release_transport(struct mlx5_core_dev *dev) +{ + struct mlx5_core_dev *peer_dev; + int i, ret; + + mlx5_lag_for_each_peer_mdev(dev, peer_dev, i) { + ret =3D mlx5_ib_set_owner_transport(peer_dev, peer_dev); + WARN_ON_ONCE(ret); + } +} + +static int mlx5_ib_take_transport(struct mlx5_core_dev *dev) +{ + struct mlx5_core_dev *peer_dev; + int ret; + int i; + + mlx5_lag_for_each_peer_mdev(dev, peer_dev, i) { + ret =3D mlx5_ib_set_owner_transport(peer_dev, dev); + if (ret) { + mlx5_ib_release_transport(dev); + return ret; + } + } + + return 0; +} + static int mlx5_ib_vport_rep_load(struct mlx5_core_dev *dev, struct mlx5_eswitch_rep = *rep) { @@ -88,10 +145,18 @@ mlx5_ib_vport_rep_load(struct mlx5_core_dev *dev, stru= ct mlx5_eswitch_rep *rep) else return mlx5_ib_set_vport_rep(lag_master, rep, vport_index); =20 + if (mlx5_lag_is_shared_fdb(dev)) { + ret =3D mlx5_ib_take_transport(lag_master); + if (ret) + return ret; + } + ibdev =3D ib_alloc_device_with_net(mlx5_ib_dev, ib_dev, mlx5_core_net(lag_master)); - if (!ibdev) - return -ENOMEM; + if (!ibdev) { + ret =3D -ENOMEM; + goto release_transport; + } =20 ibdev->port =3D kcalloc(num_ports, sizeof(*ibdev->port), GFP_KERNEL); @@ -127,6 +192,10 @@ mlx5_ib_vport_rep_load(struct mlx5_core_dev *dev, stru= ct mlx5_eswitch_rep *rep) kfree(ibdev->port); fail_port: ib_dealloc_device(&ibdev->ib_dev); +release_transport: + if (mlx5_lag_is_shared_fdb(lag_master)) + mlx5_ib_release_transport(lag_master); + return ret; } =20 @@ -182,6 +251,7 @@ mlx5_ib_vport_rep_unload(struct mlx5_eswitch_rep *rep) esw =3D peer_mdev->priv.eswitch; mlx5_eswitch_unregister_vport_reps(esw, REP_IB); } + mlx5_ib_release_transport(mdev); } __mlx5_ib_remove(dev, dev->profile, MLX5_IB_STAGE_MAX); } --=20 2.47.1