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Wed, 29 Oct 2025 08:44:18 -0700 From: Edward Srouji To: Leon Romanovsky , Saeed Mahameed , Tariq Toukan , Mark Bloch , Andrew Lunn , "David S . Miller" , "Eric Dumazet" , Jakub Kicinski , Paolo Abeni , Jason Gunthorpe CC: , , , Patrisious Haddad , "Leon Romanovsky" , Edward Srouji Subject: [PATCH mlx5-next 3/7] net/mlx5: fs, set non default device per namespace Date: Wed, 29 Oct 2025 17:42:55 +0200 Message-ID: <20251029-support-other-eswitch-v1-3-98bb707b5d57@nvidia.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20251029-support-other-eswitch-v1-0-98bb707b5d57@nvidia.com> References: <20251029-support-other-eswitch-v1-0-98bb707b5d57@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF00004FC0:EE_|CH1PR12MB9645:EE_ X-MS-Office365-Filtering-Correlation-Id: 6aa0547d-317f-4386-05c3-08de170215d5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|36860700013|376014|7416014|921020; X-Microsoft-Antispam-Message-Info: =?utf-8?B?QXpkbUlJS1JhcWdlNWU1M0RYb0I5VXZkSzlhQjRDUTFkZDFUZUR0SFpBNVVT?= =?utf-8?B?WDU1VmpXNUVDV0pySW5CWkd4Tklpc2daYU9ZWTFTb20xVG5GZHpaRitCRmlZ?= =?utf-8?B?OCtUY0d3blgzL3hZaXVYR0NLV2ExM2gveFFseHlYTm1LbVpBMXZ1REhGaE9Z?= =?utf-8?B?OXVDaG5yamVyMzFSbXgvU2M1dWZsaktnMzlNSlp4NXhGN3NrUEMxVnJIQ2N6?= =?utf-8?B?RmhYeDZTSC8yYXJtSkk3Q3lXWlRkT0xBUGg3Z0twV0ZOdDg2NlJGWVVXZ3ht?= =?utf-8?B?WVdvS3hsOG9xb0pQc3prWnAvTUdTU3hCaW8rSGxmbkZoSkFQVUpSZ2ltSGZ1?= =?utf-8?B?N2JMZkNnVWd2R0tVdEdDbjg5czJEdVVxMkMrdUVzTjlxS0h6MWNQc0VIZEd3?= =?utf-8?B?RERVejRBQWVGdHNEeElsUGUvaGE3dEorOU5DUjQxY0pFOFB3Z2lnNDFtOVp6?= =?utf-8?B?UEVYb2tjbi9DR0x6c2Z3dWpHU01xMk5FbXJSd1E5bWNFbkFPQ0loZ2ZFSFdh?= =?utf-8?B?N1RnMTNZc2pTL3Vta2VQbGh2RWtxQUhxSXZkV2JHZmV5anhyekJiVXVWd1U2?= =?utf-8?B?TlY1ZzAvN1VRdzQweEVKa0VUL1hwNjZ0MEdHYnljSmIyRmpSTnpBT1IwclBQ?= =?utf-8?B?VkhVUXRaelcvdmZiWUY0eSszTHlpRm5Vcm5xZG9ZblR5SFFDYlJiOEhHZmJa?= =?utf-8?B?emRxOWxGOXk2eFNXQ01VY1ZyNElQTUF1WmMrQXV4azlRK3AwVkVWdVBxQUJq?= =?utf-8?B?YWVLZUsxaC9BNUlOVzVRVFlPSWxkNitIUDUrYVJqZXE5TUZTNXFVMlFLVUtp?= =?utf-8?B?MDZOTjdqVHA1NHJGMW1YYlpSN3hPcnAxZkQyUHJOSXBndy9TL0JGcGgycmxG?= =?utf-8?B?YWVoS1RxUHBWWWo2RkFXTWFnM2xtVVVYcjMzL1BzQ0QyeXdZVVkvelpQdlE1?= =?utf-8?B?SVpkNURmQTlRNGNnWTlyQWdMRE5LZG9Od2xaaEdVOTEwM3U4dWwwdkJaWlVN?= =?utf-8?B?NnRBeTBLTnNIZlkzMUhDSFR1SG91SE1kU1dOY3dPbGxsdFpEQ292U1hvTkt2?= =?utf-8?B?VWZ5UlJ6T0h5UTQ1L2Q2UHQzd2FGRElQL0ZheUhJeExpMytqcTVHTmMxNGM4?= =?utf-8?B?Q2VxaGc5TmFnLzVpZ0FWUUNpaTNPNUpuTkY2RHlldlcxeFducFN1WTJBZXBP?= =?utf-8?B?SXppZTg4Q1hoaENlQU96VDVNK2xVdUJ1OVQ0UlZLVFkxeWJQTjIwSVJaOTlo?= =?utf-8?B?RTI3U1ZsdDZXc3VKZXJqRVRTZFByVnZURlpWWkF6ZkdMemN4eXUxVW83MGox?= =?utf-8?B?VU1FQ251RnhFVG84eERxOStNU2pGK3lvWC85WFJYb0I2eGxITnVRT3BPNWty?= =?utf-8?B?djFzRTllajZvaE5sYUF6WFliOUhUM2tpR2hOVlFhQlN0cU12djl0OXcyMkFX?= =?utf-8?B?UXdYUzIyUmFwOEhmaHdjaU1BL0tTS3Z3L0hZUThKWlY2KytrNkdpVXZXUy8z?= =?utf-8?B?RzQ2S3ZRRFBrYlpPeW9pWjlUMlVCdWgrb3oyZlZPUWFaWVNjbkM0TzZUNEpq?= =?utf-8?B?S3MvSjlWMUhXQlRzS284dENCdk5oTWljcUVqdklDTEtvNTZSOXl2QUlkczJD?= =?utf-8?B?VXpGbWVTZit1QTdtd0VBRCtOdlZmNzZIRjBqTWhMcEZ0WHUrbG5pTE1zZ2h5?= =?utf-8?B?UHVuUm90cWxFMzRJT1dFckVnSHdTRW9ZeldGc0xIanVabDhKdFFMUkQramtI?= =?utf-8?B?eksrWGxLOHlQbTc2WUh6S0tUQlZ1ZmxiSEdMNjdRaG9SV0pLc1JkNmFVWUI1?= =?utf-8?B?WlpKS0ZUL0VGSHFaZmJCRjZVaWlxcDRpaWxuaGQ3M3NWeHNBZnF2MUxXeTZE?= =?utf-8?B?NTN1S1MwSXN3QTlWcUpKSlUwSUJLbGhXYXR2dkVIMURTRFVqeEVwTXRPMWVi?= =?utf-8?B?VzNoY2ExMTVGK3VIelJ6a1MyK2dPOVl0RXIvb25qcWh2QlBwcG82R2lGdjBy?= =?utf-8?B?NnI5dXNMUHVUNWpyMXpSLzhPR2dVVjVsZmJPMEdmTUg3WkVOenJsN0FMRktS?= =?utf-8?B?ZVBDRmw3cjIwNTdOdHJTalZOeHVuRmdOcWk2UEZkZi9xUWcyd2xzazJGdE1v?= =?utf-8?Q?RfDX08YPugGxYm8rdCDVqfdDG?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(36860700013)(376014)(7416014)(921020);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Oct 2025 15:44:45.4960 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6aa0547d-317f-4386-05c3-08de170215d5 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF00004FC0.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH1PR12MB9645 From: Patrisious Haddad Add mlx5_fs_set_root_dev() function which swaps the root namespace core device with another one for a given table_type. It is intended for usage only by RDMA_TRANSPORT tables in case of LAG configuration, to allow the creation of tables during LAG always through the LAG master device, which is valid since during LAG the master is allowed to manage the RDMA_TRANSPORT tables of its slaves. In addition move the table_type enum to global include to allow its use in a downstream patch in the RDMA driver. Signed-off-by: Patrisious Haddad Signed-off-by: Leon Romanovsky Signed-off-by: Edward Srouji --- drivers/net/ethernet/mellanox/mlx5/core/fs_core.c | 56 +++++++++++++++++++= ++++ drivers/net/ethernet/mellanox/mlx5/core/fs_core.h | 18 -------- include/linux/mlx5/fs.h | 22 +++++++++ 3 files changed, 78 insertions(+), 18 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/fs_core.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/fs_core.c index 87e381c82ed3..5b210c54a592 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/fs_core.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/fs_core.c @@ -3308,6 +3308,62 @@ init_rdma_transport_tx_root_ns_one(struct mlx5_flow_= steering *steering, return ret; } =20 +static bool mlx5_fs_ns_is_empty(struct mlx5_flow_namespace *ns) +{ + struct fs_prio *iter_prio; + + fs_for_each_prio(iter_prio, ns) { + if (iter_prio->num_ft) + return false; + } + + return true; +} + +int mlx5_fs_set_root_dev(struct mlx5_core_dev *dev, + struct mlx5_core_dev *new_dev, + enum fs_flow_table_type table_type) +{ + struct mlx5_flow_root_namespace **root; + int total_vports; + int i; + + switch (table_type) { + case FS_FT_RDMA_TRANSPORT_TX: + root =3D dev->priv.steering->rdma_transport_tx_root_ns; + total_vports =3D dev->priv.steering->rdma_transport_tx_vports; + break; + case FS_FT_RDMA_TRANSPORT_RX: + root =3D dev->priv.steering->rdma_transport_rx_root_ns; + total_vports =3D dev->priv.steering->rdma_transport_rx_vports; + break; + default: + WARN_ON_ONCE(true); + return -EINVAL; + } + + for (i =3D 0; i < total_vports; i++) { + mutex_lock(&root[i]->chain_lock); + if (!mlx5_fs_ns_is_empty(&root[i]->ns)) { + mutex_unlock(&root[i]->chain_lock); + goto err; + } + root[i]->dev =3D new_dev; + mutex_unlock(&root[i]->chain_lock); + } + return 0; +err: + while (i--) { + mutex_lock(&root[i]->chain_lock); + root[i]->dev =3D dev; + mutex_unlock(&root[i]->chain_lock); + } + /* If you hit this error try destroying all flow tables and try again */ + mlx5_core_err(dev, "Failed to set root device for RDMA TRANSPORT\n"); + return -EINVAL; +} +EXPORT_SYMBOL(mlx5_fs_set_root_dev); + static int init_rdma_transport_rx_root_ns(struct mlx5_flow_steering *steer= ing) { struct mlx5_core_dev *dev =3D steering->dev; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/fs_core.h b/drivers/ne= t/ethernet/mellanox/mlx5/core/fs_core.h index 0a9a5ef34c21..1c6591425260 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/fs_core.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/fs_core.h @@ -103,24 +103,6 @@ enum fs_node_type { FS_TYPE_FLOW_DEST }; =20 -enum fs_flow_table_type { - FS_FT_NIC_RX =3D 0x0, - FS_FT_NIC_TX =3D 0x1, - FS_FT_ESW_EGRESS_ACL =3D 0x2, - FS_FT_ESW_INGRESS_ACL =3D 0x3, - FS_FT_FDB =3D 0X4, - FS_FT_SNIFFER_RX =3D 0X5, - FS_FT_SNIFFER_TX =3D 0X6, - FS_FT_RDMA_RX =3D 0X7, - FS_FT_RDMA_TX =3D 0X8, - FS_FT_PORT_SEL =3D 0X9, - FS_FT_FDB_RX =3D 0xa, - FS_FT_FDB_TX =3D 0xb, - FS_FT_RDMA_TRANSPORT_RX =3D 0xd, - FS_FT_RDMA_TRANSPORT_TX =3D 0xe, - FS_FT_MAX_TYPE =3D FS_FT_RDMA_TRANSPORT_TX, -}; - enum fs_flow_table_op_mod { FS_FT_OP_MOD_NORMAL, FS_FT_OP_MOD_LAG_DEMUX, diff --git a/include/linux/mlx5/fs.h b/include/linux/mlx5/fs.h index 6325a7fa0df2..fe721557bd1d 100644 --- a/include/linux/mlx5/fs.h +++ b/include/linux/mlx5/fs.h @@ -128,6 +128,24 @@ enum { FDB_PER_VPORT, }; =20 +enum fs_flow_table_type { + FS_FT_NIC_RX =3D 0x0, + FS_FT_NIC_TX =3D 0x1, + FS_FT_ESW_EGRESS_ACL =3D 0x2, + FS_FT_ESW_INGRESS_ACL =3D 0x3, + FS_FT_FDB =3D 0X4, + FS_FT_SNIFFER_RX =3D 0X5, + FS_FT_SNIFFER_TX =3D 0X6, + FS_FT_RDMA_RX =3D 0X7, + FS_FT_RDMA_TX =3D 0X8, + FS_FT_PORT_SEL =3D 0X9, + FS_FT_FDB_RX =3D 0xa, + FS_FT_FDB_TX =3D 0xb, + FS_FT_RDMA_TRANSPORT_RX =3D 0xd, + FS_FT_RDMA_TRANSPORT_TX =3D 0xe, + FS_FT_MAX_TYPE =3D FS_FT_RDMA_TRANSPORT_TX, +}; + struct mlx5_pkt_reformat; struct mlx5_modify_hdr; struct mlx5_flow_definer; @@ -355,4 +373,8 @@ u32 mlx5_flow_table_id(struct mlx5_flow_table *ft); =20 struct mlx5_flow_root_namespace * mlx5_get_root_namespace(struct mlx5_core_dev *dev, enum mlx5_flow_namespac= e_type ns_type); + +int mlx5_fs_set_root_dev(struct mlx5_core_dev *dev, + struct mlx5_core_dev *new_dev, + enum fs_flow_table_type table_type); #endif --=20 2.47.1