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Wed, 29 Oct 2025 08:44:11 -0700 From: Edward Srouji To: Leon Romanovsky , Saeed Mahameed , Tariq Toukan , Mark Bloch , Andrew Lunn , "David S . Miller" , "Eric Dumazet" , Jakub Kicinski , Paolo Abeni , Jason Gunthorpe CC: , , , Patrisious Haddad , "Leon Romanovsky" , Edward Srouji Subject: [PATCH mlx5-next 2/7] net/mlx5: fs, Add other_eswitch support for steering tables Date: Wed, 29 Oct 2025 17:42:54 +0200 Message-ID: <20251029-support-other-eswitch-v1-2-98bb707b5d57@nvidia.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20251029-support-other-eswitch-v1-0-98bb707b5d57@nvidia.com> References: <20251029-support-other-eswitch-v1-0-98bb707b5d57@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF00004684:EE_|MN2PR12MB4287:EE_ X-MS-Office365-Filtering-Correlation-Id: 64e49ee0-c531-4f14-ff8d-08de17020dc8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|376014|7416014|1800799024|36860700013|921020; X-Microsoft-Antispam-Message-Info: =?utf-8?B?QkxrMEJkUTE1N3NJaWwxaFgzWnRiSERCTWN3UlRLb1hFaWxtMHR5VnJLQnEx?= =?utf-8?B?QnN3dHJQL01pYnFIamNXeDg4MEMrdHg5WXNhakFIMUtaakZwa013SmQ5Q2Zv?= =?utf-8?B?MlkzOHlCSjVSdXRKZEk2N3ZYY3UyeUUxRWpWUXU0eC85T1Zya05kQ1FmbVpQ?= =?utf-8?B?YWlpYW1vdzYwQi8xcFN0WjNTTFdMc1BtSEJ2eTAxb2FIZ2tLSlgvTW80L1lW?= =?utf-8?B?L0xlNUhXaHJ5NVk1SU9EdWhTemhOTTVRRTZETzhacEtTbHB3RkVaSndQVGt5?= =?utf-8?B?OXB0RjlsL1lIYjBnU0FYUVBvQjJMRnNXbGt5UCt4ajdvb1FBNDU2dzFhWGxn?= =?utf-8?B?anVYOHdaZmdJdHFqaDFnM0wrcjJNcElhbDZEM2R4RE5IRkJhZU5jaUU3a0pZ?= =?utf-8?B?QURhVmhKZ2NRTXlOTHBPWVY4cUhubzBaWktEMlBiRU80aThmbnByaHNPL296?= =?utf-8?B?KzNpU2RsK3kxYTdzeDVjWlgyZHJMYmRkdmhPYWZ1RUd1cDl6M3RNVnk1SEIv?= =?utf-8?B?SG43UHFyZTl0elFRTis1N2xkZDNZV2g0YU5UMkZoc0tCZDBKaEU1QnI0R2Ji?= =?utf-8?B?YXZDQ0dyYkN3ZFpBeklqaFZBY29CZ3F6RHdhWTlpYk1sY29objFOZGNkcGdx?= =?utf-8?B?aWhNQ3g3dG54WlJqN0FOcERSYXJlWWNBVHU0RlBtYkRReXdqdVNyS3BZSTVC?= =?utf-8?B?WE1MVXhHdG83SHg5NzVYWHNtWHZ4UlJjaVE1N0JQcTJIem9sVUxteEhuVzNo?= =?utf-8?B?Sk5ORWU0SWxISW9tbHZCUjQ1dEsrb1JncXBDaDBSZVBneVh1RDV0YUlpcEtx?= =?utf-8?B?Q3pEdnYxOFBacXh0MEJTejJ4L0FPYlVLOHhxYWdUY01CcUY0L29qRHFCa2F3?= =?utf-8?B?UVVlaVZrb3FIM2pyR3lxZHVRS2tReEFxTURiRHFzMEl5WVdmMlNEVkIvcEpm?= =?utf-8?B?bzlOL3Jkem5vcStpNkRKV3dvZEYyVDlwRUVqWkh4VG9yYzZDOFZTcTNkcnRL?= =?utf-8?B?RTErR01uM2JzY3VNZlVFeUVMSUU2Znl2a1pwRTA4U2VidHNUMmFnT0c3MmIv?= =?utf-8?B?dHNoTHc1MnUreDhuMzNwaCtkeXFaOElwMUZBek5iRWQ2aFoyckpETWtJK0RS?= =?utf-8?B?elJUVkpVK3V1MkNwZ0lqWmlTYkVwZkp3WlpoblhCZHZpMWFvSm05WEtoeWdl?= =?utf-8?B?YW96YmZwTzJqWklscmhrTzJQaXMzMG8vYUJxcXpLa0hrai9zd29idnIvN2VQ?= =?utf-8?B?eVhvdi9sQXJYMUhFaG0yS1VJakRXQ2RXbjBiMmpSSm0yR0dOM3p3bFpLQzlN?= =?utf-8?B?VVRaT0JqaDI5cFNpVDJQUG5QRVhRUWdBaUswcStMbVhZTEFTSUk4Vm5iN3dW?= =?utf-8?B?cHNlaVFJT1JTN01iUHM1NnZlUUQyTUtjWmdhWVRiYzAvcTdtUXZqNEdtT0FE?= =?utf-8?B?ZjVkMDc2TkVaREtkWThiNFBiTEY4ZWFBdktlSjNodFBuN3I5eHdBMU5UTzhm?= =?utf-8?B?d2NkckhuMjJxcTM1RWF4WjgvMHlQdGtpOXIyT2VJT1dvVk9CRTlKem9zVkRz?= =?utf-8?B?UmhjYjBRSFB2R3hjWFVGbWd1eHg5cjlkU0U2aklPUmYrU2o2ckZvalhuVEJr?= =?utf-8?B?ZmJnTFVkTFkyeDZjNTh5QUhPWDhxWEl3aDdMRytjQkFkRFVqamRwdWhJQXdl?= =?utf-8?B?UGVxSkVmN0NSSmxmaTJCRXRaK0h5MnRtWjlrNk1WNU9QK0Y2WG4zUlZNeDdL?= =?utf-8?B?eGNacUdJSGdXMjN3U3BUbm1qalRnWm40aU1BbytBdWYzaGNxVHE3STNxMU95?= =?utf-8?B?d3N0SVk1dE5SSnYvYko1TFBYVkM5Y213RDRPbTIxYU5KWmFFMTltdktHLzVW?= =?utf-8?B?QlJ0aUxOaCtCWXp6YWk4NFZPdE9LckhHRWZWY3ZaSkZKT2JuUnNWZkc4c0tG?= =?utf-8?B?Wlg5QlB1YzFoM2VxR01Qbno1QUZ2Sk54ZnBQK2xVQlVibHlZcXp4WW5VM1l2?= =?utf-8?B?ZmRKUUthK0l6Mm9oWk8rV0lGZE4vV3BVQWQ5bC9DRDZhNERaWlNsbndMV3Jt?= =?utf-8?B?aGl6aG4yeUFoZnZXQTR6QWZ1dHJnTE5RU2cwbWZBNG8vS0RRNVJ2Q0dqMld5?= =?utf-8?Q?z12MXNcWe7fe6x2WR6hKy0c4K?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(376014)(7416014)(1800799024)(36860700013)(921020);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Oct 2025 15:44:31.9543 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 64e49ee0-c531-4f14-ff8d-08de17020dc8 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF00004684.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4287 From: Patrisious Haddad Add other_eswitch support which allows flow tables creation above vports that reside on different esw managers. The new flag MLX5_FLOW_TABLE_OTHER_ESWITCH indicates if the esw_owner_vhca_id attribute is supported. Note that this is only supported if the Advanced-RDMA cap- rdma_transport_manager_other_eswitch is set. And it is the caller responsibility to check that. Signed-off-by: Patrisious Haddad Signed-off-by: Leon Romanovsky Signed-off-by: Edward Srouji --- drivers/net/ethernet/mellanox/mlx5/core/fs_cmd.c | 31 +++++++++++++++++++= ++++ drivers/net/ethernet/mellanox/mlx5/core/fs_core.c | 18 ++++++------- drivers/net/ethernet/mellanox/mlx5/core/fs_core.h | 1 + include/linux/mlx5/fs.h | 2 ++ 4 files changed, 42 insertions(+), 10 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/fs_cmd.c b/drivers/net= /ethernet/mellanox/mlx5/core/fs_cmd.c index 1af76da8b132..ced747bef641 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/fs_cmd.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/fs_cmd.c @@ -239,6 +239,10 @@ static int mlx5_cmd_update_root_ft(struct mlx5_flow_ro= ot_namespace *ns, MLX5_SET(set_flow_table_root_in, in, vport_number, ft->vport); MLX5_SET(set_flow_table_root_in, in, other_vport, !!(ft->flags & MLX5_FLOW_TABLE_OTHER_VPORT)); + MLX5_SET(set_flow_table_root_in, in, eswitch_owner_vhca_id, + ft->esw_owner_vhca_id); + MLX5_SET(set_flow_table_root_in, in, other_eswitch, + !!(ft->flags & MLX5_FLOW_TABLE_OTHER_ESWITCH)); =20 err =3D mlx5_cmd_exec_in(dev, set_flow_table_root, in); if (!err && @@ -302,6 +306,10 @@ static int mlx5_cmd_create_flow_table(struct mlx5_flow= _root_namespace *ns, MLX5_SET(create_flow_table_in, in, vport_number, ft->vport); MLX5_SET(create_flow_table_in, in, other_vport, !!(ft->flags & MLX5_FLOW_TABLE_OTHER_VPORT)); + MLX5_SET(create_flow_table_in, in, eswitch_owner_vhca_id, + ft->esw_owner_vhca_id); + MLX5_SET(create_flow_table_in, in, other_eswitch, + !!(ft->flags & MLX5_FLOW_TABLE_OTHER_ESWITCH)); =20 MLX5_SET(create_flow_table_in, in, flow_table_context.decap_en, en_decap); @@ -360,6 +368,10 @@ static int mlx5_cmd_destroy_flow_table(struct mlx5_flo= w_root_namespace *ns, MLX5_SET(destroy_flow_table_in, in, vport_number, ft->vport); MLX5_SET(destroy_flow_table_in, in, other_vport, !!(ft->flags & MLX5_FLOW_TABLE_OTHER_VPORT)); + MLX5_SET(destroy_flow_table_in, in, eswitch_owner_vhca_id, + ft->esw_owner_vhca_id); + MLX5_SET(destroy_flow_table_in, in, other_eswitch, + !!(ft->flags & MLX5_FLOW_TABLE_OTHER_ESWITCH)); =20 err =3D mlx5_cmd_exec_in(dev, destroy_flow_table, in); if (!err) @@ -394,6 +406,10 @@ static int mlx5_cmd_modify_flow_table(struct mlx5_flow= _root_namespace *ns, MLX5_SET(modify_flow_table_in, in, vport_number, ft->vport); MLX5_SET(modify_flow_table_in, in, other_vport, !!(ft->flags & MLX5_FLOW_TABLE_OTHER_VPORT)); + MLX5_SET(modify_flow_table_in, in, eswitch_owner_vhca_id, + ft->esw_owner_vhca_id); + MLX5_SET(modify_flow_table_in, in, other_eswitch, + !!(ft->flags & MLX5_FLOW_TABLE_OTHER_ESWITCH)); MLX5_SET(modify_flow_table_in, in, modify_field_select, MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID); if (next_ft) { @@ -429,6 +445,10 @@ static int mlx5_cmd_create_flow_group(struct mlx5_flow= _root_namespace *ns, MLX5_SET(create_flow_group_in, in, vport_number, ft->vport); MLX5_SET(create_flow_group_in, in, other_vport, !!(ft->flags & MLX5_FLOW_TABLE_OTHER_VPORT)); + MLX5_SET(create_flow_group_in, in, eswitch_owner_vhca_id, + ft->esw_owner_vhca_id); + MLX5_SET(create_flow_group_in, in, other_eswitch, + !!(ft->flags & MLX5_FLOW_TABLE_OTHER_ESWITCH)); err =3D mlx5_cmd_exec_inout(dev, create_flow_group, in, out); if (!err) fg->id =3D MLX5_GET(create_flow_group_out, out, @@ -451,6 +471,10 @@ static int mlx5_cmd_destroy_flow_group(struct mlx5_flo= w_root_namespace *ns, MLX5_SET(destroy_flow_group_in, in, vport_number, ft->vport); MLX5_SET(destroy_flow_group_in, in, other_vport, !!(ft->flags & MLX5_FLOW_TABLE_OTHER_VPORT)); + MLX5_SET(destroy_flow_group_in, in, eswitch_owner_vhca_id, + ft->esw_owner_vhca_id); + MLX5_SET(destroy_flow_group_in, in, other_eswitch, + !!(ft->flags & MLX5_FLOW_TABLE_OTHER_ESWITCH)); return mlx5_cmd_exec_in(dev, destroy_flow_group, in); } =20 @@ -559,6 +583,9 @@ static int mlx5_cmd_set_fte(struct mlx5_core_dev *dev, MLX5_SET(set_fte_in, in, vport_number, ft->vport); MLX5_SET(set_fte_in, in, other_vport, !!(ft->flags & MLX5_FLOW_TABLE_OTHER_VPORT)); + MLX5_SET(set_fte_in, in, eswitch_owner_vhca_id, ft->esw_owner_vhca_id); + MLX5_SET(set_fte_in, in, other_eswitch, + !!(ft->flags & MLX5_FLOW_TABLE_OTHER_ESWITCH)); =20 in_flow_context =3D MLX5_ADDR_OF(set_fte_in, in, flow_context); MLX5_SET(flow_context, in_flow_context, group_id, group_id); @@ -788,6 +815,10 @@ static int mlx5_cmd_delete_fte(struct mlx5_flow_root_n= amespace *ns, MLX5_SET(delete_fte_in, in, vport_number, ft->vport); MLX5_SET(delete_fte_in, in, other_vport, !!(ft->flags & MLX5_FLOW_TABLE_OTHER_VPORT)); + MLX5_SET(delete_fte_in, in, eswitch_owner_vhca_id, + ft->esw_owner_vhca_id); + MLX5_SET(delete_fte_in, in, other_eswitch, + !!(ft->flags & MLX5_FLOW_TABLE_OTHER_ESWITCH)); =20 return mlx5_cmd_exec_in(dev, delete_fte, in); } diff --git a/drivers/net/ethernet/mellanox/mlx5/core/fs_core.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/fs_core.c index 2db3ffb0a2b2..87e381c82ed3 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/fs_core.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/fs_core.c @@ -939,10 +939,10 @@ static struct mlx5_flow_group *alloc_insert_flow_grou= p(struct mlx5_flow_table *f return fg; } =20 -static struct mlx5_flow_table *alloc_flow_table(int level, u16 vport, - enum fs_flow_table_type table_type, - enum fs_flow_table_op_mod op_mod, - u32 flags) +static struct mlx5_flow_table * +alloc_flow_table(struct mlx5_flow_table_attr *ft_attr, u16 vport, + enum fs_flow_table_type table_type, + enum fs_flow_table_op_mod op_mod) { struct mlx5_flow_table *ft; int ret; @@ -957,12 +957,13 @@ static struct mlx5_flow_table *alloc_flow_table(int l= evel, u16 vport, return ERR_PTR(ret); } =20 - ft->level =3D level; + ft->level =3D ft_attr->level; ft->node.type =3D FS_TYPE_FLOW_TABLE; ft->op_mod =3D op_mod; ft->type =3D table_type; ft->vport =3D vport; - ft->flags =3D flags; + ft->esw_owner_vhca_id =3D ft_attr->esw_owner_vhca_id; + ft->flags =3D ft_attr->flags; INIT_LIST_HEAD(&ft->fwd_rules); mutex_init(&ft->lock); =20 @@ -1370,10 +1371,7 @@ static struct mlx5_flow_table *__mlx5_create_flow_ta= ble(struct mlx5_flow_namespa /* The level is related to the * priority level range. */ - ft =3D alloc_flow_table(ft_attr->level, - vport, - root->table_type, - op_mod, ft_attr->flags); + ft =3D alloc_flow_table(ft_attr, vport, root->table_type, op_mod); if (IS_ERR(ft)) { err =3D PTR_ERR(ft); goto unlock_root; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/fs_core.h b/drivers/ne= t/ethernet/mellanox/mlx5/core/fs_core.h index 8458ce203dac..0a9a5ef34c21 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/fs_core.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/fs_core.h @@ -205,6 +205,7 @@ struct mlx5_flow_table { }; u32 id; u16 vport; + u16 esw_owner_vhca_id; unsigned int max_fte; unsigned int level; enum fs_flow_table_type type; diff --git a/include/linux/mlx5/fs.h b/include/linux/mlx5/fs.h index 6ac76a0c3827..6325a7fa0df2 100644 --- a/include/linux/mlx5/fs.h +++ b/include/linux/mlx5/fs.h @@ -71,6 +71,7 @@ enum { MLX5_FLOW_TABLE_UNMANAGED =3D BIT(3), MLX5_FLOW_TABLE_OTHER_VPORT =3D BIT(4), MLX5_FLOW_TABLE_UPLINK_VPORT =3D BIT(5), + MLX5_FLOW_TABLE_OTHER_ESWITCH =3D BIT(6), }; =20 #define LEFTOVERS_RULE_NUM 2 @@ -208,6 +209,7 @@ struct mlx5_flow_table_attr { u32 flags; u16 uid; u16 vport; + u16 esw_owner_vhca_id; struct mlx5_flow_table *next_ft; =20 struct { --=20 2.47.1