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Wed, 29 Oct 2025 08:43:56 -0700 From: Edward Srouji To: Leon Romanovsky , Saeed Mahameed , Tariq Toukan , Mark Bloch , Andrew Lunn , "David S . Miller" , "Eric Dumazet" , Jakub Kicinski , Paolo Abeni , Jason Gunthorpe CC: , , , Patrisious Haddad , "Leon Romanovsky" , Edward Srouji Subject: [PATCH mlx5-next 1/7] net/mlx5: Add OTHER_ESWITCH HW capabilities Date: Wed, 29 Oct 2025 17:42:53 +0200 Message-ID: <20251029-support-other-eswitch-v1-1-98bb707b5d57@nvidia.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20251029-support-other-eswitch-v1-0-98bb707b5d57@nvidia.com> References: <20251029-support-other-eswitch-v1-0-98bb707b5d57@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF00004682:EE_|DS0PR12MB8561:EE_ X-MS-Office365-Filtering-Correlation-Id: ab597a22-b8f7-4118-430a-08de17020658 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|376014|7416014|1800799024|36860700013|921020; X-Microsoft-Antispam-Message-Info: =?utf-8?B?YVFnV3E0ZHZoSmdXZ1VEY0dwRjZlcVIzYW02UFd0dXFxSHY0Yk9CMHo3d2RG?= =?utf-8?B?Z0VpSG9VZ1dMOFA1bXNVVUw2aHVmc29UVnVrQXlPZ3J6VUdDV0lFaG8wZXA2?= =?utf-8?B?RXNueGVzMVE4aVYrUkkzOGxHOHIxZ1I3Wjhybm83Qlg4ZENzSnh4dDFsTXdu?= =?utf-8?B?RFBxQzh0MFVod1RHdUZuWUFRN0lqZzdwRWUwYXVuTFFVWUtrdXhWdlhCc3oz?= =?utf-8?B?b3F1bjdmVXhYbkhhUWMzSWRBdzJzVWlrUEtweVRkbkMzWlRSWDRqSUNiMXgv?= =?utf-8?B?YkhIc0NZOUEvUFJVek1GcU5OZWxIZDdmc21VSFVuZWpzdlZ5Rm1KVXNTai83?= =?utf-8?B?Y0FxS0FrSWRETXR5c3pubE9WK0RrWGRZZkdPWU5RdjV5c0ZvbkJlREJrQ0hB?= =?utf-8?B?MU5PTTlpWHk1SmxNQVB6NHRVcmUvQVdzMHNYeGpkcU4zajMvYTNWV2gvaldM?= =?utf-8?B?Ti8zVFlpaVJ3aGdZcFljQkxUckJTWi9DMVVTV29ZaENRVnE1K3l4emdXV2JU?= =?utf-8?B?Tjc5elRGM0lwbDhzVFlpR0RiQjFmSVBORHFqZlg2RW1KRVF2a2ZDT1ZvZjFO?= =?utf-8?B?WDFUQUFiWEpOSFIwdGxHem1iNTI3amErTE80WjBJMENHeWtiR2VSU0VTWncz?= =?utf-8?B?TytVSUxPWm93dDhuaE1Dai9EMlp2VkJxb2ZCb2JTaHlvV3l4dmxaT2pURUhF?= =?utf-8?B?NHQxSFdhTUxHY2xoTTQ0bUN5azVPM0xHZ3dXRDB0aFRrQVhQRHhWQWhaYld0?= =?utf-8?B?YmUxMFY1dXVGY3BLOTB0TEU5U0xtNTJpb0M0RDErc1g1dTFMSWdkODhPbDBr?= =?utf-8?B?ajRSTEtCZUV1ZGRvM1c5U2hhSnRJVnViNis5SUV2ZGtuWkpCYnlSV2NZaTlT?= =?utf-8?B?Y3hlSktrbjJxRmI4UG9aSWF4V0NZU1NpNVBMMzd1NHdJRDY1anJpWmhjUGhB?= =?utf-8?B?V0FXWkxPK1NOU1h5UzN2ek9xSjVwV3djTm1YNXZzTThKWEtzMFMvc010U0k5?= =?utf-8?B?eGg1VTBzRzBuR2NXMVI5aWJKMkxxaC8zOENUMnpyaE9FbGZmYk1KWGs3UkF4?= =?utf-8?B?RlJibEJzVHVUQ2R3N01vUVYyUHVrMlRzNEo0eFRueDVJNVdUazVmdWhodGVx?= =?utf-8?B?NGNvQmMrOWtYWnRpSUV5NEdFdTlUaXVEd1VxZjgwdzJxS1RUT3pWOTZPU09H?= =?utf-8?B?UHV5a0s1Sm82WE1uS3dOd2xsSkRKSy9YeTVPakl6eXQyVmo0ay9aZWNHMU51?= =?utf-8?B?L3ZkMWtYTmVwUzlUc3NvSURxQVM4K3MzWGhRV0FrU3lueGZaQ2FEeU5PS3kz?= =?utf-8?B?UitqUW55K281d1FsRlRiNytpMTN3L1NaeHZ0STI3bXJxd3Qwc21zdTZoTGxz?= =?utf-8?B?R0ljTTdNRHc3WHF4UTVHT2RlaXVjOS83bUxOOG9jVVNYaUkrcXM5cjFTTnFM?= =?utf-8?B?VmZRQmplam1SZGtNV2FHY0xVRmNWMENjRExHVmh4RUJWeEpEcTJ3TmNCc0FQ?= =?utf-8?B?aXkrRFNTUEgvZFF0aklBcURJaGhJUHUyL2daL0RKY2RKalJ2clJRSFQyTVNX?= =?utf-8?B?c3hNYTJ4MTAyY0dqTTMyNWllOTFNcFlxbTdPU1k2V2RwOUJYVFRKVjJzQzJ6?= =?utf-8?B?TzZnNUlWU25NbnI3YSsvRkRJdTY0MXFJRUVUdFc4YWM3TUFZYU12Z285dDRQ?= =?utf-8?B?MDZOVEpqcFNZeGtJWjhRR3hFdm9tam9zam80WEZubVBGZHFiRmVjazdJajZM?= =?utf-8?B?ay91TUNIUzNsOE4zZ05RY2xFTko5VldwSzdkN1V6dmFZT3ZUcDMyR3J3b2Q4?= =?utf-8?B?WkhiZFA0VVRZbkRWY3ZRblVLNEloWEVsbjF5aEpqVUZ0cE9DMXA4QVZDdktt?= =?utf-8?B?Y2h4bUZmS1p0bmk3MWpqcXZsZGtRNTlqQi9ZeWpMTDhwZlVnbVlZRXVVKzRv?= =?utf-8?B?cGpYNXBWSmJzdVkyVHpwSzEyTExKUGlVN0Fuc0JLQnkvL1V2a0JHN3lrdHlq?= =?utf-8?B?UnpIWGlsTVI3R3NaMzlGT0hSV2FBQjMxb0R1Mzd3K2pIU25iVDN0T0g3alRG?= =?utf-8?B?dy81Sy96b3daUUpmRXhianNGVDZtZ0NuOFA3eVNwbnNVYkNCczFxeGV5Z1BJ?= =?utf-8?Q?/eL3tHwLaLnfMqfm6bRNqLbK5?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(376014)(7416014)(1800799024)(36860700013)(921020);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Oct 2025 15:44:19.5124 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ab597a22-b8f7-4118-430a-08de17020658 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF00004682.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB8561 From: Patrisious Haddad Add OTHER_ESWITCH capabilities which includes other_eswitch and eswitch_owner_vhca_id to all steering objects. Signed-off-by: Patrisious Haddad Signed-off-by: Leon Romanovsky Signed-off-by: Edward Srouji --- include/linux/mlx5/mlx5_ifc.h | 47 ++++++++++++++++++++++++++++-----------= ---- 1 file changed, 31 insertions(+), 16 deletions(-) diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h index 07614cd95bed..9b8f88987d2f 100644 --- a/include/linux/mlx5/mlx5_ifc.h +++ b/include/linux/mlx5/mlx5_ifc.h @@ -5251,13 +5251,15 @@ struct mlx5_ifc_set_fte_in_bits { u8 op_mod[0x10]; =20 u8 other_vport[0x1]; - u8 reserved_at_41[0xf]; + u8 other_eswitch[0x1]; + u8 reserved_at_42[0xe]; u8 vport_number[0x10]; =20 u8 reserved_at_60[0x20]; =20 u8 table_type[0x8]; - u8 reserved_at_88[0x18]; + u8 reserved_at_88[0x8]; + u8 eswitch_owner_vhca_id[0x10]; =20 u8 reserved_at_a0[0x8]; u8 table_id[0x18]; @@ -8809,13 +8811,15 @@ struct mlx5_ifc_destroy_flow_table_in_bits { u8 op_mod[0x10]; =20 u8 other_vport[0x1]; - u8 reserved_at_41[0xf]; + u8 other_eswitch[0x1]; + u8 reserved_at_42[0xe]; u8 vport_number[0x10]; =20 u8 reserved_at_60[0x20]; =20 u8 table_type[0x8]; - u8 reserved_at_88[0x18]; + u8 reserved_at_88[0x8]; + u8 eswitch_owner_vhca_id[0x10]; =20 u8 reserved_at_a0[0x8]; u8 table_id[0x18]; @@ -8840,13 +8844,15 @@ struct mlx5_ifc_destroy_flow_group_in_bits { u8 op_mod[0x10]; =20 u8 other_vport[0x1]; - u8 reserved_at_41[0xf]; + u8 other_eswitch[0x1]; + u8 reserved_at_42[0xe]; u8 vport_number[0x10]; =20 u8 reserved_at_60[0x20]; =20 u8 table_type[0x8]; - u8 reserved_at_88[0x18]; + u8 reserved_at_88[0x8]; + u8 eswitch_owner_vhca_id[0x10]; =20 u8 reserved_at_a0[0x8]; u8 table_id[0x18]; @@ -8985,13 +8991,15 @@ struct mlx5_ifc_delete_fte_in_bits { u8 op_mod[0x10]; =20 u8 other_vport[0x1]; - u8 reserved_at_41[0xf]; + u8 other_eswitch[0x1]; + u8 reserved_at_42[0xe]; u8 vport_number[0x10]; =20 u8 reserved_at_60[0x20]; =20 u8 table_type[0x8]; - u8 reserved_at_88[0x18]; + u8 reserved_at_88[0x8]; + u8 eswitch_owner_vhca_id[0x10]; =20 u8 reserved_at_a0[0x8]; u8 table_id[0x18]; @@ -9535,13 +9543,15 @@ struct mlx5_ifc_create_flow_table_in_bits { u8 op_mod[0x10]; =20 u8 other_vport[0x1]; - u8 reserved_at_41[0xf]; + u8 other_eswitch[0x1]; + u8 reserved_at_42[0xe]; u8 vport_number[0x10]; =20 u8 reserved_at_60[0x20]; =20 u8 table_type[0x8]; - u8 reserved_at_88[0x18]; + u8 reserved_at_88[0x8]; + u8 eswitch_owner_vhca_id[0x10]; =20 u8 reserved_at_a0[0x20]; =20 @@ -9580,7 +9590,8 @@ struct mlx5_ifc_create_flow_group_in_bits { u8 op_mod[0x10]; =20 u8 other_vport[0x1]; - u8 reserved_at_41[0xf]; + u8 other_eswitch[0x1]; + u8 reserved_at_42[0xe]; u8 vport_number[0x10]; =20 u8 reserved_at_60[0x20]; @@ -9588,7 +9599,7 @@ struct mlx5_ifc_create_flow_group_in_bits { u8 table_type[0x8]; u8 reserved_at_88[0x4]; u8 group_type[0x4]; - u8 reserved_at_90[0x10]; + u8 eswitch_owner_vhca_id[0x10]; =20 u8 reserved_at_a0[0x8]; u8 table_id[0x18]; @@ -11876,10 +11887,12 @@ struct mlx5_ifc_set_flow_table_root_in_bits { u8 op_mod[0x10]; =20 u8 other_vport[0x1]; - u8 reserved_at_41[0xf]; + u8 other_eswitch[0x1]; + u8 reserved_at_42[0xe]; u8 vport_number[0x10]; =20 - u8 reserved_at_60[0x20]; + u8 reserved_at_60[0x10]; + u8 eswitch_owner_vhca_id[0x10]; =20 u8 table_type[0x8]; u8 reserved_at_88[0x7]; @@ -11919,14 +11932,16 @@ struct mlx5_ifc_modify_flow_table_in_bits { u8 op_mod[0x10]; =20 u8 other_vport[0x1]; - u8 reserved_at_41[0xf]; + u8 other_eswitch[0x1]; + u8 reserved_at_42[0xe]; u8 vport_number[0x10]; =20 u8 reserved_at_60[0x10]; u8 modify_field_select[0x10]; =20 u8 table_type[0x8]; - u8 reserved_at_88[0x18]; + u8 reserved_at_88[0x8]; + u8 eswitch_owner_vhca_id[0x10]; =20 u8 reserved_at_a0[0x8]; u8 table_id[0x18]; --=20 2.47.1