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Wed, 29 Oct 2025 08:43:56 -0700 From: Edward Srouji To: Leon Romanovsky , Saeed Mahameed , Tariq Toukan , Mark Bloch , Andrew Lunn , "David S . Miller" , "Eric Dumazet" , Jakub Kicinski , Paolo Abeni , Jason Gunthorpe CC: , , , Patrisious Haddad , "Leon Romanovsky" , Edward Srouji Subject: [PATCH mlx5-next 1/7] net/mlx5: Add OTHER_ESWITCH HW capabilities Date: Wed, 29 Oct 2025 17:42:53 +0200 Message-ID: <20251029-support-other-eswitch-v1-1-98bb707b5d57@nvidia.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20251029-support-other-eswitch-v1-0-98bb707b5d57@nvidia.com> References: <20251029-support-other-eswitch-v1-0-98bb707b5d57@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF00004682:EE_|DS0PR12MB8561:EE_ X-MS-Office365-Filtering-Correlation-Id: ab597a22-b8f7-4118-430a-08de17020658 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|376014|7416014|1800799024|36860700013|921020; X-Microsoft-Antispam-Message-Info: =?utf-8?B?YVFnV3E0ZHZoSmdXZ1VEY0dwRjZlcVIzYW02UFd0dXFxSHY0Yk9CMHo3d2RG?= =?utf-8?B?Z0VpSG9VZ1dMOFA1bXNVVUw2aHVmc29UVnVrQXlPZ3J6VUdDV0lFaG8wZXA2?= =?utf-8?B?RXNueGVzMVE4aVYrUkkzOGxHOHIxZ1I3Wjhybm83Qlg4ZENzSnh4dDFsTXdu?= =?utf-8?B?RFBxQzh0MFVod1RHdUZuWUFRN0lqZzdwRWUwYXVuTFFVWUtrdXhWdlhCc3oz?= =?utf-8?B?b3F1bjdmVXhYbkhhUWMzSWRBdzJzVWlrUEtweVRkbkMzWlRSWDRqSUNiMXgv?= =?utf-8?B?YkhIc0NZOUEvUFJVek1GcU5OZWxIZDdmc21VSFVuZWpzdlZ5Rm1KVXNTai83?= =?utf-8?B?Y0FxS0FrSWRETXR5c3pubE9WK0RrWGRZZkdPWU5RdjV5c0ZvbkJlREJrQ0hB?= =?utf-8?B?MU5PTTlpWHk1SmxNQVB6NHRVcmUvQVdzMHNYeGpkcU4zajMvYTNWV2gvaldM?= =?utf-8?B?Ti8zVFlpaVJ3aGdZcFljQkxUckJTWi9DMVVTV29ZaENRVnE1K3l4emdXV2JU?= =?utf-8?B?Tjc5elRGM0lwbDhzVFlpR0RiQjFmSVBORHFqZlg2RW1KRVF2a2ZDT1ZvZjFO?= =?utf-8?B?WDFUQUFiWEpOSFIwdGxHem1iNTI3amErTE80WjBJMENHeWtiR2VSU0VTWncz?= =?utf-8?B?TytVSUxPWm93dDhuaE1Dai9EMlp2VkJxb2ZCb2JTaHlvV3l4dmxaT2pURUhF?= =?utf-8?B?NHQxSFdhTUxHY2xoTTQ0bUN5azVPM0xHZ3dXRDB0aFRrQVhQRHhWQWhaYld0?= =?utf-8?B?YmUxMFY1dXVGY3BLOTB0TEU5U0xtNTJpb0M0RDErc1g1dTFMSWdkODhPbDBr?= =?utf-8?B?ajRSTEtCZUV1ZGRvM1c5U2hhSnRJVnViNis5SUV2ZGtuWkpCYnlSV2NZaTlT?= =?utf-8?B?Y3hlSktrbjJxRmI4UG9aSWF4V0NZU1NpNVBMMzd1NHdJRDY1anJpWmhjUGhB?= =?utf-8?B?V0FXWkxPK1NOU1h5UzN2ek9xSjVwV3djTm1YNXZzTThKWEtzMFMvc010U0k5?= =?utf-8?B?eGg1VTBzRzBuR2NXMVI5aWJKMkxxaC8zOENUMnpyaE9FbGZmYk1KWGs3UkF4?= =?utf-8?B?RlJibEJzVHVUQ2R3N01vUVYyUHVrMlRzNEo0eFRueDVJNVdUazVmdWhodGVx?= =?utf-8?B?NGNvQmMrOWtYWnRpSUV5NEdFdTlUaXVEd1VxZjgwdzJxS1RUT3pWOTZPU09H?= =?utf-8?B?UHV5a0s1Sm82WE1uS3dOd2xsSkRKSy9YeTVPakl6eXQyVmo0ay9aZWNHMU51?= =?utf-8?B?L3ZkMWtYTmVwUzlUc3NvSURxQVM4K3MzWGhRV0FrU3lueGZaQ2FEeU5PS3kz?= =?utf-8?B?UitqUW55K281d1FsRlRiNytpMTN3L1NaeHZ0STI3bXJxd3Qwc21zdTZoTGxz?= =?utf-8?B?R0ljTTdNRHc3WHF4UTVHT2RlaXVjOS83bUxOOG9jVVNYaUkrcXM5cjFTTnFM?= =?utf-8?B?VmZRQmplam1SZGtNV2FHY0xVRmNWMENjRExHVmh4RUJWeEpEcTJ3TmNCc0FQ?= =?utf-8?B?aXkrRFNTUEgvZFF0aklBcURJaGhJUHUyL2daL0RKY2RKalJ2clJRSFQyTVNX?= =?utf-8?B?c3hNYTJ4MTAyY0dqTTMyNWllOTFNcFlxbTdPU1k2V2RwOUJYVFRKVjJzQzJ6?= =?utf-8?B?TzZnNUlWU25NbnI3YSsvRkRJdTY0MXFJRUVUdFc4YWM3TUFZYU12Z285dDRQ?= =?utf-8?B?MDZOVEpqcFNZeGtJWjhRR3hFdm9tam9zam80WEZubVBGZHFiRmVjazdJajZM?= =?utf-8?B?ay91TUNIUzNsOE4zZ05RY2xFTko5VldwSzdkN1V6dmFZT3ZUcDMyR3J3b2Q4?= =?utf-8?B?WkhiZFA0VVRZbkRWY3ZRblVLNEloWEVsbjF5aEpqVUZ0cE9DMXA4QVZDdktt?= =?utf-8?B?Y2h4bUZmS1p0bmk3MWpqcXZsZGtRNTlqQi9ZeWpMTDhwZlVnbVlZRXVVKzRv?= =?utf-8?B?cGpYNXBWSmJzdVkyVHpwSzEyTExKUGlVN0Fuc0JLQnkvL1V2a0JHN3lrdHlq?= =?utf-8?B?UnpIWGlsTVI3R3NaMzlGT0hSV2FBQjMxb0R1Mzd3K2pIU25iVDN0T0g3alRG?= =?utf-8?B?dy81Sy96b3daUUpmRXhianNGVDZtZ0NuOFA3eVNwbnNVYkNCczFxeGV5Z1BJ?= =?utf-8?Q?/eL3tHwLaLnfMqfm6bRNqLbK5?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(376014)(7416014)(1800799024)(36860700013)(921020);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Oct 2025 15:44:19.5124 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ab597a22-b8f7-4118-430a-08de17020658 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF00004682.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB8561 From: Patrisious Haddad Add OTHER_ESWITCH capabilities which includes other_eswitch and eswitch_owner_vhca_id to all steering objects. Signed-off-by: Patrisious Haddad Signed-off-by: Leon Romanovsky Signed-off-by: Edward Srouji --- include/linux/mlx5/mlx5_ifc.h | 47 ++++++++++++++++++++++++++++-----------= ---- 1 file changed, 31 insertions(+), 16 deletions(-) diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h index 07614cd95bed..9b8f88987d2f 100644 --- a/include/linux/mlx5/mlx5_ifc.h +++ b/include/linux/mlx5/mlx5_ifc.h @@ -5251,13 +5251,15 @@ struct mlx5_ifc_set_fte_in_bits { u8 op_mod[0x10]; =20 u8 other_vport[0x1]; - u8 reserved_at_41[0xf]; + u8 other_eswitch[0x1]; + u8 reserved_at_42[0xe]; u8 vport_number[0x10]; =20 u8 reserved_at_60[0x20]; =20 u8 table_type[0x8]; - u8 reserved_at_88[0x18]; + u8 reserved_at_88[0x8]; + u8 eswitch_owner_vhca_id[0x10]; =20 u8 reserved_at_a0[0x8]; u8 table_id[0x18]; @@ -8809,13 +8811,15 @@ struct mlx5_ifc_destroy_flow_table_in_bits { u8 op_mod[0x10]; =20 u8 other_vport[0x1]; - u8 reserved_at_41[0xf]; + u8 other_eswitch[0x1]; + u8 reserved_at_42[0xe]; u8 vport_number[0x10]; =20 u8 reserved_at_60[0x20]; =20 u8 table_type[0x8]; - u8 reserved_at_88[0x18]; + u8 reserved_at_88[0x8]; + u8 eswitch_owner_vhca_id[0x10]; =20 u8 reserved_at_a0[0x8]; u8 table_id[0x18]; @@ -8840,13 +8844,15 @@ struct mlx5_ifc_destroy_flow_group_in_bits { u8 op_mod[0x10]; =20 u8 other_vport[0x1]; - u8 reserved_at_41[0xf]; + u8 other_eswitch[0x1]; + u8 reserved_at_42[0xe]; u8 vport_number[0x10]; =20 u8 reserved_at_60[0x20]; =20 u8 table_type[0x8]; - u8 reserved_at_88[0x18]; + u8 reserved_at_88[0x8]; + u8 eswitch_owner_vhca_id[0x10]; =20 u8 reserved_at_a0[0x8]; u8 table_id[0x18]; @@ -8985,13 +8991,15 @@ struct mlx5_ifc_delete_fte_in_bits { u8 op_mod[0x10]; =20 u8 other_vport[0x1]; - u8 reserved_at_41[0xf]; + u8 other_eswitch[0x1]; + u8 reserved_at_42[0xe]; u8 vport_number[0x10]; =20 u8 reserved_at_60[0x20]; =20 u8 table_type[0x8]; - u8 reserved_at_88[0x18]; + u8 reserved_at_88[0x8]; + u8 eswitch_owner_vhca_id[0x10]; =20 u8 reserved_at_a0[0x8]; u8 table_id[0x18]; @@ -9535,13 +9543,15 @@ struct mlx5_ifc_create_flow_table_in_bits { u8 op_mod[0x10]; =20 u8 other_vport[0x1]; - u8 reserved_at_41[0xf]; + u8 other_eswitch[0x1]; + u8 reserved_at_42[0xe]; u8 vport_number[0x10]; =20 u8 reserved_at_60[0x20]; =20 u8 table_type[0x8]; - u8 reserved_at_88[0x18]; + u8 reserved_at_88[0x8]; + u8 eswitch_owner_vhca_id[0x10]; =20 u8 reserved_at_a0[0x20]; =20 @@ -9580,7 +9590,8 @@ struct mlx5_ifc_create_flow_group_in_bits { u8 op_mod[0x10]; =20 u8 other_vport[0x1]; - u8 reserved_at_41[0xf]; + u8 other_eswitch[0x1]; + u8 reserved_at_42[0xe]; u8 vport_number[0x10]; =20 u8 reserved_at_60[0x20]; @@ -9588,7 +9599,7 @@ struct mlx5_ifc_create_flow_group_in_bits { u8 table_type[0x8]; u8 reserved_at_88[0x4]; u8 group_type[0x4]; - u8 reserved_at_90[0x10]; + u8 eswitch_owner_vhca_id[0x10]; =20 u8 reserved_at_a0[0x8]; u8 table_id[0x18]; @@ -11876,10 +11887,12 @@ struct mlx5_ifc_set_flow_table_root_in_bits { u8 op_mod[0x10]; =20 u8 other_vport[0x1]; - u8 reserved_at_41[0xf]; + u8 other_eswitch[0x1]; + u8 reserved_at_42[0xe]; u8 vport_number[0x10]; =20 - u8 reserved_at_60[0x20]; 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Miller" , "Eric Dumazet" , Jakub Kicinski , Paolo Abeni , Jason Gunthorpe CC: , , , Patrisious Haddad , "Leon Romanovsky" , Edward Srouji Subject: [PATCH mlx5-next 2/7] net/mlx5: fs, Add other_eswitch support for steering tables Date: Wed, 29 Oct 2025 17:42:54 +0200 Message-ID: <20251029-support-other-eswitch-v1-2-98bb707b5d57@nvidia.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20251029-support-other-eswitch-v1-0-98bb707b5d57@nvidia.com> References: <20251029-support-other-eswitch-v1-0-98bb707b5d57@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF00004684:EE_|MN2PR12MB4287:EE_ X-MS-Office365-Filtering-Correlation-Id: 64e49ee0-c531-4f14-ff8d-08de17020dc8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|376014|7416014|1800799024|36860700013|921020; X-Microsoft-Antispam-Message-Info: =?utf-8?B?QkxrMEJkUTE1N3NJaWwxaFgzWnRiSERCTWN3UlRLb1hFaWxtMHR5VnJLQnEx?= =?utf-8?B?QnN3dHJQL01pYnFIamNXeDg4MEMrdHg5WXNhakFIMUtaakZwa013SmQ5Q2Zv?= =?utf-8?B?MlkzOHlCSjVSdXRKZEk2N3ZYY3UyeUUxRWpWUXU0eC85T1Zya05kQ1FmbVpQ?= =?utf-8?B?YWlpYW1vdzYwQi8xcFN0WjNTTFdMc1BtSEJ2eTAxb2FIZ2tLSlgvTW80L1lW?= =?utf-8?B?L0xlNUhXaHJ5NVk1SU9EdWhTemhOTTVRRTZETzhacEtTbHB3RkVaSndQVGt5?= =?utf-8?B?OXB0RjlsL1lIYjBnU0FYUVBvQjJMRnNXbGt5UCt4ajdvb1FBNDU2dzFhWGxn?= =?utf-8?B?anVYOHdaZmdJdHFqaDFnM0wrcjJNcElhbDZEM2R4RE5IRkJhZU5jaUU3a0pZ?= =?utf-8?B?QURhVmhKZ2NRTXlOTHBPWVY4cUhubzBaWktEMlBiRU80aThmbnByaHNPL296?= =?utf-8?B?KzNpU2RsK3kxYTdzeDVjWlgyZHJMYmRkdmhPYWZ1RUd1cDl6M3RNVnk1SEIv?= =?utf-8?B?SG43UHFyZTl0elFRTis1N2xkZDNZV2g0YU5UMkZoc0tCZDBKaEU1QnI0R2Ji?= =?utf-8?B?YXZDQ0dyYkN3ZFpBeklqaFZBY29CZ3F6RHdhWTlpYk1sY29objFOZGNkcGdx?= =?utf-8?B?aWhNQ3g3dG54WlJqN0FOcERSYXJlWWNBVHU0RlBtYkRReXdqdVNyS3BZSTVC?= =?utf-8?B?WE1MVXhHdG83SHg5NzVYWHNtWHZ4UlJjaVE1N0JQcTJIem9sVUxteEhuVzNo?= =?utf-8?B?Sk5ORWU0SWxISW9tbHZCUjQ1dEsrb1JncXBDaDBSZVBneVh1RDV0YUlpcEtx?= =?utf-8?B?Q3pEdnYxOFBacXh0MEJTejJ4L0FPYlVLOHhxYWdUY01CcUY0L29qRHFCa2F3?= =?utf-8?B?UVVlaVZrb3FIM2pyR3lxZHVRS2tReEFxTURiRHFzMEl5WVdmMlNEVkIvcEpm?= =?utf-8?B?bzlOL3Jkem5vcStpNkRKV3dvZEYyVDlwRUVqWkh4VG9yYzZDOFZTcTNkcnRL?= =?utf-8?B?RTErR01uM2JzY3VNZlVFeUVMSUU2Znl2a1pwRTA4U2VidHNUMmFnT0c3MmIv?= =?utf-8?B?dHNoTHc1MnUreDhuMzNwaCtkeXFaOElwMUZBek5iRWQ2aFoyckpETWtJK0RS?= =?utf-8?B?elJUVkpVK3V1MkNwZ0lqWmlTYkVwZkp3WlpoblhCZHZpMWFvSm05WEtoeWdl?= =?utf-8?B?YW96YmZwTzJqWklscmhrTzJQaXMzMG8vYUJxcXpLa0hrai9zd29idnIvN2VQ?= =?utf-8?B?eVhvdi9sQXJYMUhFaG0yS1VJakRXQ2RXbjBiMmpSSm0yR0dOM3p3bFpLQzlN?= =?utf-8?B?VVRaT0JqaDI5cFNpVDJQUG5QRVhRUWdBaUswcStMbVhZTEFTSUk4Vm5iN3dW?= =?utf-8?B?cHNlaVFJT1JTN01iUHM1NnZlUUQyTUtjWmdhWVRiYzAvcTdtUXZqNEdtT0FE?= =?utf-8?B?ZjVkMDc2TkVaREtkWThiNFBiTEY4ZWFBdktlSjNodFBuN3I5eHdBMU5UTzhm?= =?utf-8?B?d2NkckhuMjJxcTM1RWF4WjgvMHlQdGtpOXIyT2VJT1dvVk9CRTlKem9zVkRz?= =?utf-8?B?UmhjYjBRSFB2R3hjWFVGbWd1eHg5cjlkU0U2aklPUmYrU2o2ckZvalhuVEJr?= =?utf-8?B?ZmJnTFVkTFkyeDZjNTh5QUhPWDhxWEl3aDdMRytjQkFkRFVqamRwdWhJQXdl?= =?utf-8?B?UGVxSkVmN0NSSmxmaTJCRXRaK0h5MnRtWjlrNk1WNU9QK0Y2WG4zUlZNeDdL?= =?utf-8?B?eGNacUdJSGdXMjN3U3BUbm1qalRnWm40aU1BbytBdWYzaGNxVHE3STNxMU95?= =?utf-8?B?d3N0SVk1dE5SSnYvYko1TFBYVkM5Y213RDRPbTIxYU5KWmFFMTltdktHLzVW?= =?utf-8?B?QlJ0aUxOaCtCWXp6YWk4NFZPdE9LckhHRWZWY3ZaSkZKT2JuUnNWZkc4c0tG?= =?utf-8?B?Wlg5QlB1YzFoM2VxR01Qbno1QUZ2Sk54ZnBQK2xVQlVibHlZcXp4WW5VM1l2?= =?utf-8?B?ZmRKUUthK0l6Mm9oWk8rV0lGZE4vV3BVQWQ5bC9DRDZhNERaWlNsbndMV3Jt?= =?utf-8?B?aGl6aG4yeUFoZnZXQTR6QWZ1dHJnTE5RU2cwbWZBNG8vS0RRNVJ2Q0dqMld5?= =?utf-8?Q?z12MXNcWe7fe6x2WR6hKy0c4K?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(376014)(7416014)(1800799024)(36860700013)(921020);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Oct 2025 15:44:31.9543 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 64e49ee0-c531-4f14-ff8d-08de17020dc8 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF00004684.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4287 From: Patrisious Haddad Add other_eswitch support which allows flow tables creation above vports that reside on different esw managers. The new flag MLX5_FLOW_TABLE_OTHER_ESWITCH indicates if the esw_owner_vhca_id attribute is supported. Note that this is only supported if the Advanced-RDMA cap- rdma_transport_manager_other_eswitch is set. And it is the caller responsibility to check that. Signed-off-by: Patrisious Haddad Signed-off-by: Leon Romanovsky Signed-off-by: Edward Srouji --- drivers/net/ethernet/mellanox/mlx5/core/fs_cmd.c | 31 +++++++++++++++++++= ++++ drivers/net/ethernet/mellanox/mlx5/core/fs_core.c | 18 ++++++------- drivers/net/ethernet/mellanox/mlx5/core/fs_core.h | 1 + include/linux/mlx5/fs.h | 2 ++ 4 files changed, 42 insertions(+), 10 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/fs_cmd.c b/drivers/net= /ethernet/mellanox/mlx5/core/fs_cmd.c index 1af76da8b132..ced747bef641 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/fs_cmd.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/fs_cmd.c @@ -239,6 +239,10 @@ static int mlx5_cmd_update_root_ft(struct mlx5_flow_ro= ot_namespace *ns, MLX5_SET(set_flow_table_root_in, in, vport_number, ft->vport); MLX5_SET(set_flow_table_root_in, in, other_vport, !!(ft->flags & MLX5_FLOW_TABLE_OTHER_VPORT)); + MLX5_SET(set_flow_table_root_in, in, eswitch_owner_vhca_id, + ft->esw_owner_vhca_id); + MLX5_SET(set_flow_table_root_in, in, other_eswitch, + !!(ft->flags & MLX5_FLOW_TABLE_OTHER_ESWITCH)); =20 err =3D mlx5_cmd_exec_in(dev, set_flow_table_root, in); if (!err && @@ -302,6 +306,10 @@ static int mlx5_cmd_create_flow_table(struct mlx5_flow= _root_namespace *ns, MLX5_SET(create_flow_table_in, in, vport_number, ft->vport); MLX5_SET(create_flow_table_in, in, other_vport, !!(ft->flags & MLX5_FLOW_TABLE_OTHER_VPORT)); + MLX5_SET(create_flow_table_in, in, eswitch_owner_vhca_id, + ft->esw_owner_vhca_id); + MLX5_SET(create_flow_table_in, in, other_eswitch, + !!(ft->flags & MLX5_FLOW_TABLE_OTHER_ESWITCH)); =20 MLX5_SET(create_flow_table_in, in, flow_table_context.decap_en, en_decap); @@ -360,6 +368,10 @@ static int mlx5_cmd_destroy_flow_table(struct mlx5_flo= w_root_namespace *ns, MLX5_SET(destroy_flow_table_in, in, vport_number, ft->vport); MLX5_SET(destroy_flow_table_in, in, other_vport, !!(ft->flags & MLX5_FLOW_TABLE_OTHER_VPORT)); + MLX5_SET(destroy_flow_table_in, in, eswitch_owner_vhca_id, + ft->esw_owner_vhca_id); + MLX5_SET(destroy_flow_table_in, in, other_eswitch, + !!(ft->flags & MLX5_FLOW_TABLE_OTHER_ESWITCH)); =20 err =3D mlx5_cmd_exec_in(dev, destroy_flow_table, in); if (!err) @@ -394,6 +406,10 @@ static int mlx5_cmd_modify_flow_table(struct mlx5_flow= _root_namespace *ns, MLX5_SET(modify_flow_table_in, in, vport_number, ft->vport); MLX5_SET(modify_flow_table_in, in, other_vport, !!(ft->flags & MLX5_FLOW_TABLE_OTHER_VPORT)); + MLX5_SET(modify_flow_table_in, in, eswitch_owner_vhca_id, + ft->esw_owner_vhca_id); + MLX5_SET(modify_flow_table_in, in, other_eswitch, + !!(ft->flags & MLX5_FLOW_TABLE_OTHER_ESWITCH)); MLX5_SET(modify_flow_table_in, in, modify_field_select, MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID); if (next_ft) { @@ -429,6 +445,10 @@ static int mlx5_cmd_create_flow_group(struct mlx5_flow= _root_namespace *ns, MLX5_SET(create_flow_group_in, in, vport_number, ft->vport); MLX5_SET(create_flow_group_in, in, other_vport, !!(ft->flags & MLX5_FLOW_TABLE_OTHER_VPORT)); + MLX5_SET(create_flow_group_in, in, eswitch_owner_vhca_id, + ft->esw_owner_vhca_id); + MLX5_SET(create_flow_group_in, in, other_eswitch, + !!(ft->flags & MLX5_FLOW_TABLE_OTHER_ESWITCH)); err =3D mlx5_cmd_exec_inout(dev, create_flow_group, in, out); if (!err) fg->id =3D MLX5_GET(create_flow_group_out, out, @@ -451,6 +471,10 @@ static int mlx5_cmd_destroy_flow_group(struct mlx5_flo= w_root_namespace *ns, MLX5_SET(destroy_flow_group_in, in, vport_number, ft->vport); MLX5_SET(destroy_flow_group_in, in, other_vport, !!(ft->flags & MLX5_FLOW_TABLE_OTHER_VPORT)); + MLX5_SET(destroy_flow_group_in, in, eswitch_owner_vhca_id, + ft->esw_owner_vhca_id); + MLX5_SET(destroy_flow_group_in, in, other_eswitch, + !!(ft->flags & MLX5_FLOW_TABLE_OTHER_ESWITCH)); return mlx5_cmd_exec_in(dev, destroy_flow_group, in); } =20 @@ -559,6 +583,9 @@ static int mlx5_cmd_set_fte(struct mlx5_core_dev *dev, MLX5_SET(set_fte_in, in, vport_number, ft->vport); MLX5_SET(set_fte_in, in, other_vport, !!(ft->flags & MLX5_FLOW_TABLE_OTHER_VPORT)); + MLX5_SET(set_fte_in, in, eswitch_owner_vhca_id, ft->esw_owner_vhca_id); + MLX5_SET(set_fte_in, in, other_eswitch, + !!(ft->flags & MLX5_FLOW_TABLE_OTHER_ESWITCH)); =20 in_flow_context =3D MLX5_ADDR_OF(set_fte_in, in, flow_context); MLX5_SET(flow_context, in_flow_context, group_id, group_id); @@ -788,6 +815,10 @@ static int mlx5_cmd_delete_fte(struct mlx5_flow_root_n= amespace *ns, MLX5_SET(delete_fte_in, in, vport_number, ft->vport); MLX5_SET(delete_fte_in, in, other_vport, !!(ft->flags & MLX5_FLOW_TABLE_OTHER_VPORT)); + MLX5_SET(delete_fte_in, in, eswitch_owner_vhca_id, + ft->esw_owner_vhca_id); + MLX5_SET(delete_fte_in, in, other_eswitch, + !!(ft->flags & MLX5_FLOW_TABLE_OTHER_ESWITCH)); =20 return mlx5_cmd_exec_in(dev, delete_fte, in); } diff --git a/drivers/net/ethernet/mellanox/mlx5/core/fs_core.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/fs_core.c index 2db3ffb0a2b2..87e381c82ed3 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/fs_core.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/fs_core.c @@ -939,10 +939,10 @@ static struct mlx5_flow_group *alloc_insert_flow_grou= p(struct mlx5_flow_table *f return fg; } =20 -static struct mlx5_flow_table *alloc_flow_table(int level, u16 vport, - enum fs_flow_table_type table_type, - enum fs_flow_table_op_mod op_mod, - u32 flags) +static struct mlx5_flow_table * +alloc_flow_table(struct mlx5_flow_table_attr *ft_attr, u16 vport, + enum fs_flow_table_type table_type, + enum fs_flow_table_op_mod op_mod) { struct mlx5_flow_table *ft; int ret; @@ -957,12 +957,13 @@ static struct mlx5_flow_table *alloc_flow_table(int l= evel, u16 vport, return ERR_PTR(ret); } =20 - ft->level =3D level; + ft->level =3D ft_attr->level; ft->node.type =3D FS_TYPE_FLOW_TABLE; ft->op_mod =3D op_mod; ft->type =3D table_type; ft->vport =3D vport; - ft->flags =3D flags; + ft->esw_owner_vhca_id =3D ft_attr->esw_owner_vhca_id; + ft->flags =3D ft_attr->flags; INIT_LIST_HEAD(&ft->fwd_rules); mutex_init(&ft->lock); =20 @@ -1370,10 +1371,7 @@ static struct mlx5_flow_table *__mlx5_create_flow_ta= ble(struct mlx5_flow_namespa /* The level is related to the * priority level range. */ - ft =3D alloc_flow_table(ft_attr->level, - vport, - root->table_type, - op_mod, ft_attr->flags); + ft =3D alloc_flow_table(ft_attr, vport, root->table_type, op_mod); if (IS_ERR(ft)) { err =3D PTR_ERR(ft); goto unlock_root; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/fs_core.h b/drivers/ne= t/ethernet/mellanox/mlx5/core/fs_core.h index 8458ce203dac..0a9a5ef34c21 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/fs_core.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/fs_core.h @@ -205,6 +205,7 @@ struct mlx5_flow_table { }; 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Miller" , "Eric Dumazet" , Jakub Kicinski , Paolo Abeni , Jason Gunthorpe CC: , , , Patrisious Haddad , "Leon Romanovsky" , Edward Srouji Subject: [PATCH mlx5-next 3/7] net/mlx5: fs, set non default device per namespace Date: Wed, 29 Oct 2025 17:42:55 +0200 Message-ID: <20251029-support-other-eswitch-v1-3-98bb707b5d57@nvidia.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20251029-support-other-eswitch-v1-0-98bb707b5d57@nvidia.com> References: <20251029-support-other-eswitch-v1-0-98bb707b5d57@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF00004FC0:EE_|CH1PR12MB9645:EE_ X-MS-Office365-Filtering-Correlation-Id: 6aa0547d-317f-4386-05c3-08de170215d5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|36860700013|376014|7416014|921020; X-Microsoft-Antispam-Message-Info: =?utf-8?B?QXpkbUlJS1JhcWdlNWU1M0RYb0I5VXZkSzlhQjRDUTFkZDFUZUR0SFpBNVVT?= =?utf-8?B?WDU1VmpXNUVDV0pySW5CWkd4Tklpc2daYU9ZWTFTb20xVG5GZHpaRitCRmlZ?= =?utf-8?B?OCtUY0d3blgzL3hZaXVYR0NLV2ExM2gveFFseHlYTm1LbVpBMXZ1REhGaE9Z?= =?utf-8?B?OXVDaG5yamVyMzFSbXgvU2M1dWZsaktnMzlNSlp4NXhGN3NrUEMxVnJIQ2N6?= =?utf-8?B?RmhYeDZTSC8yYXJtSkk3Q3lXWlRkT0xBUGg3Z0twV0ZOdDg2NlJGWVVXZ3ht?= =?utf-8?B?WVdvS3hsOG9xb0pQc3prWnAvTUdTU3hCaW8rSGxmbkZoSkFQVUpSZ2ltSGZ1?= =?utf-8?B?N2JMZkNnVWd2R0tVdEdDbjg5czJEdVVxMkMrdUVzTjlxS0h6MWNQc0VIZEd3?= =?utf-8?B?RERVejRBQWVGdHNEeElsUGUvaGE3dEorOU5DUjQxY0pFOFB3Z2lnNDFtOVp6?= =?utf-8?B?UEVYb2tjbi9DR0x6c2Z3dWpHU01xMk5FbXJSd1E5bWNFbkFPQ0loZ2ZFSFdh?= =?utf-8?B?N1RnMTNZc2pTL3Vta2VQbGh2RWtxQUhxSXZkV2JHZmV5anhyekJiVXVWd1U2?= =?utf-8?B?TlY1ZzAvN1VRdzQweEVKa0VUL1hwNjZ0MEdHYnljSmIyRmpSTnpBT1IwclBQ?= =?utf-8?B?VkhVUXRaelcvdmZiWUY0eSszTHlpRm5Vcm5xZG9ZblR5SFFDYlJiOEhHZmJa?= =?utf-8?B?emRxOWxGOXk2eFNXQ01VY1ZyNElQTUF1WmMrQXV4azlRK3AwVkVWdVBxQUJq?= =?utf-8?B?YWVLZUsxaC9BNUlOVzVRVFlPSWxkNitIUDUrYVJqZXE5TUZTNXFVMlFLVUtp?= =?utf-8?B?MDZOTjdqVHA1NHJGMW1YYlpSN3hPcnAxZkQyUHJOSXBndy9TL0JGcGgycmxG?= =?utf-8?B?YWVoS1RxUHBWWWo2RkFXTWFnM2xtVVVYcjMzL1BzQ0QyeXdZVVkvelpQdlE1?= =?utf-8?B?SVpkNURmQTlRNGNnWTlyQWdMRE5LZG9Od2xaaEdVOTEwM3U4dWwwdkJaWlVN?= =?utf-8?B?NnRBeTBLTnNIZlkzMUhDSFR1SG91SE1kU1dOY3dPbGxsdFpEQ292U1hvTkt2?= =?utf-8?B?VWZ5UlJ6T0h5UTQ1L2Q2UHQzd2FGRElQL0ZheUhJeExpMytqcTVHTmMxNGM4?= =?utf-8?B?Q2VxaGc5TmFnLzVpZ0FWUUNpaTNPNUpuTkY2RHlldlcxeFducFN1WTJBZXBP?= =?utf-8?B?SXppZTg4Q1hoaENlQU96VDVNK2xVdUJ1OVQ0UlZLVFkxeWJQTjIwSVJaOTlo?= =?utf-8?B?RTI3U1ZsdDZXc3VKZXJqRVRTZFByVnZURlpWWkF6ZkdMemN4eXUxVW83MGox?= =?utf-8?B?VU1FQ251RnhFVG84eERxOStNU2pGK3lvWC85WFJYb0I2eGxITnVRT3BPNWty?= =?utf-8?B?djFzRTllajZvaE5sYUF6WFliOUhUM2tpR2hOVlFhQlN0cU12djl0OXcyMkFX?= =?utf-8?B?UXdYUzIyUmFwOEhmaHdjaU1BL0tTS3Z3L0hZUThKWlY2KytrNkdpVXZXUy8z?= =?utf-8?B?RzQ2S3ZRRFBrYlpPeW9pWjlUMlVCdWgrb3oyZlZPUWFaWVNjbkM0TzZUNEpq?= =?utf-8?B?S3MvSjlWMUhXQlRzS284dENCdk5oTWljcUVqdklDTEtvNTZSOXl2QUlkczJD?= =?utf-8?B?VXpGbWVTZit1QTdtd0VBRCtOdlZmNzZIRjBqTWhMcEZ0WHUrbG5pTE1zZ2h5?= =?utf-8?B?UHVuUm90cWxFMzRJT1dFckVnSHdTRW9ZeldGc0xIanVabDhKdFFMUkQramtI?= =?utf-8?B?eksrWGxLOHlQbTc2WUh6S0tUQlZ1ZmxiSEdMNjdRaG9SV0pLc1JkNmFVWUI1?= =?utf-8?B?WlpKS0ZUL0VGSHFaZmJCRjZVaWlxcDRpaWxuaGQ3M3NWeHNBZnF2MUxXeTZE?= =?utf-8?B?NTN1S1MwSXN3QTlWcUpKSlUwSUJLbGhXYXR2dkVIMURTRFVqeEVwTXRPMWVi?= =?utf-8?B?VzNoY2ExMTVGK3VIelJ6a1MyK2dPOVl0RXIvb25qcWh2QlBwcG82R2lGdjBy?= =?utf-8?B?NnI5dXNMUHVUNWpyMXpSLzhPR2dVVjVsZmJPMEdmTUg3WkVOenJsN0FMRktS?= =?utf-8?B?ZVBDRmw3cjIwNTdOdHJTalZOeHVuRmdOcWk2UEZkZi9xUWcyd2xzazJGdE1v?= =?utf-8?Q?RfDX08YPugGxYm8rdCDVqfdDG?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(36860700013)(376014)(7416014)(921020);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Oct 2025 15:44:45.4960 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6aa0547d-317f-4386-05c3-08de170215d5 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF00004FC0.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH1PR12MB9645 From: Patrisious Haddad Add mlx5_fs_set_root_dev() function which swaps the root namespace core device with another one for a given table_type. It is intended for usage only by RDMA_TRANSPORT tables in case of LAG configuration, to allow the creation of tables during LAG always through the LAG master device, which is valid since during LAG the master is allowed to manage the RDMA_TRANSPORT tables of its slaves. In addition move the table_type enum to global include to allow its use in a downstream patch in the RDMA driver. Signed-off-by: Patrisious Haddad Signed-off-by: Leon Romanovsky Signed-off-by: Edward Srouji --- drivers/net/ethernet/mellanox/mlx5/core/fs_core.c | 56 +++++++++++++++++++= ++++ drivers/net/ethernet/mellanox/mlx5/core/fs_core.h | 18 -------- include/linux/mlx5/fs.h | 22 +++++++++ 3 files changed, 78 insertions(+), 18 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/fs_core.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/fs_core.c index 87e381c82ed3..5b210c54a592 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/fs_core.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/fs_core.c @@ -3308,6 +3308,62 @@ init_rdma_transport_tx_root_ns_one(struct mlx5_flow_= steering *steering, return ret; } =20 +static bool mlx5_fs_ns_is_empty(struct mlx5_flow_namespace *ns) +{ + struct fs_prio *iter_prio; + + fs_for_each_prio(iter_prio, ns) { + if (iter_prio->num_ft) + return false; + } + + return true; +} + +int mlx5_fs_set_root_dev(struct mlx5_core_dev *dev, + struct mlx5_core_dev *new_dev, + enum fs_flow_table_type table_type) +{ + struct mlx5_flow_root_namespace **root; + int total_vports; + int i; + + switch (table_type) { + case FS_FT_RDMA_TRANSPORT_TX: + root =3D dev->priv.steering->rdma_transport_tx_root_ns; + total_vports =3D dev->priv.steering->rdma_transport_tx_vports; + break; + case FS_FT_RDMA_TRANSPORT_RX: + root =3D dev->priv.steering->rdma_transport_rx_root_ns; + total_vports =3D dev->priv.steering->rdma_transport_rx_vports; + break; + default: + WARN_ON_ONCE(true); + return -EINVAL; + } + + for (i =3D 0; i < total_vports; i++) { + mutex_lock(&root[i]->chain_lock); + if (!mlx5_fs_ns_is_empty(&root[i]->ns)) { + mutex_unlock(&root[i]->chain_lock); + goto err; + } + root[i]->dev =3D new_dev; + mutex_unlock(&root[i]->chain_lock); + } + return 0; +err: + while (i--) { + mutex_lock(&root[i]->chain_lock); + root[i]->dev =3D dev; + mutex_unlock(&root[i]->chain_lock); + } + /* If you hit this error try destroying all flow tables and try again */ + mlx5_core_err(dev, "Failed to set root device for RDMA TRANSPORT\n"); + return -EINVAL; +} +EXPORT_SYMBOL(mlx5_fs_set_root_dev); + static int init_rdma_transport_rx_root_ns(struct mlx5_flow_steering *steer= ing) { struct mlx5_core_dev *dev =3D steering->dev; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/fs_core.h b/drivers/ne= t/ethernet/mellanox/mlx5/core/fs_core.h index 0a9a5ef34c21..1c6591425260 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/fs_core.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/fs_core.h @@ -103,24 +103,6 @@ enum fs_node_type { FS_TYPE_FLOW_DEST }; =20 -enum fs_flow_table_type { - FS_FT_NIC_RX =3D 0x0, - FS_FT_NIC_TX =3D 0x1, - FS_FT_ESW_EGRESS_ACL =3D 0x2, - FS_FT_ESW_INGRESS_ACL =3D 0x3, - FS_FT_FDB =3D 0X4, - FS_FT_SNIFFER_RX =3D 0X5, - FS_FT_SNIFFER_TX =3D 0X6, - FS_FT_RDMA_RX =3D 0X7, - FS_FT_RDMA_TX =3D 0X8, - FS_FT_PORT_SEL =3D 0X9, - FS_FT_FDB_RX =3D 0xa, - FS_FT_FDB_TX =3D 0xb, - FS_FT_RDMA_TRANSPORT_RX =3D 0xd, - FS_FT_RDMA_TRANSPORT_TX =3D 0xe, - FS_FT_MAX_TYPE =3D FS_FT_RDMA_TRANSPORT_TX, -}; - enum fs_flow_table_op_mod { FS_FT_OP_MOD_NORMAL, FS_FT_OP_MOD_LAG_DEMUX, diff --git a/include/linux/mlx5/fs.h b/include/linux/mlx5/fs.h index 6325a7fa0df2..fe721557bd1d 100644 --- a/include/linux/mlx5/fs.h +++ b/include/linux/mlx5/fs.h @@ -128,6 +128,24 @@ enum { FDB_PER_VPORT, }; =20 +enum fs_flow_table_type { + FS_FT_NIC_RX =3D 0x0, + FS_FT_NIC_TX =3D 0x1, + FS_FT_ESW_EGRESS_ACL =3D 0x2, + FS_FT_ESW_INGRESS_ACL =3D 0x3, + FS_FT_FDB =3D 0X4, + FS_FT_SNIFFER_RX =3D 0X5, + FS_FT_SNIFFER_TX =3D 0X6, + FS_FT_RDMA_RX =3D 0X7, + FS_FT_RDMA_TX =3D 0X8, + FS_FT_PORT_SEL =3D 0X9, + FS_FT_FDB_RX =3D 0xa, + FS_FT_FDB_TX =3D 0xb, + FS_FT_RDMA_TRANSPORT_RX =3D 0xd, + FS_FT_RDMA_TRANSPORT_TX =3D 0xe, + FS_FT_MAX_TYPE =3D FS_FT_RDMA_TRANSPORT_TX, +}; + struct mlx5_pkt_reformat; struct mlx5_modify_hdr; struct mlx5_flow_definer; @@ -355,4 +373,8 @@ u32 mlx5_flow_table_id(struct mlx5_flow_table *ft); =20 struct mlx5_flow_root_namespace * mlx5_get_root_namespace(struct mlx5_core_dev *dev, enum mlx5_flow_namespac= e_type ns_type); + +int mlx5_fs_set_root_dev(struct mlx5_core_dev *dev, + struct mlx5_core_dev *new_dev, + enum fs_flow_table_type table_type); #endif --=20 2.47.1 From nobody Sun Feb 8 07:21:43 2026 Received: from PH7PR06CU001.outbound.protection.outlook.com (mail-westus3azon11010034.outbound.protection.outlook.com [52.101.201.34]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C44B934AAF0; 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Miller" , "Eric Dumazet" , Jakub Kicinski , Paolo Abeni , Jason Gunthorpe CC: , , , Patrisious Haddad , "Leon Romanovsky" , Edward Srouji Subject: [PATCH rdma-next 4/7] RDMA/mlx5: Change default device for LAG slaves in RDMA TRANSPORT namespaces Date: Wed, 29 Oct 2025 17:42:56 +0200 Message-ID: <20251029-support-other-eswitch-v1-4-98bb707b5d57@nvidia.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20251029-support-other-eswitch-v1-0-98bb707b5d57@nvidia.com> References: <20251029-support-other-eswitch-v1-0-98bb707b5d57@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF0000467F:EE_|BL1PR12MB5802:EE_ X-MS-Office365-Filtering-Correlation-Id: 3d8efe46-a8e1-4321-2feb-08de1702183f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|82310400026|7416014|376014|921020; X-Microsoft-Antispam-Message-Info: =?utf-8?B?T1RXRnNUSHJDMnd6ZG1tNWdhb1pXSkZSUWZZN1FTbFJqN1B0bFdsL0FIUHBG?= =?utf-8?B?eEhQNTh1aml2b0RJK2xzaDZocEhWS3lZU3U2QnVjSXJOOGs5K2FGaHlWeE9R?= =?utf-8?B?dTJRYm1HZHlvcy8vQkt2cU5LWmRQK0IrWmZxZ21lU0tTYnZUZDZTK2xuUjJt?= =?utf-8?B?MEhBK1VySm9WQ2R6TEQ2OVFyMkhPb2EvWldFU3hwRXd5R0NtM3VZZGwvTGFy?= =?utf-8?B?TTVlTkJKdnZ6ZTRjRmJyaGV3SGQ4Qzl6UFJCNkM0K3NOTVBBQ09LUHh3T0Yr?= =?utf-8?B?MnA5dnhPUzR0T0Z1OXpSQnlXUUM2SnBlcXhpRGtDa1ZEaThUYUlDR1ZTcHE4?= =?utf-8?B?TlYrNUFDcVI0ZVJETFVOaUZJSHFYK2xra0wwY3ZvRHVCZUxIdTY2bnpCWmEv?= =?utf-8?B?d0F6TWl5MzlJVkdSb1I0ODZwVTRsN3FEZS9vRDk2aGc3cTdhUnZ3dHRTbHNh?= =?utf-8?B?aEpsTFRzNWNSckYyc3hGS1hNVzd3cWtzcFRHYldYV0FMckp0ZGtFSzdWWngw?= =?utf-8?B?b2g2d2g5K1JHazE4Q2VpdDVPQmpVSjhPWnQwS2dJOHdmRFVvL0tYU2xCbHdh?= =?utf-8?B?WWY2OGJhVFcxMGFVbGczMFpScTVuWXlkRWNnSEN0UVpjY1RmTGt5SUJIUzRN?= =?utf-8?B?bWVaYzJwVUFxUk0zbVE1Q29RTlFoRFlJb3AxWmIrSGY0TDg2bWw4aEdCajNq?= =?utf-8?B?OWZYYVo0WlJDL3FQRmhRZHV0WHBuei9Zb3h5RWh0SmF2bzJWSXZXSy9HQnZa?= =?utf-8?B?ZzBqTnZ5SENSTGpWekduT0EwaGU4TVN0WVVwNCtqd3lPbUtncnVUTkFFVG4z?= =?utf-8?B?UmdMRVdSUlZYdEdjbHl0bTNTTThrV0dubFIra3FuWitTUWw3R2Y3MzlWbXBa?= =?utf-8?B?RWgrRmZ6VHZ0UXgvQ2V4eWl2MUhqTkZUM1JHWFluNlVsdGR2QzZIU01sc2xa?= =?utf-8?B?V0d2K2d4VFkreEp6Ym1rWG9XUHR0UGlhd25OWkpuVWVoa3lQZEVJVU01ZEVy?= =?utf-8?B?TmFYa3ZDQzFuQ2tCL2EwK3BRblhtSzRxUW9OSHFDbnJYSnRlbEJrVWhVanAv?= =?utf-8?B?aFYrYVhUc1BUVm1LRmdlTkx1RzlXL0NzbThKcEZPWlcxZ2kvNjl3L1FGZXox?= =?utf-8?B?UjcxdUZRY3BPRXR1cDFLVDIyUlVMSkdPODZrb0RMdTFKdDFWYmRVTGo2Umpy?= =?utf-8?B?bWMxc2ZTem5KVG9YYk53bDNiYVlZeWZob3JlUjVjRHVSRHlLVEVIL2RjMUc5?= =?utf-8?B?Q3p6b1c5QldzQTdsUEhXSmVLKzcrUUpjdXhsR2NnNkd6VFZNSFlYeFRnWDBU?= =?utf-8?B?MnVXbjhpZ1JoY2RUdmZPYWRlQ0pLbFp1SUNqWXFKKzJPRmZKT2tTZkZmbS8z?= =?utf-8?B?MTlyd21aZEpqWXZJZkRyc203ZDNzd2hNdUZrb2ExVHNURzFlOFFKUjlmSDg4?= =?utf-8?B?V0EydmlGQi9JUnVybmtlVzkzM3JxbUxYMVNDZGJ1bk8xMWZ6RGttQXFESmZO?= =?utf-8?B?SGM2NllEOTl6QjBkWFNnRDVUWFRMakw2ekdLL0lWY05rQU8vazdPeTcvV2xR?= =?utf-8?B?cExBL2NwbmpNMTVrcWtSWTRkNCtGZnRsZlNqM21GNzVpbFNLKy9YZm5YVUFD?= =?utf-8?B?MVRpMzRja3Q1bUhMdFZHWjUvVnp6cFNxcE55YktQLy9KWUc2cTZkUFhCOWJ2?= =?utf-8?B?NnJUVHNLNnBLclgrM2pUT2FYUFQ1L3VaM2NnYlhaMXN6N3EwckpaSEVWLzB2?= =?utf-8?B?UDVwTldvbXBacDJab0ozOGg0c1hiUWliODdhMHpOTFRCRlZSUlV6ak5WSkpU?= =?utf-8?B?VWl5SFE3cTZXclBSdFI3SzNIVVRwaEpQaFJoTUo0ZmVEd21DRzVaRkxFUnM0?= =?utf-8?B?S0dwOUFKZlVKM2dtNFR5TWQ5ZDBVQzhvRjZ1TGw4VlZuMzQ3WEZQbnYwVEpi?= =?utf-8?B?NmZCbGlaamlHektQUFFxaFN5ekhWQStKczQvWXY3OGZlWUNMaXVUMHpKY3Nm?= =?utf-8?B?UFVYVHRYMXdiekdjM1M5blhsZXd2cUhuVmltQTk5SGdMN1l5NERMbWR0UEpx?= =?utf-8?B?bjdxWjZhcDBuc0xudzEyVVRrSENZcDFGRUo2ejhzZTBiTzZObEI4bXBJMkJy?= =?utf-8?Q?c0h4WqX9Xyhu/LQDGUbMhj9ux?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(1800799024)(82310400026)(7416014)(376014)(921020);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Oct 2025 15:44:49.5587 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3d8efe46-a8e1-4321-2feb-08de1702183f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF0000467F.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5802 From: Patrisious Haddad In case of a LAG configuration change the root namespace core device for all of the LAG slaves to be the core device of the master device for RDMA_TRANSPORT namespaces, in order to ensure all tables are created through the master device. Once the LAG is disabled revert back to the native core device. Signed-off-by: Patrisious Haddad Signed-off-by: Leon Romanovsky Signed-off-by: Edward Srouji --- drivers/infiniband/hw/mlx5/ib_rep.c | 74 +++++++++++++++++++++++++++++++++= +++- 1 file changed, 72 insertions(+), 2 deletions(-) diff --git a/drivers/infiniband/hw/mlx5/ib_rep.c b/drivers/infiniband/hw/ml= x5/ib_rep.c index cc8859d3c2f5..bbecca405171 100644 --- a/drivers/infiniband/hw/mlx5/ib_rep.c +++ b/drivers/infiniband/hw/mlx5/ib_rep.c @@ -44,6 +44,63 @@ static void mlx5_ib_num_ports_update(struct mlx5_core_de= v *dev, u32 *num_ports) } } =20 +static int mlx5_ib_set_owner_transport(struct mlx5_core_dev *cur_owner, + struct mlx5_core_dev *new_owner) +{ + int ret; + + if (!MLX5_CAP_FLOWTABLE_RDMA_TRANSPORT_TX(cur_owner, ft_support) || + !MLX5_CAP_FLOWTABLE_RDMA_TRANSPORT_RX(cur_owner, ft_support)) + return 0; + + if (!MLX5_CAP_ADV_RDMA(new_owner, rdma_transport_manager) || + !MLX5_CAP_ADV_RDMA(new_owner, rdma_transport_manager_other_eswitch)) + return 0; + + ret =3D mlx5_fs_set_root_dev(cur_owner, new_owner, + FS_FT_RDMA_TRANSPORT_TX); + if (ret) + return ret; + + ret =3D mlx5_fs_set_root_dev(cur_owner, new_owner, + FS_FT_RDMA_TRANSPORT_RX); + if (ret) { + mlx5_fs_set_root_dev(cur_owner, cur_owner, + FS_FT_RDMA_TRANSPORT_TX); + return ret; + } + + return 0; +} + +static void mlx5_ib_release_transport(struct mlx5_core_dev *dev) +{ + struct mlx5_core_dev *peer_dev; + int i, ret; + + mlx5_lag_for_each_peer_mdev(dev, peer_dev, i) { + ret =3D mlx5_ib_set_owner_transport(peer_dev, peer_dev); + WARN_ON_ONCE(ret); + } +} + +static int mlx5_ib_take_transport(struct mlx5_core_dev *dev) +{ + struct mlx5_core_dev *peer_dev; + int ret; + int i; + + mlx5_lag_for_each_peer_mdev(dev, peer_dev, i) { + ret =3D mlx5_ib_set_owner_transport(peer_dev, dev); + if (ret) { + mlx5_ib_release_transport(dev); + return ret; + } + } + + return 0; +} + static int mlx5_ib_vport_rep_load(struct mlx5_core_dev *dev, struct mlx5_eswitch_rep = *rep) { @@ -88,10 +145,18 @@ mlx5_ib_vport_rep_load(struct mlx5_core_dev *dev, stru= ct mlx5_eswitch_rep *rep) else return mlx5_ib_set_vport_rep(lag_master, rep, vport_index); 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Miller" , "Eric Dumazet" , Jakub Kicinski , Paolo Abeni , Jason Gunthorpe CC: , , , Patrisious Haddad , "Leon Romanovsky" , Edward Srouji Subject: [PATCH rdma-next 5/7] RDMA/mlx5: Add other_eswitch support for devx destruction Date: Wed, 29 Oct 2025 17:42:57 +0200 Message-ID: <20251029-support-other-eswitch-v1-5-98bb707b5d57@nvidia.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20251029-support-other-eswitch-v1-0-98bb707b5d57@nvidia.com> References: <20251029-support-other-eswitch-v1-0-98bb707b5d57@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF00004FC0:EE_|CY5PR12MB9054:EE_ X-MS-Office365-Filtering-Correlation-Id: 4ee9b649-02d2-44ff-c720-08de17021d67 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|82310400026|376014|7416014|921020; X-Microsoft-Antispam-Message-Info: =?utf-8?B?amdKS3dzalFpVGxoR3FuYWZRNGRoNzdiUUp4R3F3QzhKZlhLRkRvbFI0Z1l3?= =?utf-8?B?QnB4VG9tYnNwUGo3KzI2SFZCbHR0bFZ2cmdTMVpFd1JMNDU2NjlWVkkwUTVW?= =?utf-8?B?OGVPNW1SNHlRVXMzOUZXc1IvNllNTUViVjhVbEZrZldQVHpNOXFpYmhkTVNj?= =?utf-8?B?NHh2bVJYZ1RYZkFPR3o3UTk5NTNlRDk3OGZPR2Vha0Zva25oaTRkOW9ROFFJ?= =?utf-8?B?OUFsbytGNzl0dUVsNzlraTdSRVZlYUd2TkdMMFAxd2xhWHlBSjlOQ1lrWFo0?= =?utf-8?B?WG1oZ0l1Um1kUWY3SE9sYmUveDBrN2xTL2E1T05GVUJlVm9JWElHZDRDQS9J?= =?utf-8?B?bnlDQ3hGczRVaHVsYUMrajA5MWFwb2F3VmhDUy9iazBVbFRjVzU2dFl2UFBz?= =?utf-8?B?cWdjQWliajhxYVR2eURsQnA2bGh2SE1kZjI2NjdOS0VyR1RRdEZ5LzU3TWZi?= =?utf-8?B?WUxxMEJCbnZLeUlLV2RVRGVxSlBSVzB4QlhTT2tHT3REMk1xS0FiT3I1NnpE?= =?utf-8?B?bUVXblp1UDRoK2FWTks3QlFaZzZNelErcytSMWE3S01nRUZXdDlSRzVQejQy?= =?utf-8?B?RXNCTG9QNXpSbkc1RU84M3ZUWmxXVEJUaHJQUitTWHJDYmNLNkF3REh2UzRv?= =?utf-8?B?ZEZVWjA2ZEFsQ2crNGtuL0FBaHZ2UGZ3TFJwQnRJQVlkYlNqUWpDRktyRmVN?= =?utf-8?B?aVhlM0l3UWVwQThnZDJ4VGlHTldnRTVscjBEbWRueFBFTTlOMlp4QnhPRHhU?= =?utf-8?B?VXdhK3IvdkNGVzE1a1lkT1ZaVDVOTjNvRU9hQjRGNEl5MjE1cmVhNExBMDhU?= =?utf-8?B?VlluMVhJMkl0RmhaaDVNM3pWUmtJYVlBVVB4WnRZajQ2cDdESHpkYm16aTFp?= =?utf-8?B?b1I4N0ZFKzI2bllUTWFzaWZnN1p5UUxwWU5STzM2Slpoa0xEYWRNWWdUZ3Jl?= =?utf-8?B?c3JCTGs3Y3psSWR4VlFrS3ZZZUZFYllBTnlvYW9SdjZSU09mWkRNWklzYnBK?= =?utf-8?B?OGFwRGNKUVdKSkNKRExCTGJmNE1YalppM29ETStTeWdPekgyZ2FPVm9kRXhC?= =?utf-8?B?SUNpZjAzbEp2a0FTZ2VSNHR6TlFVVzhMZGQ3anRXVDBDamFWTURZTWJiaC9O?= =?utf-8?B?MnNBSjBLM3pxd1lVb3lBM283Qm5UcGd1ZWliYlpCZWhLeW5mQ1Y0Um1pU29V?= =?utf-8?B?K2lPMzdzMy9QeFFiVDhmMDlLUDNIRmorN0xhRlQ2cmRQVEM2Vk9IYXFPUUFY?= =?utf-8?B?U0ZlZWs0dG04VjRTWUpMQ2ZEWWNxMFdDOFFHTG1FK3lDamhnd2Qza3dKN1ZS?= =?utf-8?B?UWdhaEF3U295a284SWJTbENSdVZBY3AzcWVNQmducU9LckdPYVVMZm9WcG13?= =?utf-8?B?SzNQVzlTUTI2alNYU3NvY1d3ZkNxckY5cFluODAvOXZMZ2lvYkpDTnE4bGZj?= =?utf-8?B?YmRwWHVmK1M2ck1KdE9vU245VmNvaEpzRDZtK0xPOS8yMGlpbnlEV2FUbGFz?= =?utf-8?B?WlZCL0k0dlFQUy9NdDNiN0REUWRVUFFZajBKWFhzNTlkWW9NUUtLd0lFcmR2?= =?utf-8?B?MGZ3S01YWUdYU0pvV0xmcmhxMTdpMDJZWVowL1RIYm5MaElqbGo3K1NuN2xm?= =?utf-8?B?blJBeDdSNjNqdmlUZFc0N3A3MklBYXFIaVhFNmJmb0pnMmRvN1lMaW04MXpM?= =?utf-8?B?RVJTNitac0xyTjJWeDN3U1duSW5jb291NS9CU0FDeTYvRTNxak44a3JzQkhN?= =?utf-8?B?TXBXRWNhalRINzhOdi9uY0grZ0p4Wmd1M2o3dGEzMUE3bWxDYTFFSmxZRkdt?= =?utf-8?B?M3I2SDIzaHhuUnZXWGttdmtxWlJXMURxcXhnTTdUaWtJQ0hDYkxHWXdHR0VI?= =?utf-8?B?QXNFaHFMYlR0UEhIU3VIcmdhTnJYVHRDUXZRcHR0MjExRTVwWHJyb0xIUHpu?= =?utf-8?B?NU5LRjg3RjVaeGJWVm8yT3U0UlJHR0tvUHRWMEw4Q2dGTGFwaVZtbi9sRUJS?= =?utf-8?B?OFluZzdQQjdkSkIxUHdtb3dKVGUxMnhLcUdWYkJOS0FXRi94ZjROalpKR2FW?= =?utf-8?B?UXdycko4aWhQcTd4czMyTkhDVnc0LzYyeXA0dXA5T1BDM3ordFhJUS9KVTlX?= =?utf-8?Q?1dqQdEUV/V3tmJBJBU4C8Hiyk?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(36860700013)(82310400026)(376014)(7416014)(921020);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Oct 2025 15:44:58.2094 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4ee9b649-02d2-44ff-c720-08de17021d67 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF00004FC0.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB9054 From: Patrisious Haddad When building a devx object destruction command for steering objects add consideration for other_eswitch argument to allow proper destruction for objects that were created with it. Signed-off-by: Patrisious Haddad Reviewed-by: Mark Bloch Signed-off-by: Leon Romanovsky Signed-off-by: Edward Srouji --- drivers/infiniband/hw/mlx5/devx.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/infiniband/hw/mlx5/devx.c b/drivers/infiniband/hw/mlx5= /devx.c index 8b506417ad2f..d31d7f3005c6 100644 --- a/drivers/infiniband/hw/mlx5/devx.c +++ b/drivers/infiniband/hw/mlx5/devx.c @@ -1225,6 +1225,11 @@ static void devx_obj_build_destroy_cmd(void *in, voi= d *out, void *din, MLX5_GET(create_flow_table_in, in, other_vport)); MLX5_SET(destroy_flow_table_in, din, vport_number, MLX5_GET(create_flow_table_in, in, vport_number)); + MLX5_SET(destroy_flow_table_in, din, other_eswitch, + MLX5_GET(create_flow_table_in, in, other_eswitch)); + MLX5_SET(destroy_flow_table_in, din, eswitch_owner_vhca_id, + MLX5_GET(create_flow_table_in, in, + eswitch_owner_vhca_id)); MLX5_SET(destroy_flow_table_in, din, table_type, MLX5_GET(create_flow_table_in, in, table_type)); MLX5_SET(destroy_flow_table_in, din, table_id, *obj_id); @@ -1237,6 +1242,11 @@ static void devx_obj_build_destroy_cmd(void *in, voi= d *out, void *din, MLX5_GET(create_flow_group_in, in, other_vport)); MLX5_SET(destroy_flow_group_in, din, vport_number, MLX5_GET(create_flow_group_in, in, vport_number)); + MLX5_SET(destroy_flow_group_in, din, other_eswitch, + MLX5_GET(create_flow_group_in, in, other_eswitch)); + MLX5_SET(destroy_flow_group_in, din, eswitch_owner_vhca_id, + MLX5_GET(create_flow_group_in, in, + eswitch_owner_vhca_id)); MLX5_SET(destroy_flow_group_in, din, table_type, MLX5_GET(create_flow_group_in, in, table_type)); MLX5_SET(destroy_flow_group_in, din, table_id, @@ -1251,6 +1261,10 @@ static void devx_obj_build_destroy_cmd(void *in, voi= d *out, void *din, MLX5_GET(set_fte_in, in, other_vport)); MLX5_SET(delete_fte_in, din, vport_number, MLX5_GET(set_fte_in, in, vport_number)); + MLX5_SET(delete_fte_in, din, other_eswitch, + MLX5_GET(set_fte_in, in, other_eswitch)); + MLX5_SET(delete_fte_in, din, eswitch_owner_vhca_id, + MLX5_GET(set_fte_in, in, eswitch_owner_vhca_id)); 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Miller" , "Eric Dumazet" , Jakub Kicinski , Paolo Abeni , Jason Gunthorpe CC: , , , Patrisious Haddad , "Leon Romanovsky" , Edward Srouji Subject: [PATCH rdma-next 6/7] RDMA/mlx5: Refactor _get_prio() function Date: Wed, 29 Oct 2025 17:42:58 +0200 Message-ID: <20251029-support-other-eswitch-v1-6-98bb707b5d57@nvidia.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20251029-support-other-eswitch-v1-0-98bb707b5d57@nvidia.com> References: <20251029-support-other-eswitch-v1-0-98bb707b5d57@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF00004680:EE_|IA1PR12MB8359:EE_ X-MS-Office365-Filtering-Correlation-Id: 1b5f8fac-953d-4e98-7e33-08de17021eb5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|7416014|376014|1800799024|36860700013|921020; X-Microsoft-Antispam-Message-Info: =?utf-8?B?U0VLczRYK3p5bjVLOXdxL09hc2FVdWNaYm8zWU9xdUZ5MmNqRHVmZXpOam0x?= =?utf-8?B?aGp6U0cwa3VOZXNhSFVkSDdpblAxTHB5T0wrQ3pCR1B6NHRtZTNIYWxTQWZy?= =?utf-8?B?R1d6SWwzdnkyVEI0MXpzZFFvSFJmVFQ5WWhiQkd6YXBybHZWRFJQNGlrb2M1?= =?utf-8?B?Qklpa0pnODZkcmd2OEV1dE1VaU9Za0p4RDVrSzQ0amlaZE9JR0ZYU2xmZTlL?= =?utf-8?B?dzQ3NFNPU3pFR0NDeWcvYTI3M3dzc3h2bXRzV1hPRldiYitxeWJZQ0ZOeWFD?= =?utf-8?B?OWhmWnFPaTRSQ1VFQVBaMlBWRHJwTkR5NW5vdmprN0pRcllUSzNXb2hYZDVx?= =?utf-8?B?a2h2dGhYS0ZoL2Ftb3FZYkdjV3BDSzM5dFF1cnQyQXJvZHVvSEhCZGZ0RCtv?= =?utf-8?B?Y2NVZ3N3K2s3RzJ2K1lMTnlXRE9BR3g4UTQ2OHlJeXlhVkJpMGhvS3BkTEhP?= =?utf-8?B?eVlmYzIvSE40L0kxVHBSVEdmZzRSSzRlRnp2QW5hTllSWCtFVGduaytOZ2RB?= =?utf-8?B?cTBLdGpPeFpwQVhGdFhCSmhwdkpsTVVORTd3MTJkNm82R1BzVDhGV3JPUWd3?= =?utf-8?B?MExaaWl0VHpQVEkycjRUUS9jeHI1YTl0OXhlbUtFVVpudE1pOFBYUlZ2WVBX?= =?utf-8?B?SjgxcnFuK1BBaWZUZi9EbWZ3ZmQvMS9QU2dydlFKWGRJYVdsK2YyZkUvbncz?= =?utf-8?B?N2ZheXNndkNtcG4xRjNCSEdJR0VDUlp4dkU5bFVid2FBOW50OTVLTlp0amZs?= =?utf-8?B?QU1VT054R1I3Wmhnb2pIN1VEdmdpeDBZUkRQeDgrVlFCNVhrRUJzZ1NwaWNF?= =?utf-8?B?bk9Ta2QrN2RCdXhiWEhJU2pha0JhU1J5ejF3THlWK0phNXJuZTJIWkNaOXJM?= =?utf-8?B?a1dPU05oSHYyVEorMEs5aitadkdwdmpEVVc0SitOTElxUDNGZGo3K3dUbWFu?= =?utf-8?B?dXovQ2JjNWN5azlXOE8zaTdrMml5WThBblVJUmdwenBTQmN5eWZyRzBtWFp1?= =?utf-8?B?M0NFOGNidGdJN2UwNkJrQlc4S2pON2tOT3VCeklkMDhBTHg4blNQUmZBOGUr?= =?utf-8?B?Zml4VmZtSGtURm53UkZISHU4b0hNYW93S0QzTENpVWFMQWtTbUpNdlVpSlJH?= =?utf-8?B?UUxkNzVNTzVDeHYvNE9Xb0JFRCtrR0MzNlNPVXZTTWZKbVVDQTE0VFhZUDhU?= =?utf-8?B?SEpFRkUvYXhsa0FVVGV4bmxib1FtK2ZreGVtSWxyRm1wUGZFUkdLTTFjbGJy?= =?utf-8?B?MjJocWFRUnNTYlhRTG90OHpsWFZxZUN1NmtpeE5EYmVqcUY5VGRrRHo3aEc0?= =?utf-8?B?TnZzRC9SNlZhMjdQcXpNSHBLUEJTNzdsWXF5cEF2QTc4d0l4cU5TZCtTZGd3?= =?utf-8?B?LzBya3Fxa1NuZmhwSFdITyswK2MwbUFCWUxOQlRuK2ZSWVpkSk1LS01vZHFt?= =?utf-8?B?cE1KRFQ1bzl5MmxKbnRCM3J1SzAwU1dLL2lDc0xRMWpoY2Jlekd0Z0VhdUpH?= =?utf-8?B?R2dvY0FuNVg3NEx1cWZMaXFSeVhHdFQybzV6MlM1blVEeTNiQVFtaXlld3hy?= =?utf-8?B?MmRnRHFpM25td3NIMjFoM0VZWjJjZTJzMk1DaGVTSm5VN0ZubllSQ01ZR0ov?= =?utf-8?B?dUlHVmRiNGZ2bktBaFJQQnEzdVZTbGJucDAzRlVOK295V2h4S0Z5cjN2M3ps?= =?utf-8?B?OWxrMGhtS0lBa2Jrd0dPRUVXYjdlWnJHTlZJNzc2L3dSMXJGQ2d4NE5YQmVy?= =?utf-8?B?anE1M1ljb2FxNU83R2t0TEhENHpUSmlQKzFuaTFROXNJb2ZPRWlhTklqK04y?= =?utf-8?B?V3V2b0VaWk5zWlpnNWdid3NiUUc3dW8vaEhPZ3JpRzNyR1ZwQlR5VVN0RnA4?= =?utf-8?B?dy9vdFl4NHM4S0Q2VUlQWGYzUUxOdGdZZFdJWktNb0pkenhUbzFmUHNYZXZR?= =?utf-8?B?ZUpDSUwrVFo4VEFhYzFlbFRBeVNOZ2QvRjFOYndPalpEUkhiczV5aHpFNEVV?= =?utf-8?B?dFVZWkQ5YXpoazd0ZVhDWjhJYXdXcU90MmhGaUVLWHBETGhIZDN5ZGJZU0lC?= =?utf-8?B?Q0E1VWpZRWFHMGZZaHo0YmZuYmc3V2hwaTNPemFLM0xoZmU3ZGpKYS9WQ0NK?= =?utf-8?Q?98iA=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(7416014)(376014)(1800799024)(36860700013)(921020);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Oct 2025 15:45:00.3976 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1b5f8fac-953d-4e98-7e33-08de17021eb5 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF00004680.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB8359 From: Patrisious Haddad Refactor the _get_prio() function to remove redundant arguments by reusing the existing flow table attributes struct instead of passing attributes separately. This improves code clarity and maintainability. In addition allows downstream patch to add new parameter without needing to change __get_prio() arguments. Signed-off-by: Patrisious Haddad Signed-off-by: Leon Romanovsky Signed-off-by: Edward Srouji --- drivers/infiniband/hw/mlx5/fs.c | 49 +++++++++++++++++++++++--------------= ---- 1 file changed, 28 insertions(+), 21 deletions(-) diff --git a/drivers/infiniband/hw/mlx5/fs.c b/drivers/infiniband/hw/mlx5/f= s.c index b0f7663c24c1..c8a25370aa79 100644 --- a/drivers/infiniband/hw/mlx5/fs.c +++ b/drivers/infiniband/hw/mlx5/fs.c @@ -691,22 +691,13 @@ static bool __maybe_unused mlx5_ib_shared_ft_allowed(= struct ib_device *device) return MLX5_CAP_GEN(dev->mdev, shared_object_to_user_object_allowed); } =20 -static struct mlx5_ib_flow_prio *_get_prio(struct mlx5_ib_dev *dev, - struct mlx5_flow_namespace *ns, +static struct mlx5_ib_flow_prio *_get_prio(struct mlx5_flow_namespace *ns, struct mlx5_ib_flow_prio *prio, - int priority, - int num_entries, int num_groups, - u32 flags, u16 vport) + struct mlx5_flow_table_attr *ft_attr) { - struct mlx5_flow_table_attr ft_attr =3D {}; struct mlx5_flow_table *ft; =20 - ft_attr.prio =3D priority; - ft_attr.max_fte =3D num_entries; - ft_attr.flags =3D flags; - ft_attr.vport =3D vport; - ft_attr.autogroup.max_num_groups =3D num_groups; - ft =3D mlx5_create_auto_grouped_flow_table(ns, &ft_attr); + ft =3D mlx5_create_auto_grouped_flow_table(ns, ft_attr); if (IS_ERR(ft)) return ERR_CAST(ft); =20 @@ -720,6 +711,7 @@ static struct mlx5_ib_flow_prio *get_flow_table(struct = mlx5_ib_dev *dev, enum flow_table_type ft_type) { bool dont_trap =3D flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP; + struct mlx5_flow_table_attr ft_attr =3D {}; struct mlx5_flow_namespace *ns =3D NULL; enum mlx5_flow_namespace_type fn_type; struct mlx5_ib_flow_prio *prio; @@ -797,11 +789,14 @@ static struct mlx5_ib_flow_prio *get_flow_table(struc= t mlx5_ib_dev *dev, max_table_size =3D min_t(int, num_entries, max_table_size); =20 ft =3D prio->flow_table; - if (!ft) - return _get_prio(dev, ns, prio, priority, max_table_size, - num_groups, flags, 0); + if (ft) + return prio; =20 - return prio; + ft_attr.prio =3D priority; + ft_attr.max_fte =3D max_table_size; + ft_attr.flags =3D flags; + ft_attr.autogroup.max_num_groups =3D num_groups; + return _get_prio(ns, prio, &ft_attr); } =20 enum { @@ -950,6 +945,7 @@ static int get_per_qp_prio(struct mlx5_ib_dev *dev, enum mlx5_ib_optional_counter_type type) { enum mlx5_ib_optional_counter_type per_qp_type; + struct mlx5_flow_table_attr ft_attr =3D {}; enum mlx5_flow_namespace_type fn_type; struct mlx5_flow_namespace *ns; struct mlx5_ib_flow_prio *prio; @@ -1003,7 +999,10 @@ static int get_per_qp_prio(struct mlx5_ib_dev *dev, if (prio->flow_table) return 0; =20 - prio =3D _get_prio(dev, ns, prio, priority, MLX5_FS_MAX_POOL_SIZE, 1, 0, = 0); + ft_attr.prio =3D priority; + ft_attr.max_fte =3D MLX5_FS_MAX_POOL_SIZE; + ft_attr.autogroup.max_num_groups =3D 1; + prio =3D _get_prio(ns, prio, &ft_attr); if (IS_ERR(prio)) return PTR_ERR(prio); =20 @@ -1223,6 +1222,7 @@ int mlx5_ib_fs_add_op_fc(struct mlx5_ib_dev *dev, u32= port_num, struct mlx5_ib_op_fc *opfc, enum mlx5_ib_optional_counter_type type) { + struct mlx5_flow_table_attr ft_attr =3D {}; enum mlx5_flow_namespace_type fn_type; int priority, i, err, spec_num; struct mlx5_flow_act flow_act =3D {}; @@ -1304,8 +1304,10 @@ int mlx5_ib_fs_add_op_fc(struct mlx5_ib_dev *dev, u3= 2 port_num, if (err) goto free; =20 - prio =3D _get_prio(dev, ns, prio, priority, - dev->num_ports * MAX_OPFC_RULES, 1, 0, 0); + ft_attr.prio =3D priority; + ft_attr.max_fte =3D dev->num_ports * MAX_OPFC_RULES; + ft_attr.autogroup.max_num_groups =3D 1; + prio =3D _get_prio(ns, prio, &ft_attr); if (IS_ERR(prio)) { err =3D PTR_ERR(prio); goto put_prio; @@ -1903,6 +1905,7 @@ _get_flow_table(struct mlx5_ib_dev *dev, u16 user_pri= ority, bool mcast, u32 ib_port) { struct mlx5_core_dev *ft_mdev =3D dev->mdev; + struct mlx5_flow_table_attr ft_attr =3D {}; struct mlx5_flow_namespace *ns =3D NULL; struct mlx5_ib_flow_prio *prio =3D NULL; int max_table_size =3D 0; @@ -2026,8 +2029,12 @@ _get_flow_table(struct mlx5_ib_dev *dev, u16 user_pr= iority, if (prio->flow_table) return prio; =20 - return _get_prio(dev, ns, prio, priority, max_table_size, - MLX5_FS_MAX_TYPES, flags, vport); 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Miller" , "Eric Dumazet" , Jakub Kicinski , Paolo Abeni , Jason Gunthorpe CC: , , , Patrisious Haddad , "Leon Romanovsky" , Edward Srouji Subject: [PATCH rdma-next 7/7] RDMA/mlx5: Add other eswitch support to userspace tables Date: Wed, 29 Oct 2025 17:42:59 +0200 Message-ID: <20251029-support-other-eswitch-v1-7-98bb707b5d57@nvidia.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20251029-support-other-eswitch-v1-0-98bb707b5d57@nvidia.com> References: <20251029-support-other-eswitch-v1-0-98bb707b5d57@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF0000467F:EE_|CY3PR12MB9701:EE_ X-MS-Office365-Filtering-Correlation-Id: 92fcb044-7129-4b69-9c48-08de17022169 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|82310400026|1800799024|36860700013|921020; X-Microsoft-Antispam-Message-Info: =?utf-8?B?ME9uRVpLNmdISGZ0d0hGTGt5MFVLazJ6MUQ1ZHdUdS9aaVpTRXNqM2FTK09N?= =?utf-8?B?SjI2QjN6SSt3emY0cDJydFl3N2dyWE1XZXZScVNzMTFEK0JnMXc3K0trZDVU?= =?utf-8?B?VTVJNVVTTFlFSDFlVE4zUTVRSnBtMHB0MjRDSk1TUkwvNngzOE1rTE9KVVNs?= =?utf-8?B?MEIvcUFOVWZvanJ1eldjRVh0L1lUR2dmZ0RmNnF5Vm1PVkVqeG1PYnBsa1Nw?= =?utf-8?B?QS9DQzM5OTNZKzZoRWxmQTdsdUM4Uy9BRTdwU0EwTWQ0S3lDZnZzK3NnS05T?= =?utf-8?B?Rk1vaWxJbUVDcmQ3a0ZUaEU2V1lNTk1hQTl0WGFHS3ZHZmlPekEyMUxCWmhJ?= =?utf-8?B?MXBEeUFMQTBmcU5rRDhvaFZKZEZ5QVdXK2FoeS9xN3NBMHgvVGozaHQrODRR?= =?utf-8?B?ZkpzeGJPWlplWS9XMWxCOEEreDBvcG1DYU4vanBnVVZDODNUL05ZaEs5RHVw?= =?utf-8?B?UlZLMi9xQzBpQ0g4WVRBcVJVanBpT25ISkRNMUM1RDFRMGZ0cHdxNlZGMTdl?= =?utf-8?B?WE5wM1pzRWJhcEpoL21yOXkrNnJKUVI4SHFUNGxIK1MyWVo4K2lhVEFTZGRH?= =?utf-8?B?akl4OFBVbVBocTBqWThRQk10ZEtHQU5aUVFnZHpPQlh6UzJHck1OOTNOZXlJ?= =?utf-8?B?QW5XT1k2ZURjTHdFOVhWbUN6bm15Smc2YndldVpWK3lxWGUvU1l3bDBobloy?= =?utf-8?B?M0ZvcEdzMCswR1FQazZKNkFNSnllS2JqS1JMRHBZVVEvblVzVVB0NnlrNkZ0?= =?utf-8?B?NjY4MmRlL0s5Z3RWOU54TzRockhBcHRNaHVuZ1pETnZsWXdva0lSWnE5VzVJ?= =?utf-8?B?bG1WRm9MVWsxWFJuTzBOMVl1VlNKKy9hck5aeXpEVGZGRlhZNU44N3FvSFRy?= =?utf-8?B?QlFzZjhUMlBKN1lsNnE4a2NuYy9MV3BpTlZ1cmxyR2NJdDFDUlhySGVVMHlp?= =?utf-8?B?eTlHMTNVRnRPb3Z2bmJZaGhlUGUvYldCMmNzY09hSjZmdWp3NWZwOEkyWXJw?= =?utf-8?B?ZXdVbGg4alVVcE1GTGsxSTVLVndMYjRXd0l6L0k3RVJSU2FSQml1L2lnaUNJ?= =?utf-8?B?Z09MdWRkbXBPY1pxNE0wMSt0SWVhQmZDajY1UFl0bmVPVjF4TWNJYVBYdUVE?= =?utf-8?B?Nzh6d3lRNWdKaEJhVVd3SmRUM2VaSEhkM3d4WmtLdFRPdElFV0xNZkNDS2dX?= =?utf-8?B?OEUvQ2M2VXJldDk2NisrL3dPS2RoTk5BQkVQNFFNL003WEVkR1Q3TEsybU9Q?= =?utf-8?B?TUN6VncxTG1aQm1zdFZ5VHBuaUxyNjU2cFcxZlRidHFhNFRRZFM3M3RVR0FE?= =?utf-8?B?UXl4Z09Kekp2OUVuelZTaU94RFVtblFnZkNobkJrTW1VUDVjY3lMMmVRRTUr?= =?utf-8?B?bXYxbjJIMnZFaTJuaFBDd1lSUnl5d2xmTlVudTJ3bzdYRVpScjBrWlJTeC9H?= =?utf-8?B?bW8wdW80enhqUmlqOVJEek80L0xuR0cxdmlTenZocEo5bDBQNlV2Kzc4VkJz?= =?utf-8?B?TXRYQ0kvV1Vxajh1SExoTUxqSnBWbmY0bkJqbHgvUldWYjVGYktIY1NncytC?= =?utf-8?B?YUlZaERTS2xMbkt6WXBnTVNnT1ZjKy9OM2l1MFYzTmpmVGQwd1pWQjRYOFN2?= =?utf-8?B?OUR5SzNMZG5sclVOazFYMTZJRHRkakJNaVgwRyt4TmlxeU5abU5SV0xOeWhv?= =?utf-8?B?MUxUUERnK0VsWjJkWWV1RHVydk9wYlI3UjRuTXhQcExVczhieGJ3OGEyS1lt?= =?utf-8?B?QVN1c1JQTjkwc0pibUNQZUZKekxYajBSYURGenBHTlRkYi9tTnJzeCs3SGhR?= =?utf-8?B?RllvZkkzZVpyMGdNWGJESkdYbWcySkRqYlZwdHkvOFFtQm9rd0RGUTkrTzA3?= =?utf-8?B?NkJJYVRuOE9wRWNhZzdqbmpkQ2QrM2VrZW82L05nMHI3RFBhYTI2ZDM3aUgx?= =?utf-8?B?TjhmY003MkRLTVVnMzJQc21EUnRTTFZHSWNoT01NSkpaWEN2Sno5Q1A4T2RE?= =?utf-8?B?TTZIeHRUbWhPMG9rZGhJb0hsem5TWEtZZlZGazJlSlN6eU5HYnVOT2xVTUp6?= =?utf-8?B?ZXVpNHhuNlJOSEYxQ3NqazVhQkZ6ZjQvZ2paTzU0YnVRelhqd2NSbytxcFMv?= =?utf-8?Q?DBi2Do+9uqo33/sELDyZq1TxI?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(7416014)(376014)(82310400026)(1800799024)(36860700013)(921020);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Oct 2025 15:45:04.9353 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 92fcb044-7129-4b69-9c48-08de17022169 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF0000467F.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY3PR12MB9701 From: Patrisious Haddad Allows the creation of RDMA TRANSPORT tables over VFs/SFs that belong to another eswitch manager. Which is only possible for PFs that were connected via a create_lag PRM command. Signed-off-by: Patrisious Haddad Signed-off-by: Leon Romanovsky Signed-off-by: Edward Srouji --- drivers/infiniband/hw/mlx5/fs.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/drivers/infiniband/hw/mlx5/fs.c b/drivers/infiniband/hw/mlx5/f= s.c index c8a25370aa79..d17823ce7f38 100644 --- a/drivers/infiniband/hw/mlx5/fs.c +++ b/drivers/infiniband/hw/mlx5/fs.c @@ -1874,7 +1874,7 @@ static int mlx5_ib_fill_transport_ns_info(struct mlx5= _ib_dev *dev, u32 *flags, u16 *vport_idx, u16 *vport, struct mlx5_core_dev **ft_mdev, - u32 ib_port) + u32 ib_port, u16 *esw_owner_vhca_id) { struct mlx5_core_dev *esw_mdev; =20 @@ -1888,8 +1888,13 @@ static int mlx5_ib_fill_transport_ns_info(struct mlx= 5_ib_dev *dev, return -EINVAL; =20 esw_mdev =3D mlx5_eswitch_get_core_dev(dev->port[ib_port - 1].rep->esw); - if (esw_mdev !=3D dev->mdev) - return -EOPNOTSUPP; + if (esw_mdev !=3D dev->mdev) { + if (!MLX5_CAP_ADV_RDMA(dev->mdev, + rdma_transport_manager_other_eswitch)) + return -EOPNOTSUPP; + *flags |=3D MLX5_FLOW_TABLE_OTHER_ESWITCH; + *esw_owner_vhca_id =3D MLX5_CAP_GEN(esw_mdev, vhca_id); + } =20 *flags |=3D MLX5_FLOW_TABLE_OTHER_VPORT; *ft_mdev =3D esw_mdev; @@ -1908,6 +1913,7 @@ _get_flow_table(struct mlx5_ib_dev *dev, u16 user_pri= ority, struct mlx5_flow_table_attr ft_attr =3D {}; struct mlx5_flow_namespace *ns =3D NULL; struct mlx5_ib_flow_prio *prio =3D NULL; + u16 esw_owner_vhca_id =3D 0; int max_table_size =3D 0; u16 vport_idx =3D 0; bool esw_encap; @@ -1969,7 +1975,8 @@ _get_flow_table(struct mlx5_ib_dev *dev, u16 user_pri= ority, return ERR_PTR(-EINVAL); ret =3D mlx5_ib_fill_transport_ns_info(dev, ns_type, &flags, &vport_idx, &vport, - &ft_mdev, ib_port); + &ft_mdev, ib_port, + &esw_owner_vhca_id); if (ret) return ERR_PTR(ret); =20 @@ -2033,6 +2040,7 @@ _get_flow_table(struct mlx5_ib_dev *dev, u16 user_pri= ority, ft_attr.max_fte =3D max_table_size; ft_attr.flags =3D flags; ft_attr.vport =3D vport; + ft_attr.esw_owner_vhca_id =3D esw_owner_vhca_id; ft_attr.autogroup.max_num_groups =3D MLX5_FS_MAX_TYPES; return _get_prio(ns, prio, &ft_attr); } --=20 2.47.1