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a=openpgp; fpr=EF660D07463F8B726A795413D8EED7F3C83BFA9A Remove code duplocation and improve readability by introducing a new function to setup the enhanced LTSSM mode. Signed-off-by: Sebastian Reichel --- drivers/pci/controller/dwc/pcie-dw-rockchip.c | 27 ++++++++++++++---------= ---- 1 file changed, 14 insertions(+), 13 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/co= ntroller/dwc/pcie-dw-rockchip.c index 8e584016e244..45586a964ead 100644 --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c @@ -511,13 +511,24 @@ static irqreturn_t rockchip_pcie_ep_sys_irq_thread(in= t irq, void *arg) return IRQ_HANDLED; } =20 +static void rockchip_pcie_enable_enhanced_ltssm_control_mode(struct rockch= ip_pcie *rockchip, + u32 flags) +{ + u32 val; + + /* Enable the enhanced control mode of signal app_ltssm_enable */ + val =3D FIELD_PREP_WM16(PCIE_LTSSM_ENABLE_ENHANCE, 1); + if (flags) + val |=3D FIELD_PREP_WM16(flags, 1); + rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_HOT_RESET_CTRL); +} + static int rockchip_pcie_configure_rc(struct platform_device *pdev, struct rockchip_pcie *rockchip) { struct device *dev =3D &pdev->dev; struct dw_pcie_rp *pp; int irq, ret; - u32 val; =20 if (!IS_ENABLED(CONFIG_PCIE_ROCKCHIP_DW_HOST)) return -ENODEV; @@ -534,10 +545,7 @@ static int rockchip_pcie_configure_rc(struct platform_= device *pdev, return ret; } =20 - /* LTSSM enable control mode */ - val =3D FIELD_PREP_WM16(PCIE_LTSSM_ENABLE_ENHANCE, 1); - rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_HOT_RESET_CTRL); - + rockchip_pcie_enable_enhanced_ltssm_control_mode(rockchip, 0); rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_SET_MODE(PCIE_CLIENT_MODE_RC), PCIE_CLIENT_GENERAL_CON); @@ -581,14 +589,7 @@ static int rockchip_pcie_configure_ep(struct platform_= device *pdev, return ret; } =20 - /* - * LTSSM enable control mode, and automatically delay link training on - * hot reset/link-down reset. - */ - val =3D FIELD_PREP_WM16(PCIE_LTSSM_ENABLE_ENHANCE, 1) | - FIELD_PREP_WM16(PCIE_LTSSM_APP_DLY2_EN, 1); - rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_HOT_RESET_CTRL); - + rockchip_pcie_enable_enhanced_ltssm_control_mode(rockchip, PCIE_LTSSM_APP= _DLY2_EN); rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_SET_MODE(PCIE_CLIENT_MODE_EP), PCIE_CLIENT_GENERAL_CON); --=20 2.51.0