From nobody Sun Feb 8 21:33:30 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 89B522F25E0; Wed, 29 Oct 2025 16:11:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761754298; cv=none; b=A1NRlftlOsWZWSJlGW3a8fXwTu2b4rlkMb15XqeVVu3x3XXenAdCVT2GWA37g8FTbUPpLsuhR4Rgr5esLpRkvPM3hY1do9lZUJeViM7piYMVfs6CIRamd2MM89EuNYkSbReY98/8CXz3cgAT1ma6hWQ65Mx1pJHfmqBmerEU5X0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761754298; c=relaxed/simple; bh=SBPUsQQts6myI7KNC8yymj9GqGzDulDYvcTpau9/ALk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=DUwY9wnm8x1Mc228oaElWjMc8KYN4KZU6wMcR5qKfN2MTv2Ym0CTnkdse+kvp2frojq+knfB9FIheFDuUp4pIxReRcZmNz4zTuGzPGjbm7wj592+0pBP64jPBreahiKJ/ePcwXW7ByJ6UlYGxuCECFo/R09GtXqgwD3Jgq0AgG0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=vL3wKFOI; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="vL3wKFOI" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 50589C4CEF7; Wed, 29 Oct 2025 16:11:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1761754298; bh=SBPUsQQts6myI7KNC8yymj9GqGzDulDYvcTpau9/ALk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=vL3wKFOIoq91uTTR96HuBCNCR0G7LITKAB33GwdtWlZeoGAyn+DRgPe0glvKcknJq M9dMTaEPAloeCsn6TK7lZM9RlOw7cUNUGcpknMdVf+CSTmLtZTHZjnDHZ5+KZWA8Jv e0VsXgB/8ulVgFyGI+viPeK1eZw66zUZaL4ZsnL34lkm/2q7H83ZUE0gXJCfSAUbZU QTJ2p9BZGr+TaXt1s0YcydKPPTW0I8OtPD0HnRh6m66XQCO1B20aARMNxTKscYWj/9 hKRJN5h/fHLcopvATVbruTVkBSHhP8STh4N2SZh3s+wSpQ6gDjyLDLxscXROACoR8V d3FiA4wXgiqzQ== From: Conor Dooley To: claudiu.beznea@tuxon.dev Cc: conor@kernel.org, Conor Dooley , Daire McNamara , pierre-henry.moussay@microchip.com, valentina.fernandezalanis@microchip.com, Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Philipp Zabel , linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 1/7] reset: mpfs: add non-auxiliary bus probing Date: Wed, 29 Oct 2025 16:11:17 +0000 Message-ID: <20251029-macarena-neglector-318431fec367@spud> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251029-chewing-absolve-c4e6acfe0fa4@spud> References: <20251029-chewing-absolve-c4e6acfe0fa4@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=6690; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=WjSYxPHoiecG3YZVCMCzeZtGrY72vr6u1gmlrYkaGJE=; b=owGbwMvMwCVWscWwfUFT0iXG02pJDJlMNusucCmdWFN9dEqkWdThu5L3a33SHX3fBXR6vp3+K bros658RykLgxgXg6yYIkvi7b4WqfV/XHY497yFmcPKBDKEgYtTACby6TcjQ/sq8czfXZ9/R5SZ +MfoHvu39vKcGU3K8g/llG8w7PoZtJCR4ccnFW6d3HN9xX3FZs84N9Z/8HoSZTn1yqxZV4psHsS t4wIA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley While the auxiliary bus was a nice bandaid, and meant that re-writing the representation of the clock regions in devicetree was not required, it has run its course. The "mss_top_sysreg" region that contains the clock and reset regions, also contains pinctrl and an interrupt controller, so the time has come rewrite the devicetree and probe the reset controller from an mfd devicetree node, rather than implement those drivers using the auxiliary bus. Wanting to avoid propagating this naive/incorrect description of the hardware to the new pic64gx SoC is a major motivating factor here. Signed-off-by: Conor Dooley --- v6: - depend on MFD_SYSCON - return regmap_update_bits() result directly instead of an additional return 0 v4: - Only use driver specific lock for non-regmap writes v2: - Implement the request to use regmap_update_bits(). I found that I then hated the read/write helpers since they were just bloat, so I ripped them out. I replaced the regular spin_lock_irqsave() stuff with a guard(spinlock_irqsave), since that's a simpler way of handling the two different paths through such a trivial pair of functions. --- drivers/reset/Kconfig | 1 + drivers/reset/reset-mpfs.c | 79 ++++++++++++++++++++++++++++++-------- 2 files changed, 63 insertions(+), 17 deletions(-) diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 78b7078478d4..0ec4b7cd08d6 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -200,6 +200,7 @@ config RESET_PISTACHIO config RESET_POLARFIRE_SOC bool "Microchip PolarFire SoC (MPFS) Reset Driver" depends on MCHP_CLK_MPFS + depends on MFD_SYSCON select AUXILIARY_BUS default MCHP_CLK_MPFS help diff --git a/drivers/reset/reset-mpfs.c b/drivers/reset/reset-mpfs.c index f6fa10e03ea8..25de7df55301 100644 --- a/drivers/reset/reset-mpfs.c +++ b/drivers/reset/reset-mpfs.c @@ -7,13 +7,16 @@ * */ #include +#include #include #include +#include #include #include #include -#include +#include #include +#include #include #include =20 @@ -27,11 +30,14 @@ #define MPFS_SLEEP_MIN_US 100 #define MPFS_SLEEP_MAX_US 200 =20 +#define REG_SUBBLK_RESET_CR 0x88u + /* block concurrent access to the soft reset register */ static DEFINE_SPINLOCK(mpfs_reset_lock); =20 struct mpfs_reset { void __iomem *base; + struct regmap *regmap; struct reset_controller_dev rcdev; }; =20 @@ -46,41 +52,46 @@ static inline struct mpfs_reset *to_mpfs_reset(struct r= eset_controller_dev *rcde static int mpfs_assert(struct reset_controller_dev *rcdev, unsigned long i= d) { struct mpfs_reset *rst =3D to_mpfs_reset(rcdev); - unsigned long flags; u32 reg; =20 - spin_lock_irqsave(&mpfs_reset_lock, flags); + if (rst->regmap) + return regmap_update_bits(rst->regmap, REG_SUBBLK_RESET_CR, BIT(id), BIT= (id)); + + guard(spinlock_irqsave)(&mpfs_reset_lock); =20 reg =3D readl(rst->base); reg |=3D BIT(id); writel(reg, rst->base); =20 - spin_unlock_irqrestore(&mpfs_reset_lock, flags); - return 0; } =20 static int mpfs_deassert(struct reset_controller_dev *rcdev, unsigned long= id) { struct mpfs_reset *rst =3D to_mpfs_reset(rcdev); - unsigned long flags; u32 reg; =20 - spin_lock_irqsave(&mpfs_reset_lock, flags); + if (rst->regmap) + return regmap_update_bits(rst->regmap, REG_SUBBLK_RESET_CR, BIT(id), 0); + + guard(spinlock_irqsave)(&mpfs_reset_lock); =20 reg =3D readl(rst->base); reg &=3D ~BIT(id); writel(reg, rst->base); =20 - spin_unlock_irqrestore(&mpfs_reset_lock, flags); - return 0; } =20 static int mpfs_status(struct reset_controller_dev *rcdev, unsigned long i= d) { struct mpfs_reset *rst =3D to_mpfs_reset(rcdev); - u32 reg =3D readl(rst->base); + u32 reg; + + if (rst->regmap) + regmap_read(rst->regmap, REG_SUBBLK_RESET_CR, ®); + else + reg =3D readl(rst->base); =20 /* * It is safe to return here as MPFS_NUM_RESETS makes sure the sign bit @@ -130,11 +141,45 @@ static int mpfs_reset_xlate(struct reset_controller_d= ev *rcdev, return index - MPFS_PERIPH_OFFSET; } =20 -static int mpfs_reset_probe(struct auxiliary_device *adev, - const struct auxiliary_device_id *id) +static int mpfs_reset_mfd_probe(struct platform_device *pdev) { - struct device *dev =3D &adev->dev; struct reset_controller_dev *rcdev; + struct device *dev =3D &pdev->dev; + struct mpfs_reset *rst; + + rst =3D devm_kzalloc(dev, sizeof(*rst), GFP_KERNEL); + if (!rst) + return -ENOMEM; + + rcdev =3D &rst->rcdev; + rcdev->dev =3D dev; + rcdev->ops =3D &mpfs_reset_ops; + + rcdev->of_node =3D pdev->dev.parent->of_node; + rcdev->of_reset_n_cells =3D 1; + rcdev->of_xlate =3D mpfs_reset_xlate; + rcdev->nr_resets =3D MPFS_NUM_RESETS; + + rst->regmap =3D device_node_to_regmap(pdev->dev.parent->of_node); + if (IS_ERR(rst->regmap)) + dev_err_probe(dev, PTR_ERR(rst->regmap), "Failed to find syscon regmap\n= "); + + return devm_reset_controller_register(dev, rcdev); +} + +static struct platform_driver mpfs_reset_mfd_driver =3D { + .probe =3D mpfs_reset_mfd_probe, + .driver =3D { + .name =3D "mpfs-reset", + }, +}; +module_platform_driver(mpfs_reset_mfd_driver); + +static int mpfs_reset_adev_probe(struct auxiliary_device *adev, + const struct auxiliary_device_id *id) +{ + struct reset_controller_dev *rcdev; + struct device *dev =3D &adev->dev; struct mpfs_reset *rst; =20 rst =3D devm_kzalloc(dev, sizeof(*rst), GFP_KERNEL); @@ -145,8 +190,8 @@ static int mpfs_reset_probe(struct auxiliary_device *ad= ev, =20 rcdev =3D &rst->rcdev; rcdev->dev =3D dev; - rcdev->dev->parent =3D dev->parent; rcdev->ops =3D &mpfs_reset_ops; + rcdev->of_node =3D dev->parent->of_node; rcdev->of_reset_n_cells =3D 1; rcdev->of_xlate =3D mpfs_reset_xlate; @@ -176,12 +221,12 @@ static const struct auxiliary_device_id mpfs_reset_id= s[] =3D { }; MODULE_DEVICE_TABLE(auxiliary, mpfs_reset_ids); =20 -static struct auxiliary_driver mpfs_reset_driver =3D { - .probe =3D mpfs_reset_probe, +static struct auxiliary_driver mpfs_reset_aux_driver =3D { + .probe =3D mpfs_reset_adev_probe, .id_table =3D mpfs_reset_ids, }; =20 -module_auxiliary_driver(mpfs_reset_driver); +module_auxiliary_driver(mpfs_reset_aux_driver); =20 MODULE_DESCRIPTION("Microchip PolarFire SoC Reset Driver"); MODULE_AUTHOR("Conor Dooley "); --=20 2.51.0