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Wed, 29 Oct 2025 08:46:39 -0700 (PDT) From: James Clark Date: Wed, 29 Oct 2025 15:46:01 +0000 Subject: [PATCH v9 1/5] perf: Add perf_event_attr::config4 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251029-james-perf-feat_spe_eft-v9-1-d22536b9cf94@linaro.org> References: <20251029-james-perf-feat_spe_eft-v9-0-d22536b9cf94@linaro.org> In-Reply-To: <20251029-james-perf-feat_spe_eft-v9-0-d22536b9cf94@linaro.org> To: Catalin Marinas , Will Deacon , Mark Rutland , Jonathan Corbet , Marc Zyngier , Oliver Upton , Joey Gouly , Suzuki K Poulose , Zenghui Yu , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Leo Yan , Anshuman Khandual Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev, James Clark X-Mailer: b4 0.14.0 Arm FEAT_SPE_FDS adds the ability to filter on the data source of a packet using another 64-bits of event filtering control. As the existing perf_event_attr::configN fields are all used up for SPE PMU, an additional field is needed. Add a new 'config4' field. Reviewed-by: Leo Yan Tested-by: Leo Yan Reviewed-by: Ian Rogers Signed-off-by: James Clark Acked-by: Peter Zijlstra (Intel) --- include/uapi/linux/perf_event.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/uapi/linux/perf_event.h b/include/uapi/linux/perf_even= t.h index 78a362b80027..0d0ed85ad8cb 100644 --- a/include/uapi/linux/perf_event.h +++ b/include/uapi/linux/perf_event.h @@ -382,6 +382,7 @@ enum perf_event_read_format { #define PERF_ATTR_SIZE_VER6 120 /* Add: aux_sample_size */ #define PERF_ATTR_SIZE_VER7 128 /* Add: sig_data */ #define PERF_ATTR_SIZE_VER8 136 /* Add: config3 */ +#define PERF_ATTR_SIZE_VER9 144 /* add: config4 */ =20 /* * 'struct perf_event_attr' contains various attributes that define @@ -543,6 +544,7 @@ struct perf_event_attr { __u64 sig_data; =20 __u64 config3; /* extension of config2 */ + __u64 config4; /* extension of config3 */ }; =20 /* --=20 2.34.1 From nobody Mon Feb 9 18:48:28 2026 Received: from mail-wm1-f48.google.com (mail-wm1-f48.google.com [209.85.128.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 34C453431F6 for ; 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Wed, 29 Oct 2025 08:46:41 -0700 (PDT) Received: from ho-tower-lan.lan ([185.48.77.170]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4771e3b9994sm53745535e9.16.2025.10.29.08.46.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Oct 2025 08:46:40 -0700 (PDT) From: James Clark Date: Wed, 29 Oct 2025 15:46:02 +0000 Subject: [PATCH v9 2/5] perf: arm_spe: Add support for filtering on data source Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251029-james-perf-feat_spe_eft-v9-2-d22536b9cf94@linaro.org> References: <20251029-james-perf-feat_spe_eft-v9-0-d22536b9cf94@linaro.org> In-Reply-To: <20251029-james-perf-feat_spe_eft-v9-0-d22536b9cf94@linaro.org> To: Catalin Marinas , Will Deacon , Mark Rutland , Jonathan Corbet , Marc Zyngier , Oliver Upton , Joey Gouly , Suzuki K Poulose , Zenghui Yu , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Leo Yan , Anshuman Khandual Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev, James Clark X-Mailer: b4 0.14.0 SPE_FEAT_FDS adds the ability to filter on the data source of packets. Like the other existing filters, enable filtering with PMSFCR_EL1.FDS when any of the filter bits are set. Each bit maps to data sources 0-63 described by bits[0:5] in the data source packet (although the full range of data source is 16 bits so higher value data sources can't be filtered on). The filter is an OR of all the bits, so for example clearing bits 0 and 3 only includes packets from data sources 0 OR 3. Invert the filter given by userspace so that the default value of 0 is equivalent to including all values (no filtering). This allows us to skip adding a new format bit to enable filtering and still support excluding all data sources which would have been a filter value of 0 if not for the inversion. Tested-by: Leo Yan Reviewed-by: Leo Yan Signed-off-by: James Clark --- drivers/perf/arm_spe_pmu.c | 37 +++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/drivers/perf/arm_spe_pmu.c b/drivers/perf/arm_spe_pmu.c index fa50645fedda..617f8a98dd63 100644 --- a/drivers/perf/arm_spe_pmu.c +++ b/drivers/perf/arm_spe_pmu.c @@ -87,6 +87,7 @@ struct arm_spe_pmu { #define SPE_PMU_FEAT_INV_FILT_EVT (1UL << 6) #define SPE_PMU_FEAT_DISCARD (1UL << 7) #define SPE_PMU_FEAT_EFT (1UL << 8) +#define SPE_PMU_FEAT_FDS (1UL << 9) #define SPE_PMU_FEAT_DEV_PROBED (1UL << 63) u64 features; =20 @@ -252,6 +253,10 @@ static const struct attribute_group arm_spe_pmu_cap_gr= oup =3D { #define ATTR_CFG_FLD_inv_event_filter_LO 0 #define ATTR_CFG_FLD_inv_event_filter_HI 63 =20 +#define ATTR_CFG_FLD_inv_data_src_filter_CFG config4 /* inverse of PMSDSFR= _EL1 */ +#define ATTR_CFG_FLD_inv_data_src_filter_LO 0 +#define ATTR_CFG_FLD_inv_data_src_filter_HI 63 + GEN_PMU_FORMAT_ATTR(ts_enable); GEN_PMU_FORMAT_ATTR(pa_enable); GEN_PMU_FORMAT_ATTR(pct_enable); @@ -268,6 +273,7 @@ GEN_PMU_FORMAT_ATTR(float_filter); GEN_PMU_FORMAT_ATTR(float_filter_mask); GEN_PMU_FORMAT_ATTR(event_filter); GEN_PMU_FORMAT_ATTR(inv_event_filter); +GEN_PMU_FORMAT_ATTR(inv_data_src_filter); GEN_PMU_FORMAT_ATTR(min_latency); GEN_PMU_FORMAT_ATTR(discard); =20 @@ -288,6 +294,7 @@ static struct attribute *arm_spe_pmu_formats_attr[] =3D= { &format_attr_float_filter_mask.attr, &format_attr_event_filter.attr, &format_attr_inv_event_filter.attr, + &format_attr_inv_data_src_filter.attr, &format_attr_min_latency.attr, &format_attr_discard.attr, NULL, @@ -306,6 +313,10 @@ static umode_t arm_spe_pmu_format_attr_is_visible(stru= ct kobject *kobj, if (attr =3D=3D &format_attr_inv_event_filter.attr && !(spe_pmu->features= & SPE_PMU_FEAT_INV_FILT_EVT)) return 0; =20 + if (attr =3D=3D &format_attr_inv_data_src_filter.attr && + !(spe_pmu->features & SPE_PMU_FEAT_FDS)) + return 0; + if ((attr =3D=3D &format_attr_branch_filter_mask.attr || attr =3D=3D &format_attr_load_filter_mask.attr || attr =3D=3D &format_attr_store_filter_mask.attr || @@ -430,6 +441,9 @@ static u64 arm_spe_event_to_pmsfcr(struct perf_event *e= vent) if (ATTR_CFG_GET_FLD(attr, inv_event_filter)) reg |=3D PMSFCR_EL1_FnE; =20 + if (ATTR_CFG_GET_FLD(attr, inv_data_src_filter)) + reg |=3D PMSFCR_EL1_FDS; + if (ATTR_CFG_GET_FLD(attr, min_latency)) reg |=3D PMSFCR_EL1_FL; =20 @@ -454,6 +468,17 @@ static u64 arm_spe_event_to_pmslatfr(struct perf_event= *event) return FIELD_PREP(PMSLATFR_EL1_MINLAT, ATTR_CFG_GET_FLD(attr, min_latency= )); } =20 +static u64 arm_spe_event_to_pmsdsfr(struct perf_event *event) +{ + struct perf_event_attr *attr =3D &event->attr; + + /* + * Data src filter is inverted so that the default value of 0 is + * equivalent to no filtering. + */ + return ~ATTR_CFG_GET_FLD(attr, inv_data_src_filter); +} + static void arm_spe_pmu_pad_buf(struct perf_output_handle *handle, int len) { struct arm_spe_pmu_buf *buf =3D perf_get_aux(handle); @@ -791,6 +816,10 @@ static int arm_spe_pmu_event_init(struct perf_event *e= vent) if (arm_spe_event_to_pmsnevfr(event) & spe_pmu->pmsevfr_res0) return -EOPNOTSUPP; =20 + if (arm_spe_event_to_pmsdsfr(event) !=3D U64_MAX && + !(spe_pmu->features & SPE_PMU_FEAT_FDS)) + return -EOPNOTSUPP; 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Tested-by: Leo Yan Reviewed-by: Ian Rogers Signed-off-by: James Clark --- tools/include/uapi/linux/perf_event.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/tools/include/uapi/linux/perf_event.h b/tools/include/uapi/lin= ux/perf_event.h index 78a362b80027..0d0ed85ad8cb 100644 --- a/tools/include/uapi/linux/perf_event.h +++ b/tools/include/uapi/linux/perf_event.h @@ -382,6 +382,7 @@ enum perf_event_read_format { #define PERF_ATTR_SIZE_VER6 120 /* Add: aux_sample_size */ #define PERF_ATTR_SIZE_VER7 128 /* Add: sig_data */ #define PERF_ATTR_SIZE_VER8 136 /* Add: config3 */ +#define PERF_ATTR_SIZE_VER9 144 /* add: config4 */ =20 /* * 'struct perf_event_attr' contains various attributes that define @@ -543,6 +544,7 @@ struct perf_event_attr { __u64 sig_data; =20 __u64 config3; /* extension of config2 */ + __u64 config4; /* extension of config3 */ }; =20 /* --=20 2.34.1 From nobody Mon Feb 9 18:48:28 2026 Received: from mail-wm1-f48.google.com (mail-wm1-f48.google.com [209.85.128.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 355A3346A06 for ; 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Wed, 29 Oct 2025 08:46:44 -0700 (PDT) Received: from ho-tower-lan.lan ([185.48.77.170]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4771e3b9994sm53745535e9.16.2025.10.29.08.46.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Oct 2025 08:46:43 -0700 (PDT) From: James Clark Date: Wed, 29 Oct 2025 15:46:04 +0000 Subject: [PATCH v9 4/5] perf tools: Add support for perf_event_attr::config4 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251029-james-perf-feat_spe_eft-v9-4-d22536b9cf94@linaro.org> References: <20251029-james-perf-feat_spe_eft-v9-0-d22536b9cf94@linaro.org> In-Reply-To: <20251029-james-perf-feat_spe_eft-v9-0-d22536b9cf94@linaro.org> To: Catalin Marinas , Will Deacon , Mark Rutland , Jonathan Corbet , Marc Zyngier , Oliver Upton , Joey Gouly , Suzuki K Poulose , Zenghui Yu , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Leo Yan , Anshuman Khandual Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev, James Clark X-Mailer: b4 0.14.0 perf_event_attr has gained a new field, config4, so add support for it extending the existing configN support. Reviewed-by: Leo Yan Reviewed-by: Ian Rogers Tested-by: Leo Yan Signed-off-by: James Clark --- tools/perf/tests/parse-events.c | 13 ++++++++++++- tools/perf/util/parse-events.c | 11 +++++++++++ tools/perf/util/parse-events.h | 1 + tools/perf/util/parse-events.l | 1 + tools/perf/util/pmu.c | 8 ++++++++ tools/perf/util/pmu.h | 1 + 6 files changed, 34 insertions(+), 1 deletion(-) diff --git a/tools/perf/tests/parse-events.c b/tools/perf/tests/parse-event= s.c index e4cdb517c10e..128d21dc389f 100644 --- a/tools/perf/tests/parse-events.c +++ b/tools/perf/tests/parse-events.c @@ -647,6 +647,7 @@ static int test__checkevent_pmu(struct evlist *evlist) TEST_ASSERT_EVSEL("wrong config1", 1 =3D=3D evsel->core.attr.config1, = evsel); TEST_ASSERT_EVSEL("wrong config2", 3 =3D=3D evsel->core.attr.config2, = evsel); TEST_ASSERT_EVSEL("wrong config3", 0 =3D=3D evsel->core.attr.config3, = evsel); + TEST_ASSERT_EVSEL("wrong config4", 0 =3D=3D evsel->core.attr.config4, = evsel); /* * The period value gets configured within evlist__config, * while this test executes only parse events method. @@ -669,6 +670,7 @@ static int test__checkevent_list(struct evlist *evlist) TEST_ASSERT_EVSEL("wrong config1", 0 =3D=3D evsel->core.attr.config1, ev= sel); TEST_ASSERT_EVSEL("wrong config2", 0 =3D=3D evsel->core.attr.config2, ev= sel); TEST_ASSERT_EVSEL("wrong config3", 0 =3D=3D evsel->core.attr.config3, ev= sel); + TEST_ASSERT_EVSEL("wrong config4", 0 =3D=3D evsel->core.attr.config4, ev= sel); TEST_ASSERT_EVSEL("wrong exclude_user", !evsel->core.attr.exclude_user, = evsel); TEST_ASSERT_EVSEL("wrong exclude_kernel", !evsel->core.attr.exclude_kern= el, evsel); TEST_ASSERT_EVSEL("wrong exclude_hv", !evsel->core.attr.exclude_hv, evse= l); @@ -849,6 +851,15 @@ static int test__checkterms_simple(struct parse_events= _terms *terms) TEST_ASSERT_VAL("wrong val", term->val.num =3D=3D 4); TEST_ASSERT_VAL("wrong config", !strcmp(term->config, "config3")); =20 + /* config4=3D5 */ + term =3D list_entry(term->list.next, struct parse_events_term, list); + TEST_ASSERT_VAL("wrong type term", + term->type_term =3D=3D PARSE_EVENTS__TERM_TYPE_CONFIG4); + TEST_ASSERT_VAL("wrong type val", + term->type_val =3D=3D PARSE_EVENTS__TERM_TYPE_NUM); + TEST_ASSERT_VAL("wrong val", term->val.num =3D=3D 5); + TEST_ASSERT_VAL("wrong config", !strcmp(term->config, "config4")); + /* umask=3D1*/ term =3D list_entry(term->list.next, struct parse_events_term, list); TEST_ASSERT_VAL("wrong type term", @@ -2516,7 +2527,7 @@ struct terms_test { =20 static const struct terms_test test__terms[] =3D { [0] =3D { - .str =3D "config=3D10,config1,config2=3D3,config3=3D4,umask=3D1,read,r= 0xead", + .str =3D "config=3D10,config1,config2=3D3,config3=3D4,config4=3D5,umas= k=3D1,read,r0xead", .check =3D test__checkterms_simple, }, }; diff --git a/tools/perf/util/parse-events.c b/tools/perf/util/parse-events.c index 0c0dc20b1c13..ee4f55cbd3cb 100644 --- a/tools/perf/util/parse-events.c +++ b/tools/perf/util/parse-events.c @@ -215,6 +215,8 @@ __add_event(struct list_head *list, int *idx, PERF_PMU_FORMAT_VALUE_CONFIG2, "config2"); perf_pmu__warn_invalid_config(pmu, attr->config3, name, PERF_PMU_FORMAT_VALUE_CONFIG3, "config3"); + perf_pmu__warn_invalid_config(pmu, attr->config4, name, + PERF_PMU_FORMAT_VALUE_CONFIG4, "config4"); } } /* @@ -700,6 +702,7 @@ const char *parse_events__term_type_str(enum parse_even= ts__term_type term_type) [PARSE_EVENTS__TERM_TYPE_CONFIG1] =3D "config1", [PARSE_EVENTS__TERM_TYPE_CONFIG2] =3D "config2", [PARSE_EVENTS__TERM_TYPE_CONFIG3] =3D "config3", + [PARSE_EVENTS__TERM_TYPE_CONFIG4] =3D "config4", [PARSE_EVENTS__TERM_TYPE_NAME] =3D "name", [PARSE_EVENTS__TERM_TYPE_SAMPLE_PERIOD] =3D "period", [PARSE_EVENTS__TERM_TYPE_SAMPLE_FREQ] =3D "freq", @@ -749,6 +752,7 @@ config_term_avail(enum parse_events__term_type term_typ= e, struct parse_events_er case PARSE_EVENTS__TERM_TYPE_CONFIG1: case PARSE_EVENTS__TERM_TYPE_CONFIG2: case PARSE_EVENTS__TERM_TYPE_CONFIG3: + case PARSE_EVENTS__TERM_TYPE_CONFIG4: case PARSE_EVENTS__TERM_TYPE_NAME: case PARSE_EVENTS__TERM_TYPE_METRIC_ID: case PARSE_EVENTS__TERM_TYPE_SAMPLE_PERIOD: @@ -819,6 +823,10 @@ do { \ CHECK_TYPE_VAL(NUM); attr->config3 =3D term->val.num; break; + case PARSE_EVENTS__TERM_TYPE_CONFIG4: + CHECK_TYPE_VAL(NUM); + attr->config4 =3D term->val.num; + break; case PARSE_EVENTS__TERM_TYPE_SAMPLE_PERIOD: CHECK_TYPE_VAL(NUM); break; @@ -1064,6 +1072,7 @@ static int config_term_tracepoint(struct perf_event_a= ttr *attr, case PARSE_EVENTS__TERM_TYPE_CONFIG1: case PARSE_EVENTS__TERM_TYPE_CONFIG2: case PARSE_EVENTS__TERM_TYPE_CONFIG3: + case PARSE_EVENTS__TERM_TYPE_CONFIG4: case PARSE_EVENTS__TERM_TYPE_LEGACY_HARDWARE_CONFIG: case PARSE_EVENTS__TERM_TYPE_LEGACY_CACHE_CONFIG: case PARSE_EVENTS__TERM_TYPE_NAME: @@ -1207,6 +1216,7 @@ do { \ case PARSE_EVENTS__TERM_TYPE_CONFIG1: case PARSE_EVENTS__TERM_TYPE_CONFIG2: case PARSE_EVENTS__TERM_TYPE_CONFIG3: + case PARSE_EVENTS__TERM_TYPE_CONFIG4: case PARSE_EVENTS__TERM_TYPE_LEGACY_HARDWARE_CONFIG: case PARSE_EVENTS__TERM_TYPE_LEGACY_CACHE_CONFIG: case PARSE_EVENTS__TERM_TYPE_NAME: @@ -1245,6 +1255,7 @@ static int get_config_chgs(struct perf_pmu *pmu, stru= ct parse_events_terms *head case PARSE_EVENTS__TERM_TYPE_CONFIG1: case PARSE_EVENTS__TERM_TYPE_CONFIG2: case PARSE_EVENTS__TERM_TYPE_CONFIG3: + case PARSE_EVENTS__TERM_TYPE_CONFIG4: case PARSE_EVENTS__TERM_TYPE_LEGACY_HARDWARE_CONFIG: case PARSE_EVENTS__TERM_TYPE_LEGACY_CACHE_CONFIG: case PARSE_EVENTS__TERM_TYPE_NAME: diff --git a/tools/perf/util/parse-events.h b/tools/perf/util/parse-events.h index 1012b441e9cd..3577ab213730 100644 --- a/tools/perf/util/parse-events.h +++ b/tools/perf/util/parse-events.h @@ -59,6 +59,7 @@ enum parse_events__term_type { PARSE_EVENTS__TERM_TYPE_CONFIG1, PARSE_EVENTS__TERM_TYPE_CONFIG2, PARSE_EVENTS__TERM_TYPE_CONFIG3, + PARSE_EVENTS__TERM_TYPE_CONFIG4, PARSE_EVENTS__TERM_TYPE_NAME, PARSE_EVENTS__TERM_TYPE_SAMPLE_PERIOD, PARSE_EVENTS__TERM_TYPE_SAMPLE_FREQ, diff --git a/tools/perf/util/parse-events.l b/tools/perf/util/parse-events.l index 8e0ea441e57f..251ce4321878 100644 --- a/tools/perf/util/parse-events.l +++ b/tools/perf/util/parse-events.l @@ -287,6 +287,7 @@ config { return term(yyscanner, PARSE_EVENTS__TERM_TY= PE_CONFIG); } config1 { return term(yyscanner, PARSE_EVENTS__TERM_TYPE_CONFIG1); } config2 { return term(yyscanner, PARSE_EVENTS__TERM_TYPE_CONFIG2); } config3 { return term(yyscanner, PARSE_EVENTS__TERM_TYPE_CONFIG3); } +config4 { return term(yyscanner, PARSE_EVENTS__TERM_TYPE_CONFIG4); } name { return term(yyscanner, PARSE_EVENTS__TERM_TYPE_NAME); } period { return term(yyscanner, PARSE_EVENTS__TERM_TYPE_SAMPLE_PERIOD); } freq { return term(yyscanner, PARSE_EVENTS__TERM_TYPE_SAMPLE_FREQ); } diff --git a/tools/perf/util/pmu.c b/tools/perf/util/pmu.c index d597263fab4f..dce03c19dc4d 100644 --- a/tools/perf/util/pmu.c +++ b/tools/perf/util/pmu.c @@ -1566,6 +1566,10 @@ static int pmu_config_term(const struct perf_pmu *pm= u, assert(term->type_val =3D=3D PARSE_EVENTS__TERM_TYPE_NUM); pmu_format_value(bits, term->val.num, &attr->config3, zero); break; + case PARSE_EVENTS__TERM_TYPE_CONFIG4: + assert(term->type_val =3D=3D PARSE_EVENTS__TERM_TYPE_NUM); + pmu_format_value(bits, term->val.num, &attr->config4, zero); + break; case PARSE_EVENTS__TERM_TYPE_LEGACY_HARDWARE_CONFIG: assert(term->type_val =3D=3D PARSE_EVENTS__TERM_TYPE_NUM); assert(term->val.num < PERF_COUNT_HW_MAX); @@ -1641,6 +1645,9 @@ static int pmu_config_term(const struct perf_pmu *pmu, case PERF_PMU_FORMAT_VALUE_CONFIG3: vp =3D &attr->config3; break; + case PERF_PMU_FORMAT_VALUE_CONFIG4: + vp =3D &attr->config4; + break; default: return -EINVAL; } @@ -2000,6 +2007,7 @@ int perf_pmu__for_each_format(struct perf_pmu *pmu, v= oid *state, pmu_format_call "config1=3D0..0xffffffffffffffff", "config2=3D0..0xffffffffffffffff", "config3=3D0..0xffffffffffffffff", + "config4=3D0..0xffffffffffffffff", "legacy-hardware-config=3D0..9,", "legacy-cache-config=3D0..0xffffff,", "name=3Dstring", diff --git a/tools/perf/util/pmu.h b/tools/perf/util/pmu.h index 1ebcf0242af8..67431f765266 100644 --- a/tools/perf/util/pmu.h +++ b/tools/perf/util/pmu.h @@ -23,6 +23,7 @@ enum { PERF_PMU_FORMAT_VALUE_CONFIG1, PERF_PMU_FORMAT_VALUE_CONFIG2, PERF_PMU_FORMAT_VALUE_CONFIG3, + PERF_PMU_FORMAT_VALUE_CONFIG4, PERF_PMU_FORMAT_VALUE_CONFIG_END, }; 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Wed, 29 Oct 2025 08:46:45 -0700 (PDT) From: James Clark Date: Wed, 29 Oct 2025 15:46:05 +0000 Subject: [PATCH v9 5/5] perf docs: arm-spe: Document new SPE filtering features Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251029-james-perf-feat_spe_eft-v9-5-d22536b9cf94@linaro.org> References: <20251029-james-perf-feat_spe_eft-v9-0-d22536b9cf94@linaro.org> In-Reply-To: <20251029-james-perf-feat_spe_eft-v9-0-d22536b9cf94@linaro.org> To: Catalin Marinas , Will Deacon , Mark Rutland , Jonathan Corbet , Marc Zyngier , Oliver Upton , Joey Gouly , Suzuki K Poulose , Zenghui Yu , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Leo Yan , Anshuman Khandual Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev, James Clark X-Mailer: b4 0.14.0 FEAT_SPE_EFT and FEAT_SPE_FDS etc have new user facing format attributes so document them. Also document existing 'event_filter' bits that were missing from the doc and the fact that latency values are stored in the weight field. Reviewed-by: Leo Yan Tested-by: Leo Yan Reviewed-by: Ian Rogers Signed-off-by: James Clark --- tools/perf/Documentation/perf-arm-spe.txt | 104 ++++++++++++++++++++++++++= +--- 1 file changed, 95 insertions(+), 9 deletions(-) diff --git a/tools/perf/Documentation/perf-arm-spe.txt b/tools/perf/Documen= tation/perf-arm-spe.txt index cda8dd47fc4d..8b02e5b983fa 100644 --- a/tools/perf/Documentation/perf-arm-spe.txt +++ b/tools/perf/Documentation/perf-arm-spe.txt @@ -141,27 +141,65 @@ Config parameters These are placed between the // in the event and comma separated. For exam= ple '-e arm_spe/load_filter=3D1,min_latency=3D10/' =20 - branch_filter=3D1 - collect branches only (PMSFCR.B) - event_filter=3D - filter on specific events (PMSEVFR) - see bitfie= ld description below + event_filter=3D - logical AND filter on specific events (PMSEVFR) = - see bitfield description below + inv_event_filter=3D - logical OR to filter out specific events (PM= SNEVFR, FEAT_SPEv1p2) - see bitfield description below jitter=3D1 - use jitter to avoid resonance when sampling (PMS= IRR.RND) - load_filter=3D1 - collect loads only (PMSFCR.LD) min_latency=3D - collect only samples with this latency or higher= * (PMSLATFR) pa_enable=3D1 - collect physical address (as well as VA) of load= s/stores (PMSCR.PA) - requires privilege pct_enable=3D1 - collect physical timestamp instead of virtual ti= mestamp (PMSCR.PCT) - requires privilege - store_filter=3D1 - collect stores only (PMSFCR.ST) ts_enable=3D1 - enable timestamping with value of generic timer = (PMSCR.TS) discard=3D1 - enable SPE PMU events but don't collect sample d= ata - see 'Discard mode' (PMBLIMITR.FM =3D DISCARD) + inv_data_src_filter=3D - mask to filter from 0-63 possible data so= urces (PMSDSFR, FEAT_SPE_FDS) - See 'Data source filtering' =20 +++*+++ Latency is the total latency from the point at which sampling star= ted on that instruction, rather than only the execution latency. =20 -Only some events can be filtered on; these include: - - bit 1 - instruction retired (i.e. omit speculative instructions) +Only some events can be filtered on using 'event_filter' bits. The overall +filter is the logical AND of these bits, for example if bits 3 and 5 are s= et +only samples that have both 'L1D cache refill' AND 'TLB walk' are recorded= . When +FEAT_SPEv1p2 is implemented 'inv_event_filter' can also be used to exclude +events that have any (OR) of the filter's bits set. For example setting bi= ts 3 +and 5 in 'inv_event_filter' will exclude any events that are either L1D ca= che +refill OR TLB walk. If the same bit is set in both filters it's UNPREDICTA= BLE +whether the sample is included or excluded. Filter bits for both event_fil= ter +and inv_event_filter are: + + bit 1 - Instruction retired (i.e. omit speculative instructions) + bit 2 - L1D access (FEAT_SPEv1p4) bit 3 - L1D refill + bit 4 - TLB access (FEAT_SPEv1p4) bit 5 - TLB refill - bit 7 - mispredict - bit 11 - misaligned access + bit 6 - Not taken event (FEAT_SPEv1p2) + bit 7 - Mispredict + bit 8 - Last level cache access (FEAT_SPEv1p4) + bit 9 - Last level cache miss (FEAT_SPEv1p4) + bit 10 - Remote access (FEAT_SPEv1p4) + bit 11 - Misaligned access (FEAT_SPEv1p1) + bit 12-15 - IMPLEMENTATION DEFINED events (when implemented) + bit 16 - Transaction (FEAT_TME) + bit 17 - Partial or empty SME or SVE predicate (FEAT_SPEv1p1) + bit 18 - Empty SME or SVE predicate (FEAT_SPEv1p1) + bit 19 - L2D access (FEAT_SPEv1p4) + bit 20 - L2D miss (FEAT_SPEv1p4) + bit 21 - Cache data modified (FEAT_SPEv1p4) + bit 22 - Recently fetched (FEAT_SPEv1p4) + bit 23 - Data snooped (FEAT_SPEv1p4) + bit 24 - Streaming SVE mode event (when FEAT_SPE_SME is implemented),= or + IMPLEMENTATION DEFINED event 24 (when implemented, only vers= ions + less than FEAT_SPEv1p4) + bit 25 - SMCU or external coprocessor operation event when FEAT_SPE_S= ME is + implemented, or IMPLEMENTATION DEFINED event 25 (when implem= ented, + only versions less than FEAT_SPEv1p4) + bit 26-31 - IMPLEMENTATION DEFINED events (only versions less than FEAT_= SPEv1p4) + bit 48-63 - IMPLEMENTATION DEFINED events (when implemented) + +For IMPLEMENTATION DEFINED bits, refer to the CPU TRM if these bits are +implemented. + +The driver will reject events if requested filter bits require unimplement= ed SPE +versions, but will not reject filter bits for unimplemented IMPDEF bits or= when +their related feature is not present (e.g. SME). For example, if FEAT_SPEv= 1p2 is +not implemented, filtering on "Not taken event" (bit 6) will be rejected. =20 So to sample just retired instructions: =20 @@ -171,6 +209,31 @@ or just mispredicted branches: =20 perf record -e arm_spe/event_filter=3D0x80/ -- ./mybench =20 +When set, the following filters can be used to select samples that match a= ny of +the operation types (OR filtering). If only one is set then only samples o= f that +type are collected: + + branch_filter=3D1 - Collect branches (PMSFCR.B) + load_filter=3D1 - Collect loads (PMSFCR.LD) + store_filter=3D1 - Collect stores (PMSFCR.ST) + +When extended filtering is supported (FEAT_SPE_EFT), SIMD and float +pointer operations can also be selected: + + simd_filter=3D1 - Collect SIMD loads, stores and operations (PMS= FCR.SIMD) + float_filter=3D1 - Collect floating point loads, stores and opera= tions (PMSFCR.FP) + +When extended filtering is supported (FEAT_SPE_EFT), operation type filter= s can +be changed to AND using _mask fields. For example samples could be selecte= d if +they are store AND SIMD by setting 'store_filter=3D1,simd_filter=3D1, +store_filter_mask=3D1,simd_filter_mask=3D1'. The new masks are as follows: + + branch_filter_mask=3D1 - Change branch filter behavior from OR to AND (= PMSFCR.Bm) + load_filter_mask=3D1 - Change load filter behavior from OR to AND (PM= SFCR.LDm) + store_filter_mask=3D1 - Change store filter behavior from OR to AND (P= MSFCR.STm) + simd_filter_mask=3D1 - Change SIMD filter behavior from OR to AND (PM= SFCR.SIMDm) + float_filter_mask=3D1 - Change floating point filter behavior from OR = to AND (PMSFCR.FPm) + Viewing the data ~~~~~~~~~~~~~~~~~ =20 @@ -210,6 +273,10 @@ Memory access details are also stored on the samples a= nd this can be viewed with =20 perf report --mem-mode =20 +The latency value from the SPE sample is stored in the 'weight' field of t= he +Perf samples and can be displayed in Perf script and report outputs by ena= bling +its display from the command line. + Common errors ~~~~~~~~~~~~~ =20 @@ -253,6 +320,25 @@ to minimize output. Then run perf stat: perf record -e arm_spe/discard/ -a -N -B --no-bpf-event -o - > /dev/null= & perf stat -e SAMPLE_FEED_LD =20 +Data source filtering +~~~~~~~~~~~~~~~~~~~~~ + +When FEAT_SPE_FDS is present, 'inv_data_src_filter' can be used as a mask = to +filter on a subset (0 - 63) of possible data source IDs. The full range of= data +sources is 0 - 65535 although these are unlikely to be used in practice. D= ata +sources are IMPDEF so refer to the TRM for the mappings. Each bit N of the +filter maps to data source N. The filter is an OR of all the bits, and the= value +provided inv_data_src_filter is inverted before writing to PMSDSFR_EL1 so = that +set bits exclude that data source and cleared bits include that data sourc= e. +Therefore the default value of 0 is equivalent to no filtering (all data s= ources +included). + +For example, to include only data sources 0 and 3, clear bits 0 and 3 +(0xFFFFFFFFFFFFFFF6) + +When 'inv_data_src_filter' is set to 0xFFFFFFFFFFFFFFFF, any samples with = any +data source set are excluded. + SEE ALSO -------- =20 --=20 2.34.1