From nobody Mon Dec 15 18:45:06 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 58C0F3128A9; Wed, 29 Oct 2025 08:37:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761727038; cv=none; b=RrzpBQ099a2opTGlJ9Xu+I8oqk+8WHZN3ovG4LpIpaZ+ldLOzUSvHoenGMKyv6VZVwDLqcuaESW99ptpeGwwTcNMs9sZoEY26QaLSoHNNJVoG/zVN3726iq7fsHrxaivh7HWQGQUIBLT3U8uMjmGVdlYXRl9q9h0yZT1cIZftzE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761727038; c=relaxed/simple; bh=BVLvqWYiknuE3RTsMI3OFst20j+dvTINoUrb8fOh9xA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=kK7bmLhivJzwgZJ5zSQFhPVsJ87IlFtwbzgahqeldrlhRWMQONw5cHfgGchkuH838E35K0ZU5zWF9KoVBSdNCbW0TYIMEFJcA8jEeekBvVmd+lUelaIXEdRUPQhmRoh7CVPuxbQjPUriynIgVluEmzjWQkhRpzIq6czItYYXx3U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=F6xxwPwg; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="F6xxwPwg" Received: by smtp.kernel.org (Postfix) with ESMTPS id F3F3AC113D0; Wed, 29 Oct 2025 08:37:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1761727038; bh=BVLvqWYiknuE3RTsMI3OFst20j+dvTINoUrb8fOh9xA=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=F6xxwPwgJubY/fgqaJyx38EC/9UjhQ095IVSwcFX7bHinsckvFqebts0Z7aWtjuTA b+86uSwFtNvHHALeX/J/6GI+4/NMjGMNu/8/w60GK62vC5W0JBPnd84tD/2hh5EW02 Te5vW9TH+9NjvTmfBLsPJ9Ld/y2hq+ObSaJyGttPPAcAjBQpsMBnf8ldX2e1dLU2v5 5Una846+mOTr+vA4Rbxp1+9wLQi0Zf8k14mRrfvF6e9GLPeMiJHY7wAMFS37dmqkdM ZhE9pVcMVJ1t1MjxQhzPdUF8DWUdftVCdDnzkd7phD1KHEt5c6L8PnE8G0409zPbv/ PTONYnZizlBtA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id DBC32CCF9EE; Wed, 29 Oct 2025 08:37:17 +0000 (UTC) From: George Moussalem via B4 Relay Date: Wed, 29 Oct 2025 12:36:57 +0400 Subject: [PATCH v18 1/6] dt-bindings: pwm: add IPQ6018 binding Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251029-ipq-pwm-v18-1-edbef8efbb8e@outlook.com> References: <20251029-ipq-pwm-v18-0-edbef8efbb8e@outlook.com> In-Reply-To: <20251029-ipq-pwm-v18-0-edbef8efbb8e@outlook.com> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Baruch Siach , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, George Moussalem , Devi Priya , Baruch Siach , Bjorn Andersson , Krzysztof Kozlowski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1761727035; l=2105; i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; bh=Ibx3MGKBQtG5XFPAvH9GByVAP62xXho2RMoxEtRDVSE=; b=f7TOV9DLImZRAlFXH+UlWkM3QpjTimIXm6kAZoeMQiSqb82rBfXfiQwfKDhqkK0zrBoki07TR RKbQtftTVmXBVT0FvJ7z5VfqyFLXYkEiblHX/XBHtsW5XW5CUz+JHhx X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 with auth_id=364 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: Devi Priya DT binding for the PWM block in Qualcomm IPQ6018 SoC. [George: added compatibles for IPQ5018, IPQ5332, and IPQ9574] Reviewed-by: Bjorn Andersson Reviewed-by: Krzysztof Kozlowski Co-developed-by: Baruch Siach Signed-off-by: Baruch Siach Signed-off-by: Devi Priya Signed-off-by: George Moussalem --- .../devicetree/bindings/pwm/qcom,ipq6018-pwm.yaml | 51 ++++++++++++++++++= ++++ 1 file changed, 51 insertions(+) diff --git a/Documentation/devicetree/bindings/pwm/qcom,ipq6018-pwm.yaml b/= Documentation/devicetree/bindings/pwm/qcom,ipq6018-pwm.yaml new file mode 100644 index 0000000000000000000000000000000000000000..ca8e916f03276e93d755d574e25= 67b0e4b86a8ce --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/qcom,ipq6018-pwm.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/qcom,ipq6018-pwm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm IPQ6018 PWM controller + +maintainers: + - George Moussalem + +properties: + compatible: + oneOf: + - items: + - enum: + - qcom,ipq5018-pwm + - qcom,ipq5332-pwm + - qcom,ipq9574-pwm + - const: qcom,ipq6018-pwm + - const: qcom,ipq6018-pwm + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + "#pwm-cells": + const: 2 + +required: + - compatible + - reg + - clocks + - "#pwm-cells" + +additionalProperties: false + +examples: + - | + #include + + pwm: pwm@1941010 { + compatible =3D "qcom,ipq6018-pwm"; + reg =3D <0x01941010 0x20>; + clocks =3D <&gcc GCC_ADSS_PWM_CLK>; + assigned-clocks =3D <&gcc GCC_ADSS_PWM_CLK>; + assigned-clock-rates =3D <100000000>; + #pwm-cells =3D <2>; + }; --=20 2.51.1 From nobody Mon Dec 15 18:45:06 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 58B953126C1; Wed, 29 Oct 2025 08:37:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761727038; cv=none; b=oHYhaQvGiDxMP5k5N4TnYyE+JsAFOPPbXA1efINMsNU+yUNSlpuLvSv6VXj1rAW4uQv5uyGqbLDq1GfMrerPgD35q+sZdZNdRC1XUR5IrihxfASsFz49GrINLeSS64z0nVW0YdRCCShxbpCTjvrYH/0SUHvJn+jdXtKEE6t64Iw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761727038; c=relaxed/simple; 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Wed, 29 Oct 2025 08:37:17 +0000 (UTC) From: George Moussalem via B4 Relay Date: Wed, 29 Oct 2025 12:36:58 +0400 Subject: [PATCH v18 2/6] pwm: driver for qualcomm ipq6018 pwm block Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251029-ipq-pwm-v18-2-edbef8efbb8e@outlook.com> References: <20251029-ipq-pwm-v18-0-edbef8efbb8e@outlook.com> In-Reply-To: <20251029-ipq-pwm-v18-0-edbef8efbb8e@outlook.com> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Baruch Siach , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, George Moussalem , Devi Priya , Baruch Siach X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1761727035; l=9989; i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; bh=JkkDkFCiJmTKtp65InDainpOUSmguzyNLU/LCP8xYP8=; b=GBnJxGs40nfOa4a4cGt/zpQ/LhVBhltfuPnjsBAiL8zT5Dm5GFa1QrAGkAe9tx9mXEQL29My4 3rqt9AS9Y6jCj2nCtguLSwUcX+NWjTCkRFbf0O4rqrV/Q5jIpUffSrE X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 with auth_id=364 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: Devi Priya Driver for the PWM block in Qualcomm IPQ6018 line of SoCs. Based on driver from downstream Codeaurora kernel tree. Removed support for older (V1) variants because I have no access to that hardware. Tested on IPQ5018 and IPQ6010 based hardware. Co-developed-by: Baruch Siach Signed-off-by: Baruch Siach Signed-off-by: Devi Priya Reviewed-by: Bjorn Andersson Signed-off-by: George Moussalem --- v17: Removed unnecessary code comments v16: Simplified code to calculate divs and duty cycle as per Uwe's comments Removed unused pwm_chip struct from ipq_pwm_chip struct Removed unnecessary cast as per Uwe's comment Replaced devm_clk_get & clk_prepare_enable by devm_clk_get_enabled Replaced pwmchip_add by devm_pwmchip_add and removed .remove function Removed .owner from driver struct v15: No change v14: Picked up the R-b tag v13: Updated the file name to match the compatible Sorted the properties and updated the order in the required field Dropped the syscon node from examples v12: Picked up the R-b tag v11: No change v10: No change v9: Add 'ranges' property to example (Rob) Drop label in example (Rob) v8: Add size cell to 'reg' (Rob) v7: Use 'reg' instead of 'offset' (Rob) Drop 'clock-names' and 'assigned-clock*' (Bjorn) Use single cell address/size in example node (Bjorn) Move '#pwm-cells' lower in example node (Bjorn) List 'reg' as required v6: Device node is child of TCSR; remove phandle (Rob Herring) Add assigned-clocks/assigned-clock-rates (Uwe Kleine-K=C3=B6nig) v5: Use qcom,pwm-regs for phandle instead of direct regs (Bjorn Andersson, Kathiravan T) v4: Update the binding example node as well (Rob Herring's bot) v3: s/qcom,pwm-ipq6018/qcom,ipq6018-pwm/ (Rob Herring) v2: Make #pwm-cells const (Rob Herring) --- drivers/pwm/Kconfig | 12 +++ drivers/pwm/Makefile | 1 + drivers/pwm/pwm-ipq.c | 212 ++++++++++++++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 225 insertions(+) diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index 0b47456e2d57bbdda54b1318911994812e315612..e9bdb7f3b8114db4b15ce0488fb= f0b78aad7625f 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -337,6 +337,18 @@ config PWM_INTEL_LGM To compile this driver as a module, choose M here: the module will be called pwm-intel-lgm. =20 +config PWM_IPQ + tristate "IPQ PWM support" + depends on ARCH_QCOM || COMPILE_TEST + depends on HAVE_CLK && HAS_IOMEM + help + Generic PWM framework driver for IPQ PWM block which supports + 4 pwm channels. Each of the these channels can be configured + independent of each other. + + To compile this driver as a module, choose M here: the module + will be called pwm-ipq. + config PWM_IQS620A tristate "Azoteq IQS620A PWM support" depends on MFD_IQS62X || COMPILE_TEST diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index aed403f0a42b339778c37150007635d7efccfd51..8611373257cb88e1b4f762b15a5= 9ff265aff0173 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -28,6 +28,7 @@ obj-$(CONFIG_PWM_IMX1) +=3D pwm-imx1.o obj-$(CONFIG_PWM_IMX27) +=3D pwm-imx27.o obj-$(CONFIG_PWM_IMX_TPM) +=3D pwm-imx-tpm.o obj-$(CONFIG_PWM_INTEL_LGM) +=3D pwm-intel-lgm.o +obj-$(CONFIG_PWM_IPQ) +=3D pwm-ipq.o obj-$(CONFIG_PWM_IQS620A) +=3D pwm-iqs620a.o obj-$(CONFIG_PWM_JZ4740) +=3D pwm-jz4740.o obj-$(CONFIG_PWM_KEEMBAY) +=3D pwm-keembay.o diff --git a/drivers/pwm/pwm-ipq.c b/drivers/pwm/pwm-ipq.c new file mode 100644 index 0000000000000000000000000000000000000000..bd6b3ad86596e3c5b19f80f97fe= 7913a8ce2d940 --- /dev/null +++ b/drivers/pwm/pwm-ipq.c @@ -0,0 +1,212 @@ +// SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 +/* + * Copyright (c) 2016-2017, 2020 The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* The frequency range supported is 1 Hz to clock rate */ +#define IPQ_PWM_MAX_PERIOD_NS ((u64)NSEC_PER_SEC) + +/* + * The max value specified for each field is based on the number of bits + * in the pwm control register for that field + */ +#define IPQ_PWM_MAX_DIV 0xFFFF + +/* + * Two 32-bit registers for each PWM: REG0, and REG1. + * Base offset for PWM #i is at 8 * #i. + */ +#define IPQ_PWM_REG0 0 +#define IPQ_PWM_REG0_PWM_DIV GENMASK(15, 0) +#define IPQ_PWM_REG0_HI_DURATION GENMASK(31, 16) + +#define IPQ_PWM_REG1 4 +#define IPQ_PWM_REG1_PRE_DIV GENMASK(15, 0) +/* + * Enable bit is set to enable output toggling in pwm device. + * Update bit is set to reflect the changed divider and high duration + * values in register. + */ +#define IPQ_PWM_REG1_UPDATE BIT(30) +#define IPQ_PWM_REG1_ENABLE BIT(31) + +struct ipq_pwm_chip { + struct clk *clk; + void __iomem *mem; +}; + +static struct ipq_pwm_chip *ipq_pwm_from_chip(struct pwm_chip *chip) +{ + return pwmchip_get_drvdata(chip); +} + +static unsigned int ipq_pwm_reg_read(struct pwm_device *pwm, unsigned int = reg) +{ + struct ipq_pwm_chip *ipq_chip =3D ipq_pwm_from_chip(pwm->chip); + unsigned int off =3D 8 * pwm->hwpwm + reg; + + return readl(ipq_chip->mem + off); +} + +static void ipq_pwm_reg_write(struct pwm_device *pwm, unsigned int reg, + unsigned int val) +{ + struct ipq_pwm_chip *ipq_chip =3D ipq_pwm_from_chip(pwm->chip); + unsigned int off =3D 8 * pwm->hwpwm + reg; + + writel(val, ipq_chip->mem + off); +} + +static void config_div_and_duty(struct pwm_device *pwm, unsigned int pre_d= iv, + unsigned int pwm_div, unsigned long rate, u64 duty_ns, + bool enable) +{ + unsigned long hi_dur; + unsigned long val =3D 0; + + /* + * high duration =3D pwm duty * (pwm div + 1) + * pwm duty =3D duty_ns / period_ns + */ + hi_dur =3D div64_u64(duty_ns * rate, (pre_div + 1) * NSEC_PER_SEC); + + val =3D FIELD_PREP(IPQ_PWM_REG0_HI_DURATION, hi_dur) | + FIELD_PREP(IPQ_PWM_REG0_PWM_DIV, pwm_div); + ipq_pwm_reg_write(pwm, IPQ_PWM_REG0, val); + + val =3D FIELD_PREP(IPQ_PWM_REG1_PRE_DIV, pre_div); + ipq_pwm_reg_write(pwm, IPQ_PWM_REG1, val); + + /* PWM enable toggle needs a separate write to REG1 */ + val |=3D IPQ_PWM_REG1_UPDATE; + if (enable) + val |=3D IPQ_PWM_REG1_ENABLE; + ipq_pwm_reg_write(pwm, IPQ_PWM_REG1, val); +} + +static int ipq_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, + const struct pwm_state *state) +{ + struct ipq_pwm_chip *ipq_chip =3D ipq_pwm_from_chip(chip); + unsigned long rate =3D clk_get_rate(ipq_chip->clk); + unsigned int pre_div, pwm_div; + u64 period_ns, duty_ns; + + if (state->polarity !=3D PWM_POLARITY_NORMAL) + return -EINVAL; + + if (state->period < DIV64_U64_ROUND_UP(NSEC_PER_SEC, rate)) + return -ERANGE; + + if ((unsigned long long)rate > 16ULL * GIGA) + return -EINVAL; + + period_ns =3D min(state->period, IPQ_PWM_MAX_PERIOD_NS); + duty_ns =3D min(state->duty_cycle, period_ns); + + /* Restrict pwm_div to 0xfffe */ + pwm_div =3D IPQ_PWM_MAX_DIV - 1; + pre_div =3D DIV64_U64_ROUND_UP(period_ns * rate, (u64)NSEC_PER_SEC * (pwm= _div + 1)); + + if (pre_div > IPQ_PWM_MAX_DIV) + return -ERANGE; + + config_div_and_duty(pwm, pre_div, pwm_div, rate, duty_ns, state->enabled); + + return 0; +} + +static int ipq_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, + struct pwm_state *state) +{ + struct ipq_pwm_chip *ipq_chip =3D ipq_pwm_from_chip(chip); + unsigned long rate =3D clk_get_rate(ipq_chip->clk); + unsigned int pre_div, pwm_div, hi_dur; + u64 effective_div, hi_div; + u32 reg0, reg1; + + reg0 =3D ipq_pwm_reg_read(pwm, IPQ_PWM_REG0); + reg1 =3D ipq_pwm_reg_read(pwm, IPQ_PWM_REG1); + + state->polarity =3D PWM_POLARITY_NORMAL; + state->enabled =3D reg1 & IPQ_PWM_REG1_ENABLE; + + pwm_div =3D FIELD_GET(IPQ_PWM_REG0_PWM_DIV, reg0); + hi_dur =3D FIELD_GET(IPQ_PWM_REG0_HI_DURATION, reg0); + pre_div =3D FIELD_GET(IPQ_PWM_REG1_PRE_DIV, reg1); + + /* No overflow here, both pre_div and pwm_div <=3D 0xffff */ + effective_div =3D (pre_div + 1) * (pwm_div + 1); + state->period =3D DIV64_U64_ROUND_UP(effective_div * NSEC_PER_SEC, rate); + + hi_div =3D hi_dur * (pre_div + 1); + state->duty_cycle =3D DIV64_U64_ROUND_UP(hi_div * NSEC_PER_SEC, rate); + + return 0; +} + +static const struct pwm_ops ipq_pwm_ops =3D { + .apply =3D ipq_pwm_apply, + .get_state =3D ipq_pwm_get_state, +}; + +static int ipq_pwm_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct ipq_pwm_chip *pwm; + struct pwm_chip *chip; + int ret; + + chip =3D devm_pwmchip_alloc(dev, 4, sizeof(*pwm)); + if (IS_ERR(chip)) + return PTR_ERR(chip); + pwm =3D ipq_pwm_from_chip(chip); + + pwm->mem =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(pwm->mem)) + return dev_err_probe(dev, PTR_ERR(pwm->mem), + "regs map failed"); + + pwm->clk =3D devm_clk_get_enabled(dev, NULL); + if (IS_ERR(pwm->clk)) + return dev_err_probe(dev, PTR_ERR(pwm->clk), + "failed to get clock"); + + chip->ops =3D &ipq_pwm_ops; + chip->npwm =3D 4; + + ret =3D devm_pwmchip_add(dev, chip); + if (ret < 0) + return dev_err_probe(dev, ret, "failed to add pwm chip\n"); + + return ret; +} + +static const struct of_device_id pwm_ipq_dt_match[] =3D { + { .compatible =3D "qcom,ipq6018-pwm", }, + {} +}; +MODULE_DEVICE_TABLE(of, pwm_ipq_dt_match); + +static struct platform_driver ipq_pwm_driver =3D { + .driver =3D { + .name =3D "ipq-pwm", + .of_match_table =3D pwm_ipq_dt_match, + }, + .probe =3D ipq_pwm_probe, +}; + +module_platform_driver(ipq_pwm_driver); + +MODULE_LICENSE("GPL"); --=20 2.51.1 From nobody Mon Dec 15 18:45:06 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 58A943112B6; Wed, 29 Oct 2025 08:37:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251029-ipq-pwm-v18-3-edbef8efbb8e@outlook.com> References: <20251029-ipq-pwm-v18-0-edbef8efbb8e@outlook.com> In-Reply-To: <20251029-ipq-pwm-v18-0-edbef8efbb8e@outlook.com> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Baruch Siach , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, George Moussalem , Devi Priya , Baruch Siach , Krzysztof Kozlowski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1761727035; l=1391; i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; bh=atW+yJDrnsJeLsNipKDdbSHJZ/mFlqUkSThj04bN9Yg=; b=w8NUtghJxEofwj0/TJP6pVqkXTsDYfGD5sKOjlnfYHfbQta/IIsGC7lFuMye7YfHSzozQpM4b wSRl/z9MzSWAdJK1hiEA5japGoHAS/lW5+qZZOfi+SGZK+s15j2GDWs X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 with auth_id=364 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: Devi Priya Describe the PWM block on IPQ6018. Although PWM is in the TCSR area, make pwm its own node as simple-mfd has been removed from the bindings and as such hardware components should have its own node. Reviewed-by: Krzysztof Kozlowski Co-developed-by: Baruch Siach Signed-off-by: Baruch Siach Signed-off-by: Devi Priya Signed-off-by: George Moussalem --- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qc= om/ipq6018.dtsi index 40f1c262126eff3761430a47472b52d27f961040..7925c9a6b0dcff9e3157dd9de01= fbc2d240486a4 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -413,6 +413,16 @@ tcsr: syscon@1937000 { reg =3D <0x0 0x01937000 0x0 0x21000>; }; =20 + pwm: pwm@1941010 { + compatible =3D "qcom,ipq6018-pwm"; + reg =3D <0x0 0x01941010 0x0 0x20>; + clocks =3D <&gcc GCC_ADSS_PWM_CLK>; + assigned-clocks =3D <&gcc GCC_ADSS_PWM_CLK>; + assigned-clock-rates =3D <100000000>; + #pwm-cells =3D <2>; + status =3D "disabled"; + }; + usb2: usb@70f8800 { compatible =3D "qcom,ipq6018-dwc3", "qcom,dwc3"; reg =3D <0x0 0x070f8800 0x0 0x400>; --=20 2.51.1 From nobody Mon Dec 15 18:45:06 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 589AA30B533; Wed, 29 Oct 2025 08:37:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761727038; cv=none; b=X7ijjvkWSF+sMLtmE+XHdwMjfyVwGdBqylG5h0FeSJzlODz1qTuF+cp4X9zgAyw/zTdnu8DxexlhOU5ga6z1LEPjov7yaL5gKN7A0236iKhRJRVgI0rK3+aFOBZ2exJHTmB33N2wlHERrsp2UVCzsHgcjqylytYbcaZPUJIn3y8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761727038; c=relaxed/simple; bh=GJAfy7iKEcJpEfXRc0Uu3ufFD0wbM4VeuQSosfa52Vc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=pWfWCUBD6g+Xch+vT6yUCs9Y+GVR7fxxE8FnaEC5vzzPkOkxG5jctbjdlIaZs2JApfB9UnTrxi88dbM++tqF6s8bg3oPLrBnFSnmsjANCHkIOTRgp3FawOTgAJEaSdjhwyi9RdutYN0iwZ9DK9e38kXu89h9ApfA2YXL+uqiWK0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=KsVsks/x; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="KsVsks/x" Received: by smtp.kernel.org (Postfix) with ESMTPS id 20417C4CEF7; Wed, 29 Oct 2025 08:37:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1761727038; bh=GJAfy7iKEcJpEfXRc0Uu3ufFD0wbM4VeuQSosfa52Vc=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=KsVsks/xdOve8Ep3E7YiKEdtxIfVorqAFAjiViyiO84OIfEXvNzGW3qpSlPgLD9g+ IoEgoySO6BKqriHq8zv4BM1GtlegxIBor0XfJjuaWoMeU1hdjUBbeULMBfHWbjMXSA STSf6sDPqX1sEC488KpYMZ8Wta5mo21o/WSq+i6UGWKwpRuZ4fl1DShzJRUFW4K39W awaaAH0WO6zxJj1tgxMs1uNhheeD5Kbf5fd/DtnxuydCgtncewcnVSZZnbo/u3Onrq C/7+z4D9rumnpBsw+gwNbRPMIi1xqt9DlTqLvtLY5STdOZ/vFvlSSilE3dcK0AsDqY hrV4RP/nOqDNA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 169B4CCF9F6; Wed, 29 Oct 2025 08:37:18 +0000 (UTC) From: George Moussalem via B4 Relay Date: Wed, 29 Oct 2025 12:37:00 +0400 Subject: [PATCH v18 4/6] arm64: dts: qcom: ipq5018: add pwm node Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251029-ipq-pwm-v18-4-edbef8efbb8e@outlook.com> References: <20251029-ipq-pwm-v18-0-edbef8efbb8e@outlook.com> In-Reply-To: <20251029-ipq-pwm-v18-0-edbef8efbb8e@outlook.com> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Baruch Siach , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, George Moussalem , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1761727035; l=1233; i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; bh=+/1aXltD7q4tXAN+T3JtxPoncHcVNEKWMgEN9+0w1GA=; b=i3q1JE/4S1Tu1RWYInUDD8rmTZiDQocGH8conPr4Kla25HlnvgknFXIl5hu+YjWdHlHwCAKnK qgNOdez+TAhBDSeSSv0mVHXGVGw4srRUmA1iRmbFSEUiaTMUaw6GTt0 X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 with auth_id=364 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: George Moussalem Describe the PWM block on IPQ5018. Although PWM is in the TCSR area, make pwm its own node as simple-mfd has been removed from the bindings and as such hardware components should have its own node. Reviewed-by: Dmitry Baryshkov Signed-off-by: George Moussalem --- arch/arm64/boot/dts/qcom/ipq5018.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qc= om/ipq5018.dtsi index f024b3cba33f6100ac3f4d45598ff2356e026dcf..d4bdf2884aa7f73711cf8a37b7a= 4c4e7e54c503c 100644 --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi @@ -453,6 +453,16 @@ tcsr: syscon@1937000 { reg =3D <0x01937000 0x21000>; }; =20 + pwm: pwm@1941010 { + compatible =3D "qcom,ipq5018-pwm", "qcom,ipq6018-pwm"; + reg =3D <0x01941010 0x20>; + clocks =3D <&gcc GCC_ADSS_PWM_CLK>; + assigned-clocks =3D <&gcc GCC_ADSS_PWM_CLK>; + assigned-clock-rates =3D <100000000>; + #pwm-cells =3D <2>; + status =3D "disabled"; + }; + sdhc_1: mmc@7804000 { compatible =3D "qcom,ipq5018-sdhci", "qcom,sdhci-msm-v5"; reg =3D <0x7804000 0x1000>; --=20 2.51.1 From nobody Mon Dec 15 18:45:06 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A31F8314B72; Wed, 29 Oct 2025 08:37:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761727038; cv=none; b=YDTfXKFT1qRGs4Jcekb8SVosMLC1MLypgqkbvwfjqOAsVrG43LX8CmIW1+c4DW5KVQcF+0Jzv29ln18gXC9P8Oc/jJeZNIJkNdFjDVFfJvIOw3MilpG7JfAti6MQFG38YdVXZw3bl4/zRYM45rr8JkDajev8NfeS+hC2E45hKj4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761727038; c=relaxed/simple; bh=fL1x1mnIPGe9KAdv1TNu7o+YjQMNVpX1h/iR0w/TSJs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ZTsP/7VIZ02UE5ofWdmFxMsBAI+F+8cpz6DjYzkKSJIGJTU30PlRFdkwlSlMis2QXZcn9lzi8tNrrEyc/jVWWNcqSmEOLhC619bV9doPaCf/2JUKxJY7Rm2P3XvhwiB2INWXdzLuLTJRVubrtFUeqjH+rZZ6N/9qHBaa0Ws+0PE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ItDWNfS/; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ItDWNfS/" Received: by smtp.kernel.org (Postfix) with ESMTPS id 32E6DC19424; Wed, 29 Oct 2025 08:37:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1761727038; bh=fL1x1mnIPGe9KAdv1TNu7o+YjQMNVpX1h/iR0w/TSJs=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=ItDWNfS/WK7HKyXNC22EEZGL5N13cc/vr6cEgiXdwBjDwRlpeTZD8k3iSRgcuzjGn PUCTLWhzKw7U8vat8fhRvjEMDkn4TX0f1akrygKTupTrVjUqsMRCvQQj4S0FtMQy9g pYISwcif/sUghqir26c25E8jw990Aip1DzaUq/GaMg60TabhXsfv9+TWyFchzRLuod 8VfD59rXi3rewCBgH9c0/s1sQFUYjcdHtLMWuhgwXldtwEvnOxAOJNzEjQaRS3u6w+ yNHHyFgMQfJbk2RkmJHENqe3Ecc/9ZkEYZ1/Er0LG2Uv34oR/iAIjPWb/Ch57Dm8Cb V1MYXV7+TlRUQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 27BCECCF9E9; Wed, 29 Oct 2025 08:37:18 +0000 (UTC) From: George Moussalem via B4 Relay Date: Wed, 29 Oct 2025 12:37:01 +0400 Subject: [PATCH v18 5/6] arm64: dts: qcom: ipq5332: add pwm node Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251029-ipq-pwm-v18-5-edbef8efbb8e@outlook.com> References: <20251029-ipq-pwm-v18-0-edbef8efbb8e@outlook.com> In-Reply-To: <20251029-ipq-pwm-v18-0-edbef8efbb8e@outlook.com> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Baruch Siach , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, George Moussalem , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1761727035; l=1253; i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; bh=1ZzS7PizDZ8r2SLfXGWgikFAfQuCYtJt9bX6cccE5Pg=; b=l0+bANDB7GpTv6ZGkRwIMmcjY9SC9v/vuzOHek0LXwUB6Z0oQILG9OFMxkaxtJhc6u+kn5PcV Po7gRRuEis3CjHkqVT3VS/POqCCF5tynBqkz3diztio9FrkJ22JaGbk X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 with auth_id=364 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: George Moussalem Describe the PWM block on IPQ5332. Although PWM is in the TCSR area, make pwm its own node as simple-mfd has been removed from the bindings and as such hardware components should have its own node. Reviewed-by: Dmitry Baryshkov Signed-off-by: George Moussalem --- arch/arm64/boot/dts/qcom/ipq5332.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qc= om/ipq5332.dtsi index 45fc512a3bab221c0d99f819294abf63369987da..4ff6e38521ed94fac0f4caac5c5= b0d9be3704d7e 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi @@ -334,6 +334,16 @@ tcsr: syscon@1937000 { reg =3D <0x01937000 0x21000>; }; =20 + pwm: pwm@1941010 { + compatible =3D "qcom,ipq5332-pwm", "qcom,ipq6018-pwm"; + reg =3D <0x01941010 0x20>; + clocks =3D <&gcc GCC_ADSS_PWM_CLK>; + assigned-clocks =3D <&gcc GCC_ADSS_PWM_CLK>; + assigned-clock-rates =3D <100000000>; + #pwm-cells =3D <2>; + status =3D "disabled"; + }; + sdhc: mmc@7804000 { compatible =3D "qcom,ipq5332-sdhci", "qcom,sdhci-msm-v5"; reg =3D <0x07804000 0x1000>, <0x07805000 0x1000>; --=20 2.51.1 From nobody Mon Dec 15 18:45:06 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A371C314B77; Wed, 29 Oct 2025 08:37:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761727038; cv=none; b=g2Ea0b9edgA0QIabov09oZ15A5BXobsUTAUlgKCHihl8Io8DpzKzwzaJxfEfZQxKL5/HDXfgJvLUg/OlwSa4nidO68vbZ4oZtTAhyh/WelH2YxBBR5JyE48odCCFVDLMZ8GxKeuWY+5ua8ZMHZ26ttzs6a/xbh4qNVaFIOnOb3M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761727038; c=relaxed/simple; bh=6qW85vJpsbRJXw1O0YT5oAnSuUBGMKsjU9actwwSC/Y=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=kQJAtfnlpkjAY6pG7Br281sXoJGC23pMhZaHByWA2CLYR41JUWlKBx99Y55qjXans5XhPMurMpRxpjfQQCqGqVlEJkOd8vbMk74II/LsaU7o2OwGiomQEbSCttLcQRyFtgck0RiyYEVjySl0O0uYW0apiuH7DiWDdt/lSQZJcec= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=P8iKZL/c; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="P8iKZL/c" Received: by smtp.kernel.org (Postfix) with ESMTPS id 400F6C19421; Wed, 29 Oct 2025 08:37:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1761727038; bh=6qW85vJpsbRJXw1O0YT5oAnSuUBGMKsjU9actwwSC/Y=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=P8iKZL/cIwO0RM51lYB3A481gBJcA8zzScDjJZUCI7ptVD4V4iikdRzXdgDJF+NQv LALPyM3SHe6qFxZUwyP7Ib8RbadQliIim8OAcEDxS/lm7Sq0PkbC/eyxNbWtuY3WVE /Jjr34RDMpHv9X0jdpRKQDF8AbdOMllm/Lq2bdthIgdCB5lAwh2dCZcLul0Jm3hQRE ZKaWung2va2PbE9QnrNXOB7Ii74k9dtX7T2OWksuGQvzWcN40wLsOmA+YROOW4wy3C g7sLUx5MDEjvOr6xJM2pO4GGniurhckcxVEHeUMS/XFqmLYlxdWN4nG9f0QAUUkYPB +/NackzOlaVMQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 361BFCCF9F5; Wed, 29 Oct 2025 08:37:18 +0000 (UTC) From: George Moussalem via B4 Relay Date: Wed, 29 Oct 2025 12:37:02 +0400 Subject: [PATCH v18 6/6] arm64: dts: qcom: ipq9574: add pwm node Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251029-ipq-pwm-v18-6-edbef8efbb8e@outlook.com> References: <20251029-ipq-pwm-v18-0-edbef8efbb8e@outlook.com> In-Reply-To: <20251029-ipq-pwm-v18-0-edbef8efbb8e@outlook.com> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Baruch Siach , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, George Moussalem , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1761727035; l=1234; i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; bh=YRF2XaROzhwVt/Pu0p6PQImVfL/oaIfrTBMqULFpuLg=; b=b+tdYlgh5p3xWcAR2IF0eHikC5VbtzjET/JgkRJKq/yVMg2MiwEi/UwFwyz4feZ3iaT4/fvhh 4XHBb5sIWsPDvnUTOArWicqId7AhW4OtI/xRD2MsfGsEDIKahPiBXnJ X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 with auth_id=364 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: George Moussalem Describe the PWM block on IPQ9574. Although PWM is in the TCSR area, make pwm its own node as simple-mfd has been removed from the bindings and as such hardware components should have its own node. Reviewed-by: Dmitry Baryshkov Signed-off-by: George Moussalem --- arch/arm64/boot/dts/qcom/ipq9574.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qc= om/ipq9574.dtsi index 86c9cb9fffc98fdd1b0b08e81428ce5e7bb87e17..8dba80d76d609a317a66f514c64= ab8f5612e6938 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -449,6 +449,16 @@ tcsr: syscon@1937000 { reg =3D <0x01937000 0x21000>; }; =20 + pwm: pwm@1941010 { + compatible =3D "qcom,ipq9574-pwm", "qcom,ipq6018-pwm"; + reg =3D <0x01941010 0x20>; + clocks =3D <&gcc GCC_ADSS_PWM_CLK>; + assigned-clocks =3D <&gcc GCC_ADSS_PWM_CLK>; + assigned-clock-rates =3D <100000000>; + #pwm-cells =3D <2>; + status =3D "disabled"; + }; + sdhc_1: mmc@7804000 { compatible =3D "qcom,ipq9574-sdhci", "qcom,sdhci-msm-v5"; reg =3D <0x07804000 0x1000>, --=20 2.51.1