From nobody Sun Feb 8 21:42:19 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A94E95227; Wed, 29 Oct 2025 15:51:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761753105; cv=none; b=EZq0WjZTkxBVVhJITIvkbR4gmwCR3rdlYxBj4ZExI+z947cfKZxsCcUbnJKlUjL4rvBH8Jl2gQTkTSZh1muj47wQ3LFTR4qzF4XB3EV9+QTlv7GpU9vM0o6PD92OkzR0R1QsAij6rktwzQHKFT2yNFxhvhfVdEZg4+MJZjiOiNs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761753105; c=relaxed/simple; bh=ZKAuhcvGiMxkVSfeD/IFEzXCfmgMtELVjkUql9TTJWA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=UsM2knWkxUc+qiIEbsY64UvqhwMWSbAlAeAPQga52rCj/dyg7m+u9ff74l48grKr4SK23zf3iUZRRv/zbRWTjfI3dzbMBtn8Vh87QJzRI1Z/UH+EMB33j6tBiFZsElRXaiE6ZTAVqz0O+/wS+LJqci4Y71+qqzaUL1EBBrYw+dU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=xMSZDXe7; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="xMSZDXe7" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1761753103; x=1793289103; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=ZKAuhcvGiMxkVSfeD/IFEzXCfmgMtELVjkUql9TTJWA=; b=xMSZDXe7jb3e5heGw4r0VdrQnrAgLrinXhz/Hz9IcXXV4BzplSTflnrf s5URZ4QyRxXxFtrrjyDbzDPiI0XsMDVNlqmcxWSfYcJfrdBc+D4/JRVN+ NX93DhAT0gWJe4cWD/DerK77DCn4HrzFSmh3p3HfRAdgsrB6Vj4BOrVNF 0vIo2XtRHmS1RqaDuaSoBsWooHzN1WuQSx9K9uBN9DZQJps+YH8SvXMFR SSnn/MYYGNFYjmDvUyOlYetXWJDAWLFpe1RKqgYn6DXke3jFUnqL81O7x fCL1lSEJrDLokuz8HeH+Y1ncCd82MOzsgmFI6Q8hraGk/sG03+WqFbrDb g==; X-CSE-ConnectionGUID: iyBWzYvURAWNjcJpeOx0pg== X-CSE-MsgGUID: LQIPOVeNQw6DPkGEZJ6fLQ== X-IronPort-AV: E=Sophos;i="6.19,264,1754982000"; d="scan'208";a="54712635" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Oct 2025 08:51:42 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.87.72) by chn-vm-ex2.mchp-main.com (10.10.87.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.2.2562.29; Wed, 29 Oct 2025 08:51:12 -0700 Received: from marius-VM.mshome.net (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Wed, 29 Oct 2025 08:51:10 -0700 From: Marius Cristea Date: Wed, 29 Oct 2025 17:50:58 +0200 Subject: [PATCH 1/2] dt-bindings: hwmon: temperature: add support for EMC1812 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20251029-hw_mon-emc1812-v1-1-be4fd8af016a@microchip.com> References: <20251029-hw_mon-emc1812-v1-0-be4fd8af016a@microchip.com> In-Reply-To: <20251029-hw_mon-emc1812-v1-0-be4fd8af016a@microchip.com> To: Guenter Roeck , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonathan Corbet CC: , , , , Marius Cristea X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=5901; i=marius.cristea@microchip.com; h=from:subject:message-id; bh=ZKAuhcvGiMxkVSfeD/IFEzXCfmgMtELVjkUql9TTJWA=; b=owGbwMvMwCW2tbSTZa7u0x2Mp9WSGDKZzF8dFE57LcAzw14iwzvlJo9Yz8YDDPb22Z5reWJle F/OiK/pKGVhEONikBVTZFnx1k+tau2Hy0pimTowc1iZQIYwcHEKwEQ+HmRkaA6f5rRu/VP3dl2D Lzbtvy7tiBF3+D3nxKajoroSP/cw7GVkOFH0auutAqNdZ6YdPOkhOXvaUuvG2cYd2bt/WxQdrXS PZwEA X-Developer-Key: i=marius.cristea@microchip.com; a=openpgp; fpr=E32F8D4396E72E463E8CCD91446DE0ABD9140C3E This is the devicetree schema for Microchip EMC1812/13/14/15/33 Multichannel Low-Voltage Remote Diode Sensor Family. Signed-off-by: Marius Cristea --- .../bindings/hwmon/microchip,emc1812.yaml | 176 +++++++++++++++++= ++++ MAINTAINERS | 6 + 2 files changed, 182 insertions(+) diff --git a/Documentation/devicetree/bindings/hwmon/microchip,emc1812.yaml= b/Documentation/devicetree/bindings/hwmon/microchip,emc1812.yaml new file mode 100644 index 0000000000000000000000000000000000000000..cc4c7bb53cb13416c1e9419cc8c= 6c8a56da22df8 --- /dev/null +++ b/Documentation/devicetree/bindings/hwmon/microchip,emc1812.yaml @@ -0,0 +1,176 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/hwmon/microchip,emc1812.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip EMC1812/13/14/15/33 multichannel temperature sensor + +maintainers: + - Marius Cristea + +description: | + The Microchip EMC1812/13/14/15/33 is a high-accuracy 2-wire multichannel + low-voltage remote diode temperature monitor. + + The datasheet can be found here: + https://ww1.microchip.com/downloads/aemDocuments/documents/MSLD/Produc= tDocuments/DataSheets/EMC1812-3-4-5-33-Data-Sheet-DS20005751.pdf + +properties: + compatible: + enum: + - microchip,emc1812 + - microchip,emc1813 + - microchip,emc1814 + - microchip,emc1815 + - microchip,emc1833 + + reg: + maxItems: 1 + + interrupts: + maxItems: 2 + + interrupt-names: + description: + -alert-therm2 asserts when a diode temperature exceeds the ALERT + threshold. + -therm-addr asserts low when the hardware-set THERM limit threshold = is + exceeded by one of the temperature sensors. + items: + - const: alert-therm2 + - const: therm-addr + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + microchip,parasitic-res-on-channel1-2: + description: + Indicates that the chip and the diodes/transistors are sufficiently + far apart that a parasitic resistance is added to the wires, which c= an + affect the measurements. Due to the anti-parallel diode connections, + channels 1 and 2 are affected together. + type: boolean + + microchip,parasitic-res-on-channel3-4: + description: + Indicates that the chip and the diodes/transistors are sufficiently = far + apart that a parasitic resistance is added to the wires, which can a= ffect + the measurements. Due to the anti-parallel diode connections, channe= ls + 3 and 4 are affected together. + type: boolean + + vdd-supply: true + +patternProperties: + "^channel@[1-4]$": + description: + Represents the external temperature channels to which + a remote diode is connected. + type: object + + properties: + reg: + items: + minimum: 1 + maximum: 4 + + label: + description: Unique name to identify which channel this is. + + required: + - reg + + additionalProperties: false + +required: + - compatible + - reg + - vdd-supply + +allOf: + - if: + properties: + compatible: + contains: + enum: + - microchip,emc1812 + - microchip,emc1813 + - microchip,emc1833 + then: + properties: + microchip,parasitic-res-on-channel3-4: false + - if: + properties: + compatible: + contains: + enum: + - microchip,emc1812 + then: + properties: + channel@1: + properties: + reg: + items: + const: 1 + patternProperties: + "^channel@[2-4]$": false + - if: + properties: + compatible: + pattern: "^microchip,emc18[13]3" + then: + patternProperties: + "^channel@[12]$": + properties: + reg: + items: + maximum: 2 + "^channel@[34]$": false + - if: + properties: + compatible: + pattern: "^microchip,emc1814" + then: + patternProperties: + "^channel@[1-3]$": + properties: + reg: + items: + maximum: 3 + properties: + channel@4: false + +additionalProperties: false + +examples: + - | + i2c { + #address-cells =3D <1>; + #size-cells =3D <0>; + + temperature-sensor@4c { + compatible =3D "microchip,emc1813"; + reg =3D <0x4c>; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + microchip,parasitic-res-on-channel1-2; + + vdd-supply =3D <&vdd>; + + channel@1 { + reg =3D <1>; + label =3D "External CH1 Temperature"; + }; + + channel@2 { + reg =3D <2>; + label =3D "External CH2 Temperature"; + }; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 6d7b697bfdba16e4f0ee5f4f0195b9d7da06dae5..85c236df781e47c78deeb7ef4d8= 0bc94bba604c4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -16646,6 +16646,12 @@ S: Supported F: Documentation/devicetree/bindings/interrupt-controller/microchip,sama7g= 5-eic.yaml F: drivers/irqchip/irq-mchp-eic.c =20 +MICROCHIP EMC1812 DRIVER +M: Marius Cristea +L: linux-hwmon@vger.kernel.org +S: Supported +F: Documentation/devicetree/bindings/hwmon/microchip,emc1812.yaml + MICROCHIP I2C DRIVER M: Codrin Ciubotariu L: linux-i2c@vger.kernel.org --=20 2.48.1 From nobody Sun Feb 8 21:42:19 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7B27732BF3D; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20251029-hw_mon-emc1812-v1-2-be4fd8af016a@microchip.com> References: <20251029-hw_mon-emc1812-v1-0-be4fd8af016a@microchip.com> In-Reply-To: <20251029-hw_mon-emc1812-v1-0-be4fd8af016a@microchip.com> To: Guenter Roeck , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonathan Corbet CC: , , , , Marius Cristea X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=35595; i=marius.cristea@microchip.com; h=from:subject:message-id; bh=1IDdOpeFlq0bn2+3tK04M34Fqe0y9mYhrBdVMI+8xEM=; b=owGbwMvMwCW2tbSTZa7u0x2Mp9WSGDKZzF/LbeOv+dErkZB+7/SiKw8P7Vt+06TzeXKu5T6WW 9IaG00aOkpZGMS4GGTFFFlWvPVTq1r74bKSWKYOzBxWJpAhDFycAjAR55OMDJd4tleG+Hx5kuvz TUxycU//lmVuM+fZnxDmqj+ZNqew8jvD/zCHXy6vBG89vLF7qS6v3ZrTGjOntZXEleh3eB9/pn9 TkRkA X-Developer-Key: i=marius.cristea@microchip.com; a=openpgp; fpr=E32F8D4396E72E463E8CCD91446DE0ABD9140C3E This is the hwmon driver for Microchip EMC1812/13/14/15/33 Multichannel Low-Voltage Remote Diode Sensor Family. Signed-off-by: Marius Cristea --- Documentation/hwmon/emc1812.rst | 68 +++ MAINTAINERS | 2 + drivers/hwmon/Kconfig | 11 + drivers/hwmon/Makefile | 1 + drivers/hwmon/emc1812.c | 967 ++++++++++++++++++++++++++++++++++++= ++++ 5 files changed, 1049 insertions(+) diff --git a/Documentation/hwmon/emc1812.rst b/Documentation/hwmon/emc1812.= rst new file mode 100644 index 0000000000000000000000000000000000000000..799111a89541c57a839a121bb3d= fc12f42604bc2 --- /dev/null +++ b/Documentation/hwmon/emc1812.rst @@ -0,0 +1,68 @@ +.. SPDX-License-Identifier: GPL-2.0-or-later + +Kernel driver emc1802 +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +Supported chips: + + * Microchip EMC1812, EMC1813, EMC1814, EMC1815, EMC1833 + + Addresses scanned: I2C 0x1c, 0x3c, 0x4c, 0x4d, 0x5c, 0x6c, 0x7c + + Prefix: 'emc1812' + + Datasheets: + + - https://ww1.microchip.com/downloads/aemDocuments/documents/MSLD/Product= Documents/DataSheets/EMC1812-3-4-5-33-Data-Sheet-DS20005751.pdf + +Author: + Marius Cristea L: linux-hwmon@vger.kernel.org S: Supported F: Documentation/devicetree/bindings/hwmon/microchip,emc1812.yaml +F: Documentation/hwmon/emc1812.rst +F: drivers/hwmon/emc1812.c =20 MICROCHIP I2C DRIVER M: Codrin Ciubotariu diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig index 2760feb9f83b5d3b990b27acff572e587b373e9d..3b53572fd8bfbd752c2235ca429= c4f74b1db3095 100644 --- a/drivers/hwmon/Kconfig +++ b/drivers/hwmon/Kconfig @@ -2042,6 +2042,17 @@ config SENSORS_EMC1403 Threshold values can be configured using sysfs. Data from the different diodes are accessible via sysfs. =20 +config SENSORS_EMC1812 + tristate "Microchip Technology EMC1812 driver" + depends on I2C + select REGMAP_I2C + help + If you say yes here to build support for Microchip Technology's + EMC181X/33 Multichannel Low-Voltage Remote Diode Sensor Family. + + This driver can also be built as a module. If so, the module + will be called emc1812. + config SENSORS_EMC2103 tristate "SMSC EMC2103" depends on I2C diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile index 73b2abdcc6dd9cfae4c84b350febc5d8c191e385..e93e4051e99db698dbaae97ac48= 41e6d810ee8c4 100644 --- a/drivers/hwmon/Makefile +++ b/drivers/hwmon/Makefile @@ -73,6 +73,7 @@ obj-$(CONFIG_SENSORS_DRIVETEMP) +=3D drivetemp.o obj-$(CONFIG_SENSORS_DS620) +=3D ds620.o obj-$(CONFIG_SENSORS_DS1621) +=3D ds1621.o obj-$(CONFIG_SENSORS_EMC1403) +=3D emc1403.o +obj-$(CONFIG_SENSORS_EMC1812) +=3D emc1812.o obj-$(CONFIG_SENSORS_EMC2103) +=3D emc2103.o obj-$(CONFIG_SENSORS_EMC2305) +=3D emc2305.o obj-$(CONFIG_SENSORS_EMC6W201) +=3D emc6w201.o diff --git a/drivers/hwmon/emc1812.c b/drivers/hwmon/emc1812.c new file mode 100644 index 0000000000000000000000000000000000000000..78038dace1fd218346beae7c7d7= 447f68072d0f4 --- /dev/null +++ b/drivers/hwmon/emc1812.c @@ -0,0 +1,967 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * HWMON driver for Microchip EMC1812/13/14/15/33 Multichannel high-accura= cy + * 2-wire low-voltage remote diode temperature monitor family. + * + * Copyright (C) 2025 Microchip Technology Inc. and its subsidiaries + * + * Author: Marius Cristea + * + * Datasheet can be found here: + * https://ww1.microchip.com/downloads/aemDocuments/documents/MSLD/Product= Documents/DataSheets/EMC1812-3-4-5-33-Data-Sheet-DS20005751.pdf + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* EMC1812 Registers Addresses */ +#define EMC1812_STATUS_ADDR 0x02 +#define EMC1812_CONFIG_LO_ADDR 0x03 + +#define EMC1812_CFG_ADDR 0x09 +#define EMC1812_CONV_ADDR 0x0A +#define EMC1812_INT_DIODE_HIGH_LIMIT_ADDR 0x0B +#define EMC1812_INT_DIODE_LOW_LIMIT_ADDR 0x0C +#define EMC1812_EXT1_HIGH_LIMIT_HIGH_BYTE_ADDR 0x0D +#define EMC1812_EXT1_LOW_LIMIT_HIGH_BYTE_ADDR 0x0E +#define EMC1812_ONE_SHOT_ADDR 0x0F + +#define EMC1812_EXT1_HIGH_LIMIT_LOW_BYTE_ADDR 0x13 +#define EMC1812_EXT1_LOW_LIMIT_LOW_BYTE_ADDR 0x14 +#define EMC1812_EXT2_HIGH_LIMIT_HIGH_BYTE_ADDR 0x15 +#define EMC1812_EXT2_LOW_LIMIT_HIGH_BYTE_ADDR 0x16 +#define EMC1812_EXT2_HIGH_LIMIT_LOW_BYTE_ADDR 0x17 +#define EMC1812_EXT2_LOW_LIMIT_LOW_BYTE_ADDR 0x18 +#define EMC1812_EXT1_THERM_LIMIT_ADDR 0x19 +#define EMC1812_EXT2_THERM_LIMIT_ADDR 0x1A +#define EMC1812_EXT_DIODE_FAULT_STATUS_ADDR 0x1B + +#define EMC1812_DIODE_FAULT_MASK_ADDR 0x1F +#define EMC1812_INT_DIODE_THERM_LIMIT_ADDR 0x20 +#define EMC1812_THRM_HYS_ADDR 0x21 +#define EMC1812_CONSEC_ALERT_ADDR 0x22 + +#define EMC1812_EXT1_BETA_CONFIG_ADDR 0x25 +#define EMC1812_EXT2_BETA_CONFIG_ADDR 0x26 +#define EMC1812_EXT1_IDEALITY_FACTOR_ADDR 0x27 +#define EMC1812_EXT2_IDEALITY_FACTOR_ADDR 0x28 + +#define EMC1812_EXT3_HIGH_LIMIT_HIGH_BYTE_ADDR 0x2C +#define EMC1812_EXT3_LOW_LIMIT_HIGH_BYTE_ADDR 0x2D +#define EMC1812_EXT3_HIGH_LIMIT_LOW_BYTE_ADDR 0x2E +#define EMC1812_EXT3_LOW_LIMIT_LOW_BYTE_ADDR 0x2F +#define EMC1812_EXT3_THERM_LIMIT_ADDR 0x30 +#define EMC1812_EXT3_IDEALITY_FACTOR_ADDR 0x31 + +#define EMC1812_EXT4_HIGH_LIMIT_HIGH_BYTE_ADDR 0x34 +#define EMC1812_EXT4_LOW_LIMIT_HIGH_BYTE_ADDR 0x35 +#define EMC1812_EXT4_HIGH_LIMIT_LOW_BYTE_ADDR 0x36 +#define EMC1812_EXT4_LOW_LIMIT_LOW_BYTE_ADDR 0x37 +#define EMC1812_EXT4_THERM_LIMIT_ADDR 0x38 +#define EMC1812_EXT4_IDEALITY_FACTOR_ADDR 0x39 +#define EMC1812_HIGH_LIMIT_STATUS_ADDR 0x3A +#define EMC1812_LOW_LIMIT_STATUS_ADDR 0x3B +#define EMC1812_THERM_LIMIT_STATUS_ADDR 0x3C +#define EMC1812_ROC_GAIN_ADDR 0x3D +#define EMC1812_ROC_CONFIG_ADDR 0x3E +#define EMC1812_ROC_STATUS_ADDR 0x3F +#define EMC1812_R1_RESH_ADDR 0x40 +#define EMC1812_R1_LIMH_ADDR 0x41 +#define EMC1812_R1_LIML_ADDR 0x42 +#define EMC1812_R1_SMPL_ADDR 0x43 +#define EMC1812_R2_RESH_ADDR 0x44 +#define EMC1812_R2_3_RESL_ADDR 0x45 +#define EMC1812_R2_LIMH_ADDR 0x46 +#define EMC1812_R2_LIML_ADDR 0x47 +#define EMC1812_R2_SMPL_ADDR 0x48 +#define EMC1812_PER_MAXTH_1_ADDR 0x49 +#define EMC1812_PER_MAXT1L_ADDR 0x4A +#define EMC1812_PER_MAXTH_2_ADDR 0x4B +#define EMC1812_PER_MAXT2_3L_ADDR 0x4C +#define EMC1812_GBL_MAXT1H_ADDR 0x4D +#define EMC1812_GBL_MAXT1L_ADDR 0x4E +#define EMC1812_GBL_MAXT2H_ADDR 0x4F +#define EMC1812_GBL_MAXT2L_ADDR 0x50 +#define EMC1812_FILTER_SEL_ADDR 0x51 + +#define EMC1812_INT_HIGH_BYTE_ADDR 0x60 +#define EMC1812_INT_LOW_BYTE_ADDR 0x61 +#define EMC1812_EXT1_HIGH_BYTE_ADDR 0x62 +#define EMC1812_EXT1_LOW_BYTE_ADDR 0x63 +#define EMC1812_EXT2_HIGH_BYTE_ADDR 0x64 +#define EMC1812_EXT2_LOW_BYTE_ADDR 0x65 +#define EMC1812_EXT3_HIGH_BYTE_ADDR 0x66 +#define EMC1812_EXT3_LOW_BYTE_ADDR 0x67 +#define EMC1812_EXT4_HIGH_BYTE_ADDR 0x68 +#define EMC1812_EXT4_LOW_BYTE_ADDR 0x69 +#define EMC1812_HOTTEST_DIODE_HIGH_BYTE_ADDR 0x6A +#define EMC1812_HOTTEST_DIODE_LOW_BYTE_ADDR 0x6B +#define EMC1812_HOTTEST_STATUS_ADDR 0x6C +#define EMC1812_HOTTEST_CFG_ADDR 0x6D + +#define EMC1812_PRODUCT_ID_ADDR 0xFD +#define EMC1812_MANUFACTURER_ID_ADDR 0xFE +#define EMC1812_REVISION_ADDR 0xFF + +/* EMC1812 Config Bits */ +#define EMC1812_CFG_MSKAL BIT(7) +#define EMC1812_CFG_RS BIT(6) +#define EMC1812_CFG_ATTHM BIT(5) +#define EMC1812_CFG_RECD12 BIT(4) +#define EMC1812_CFG_RECD34 BIT(3) +#define EMC1812_CFG_RANGE BIT(2) +#define EMC1812_CFG_DA_ENA BIT(1) +#define EMC1812_CFG_APDD BIT(0) + +/* EMC1812 Status Bits */ +#define EMC1812_STATUS_ROCF BIT(7) +#define EMC1812_STATUS_HOTCHG BIT(6) +#define EMC1812_STATUS_BUSY BIT(5) +#define EMC1812_STATUS_HIGH BIT(4) +#define EMC1812_STATUS_LOW BIT(3) +#define EMC1812_STATUS_FAULT BIT(2) +#define EMC1812_STATUS_ETHRM BIT(1) +#define EMC1812_STATUS_ITHRM BIT(0) + +#define EMC1812_BETA_LOCK_VAL 0x0F + +#define EMC1812_TEMP_CH_ADDR(index) (0x60 + 2 * (index)) + +#define EMC1812_FILTER_MASK_LEN 2 + +#define EMC1812_PID 0x81 +#define EMC1813_PID 0x87 +#define EMC1814_PID 0x84 +#define EMC1815_PID 0x85 +#define EMC1833_PID 0x83 + +/* The maximum number of channels a member of the family can have */ +#define EMC1812_MAX_NUM_CHANNELS 5 +#define EMC1812_TEMP_OFFSET 64 + +#define EMC1812_DEFAULT_IDEALITY_FACTOR 0x12 + +static const struct hwmon_channel_info * const emc1812_info[] =3D { + HWMON_CHANNEL_INFO(chip, HWMON_C_UPDATE_INTERVAL), + HWMON_CHANNEL_INFO(temp, + HWMON_T_INPUT | HWMON_T_MIN | HWMON_T_MAX | + HWMON_T_CRIT | HWMON_T_MIN_HYST | HWMON_T_MAX_HYST | + HWMON_T_CRIT_HYST | HWMON_T_MIN_ALARM | + HWMON_T_MAX_ALARM | HWMON_T_CRIT_ALARM | HWMON_T_FAULT | + HWMON_T_LABEL, + + HWMON_T_INPUT | HWMON_T_MIN | HWMON_T_MAX | + HWMON_T_CRIT | HWMON_T_MIN_HYST | HWMON_T_MAX_HYST | + HWMON_T_CRIT_HYST | HWMON_T_MIN_ALARM | + HWMON_T_MAX_ALARM | HWMON_T_CRIT_ALARM | HWMON_T_FAULT | + HWMON_T_LABEL, + + HWMON_T_INPUT | HWMON_T_MIN | HWMON_T_MAX | + HWMON_T_CRIT | HWMON_T_MIN_HYST | HWMON_T_MAX_HYST | + HWMON_T_CRIT_HYST | HWMON_T_MIN_ALARM | + HWMON_T_MAX_ALARM | HWMON_T_CRIT_ALARM | HWMON_T_FAULT | + HWMON_T_LABEL, + + HWMON_T_INPUT | HWMON_T_MIN | HWMON_T_MAX | + HWMON_T_CRIT | HWMON_T_MIN_HYST | HWMON_T_MAX_HYST | + HWMON_T_CRIT_HYST | HWMON_T_MIN_ALARM | + HWMON_T_MAX_ALARM | HWMON_T_CRIT_ALARM | HWMON_T_FAULT | + HWMON_T_LABEL, + + HWMON_T_INPUT | HWMON_T_MIN | HWMON_T_MAX | + HWMON_T_CRIT | HWMON_T_MIN_HYST | HWMON_T_MAX_HYST | + HWMON_T_CRIT_HYST | HWMON_T_MIN_ALARM | + HWMON_T_MAX_ALARM | HWMON_T_CRIT_ALARM | HWMON_T_FAULT | + HWMON_T_LABEL + ), + NULL +}; + +/** + * struct emc1812_features - features of a emc1812 instance + * @name: chip's name + * @phys_channels: number of physical channels supported by the chip + */ +struct emc1812_features { + const char *name; + u8 phys_channels; +}; + +static const struct emc1812_features emc1833_chip_config =3D { + .name =3D "emc1833", + .phys_channels =3D 3, +}; + +static const struct emc1812_features emc1812_chip_config =3D { + .name =3D "emc1812", + .phys_channels =3D 2, +}; + +static const struct emc1812_features emc1813_chip_config =3D { + .name =3D "emc1813", + .phys_channels =3D 3, +}; + +static const struct emc1812_features emc1814_chip_config =3D { + .name =3D "emc1814", + .phys_channels =3D 4, +}; + +static const struct emc1812_features emc1815_chip_config =3D { + .name =3D "emc1815", + .phys_channels =3D 5, +}; + +enum emc1812_limit_type {temp_min, temp_max}; + +static u8 emc1812_temp_map[] =3D { + [hwmon_temp_min] =3D temp_min, + [hwmon_temp_max] =3D temp_max, +}; + +static u8 emc1812_temp_crit_regs[] =3D { + [0] =3D EMC1812_INT_DIODE_THERM_LIMIT_ADDR, + [1] =3D EMC1812_EXT1_THERM_LIMIT_ADDR, + [2] =3D EMC1812_EXT2_THERM_LIMIT_ADDR, + [3] =3D EMC1812_EXT3_THERM_LIMIT_ADDR, + [4] =3D EMC1812_EXT4_THERM_LIMIT_ADDR, +}; + +static u8 emc1812_limit_regs[][2] =3D { + [0] =3D { + [temp_min] =3D EMC1812_INT_DIODE_LOW_LIMIT_ADDR, + [temp_max] =3D EMC1812_INT_DIODE_HIGH_LIMIT_ADDR, + }, + [1] =3D { + [temp_min] =3D EMC1812_EXT1_LOW_LIMIT_HIGH_BYTE_ADDR, + [temp_max] =3D EMC1812_EXT1_HIGH_LIMIT_HIGH_BYTE_ADDR, + }, + [2] =3D { + [temp_min] =3D EMC1812_EXT2_LOW_LIMIT_HIGH_BYTE_ADDR, + [temp_max] =3D EMC1812_EXT2_HIGH_LIMIT_HIGH_BYTE_ADDR, + }, + [3] =3D { + [temp_min] =3D EMC1812_EXT3_LOW_LIMIT_HIGH_BYTE_ADDR, + [temp_max] =3D EMC1812_EXT3_HIGH_LIMIT_HIGH_BYTE_ADDR, + }, + [4] =3D { + [temp_min] =3D EMC1812_EXT4_LOW_LIMIT_HIGH_BYTE_ADDR, + [temp_max] =3D EMC1812_EXT4_HIGH_LIMIT_HIGH_BYTE_ADDR, + }, +}; + +static u8 emc1812_limit_regs_low[][3] =3D { + [0] =3D { + [temp_min] =3D 0xff, + [temp_max] =3D 0xff, + }, + [1] =3D { + [temp_min] =3D EMC1812_EXT1_LOW_LIMIT_LOW_BYTE_ADDR, + [temp_max] =3D EMC1812_EXT1_HIGH_LIMIT_LOW_BYTE_ADDR, + }, + [2] =3D { + [temp_min] =3D EMC1812_EXT2_LOW_LIMIT_LOW_BYTE_ADDR, + [temp_max] =3D EMC1812_EXT2_HIGH_LIMIT_LOW_BYTE_ADDR, + }, + [3] =3D { + [temp_min] =3D EMC1812_EXT3_LOW_LIMIT_LOW_BYTE_ADDR, + [temp_max] =3D EMC1812_EXT3_HIGH_LIMIT_LOW_BYTE_ADDR, + }, + [4] =3D { + [temp_min] =3D EMC1812_EXT4_LOW_LIMIT_LOW_BYTE_ADDR, + [temp_max] =3D EMC1812_EXT4_HIGH_LIMIT_LOW_BYTE_ADDR, + }, +}; + +/* Lookup table for temperature conversion times in msec */ +static const u16 emc1812_conv_time[] =3D { + 16000, 8000, 4000, 2000, 1000, 500, 250, 125, 62, 31, 16 +}; + +/** + * struct emc1812_data - information about chip parameters + * @client: i2c client + * @hwmon_dev: hwmon device + * @labels: labels of the channels + * @active_ch_mask: active channels + * @chip: pointer to structure holding chip features + * @freq_idx: index representing the current sampling frequency + * @regmap: device register map + * @recd34_en: state of Resistance Error Correction (REC) on channels 3 a= nd 4 + * @recd12_en: state of Resistance Error Correction (REC) on channels 1 a= nd 2 + * @lock: synchronize access to driver's state members + * @apdd_en: state of anti-parallel diode mode + * @num_channels: number of active physical channels + */ +struct emc1812_data { + struct i2c_client *client; + struct device *hwmon_dev; + const char *labels[EMC1812_MAX_NUM_CHANNELS]; + unsigned long active_ch_mask; + const struct emc1812_features *chip; + unsigned int freq_idx; + struct regmap *regmap; + bool recd34_en; + bool recd12_en; + struct mutex lock; /* Synchronize access to driver's state members */ + bool apdd_en; + u8 num_channels; +}; + +/* emc1812 regmap configuration */ +static const struct regmap_range emc1812_regmap_writable_ranges[] =3D { + regmap_reg_range(EMC1812_CFG_ADDR, EMC1812_ONE_SHOT_ADDR), + regmap_reg_range(EMC1812_EXT1_HIGH_LIMIT_LOW_BYTE_ADDR, + EMC1812_EXT_DIODE_FAULT_STATUS_ADDR), + regmap_reg_range(EMC1812_DIODE_FAULT_MASK_ADDR, EMC1812_CONSEC_ALERT_ADDR= ), + regmap_reg_range(EMC1812_EXT1_BETA_CONFIG_ADDR, EMC1812_FILTER_SEL_ADDR), + regmap_reg_range(EMC1812_HOTTEST_STATUS_ADDR, EMC1812_HOTTEST_CFG_ADDR), +}; + +static const struct regmap_access_table emc1812_regmap_wr_table =3D { + .yes_ranges =3D emc1812_regmap_writable_ranges, + .n_yes_ranges =3D ARRAY_SIZE(emc1812_regmap_writable_ranges), +}; + +static const struct regmap_range emc1812_regmap_rd_ranges[] =3D { + regmap_reg_range(EMC1812_STATUS_ADDR, EMC1812_CONFIG_LO_ADDR), + regmap_reg_range(EMC1812_CFG_ADDR, EMC1812_ONE_SHOT_ADDR), + regmap_reg_range(EMC1812_EXT1_HIGH_LIMIT_LOW_BYTE_ADDR, + EMC1812_EXT_DIODE_FAULT_STATUS_ADDR), + regmap_reg_range(EMC1812_DIODE_FAULT_MASK_ADDR, EMC1812_CONSEC_ALERT_ADDR= ), + regmap_reg_range(EMC1812_EXT1_BETA_CONFIG_ADDR, EMC1812_FILTER_SEL_ADDR), + regmap_reg_range(EMC1812_INT_HIGH_BYTE_ADDR, EMC1812_HOTTEST_CFG_ADDR), + regmap_reg_range(EMC1812_PRODUCT_ID_ADDR, EMC1812_REVISION_ADDR), +}; + +static const struct regmap_access_table emc1812_regmap_rd_table =3D { + .yes_ranges =3D emc1812_regmap_rd_ranges, + .n_yes_ranges =3D ARRAY_SIZE(emc1812_regmap_rd_ranges), +}; + +static bool emc1812_is_volatile_reg(struct device *dev, unsigned int reg) +{ + switch (reg) { + case EMC1812_STATUS_ADDR: + case EMC1812_EXT_DIODE_FAULT_STATUS_ADDR: + case EMC1812_DIODE_FAULT_MASK_ADDR: + case EMC1812_EXT1_BETA_CONFIG_ADDR: + case EMC1812_EXT2_BETA_CONFIG_ADDR: + case EMC1812_HIGH_LIMIT_STATUS_ADDR: + case EMC1812_LOW_LIMIT_STATUS_ADDR: + case EMC1812_THERM_LIMIT_STATUS_ADDR: + case EMC1812_ROC_STATUS_ADDR: + case EMC1812_PER_MAXTH_1_ADDR: + case EMC1812_PER_MAXT1L_ADDR: + case EMC1812_PER_MAXTH_2_ADDR: + case EMC1812_PER_MAXT2_3L_ADDR: + case EMC1812_GBL_MAXT1H_ADDR: + case EMC1812_GBL_MAXT1L_ADDR: + case EMC1812_GBL_MAXT2H_ADDR: + case EMC1812_GBL_MAXT2L_ADDR: + case EMC1812_INT_HIGH_BYTE_ADDR: + case EMC1812_INT_LOW_BYTE_ADDR: + case EMC1812_EXT1_HIGH_BYTE_ADDR: + case EMC1812_EXT1_LOW_BYTE_ADDR: + case EMC1812_EXT2_HIGH_BYTE_ADDR: + case EMC1812_EXT2_LOW_BYTE_ADDR: + case EMC1812_EXT3_HIGH_BYTE_ADDR: + case EMC1812_EXT3_LOW_BYTE_ADDR: + case EMC1812_EXT4_HIGH_BYTE_ADDR: + case EMC1812_EXT4_LOW_BYTE_ADDR: + case EMC1812_HOTTEST_DIODE_HIGH_BYTE_ADDR: + case EMC1812_HOTTEST_DIODE_LOW_BYTE_ADDR: + case EMC1812_HOTTEST_STATUS_ADDR: + return true; + default: + return false; + } +} + +static const struct regmap_config emc1812_regmap_config =3D { + .reg_bits =3D 8, + .val_bits =3D 8, + .rd_table =3D &emc1812_regmap_rd_table, + .wr_table =3D &emc1812_regmap_wr_table, + .volatile_reg =3D emc1812_is_volatile_reg, + .max_register =3D EMC1812_REVISION_ADDR, + .cache_type =3D REGCACHE_MAPLE, +}; + +static umode_t emc1812_is_visible(const void *_data, enum hwmon_sensor_typ= es type, + u32 attr, int channel) +{ + const struct emc1812_data *data =3D _data; + + switch (type) { + case hwmon_temp: + /* Don't show channels which are not described into the device tree. */ + if (!(data->active_ch_mask & (1 << channel))) + return 0; + + /* Don't show channels which are not physically connected. */ + if (channel >=3D data->chip->phys_channels) + return 0; + + switch (attr) { + case hwmon_temp_input: + case hwmon_temp_min_alarm: + case hwmon_temp_max_alarm: + case hwmon_temp_crit_alarm: + case hwmon_temp_fault: + case hwmon_temp_min_hyst: + case hwmon_temp_max_hyst: + case hwmon_temp_label: + return 0444; + case hwmon_temp_min: + case hwmon_temp_max: + case hwmon_temp_crit: + case hwmon_temp_crit_hyst: + return 0644; + default: + return 0; + } + case hwmon_chip: + switch (attr) { + case hwmon_chip_update_interval: + return 0644; + default: + return 0; + } + default: + return 0; + } +}; + +static int emc1812_get_temp(struct emc1812_data *data, int channel, long *= val) +{ + __be16 tmp_be16; + int ret; + + ret =3D regmap_bulk_read(data->regmap, EMC1812_TEMP_CH_ADDR(channel), + &tmp_be16, sizeof(tmp_be16)); + if (ret) + return ret; + + /* Range is always -64 to 191.875=C2=B0C */ + *val =3D ((be16_to_cpu(tmp_be16) >> 5) - 512) * 125; + + return 0; +} + +static int emc1812_get_crit_limit_temp(struct emc1812_data *data, int chan= nel, long *val) +{ + unsigned int tmp; + int ret; + + /* Critical register is 8bits long and keeps only integer part of tempera= ture */ + ret =3D regmap_read(data->regmap, emc1812_temp_crit_regs[channel], &tmp); + if (ret) + return ret; + + /* Range is always -64 to 191=C2=B0C */ + *val =3D (tmp - EMC1812_TEMP_OFFSET) * 1000; + + return 0; +} + +static int emc1812_get_limit_temp(struct emc1812_data *data, int ch, + enum emc1812_limit_type type, long *val) +{ + unsigned int regvalh; + unsigned int regvall =3D 0; + int ret; + + ret =3D regmap_read(data->regmap, emc1812_limit_regs[ch][type], ®valh); + if (ret < 0) + return ret; + + if (ch) { + ret =3D regmap_read(data->regmap, emc1812_limit_regs_low[ch][type], ®= vall); + if (ret < 0) + return ret; + } + /* Range is always -64 to 191.875=C2=B0C */ + *val =3D (((regvalh - EMC1812_TEMP_OFFSET) << 3) | (regvall >> 5)) * 125; + + return 0; +} + +static int emc1812_read_reg(struct device *dev, struct emc1812_data *data,= u32 attr, + int channel, long *val) +{ + unsigned int mask; + int hyst, ret; + + switch (attr) { + case hwmon_temp_min: + return emc1812_get_limit_temp(data, channel, temp_min, val); + case hwmon_temp_max: + return emc1812_get_limit_temp(data, channel, temp_max, val); + case hwmon_temp_crit: + return emc1812_get_crit_limit_temp(data, channel, val); + case hwmon_temp_input: + return emc1812_get_temp(data, channel, val); + case hwmon_temp_min_hyst: + ret =3D emc1812_get_limit_temp(data, channel, temp_min, val); + if (ret < 0) + return ret; + + ret =3D regmap_read(data->regmap, EMC1812_THRM_HYS_ADDR, &hyst); + if (ret < 0) + return ret; + + *val =3D *val + hyst * 1000; + + return 0; + + case hwmon_temp_max_hyst: + ret =3D emc1812_get_limit_temp(data, channel, temp_max, val); + if (ret < 0) + return ret; + + ret =3D regmap_read(data->regmap, EMC1812_THRM_HYS_ADDR, &hyst); + if (ret < 0) + return ret; + + *val =3D *val - hyst * 1000; + + return 0; + case hwmon_temp_crit_hyst: + ret =3D emc1812_get_crit_limit_temp(data, channel, val); + if (ret < 0) + return ret; + + ret =3D regmap_read(data->regmap, EMC1812_THRM_HYS_ADDR, &hyst); + if (ret < 0) + return ret; + + *val =3D *val - hyst * 1000; + return 0; + case hwmon_temp_min_alarm: + mask =3D 1 << channel; + *val =3D regmap_test_bits(data->regmap, EMC1812_LOW_LIMIT_STATUS_ADDR, m= ask); + if (*val < 0) + return *val; + return 0; + case hwmon_temp_max_alarm: + mask =3D 1 << channel; + *val =3D regmap_test_bits(data->regmap, EMC1812_HIGH_LIMIT_STATUS_ADDR, = mask); + if (*val < 0) + return *val; + return 0; + case hwmon_temp_crit_alarm: + mask =3D 1 << channel; + *val =3D regmap_test_bits(data->regmap, EMC1812_THERM_LIMIT_STATUS_ADDR,= mask); + if (*val < 0) + return *val; + return 0; + case hwmon_temp_fault: + mask =3D 1 << channel; + *val =3D regmap_test_bits(data->regmap, EMC1812_EXT_DIODE_FAULT_STATUS_A= DDR, mask); + if (*val < 0) + return *val; + return 0; + default: + return -EOPNOTSUPP; + } +} + +static int emc1812_read(struct device *dev, enum hwmon_sensor_types type, = u32 attr, + int channel, long *val) +{ + struct emc1812_data *data =3D dev_get_drvdata(dev); + unsigned int convrate; + int ret; + + switch (type) { + case hwmon_temp: + return emc1812_read_reg(dev, data, attr, channel, val); + case hwmon_chip: + switch (attr) { + case hwmon_chip_update_interval: + ret =3D regmap_read(data->regmap, EMC1812_CONV_ADDR, &convrate); + if (ret < 0) + return ret; + + if (convrate > 10) + convrate =3D 4; + + *val =3D 16000 >> convrate; + return 0; + default: + return -EOPNOTSUPP; + } + default: + return -EOPNOTSUPP; + } +} + +static int emc1812_read_string(struct device *dev, enum hwmon_sensor_types= type, + u32 attr, int channel, const char **str) +{ + struct emc1812_data *data =3D dev_get_drvdata(dev); + + if (channel >=3D data->chip->phys_channels) + return 0; + + switch (type) { + case hwmon_temp: + switch (attr) { + case hwmon_temp_label: + *str =3D data->labels[channel]; + return 0; + default: + return -EOPNOTSUPP; + } + default: + return -EOPNOTSUPP; + } +} + +static int emc1812_set_hyst(struct emc1812_data *data, int channel, long v= al) +{ + int hyst, ret; + int limit; + + /* Critical register is 8bits long and keeps only integer part of tempera= ture */ + ret =3D regmap_read(data->regmap, emc1812_temp_crit_regs[channel], &limit= ); + if (ret) + return ret; + + hyst =3D clamp_val(limit - val, 0, 256); + + ret =3D regmap_write(data->regmap, EMC1812_THRM_HYS_ADDR, hyst); + + return ret; +} + +static int emc1812_set_temp(struct emc1812_data *data, int channel, + enum emc1812_limit_type map, long val) +{ + int ret; + u8 regh, regl; + + regh =3D emc1812_limit_regs[channel][map]; + regl =3D emc1812_limit_regs_low[channel][map]; + + ret =3D regmap_write(data->regmap, regh, (val >> 3) & 0xff); + if (ret < 0) + return ret; + + if (channel) + ret =3D regmap_write(data->regmap, regl, (val & 0x07) << 5); + + return ret; +} + +static int emc1812_write(struct device *dev, enum hwmon_sensor_types type,= u32 attr, + int channel, long val) +{ + struct emc1812_data *data =3D dev_get_drvdata(dev); + unsigned int interval; + int convrate; + + switch (type) { + case hwmon_temp: + /* Range is always -64 to 191.875=C2=B0C */ + val =3D clamp_val(val, -64000, 191875); + val =3D val + (EMC1812_TEMP_OFFSET * 1000); + val =3D DIV_ROUND_CLOSEST(val, 125); + + switch (attr) { + case hwmon_temp_min: + case hwmon_temp_max: + return emc1812_set_temp(data, channel, emc1812_temp_map[attr], val); + case hwmon_temp_crit: + val =3D (val >> 3) & 0xff; + return regmap_write(data->regmap, emc1812_temp_crit_regs[channel], val); + case hwmon_temp_crit_hyst: + val =3D (val >> 3) & 0xff; + return emc1812_set_hyst(data, channel, val); + default: + return -EOPNOTSUPP; + } + case hwmon_chip: + switch (attr) { + case hwmon_chip_update_interval: + interval =3D clamp_val(val, 0, 16000); + convrate =3D find_closest_descending(interval, emc1812_conv_time, + ARRAY_SIZE(emc1812_conv_time)); + return regmap_write(data->regmap, EMC1812_CONV_ADDR, convrate); + default: + return -EOPNOTSUPP; + } + default: + return -EOPNOTSUPP; + } +} + +static int emc1812_init(struct emc1812_data *priv) +{ + int ret; + u8 val; + + /* + * Set default values in registers. APDD, RECD12 and RECD34 are active + * on 0. + * Set the device to be in Run (Active) state and converting on all + * channels. + * The temperature measurement range is -64=C2=B0C to +191.875=C2=B0C. + */ + val =3D FIELD_PREP(EMC1812_CFG_MSKAL, 1) | + FIELD_PREP(EMC1812_CFG_RS, 0) | + FIELD_PREP(EMC1812_CFG_ATTHM, 1) | + FIELD_PREP(EMC1812_CFG_RECD12, !priv->recd12_en) | + FIELD_PREP(EMC1812_CFG_RECD34, !priv->recd34_en) | + FIELD_PREP(EMC1812_CFG_RANGE, 1) | + FIELD_PREP(EMC1812_CFG_DA_ENA, 0) | + FIELD_PREP(EMC1812_CFG_APDD, !priv->apdd_en); + + ret =3D regmap_write(priv->regmap, EMC1812_CFG_ADDR, val); + if (ret) + return ret; + + /* Default is 4 conversions/seconds */ + ret =3D regmap_write(priv->regmap, EMC1812_CONV_ADDR, 6); + if (ret) + return ret; + priv->freq_idx =3D 6; + + ret =3D regmap_write(priv->regmap, EMC1812_THRM_HYS_ADDR, 0x0A); + if (ret) + return ret; + + ret =3D regmap_write(priv->regmap, EMC1812_CONSEC_ALERT_ADDR, 0x70); + if (ret) + return ret; + + ret =3D regmap_write(priv->regmap, EMC1812_FILTER_SEL_ADDR, 0); + if (ret) + return ret; + + ret =3D regmap_write(priv->regmap, EMC1812_HOTTEST_CFG_ADDR, 0); + if (ret) + return ret; + + /* Enables the beta compensation factor auto-detection function for beta1= and beta2 */ + ret =3D regmap_write(priv->regmap, EMC1812_EXT1_BETA_CONFIG_ADDR, + EMC1812_BETA_LOCK_VAL); + if (ret) + return ret; + + ret =3D regmap_write(priv->regmap, EMC1812_EXT2_BETA_CONFIG_ADDR, + EMC1812_BETA_LOCK_VAL); + if (ret) + return ret; + + /* Set ideality factor for all external channels */ + ret =3D regmap_write(priv->regmap, EMC1812_EXT1_IDEALITY_FACTOR_ADDR, + EMC1812_DEFAULT_IDEALITY_FACTOR); + if (ret) + return ret; + + ret =3D regmap_write(priv->regmap, EMC1812_EXT2_IDEALITY_FACTOR_ADDR, + EMC1812_DEFAULT_IDEALITY_FACTOR); + if (ret) + return ret; + + ret =3D regmap_write(priv->regmap, EMC1812_EXT3_IDEALITY_FACTOR_ADDR, + EMC1812_DEFAULT_IDEALITY_FACTOR); + if (ret) + return ret; + + ret =3D regmap_write(priv->regmap, EMC1812_EXT4_IDEALITY_FACTOR_ADDR, + EMC1812_DEFAULT_IDEALITY_FACTOR); + if (ret) + return ret; + + return 0; +} + +static int emc1812_parse_fw_config(struct emc1812_data *data, struct devic= e *dev) +{ + unsigned int reg_nr =3D 0; + int ret; + + data->apdd_en =3D device_property_read_bool(dev, "microchip,enable-anti-p= arallel"); + data->recd12_en =3D device_property_read_bool(dev, "microchip,parasitic-r= es-on-channel1-2"); + data->recd34_en =3D device_property_read_bool(dev, "microchip,parasitic-r= es-on-channel3-4"); + + data->num_channels =3D device_get_child_node_count(dev) + 1; + + if (data->num_channels > data->chip->phys_channels) + return dev_err_probe(dev, -E2BIG, "More channels than the chip supports\= n"); + + /* internal temperature channel as always active */ + data->labels[reg_nr] =3D "internal_diode"; + set_bit(reg_nr, &data->active_ch_mask); + + device_for_each_child_node_scoped(dev, child) { + ret =3D fwnode_property_read_u32(child, "reg", ®_nr); + if (ret || reg_nr >=3D data->chip->phys_channels) + return dev_err_probe(dev, -EINVAL, + "The index of the channels does not match the chip\n"); + /* mark external channel as active */ + set_bit(reg_nr, &data->active_ch_mask); + + fwnode_property_read_string(child, "label", &data->labels[reg_nr]); + } + + return 0; +} + +static int emc1812_chip_identify(struct emc1812_data *data, struct i2c_cli= ent *client) +{ + int ret, tmp; + + ret =3D regmap_read(data->regmap, EMC1812_PRODUCT_ID_ADDR, &tmp); + if (ret) + return ret; + + switch (tmp) { + case EMC1812_PID: + data->chip =3D &emc1812_chip_config; + break; + case EMC1813_PID: + data->chip =3D &emc1813_chip_config; + break; + case EMC1814_PID: + data->chip =3D &emc1814_chip_config; + break; + case EMC1815_PID: + data->chip =3D &emc1815_chip_config; + break; + case EMC1833_PID: + data->chip =3D &emc1833_chip_config; + break; + default: + /* + * If failed to identify the hardware based on internal registers, + * try using fallback compatible in device tree to deal with some + * newer part number. + */ + data->chip =3D device_get_match_data(&client->dev); + if (!data->chip) + return -EINVAL; + break; + } + + return 0; +} + +static const struct hwmon_ops emc1812_ops =3D { + .is_visible =3D emc1812_is_visible, + .read =3D emc1812_read, + .read_string =3D emc1812_read_string, + .write =3D emc1812_write, +}; + +static const struct hwmon_chip_info emc1812_chip_info =3D { + .ops =3D &emc1812_ops, + .info =3D emc1812_info, +}; + +static int emc1812_probe(struct i2c_client *client) +{ + struct device *dev =3D &client->dev; + struct emc1812_data *data; + int ret; + + data =3D devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + i2c_set_clientdata(client, data); + data->client =3D client; + + data->regmap =3D devm_regmap_init_i2c(client, &emc1812_regmap_config); + if (IS_ERR(data->regmap)) + return dev_err_probe(dev, PTR_ERR(data->regmap), + "Cannot initialize register map\n"); + + ret =3D devm_mutex_init(dev, &data->lock); + if (ret) + return ret; + + ret =3D emc1812_chip_identify(data, client); + if (ret) + return dev_err_probe(dev, ret, "Chip identification fails\n"); + + dev_info(dev, "Device name: %s\n", data->chip->name); + + ret =3D emc1812_parse_fw_config(data, dev); + if (ret) + return ret; + + ret =3D emc1812_init(data); + if (ret) + return dev_err_probe(dev, ret, "Cannot initialize device\n"); + + data->hwmon_dev =3D devm_hwmon_device_register_with_info(dev, client->nam= e, data, + &emc1812_chip_info, NULL); + if (IS_ERR(data->hwmon_dev)) + return PTR_ERR(data->hwmon_dev); + + return 0; +} + +static const struct i2c_device_id emc1812_id[] =3D { + { .name =3D "emc1812", .driver_data =3D (kernel_ulong_t)&emc1812_chip_con= fig }, + { .name =3D "emc1813", .driver_data =3D (kernel_ulong_t)&emc1813_chip_con= fig }, + { .name =3D "emc1814", .driver_data =3D (kernel_ulong_t)&emc1814_chip_con= fig }, + { .name =3D "emc1815", .driver_data =3D (kernel_ulong_t)&emc1815_chip_con= fig }, + { .name =3D "emc1833", .driver_data =3D (kernel_ulong_t)&emc1833_chip_con= fig }, + { } +}; +MODULE_DEVICE_TABLE(i2c, emc1812_id); + +static const struct of_device_id emc1812_of_match[] =3D { + { + .compatible =3D "microchip,emc1812", + .data =3D &emc1812_chip_config + }, + { + .compatible =3D "microchip,emc1813", + .data =3D &emc1813_chip_config + }, + { + .compatible =3D "microchip,emc1814", + .data =3D &emc1814_chip_config + }, + { + .compatible =3D "microchip,emc1815", + .data =3D &emc1815_chip_config + }, + { + .compatible =3D "microchip,emc1833", + .data =3D &emc1833_chip_config + }, + { } +}; +MODULE_DEVICE_TABLE(of, emc1812_of_match); + +static struct i2c_driver emc1812_driver =3D { + .driver =3D { + .name =3D "emc1812", + .of_match_table =3D emc1812_of_match, + }, + .probe =3D emc1812_probe, + .id_table =3D emc1812_id, +}; +module_i2c_driver(emc1812_driver); + +MODULE_AUTHOR("Marius Cristea "); +MODULE_DESCRIPTION("EMC1812/13/14/15/33 high-accuracy remote diode tempera= ture monitor Driver"); +MODULE_LICENSE("GPL"); --=20 2.48.1