From nobody Sat Feb 7 13:41:35 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 89B522F25E0; Wed, 29 Oct 2025 16:11:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761754298; cv=none; b=A1NRlftlOsWZWSJlGW3a8fXwTu2b4rlkMb15XqeVVu3x3XXenAdCVT2GWA37g8FTbUPpLsuhR4Rgr5esLpRkvPM3hY1do9lZUJeViM7piYMVfs6CIRamd2MM89EuNYkSbReY98/8CXz3cgAT1ma6hWQ65Mx1pJHfmqBmerEU5X0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761754298; c=relaxed/simple; bh=SBPUsQQts6myI7KNC8yymj9GqGzDulDYvcTpau9/ALk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=DUwY9wnm8x1Mc228oaElWjMc8KYN4KZU6wMcR5qKfN2MTv2Ym0CTnkdse+kvp2frojq+knfB9FIheFDuUp4pIxReRcZmNz4zTuGzPGjbm7wj592+0pBP64jPBreahiKJ/ePcwXW7ByJ6UlYGxuCECFo/R09GtXqgwD3Jgq0AgG0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=vL3wKFOI; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="vL3wKFOI" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 50589C4CEF7; Wed, 29 Oct 2025 16:11:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1761754298; bh=SBPUsQQts6myI7KNC8yymj9GqGzDulDYvcTpau9/ALk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=vL3wKFOIoq91uTTR96HuBCNCR0G7LITKAB33GwdtWlZeoGAyn+DRgPe0glvKcknJq M9dMTaEPAloeCsn6TK7lZM9RlOw7cUNUGcpknMdVf+CSTmLtZTHZjnDHZ5+KZWA8Jv e0VsXgB/8ulVgFyGI+viPeK1eZw66zUZaL4ZsnL34lkm/2q7H83ZUE0gXJCfSAUbZU QTJ2p9BZGr+TaXt1s0YcydKPPTW0I8OtPD0HnRh6m66XQCO1B20aARMNxTKscYWj/9 hKRJN5h/fHLcopvATVbruTVkBSHhP8STh4N2SZh3s+wSpQ6gDjyLDLxscXROACoR8V d3FiA4wXgiqzQ== From: Conor Dooley To: claudiu.beznea@tuxon.dev Cc: conor@kernel.org, Conor Dooley , Daire McNamara , pierre-henry.moussay@microchip.com, valentina.fernandezalanis@microchip.com, Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Philipp Zabel , linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 1/7] reset: mpfs: add non-auxiliary bus probing Date: Wed, 29 Oct 2025 16:11:17 +0000 Message-ID: <20251029-macarena-neglector-318431fec367@spud> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251029-chewing-absolve-c4e6acfe0fa4@spud> References: <20251029-chewing-absolve-c4e6acfe0fa4@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=6690; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=WjSYxPHoiecG3YZVCMCzeZtGrY72vr6u1gmlrYkaGJE=; b=owGbwMvMwCVWscWwfUFT0iXG02pJDJlMNusucCmdWFN9dEqkWdThu5L3a33SHX3fBXR6vp3+K bros658RykLgxgXg6yYIkvi7b4WqfV/XHY497yFmcPKBDKEgYtTACby6TcjQ/sq8czfXZ9/R5SZ +MfoHvu39vKcGU3K8g/llG8w7PoZtJCR4ccnFW6d3HN9xX3FZs84N9Z/8HoSZTn1yqxZV4psHsS t4wIA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley While the auxiliary bus was a nice bandaid, and meant that re-writing the representation of the clock regions in devicetree was not required, it has run its course. The "mss_top_sysreg" region that contains the clock and reset regions, also contains pinctrl and an interrupt controller, so the time has come rewrite the devicetree and probe the reset controller from an mfd devicetree node, rather than implement those drivers using the auxiliary bus. Wanting to avoid propagating this naive/incorrect description of the hardware to the new pic64gx SoC is a major motivating factor here. Signed-off-by: Conor Dooley --- v6: - depend on MFD_SYSCON - return regmap_update_bits() result directly instead of an additional return 0 v4: - Only use driver specific lock for non-regmap writes v2: - Implement the request to use regmap_update_bits(). I found that I then hated the read/write helpers since they were just bloat, so I ripped them out. I replaced the regular spin_lock_irqsave() stuff with a guard(spinlock_irqsave), since that's a simpler way of handling the two different paths through such a trivial pair of functions. --- drivers/reset/Kconfig | 1 + drivers/reset/reset-mpfs.c | 79 ++++++++++++++++++++++++++++++-------- 2 files changed, 63 insertions(+), 17 deletions(-) diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 78b7078478d4..0ec4b7cd08d6 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -200,6 +200,7 @@ config RESET_PISTACHIO config RESET_POLARFIRE_SOC bool "Microchip PolarFire SoC (MPFS) Reset Driver" depends on MCHP_CLK_MPFS + depends on MFD_SYSCON select AUXILIARY_BUS default MCHP_CLK_MPFS help diff --git a/drivers/reset/reset-mpfs.c b/drivers/reset/reset-mpfs.c index f6fa10e03ea8..25de7df55301 100644 --- a/drivers/reset/reset-mpfs.c +++ b/drivers/reset/reset-mpfs.c @@ -7,13 +7,16 @@ * */ #include +#include #include #include +#include #include #include #include -#include +#include #include +#include #include #include =20 @@ -27,11 +30,14 @@ #define MPFS_SLEEP_MIN_US 100 #define MPFS_SLEEP_MAX_US 200 =20 +#define REG_SUBBLK_RESET_CR 0x88u + /* block concurrent access to the soft reset register */ static DEFINE_SPINLOCK(mpfs_reset_lock); =20 struct mpfs_reset { void __iomem *base; + struct regmap *regmap; struct reset_controller_dev rcdev; }; =20 @@ -46,41 +52,46 @@ static inline struct mpfs_reset *to_mpfs_reset(struct r= eset_controller_dev *rcde static int mpfs_assert(struct reset_controller_dev *rcdev, unsigned long i= d) { struct mpfs_reset *rst =3D to_mpfs_reset(rcdev); - unsigned long flags; u32 reg; =20 - spin_lock_irqsave(&mpfs_reset_lock, flags); + if (rst->regmap) + return regmap_update_bits(rst->regmap, REG_SUBBLK_RESET_CR, BIT(id), BIT= (id)); + + guard(spinlock_irqsave)(&mpfs_reset_lock); =20 reg =3D readl(rst->base); reg |=3D BIT(id); writel(reg, rst->base); =20 - spin_unlock_irqrestore(&mpfs_reset_lock, flags); - return 0; } =20 static int mpfs_deassert(struct reset_controller_dev *rcdev, unsigned long= id) { struct mpfs_reset *rst =3D to_mpfs_reset(rcdev); - unsigned long flags; u32 reg; =20 - spin_lock_irqsave(&mpfs_reset_lock, flags); + if (rst->regmap) + return regmap_update_bits(rst->regmap, REG_SUBBLK_RESET_CR, BIT(id), 0); + + guard(spinlock_irqsave)(&mpfs_reset_lock); =20 reg =3D readl(rst->base); reg &=3D ~BIT(id); writel(reg, rst->base); =20 - spin_unlock_irqrestore(&mpfs_reset_lock, flags); - return 0; } =20 static int mpfs_status(struct reset_controller_dev *rcdev, unsigned long i= d) { struct mpfs_reset *rst =3D to_mpfs_reset(rcdev); - u32 reg =3D readl(rst->base); + u32 reg; + + if (rst->regmap) + regmap_read(rst->regmap, REG_SUBBLK_RESET_CR, ®); + else + reg =3D readl(rst->base); =20 /* * It is safe to return here as MPFS_NUM_RESETS makes sure the sign bit @@ -130,11 +141,45 @@ static int mpfs_reset_xlate(struct reset_controller_d= ev *rcdev, return index - MPFS_PERIPH_OFFSET; } =20 -static int mpfs_reset_probe(struct auxiliary_device *adev, - const struct auxiliary_device_id *id) +static int mpfs_reset_mfd_probe(struct platform_device *pdev) { - struct device *dev =3D &adev->dev; struct reset_controller_dev *rcdev; + struct device *dev =3D &pdev->dev; + struct mpfs_reset *rst; + + rst =3D devm_kzalloc(dev, sizeof(*rst), GFP_KERNEL); + if (!rst) + return -ENOMEM; + + rcdev =3D &rst->rcdev; + rcdev->dev =3D dev; + rcdev->ops =3D &mpfs_reset_ops; + + rcdev->of_node =3D pdev->dev.parent->of_node; + rcdev->of_reset_n_cells =3D 1; + rcdev->of_xlate =3D mpfs_reset_xlate; + rcdev->nr_resets =3D MPFS_NUM_RESETS; + + rst->regmap =3D device_node_to_regmap(pdev->dev.parent->of_node); + if (IS_ERR(rst->regmap)) + dev_err_probe(dev, PTR_ERR(rst->regmap), "Failed to find syscon regmap\n= "); + + return devm_reset_controller_register(dev, rcdev); +} + +static struct platform_driver mpfs_reset_mfd_driver =3D { + .probe =3D mpfs_reset_mfd_probe, + .driver =3D { + .name =3D "mpfs-reset", + }, +}; +module_platform_driver(mpfs_reset_mfd_driver); + +static int mpfs_reset_adev_probe(struct auxiliary_device *adev, + const struct auxiliary_device_id *id) +{ + struct reset_controller_dev *rcdev; + struct device *dev =3D &adev->dev; struct mpfs_reset *rst; =20 rst =3D devm_kzalloc(dev, sizeof(*rst), GFP_KERNEL); @@ -145,8 +190,8 @@ static int mpfs_reset_probe(struct auxiliary_device *ad= ev, =20 rcdev =3D &rst->rcdev; rcdev->dev =3D dev; - rcdev->dev->parent =3D dev->parent; rcdev->ops =3D &mpfs_reset_ops; + rcdev->of_node =3D dev->parent->of_node; rcdev->of_reset_n_cells =3D 1; rcdev->of_xlate =3D mpfs_reset_xlate; @@ -176,12 +221,12 @@ static const struct auxiliary_device_id mpfs_reset_id= s[] =3D { }; MODULE_DEVICE_TABLE(auxiliary, mpfs_reset_ids); =20 -static struct auxiliary_driver mpfs_reset_driver =3D { - .probe =3D mpfs_reset_probe, +static struct auxiliary_driver mpfs_reset_aux_driver =3D { + .probe =3D mpfs_reset_adev_probe, .id_table =3D mpfs_reset_ids, }; =20 -module_auxiliary_driver(mpfs_reset_driver); +module_auxiliary_driver(mpfs_reset_aux_driver); =20 MODULE_DESCRIPTION("Microchip PolarFire SoC Reset Driver"); MODULE_AUTHOR("Conor Dooley "); --=20 2.51.0 From nobody Sat Feb 7 13:41:35 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B520F283FC3; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="fA2O1tJp" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7E642C116B1; Wed, 29 Oct 2025 16:11:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1761754301; bh=4kdgWfgvg7oJNRXLjBlOXle1kvB7aBe2YNXbD+Y8Wc4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=fA2O1tJpjhyVcByXd5DncoIYTApookFFqCDKIZGPVqRjefyNz4lrk7Rn+AF3Lk5VR 9NoEKm4rKP6AztvLlrZPxedFaP/t8UHp5gfE/Qw9OPlqvqCSOvHyeAObXn18N5ACZp vFl0KHqwQ/xKYOpYSIGpuTbLDxguUuuWMXYsfjWynbaw3+oyqT9OugWoI3aDfOfhDd JQSKj8Qwd6dJTn8mjf2vmtvL7p5mRPEe7jr9C/AVmiimIRwiCkGXbkzU4qeFRCVnoR 77pbvRmEk9yQfbK63TTqZqUDqJrQ0q1Q3MK2lTUkHFqiGyowEnPoZ2F59LR842+qpK xSNokMN91RH9A== From: Conor Dooley To: claudiu.beznea@tuxon.dev Cc: conor@kernel.org, Conor Dooley , Daire McNamara , pierre-henry.moussay@microchip.com, valentina.fernandezalanis@microchip.com, Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Philipp Zabel , linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 2/7] dt-bindings: clk: microchip: mpfs: remove first reg region Date: Wed, 29 Oct 2025 16:11:18 +0000 Message-ID: <20251029-unwatched-family-e47cb29ea815@spud> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251029-chewing-absolve-c4e6acfe0fa4@spud> References: <20251029-chewing-absolve-c4e6acfe0fa4@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=3159; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=3LZvSpbfmHa0zvD2pQSWl0P8VI7zypG9G9PgJJXjfzU=; b=owGbwMvMwCVWscWwfUFT0iXG02pJDJlMNuvyX8YrL94jPHv+yWCr81IVlppiJ7tZn344oM587 8Oza/m1HaUsDGJcDLJiiiyJt/tapNb/cdnh3PMWZg4rE8gQBi5OAZiI0HOG/5X5vVL37hzODdGf YG7z0qlfe86G+Vym82wVl3PESe/a/Y/hf9bsWT1XuxveGhf63J14a9tP+/U7G579TWr89v3XnZ2 +C3kA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley The first reg region in this binding is not exclusively for clocks, as evidenced by the dual role of this device as a reset controller at present. The first region is however better described by a simple-mfd syscon, but this would have require a significant re-write of the devicetree for the platform, so the easy way out was chosen when reset support was first introduced. The region doesn't just contain clock and reset registers, it also contains pinctrl and interrupt controller functionality, so drop the region from the clock binding so that it can be described instead by a simple-mfd syscon rather than propagate this incorrect description of the hardware to the new pic64gx SoC. Acked-by: Rob Herring (Arm) Signed-off-by: Conor Dooley --- .../bindings/clock/microchip,mpfs-clkcfg.yaml | 36 +++++++++++-------- 1 file changed, 22 insertions(+), 14 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/microchip,mpfs-clkcfg.= yaml b/Documentation/devicetree/bindings/clock/microchip,mpfs-clkcfg.yaml index e4e1c31267d2..ee4f31596d97 100644 --- a/Documentation/devicetree/bindings/clock/microchip,mpfs-clkcfg.yaml +++ b/Documentation/devicetree/bindings/clock/microchip,mpfs-clkcfg.yaml @@ -22,16 +22,23 @@ properties: const: microchip,mpfs-clkcfg =20 reg: - items: - - description: | - clock config registers: - These registers contain enable, reset & divider tables for the, = cpu, - axi, ahb and rtc/mtimer reference clocks as well as enable and r= eset - for the peripheral clocks. - - description: | - mss pll dri registers: - Block of registers responsible for dynamic reconfiguration of th= e mss - pll + oneOf: + - items: + - description: | + clock config registers: + These registers contain enable, reset & divider tables for t= he, cpu, + axi, ahb and rtc/mtimer reference clocks as well as enable a= nd reset + for the peripheral clocks. + - description: | + mss pll dri registers: + Block of registers responsible for dynamic reconfiguration o= f the mss + pll + deprecated: true + - items: + - description: | + mss pll dri registers: + Block of registers responsible for dynamic reconfiguration o= f the mss + pll =20 clocks: maxItems: 1 @@ -69,11 +76,12 @@ examples: - | #include soc { - #address-cells =3D <2>; - #size-cells =3D <2>; - clkcfg: clock-controller@20002000 { + #address-cells =3D <1>; + #size-cells =3D <1>; + + clkcfg: clock-controller@3E001000 { compatible =3D "microchip,mpfs-clkcfg"; - reg =3D <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0= x1000>; + reg =3D <0x3E001000 0x1000>; clocks =3D <&ref>; #clock-cells =3D <1>; }; --=20 2.51.0 From nobody Sat Feb 7 13:41:35 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E3EB9344025; Wed, 29 Oct 2025 16:11:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761754305; cv=none; b=kGIctDRwOtQq8frwcNCmG5IjpOEby99gBVawgHZKdLDDZzVSlRFPt6+8YZ3nqciisdVl13akcrKW7jOnuhjwgdUEBxE1rcI9UlHYV2h+IHru0ijadezGxlvgbKzN6771yZu8XKMvnnh3y6ljUvRjJVxH1pr5CRA70SKB4PDP7l8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761754305; c=relaxed/simple; bh=aZIjHtly/v+niXScbbIy10UhhOoZxWZhit3d3603RhY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=fQeINGuqgZcvnBrHQN/yiqrozq67TVh59uI9CVhPlDCpTuZfN1jq5VtJFVa+HjFP+aObeHCf0lQ1jxkjgmAgi0a3VzHLokmRC3MLf8YL6o/9PehTdfnUrOsa6xGf3SML93/2MHku6IFaqcvAiMZPOQoETeaecTkRMutJij/C57s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=tdlDZRf1; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="tdlDZRf1" Received: by smtp.kernel.org (Postfix) with ESMTPSA id AC19DC4CEFF; Wed, 29 Oct 2025 16:11:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1761754304; bh=aZIjHtly/v+niXScbbIy10UhhOoZxWZhit3d3603RhY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=tdlDZRf1jkmshb1ohgOVmDVz/GFvSt/bj3DAklQ9Pwy2WFR7rY6dHk+EMrVC/VRse S0bcjXVlln+8ATIUMn1UEA/PoAq/G0bF0oaYDY8+aoUal+CBgmIbkv9cx0PkjgCD4R f6/6HwD1OIODRXodm3FUc1wMcnOvq1JG+pERZnsWQ38CPdYNtHJPQNHKH9AtojRvD9 kPQKca8+WzWOcvzuWCtUnWMSdqH1HDWWUOsIrcYBynNo1dmCxd842se5LL7pfbGwy6 pnLfw5ia0wDpzi2nXaZZtN+B6+IwkXqmQ/RXj2sCen66SRYhIcJfblcwuM4WXXALfg WKDGJEF9ZUPAA== From: Conor Dooley To: claudiu.beznea@tuxon.dev Cc: conor@kernel.org, Conor Dooley , Daire McNamara , pierre-henry.moussay@microchip.com, valentina.fernandezalanis@microchip.com, Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Philipp Zabel , linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 3/7] clk: microchip: mpfs: use regmap for clocks Date: Wed, 29 Oct 2025 16:11:19 +0000 Message-ID: <20251029-surfboard-refocus-ca9b135ab123@spud> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251029-chewing-absolve-c4e6acfe0fa4@spud> References: <20251029-chewing-absolve-c4e6acfe0fa4@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=12535; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=kAOkUiiat4dSSwrUrQMbpHYhZj3/SqHFi7V2PyRP9Rk=; b=owGbwMvMwCVWscWwfUFT0iXG02pJDJlMNuvqG6aYTyo4q7xpody2i9sqftbsP3vi7BfbLY/ux BxaoLVOtKOUhUGMi0FWTJEl8XZfi9T6Py47nHvewsxhZQIZwsDFKQATcTnFyND9INJ37YXs0Efr 2/Td9LbLeX58mTL58mQ/pqXrtMT/PVrG8Fe+qie7nVMyn+nNgR99CeaSJomzu0T+rnXmP2fUt1o mnhcA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley Convert the PolarFire SoC clock driver to use regmaps instead of iomem addresses as a preparatory work for supporting the new binding for this device that will only provide the second of the two register regions, and will require the use of syscon regmap to access the "cfg" and "periph" clocks currently supported by the driver. This is effectively a revert of commit 4da2404bb003 ("clk: microchip: mpfs: convert cfg_clk to clk_divider") and commit d815569783e6 ("clk: microchip: mpfs: convert periph_clk to clk_gate") as it resurrects the ops structures removed in those commits, with the readl()s and writel()s replaced by regmap_read()s and regmap_writes()s. Signed-off-by: Conor Dooley Reviewed-by: Claudiu Beznea --- v6: - use regmap_update_bits() instead of regmap_read() -> regmap_write() RMW sequences - drop driver specific lock, since regmap has internal locking - implement determine_rate instead of round_rate --- drivers/clk/microchip/Kconfig | 2 + drivers/clk/microchip/clk-mpfs.c | 227 +++++++++++++++++++++++++------ 2 files changed, 186 insertions(+), 43 deletions(-) diff --git a/drivers/clk/microchip/Kconfig b/drivers/clk/microchip/Kconfig index 0724ce65898f..1b9e43eb5497 100644 --- a/drivers/clk/microchip/Kconfig +++ b/drivers/clk/microchip/Kconfig @@ -7,6 +7,8 @@ config MCHP_CLK_MPFS bool "Clk driver for PolarFire SoC" depends on ARCH_MICROCHIP_POLARFIRE || COMPILE_TEST default ARCH_MICROCHIP_POLARFIRE + depends on MFD_SYSCON select AUXILIARY_BUS + select REGMAP_MMIO help Supports Clock Configuration for PolarFire SoC diff --git a/drivers/clk/microchip/clk-mpfs.c b/drivers/clk/microchip/clk-m= pfs.c index c22632a7439c..484893e68b67 100644 --- a/drivers/clk/microchip/clk-mpfs.c +++ b/drivers/clk/microchip/clk-mpfs.c @@ -4,10 +4,13 @@ * * Copyright (C) 2020-2022 Microchip Technology Inc. All rights reserved. */ +#include #include #include +#include #include #include +#include #include #include =20 @@ -30,6 +33,14 @@ #define MSSPLL_POSTDIV_WIDTH 0x07u #define MSSPLL_FIXED_DIV 4u =20 +static const struct regmap_config mpfs_clk_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .val_format_endian =3D REGMAP_ENDIAN_LITTLE, + .max_register =3D REG_SUBBLK_CLOCK_CR, +}; + /* * This clock ID is defined here, rather than the binding headers, as it i= s an * internal clock only, and therefore has no consumers in other peripheral @@ -39,6 +50,7 @@ =20 struct mpfs_clock_data { struct device *dev; + struct regmap *regmap; void __iomem *base; void __iomem *msspll_base; struct clk_hw_onecell_data hw_data; @@ -67,21 +79,39 @@ struct mpfs_msspll_out_hw_clock { =20 #define to_mpfs_msspll_out_clk(_hw) container_of(_hw, struct mpfs_msspll_o= ut_hw_clock, hw) =20 +struct mpfs_cfg_clock { + struct regmap *map; + const struct clk_div_table *table; + u8 map_offset; + u8 shift; + u8 width; + u8 flags; +}; + struct mpfs_cfg_hw_clock { - struct clk_divider cfg; - struct clk_init_data init; + struct clk_hw hw; + struct mpfs_cfg_clock cfg; unsigned int id; - u32 reg_offset; +}; + +#define to_mpfs_cfg_clk(_hw) container_of(_hw, struct mpfs_cfg_hw_clock, h= w) + +struct mpfs_periph_clock { + struct regmap *map; + u8 map_offset; + u8 shift; }; =20 struct mpfs_periph_hw_clock { - struct clk_gate periph; + struct clk_hw hw; + struct mpfs_periph_clock periph; unsigned int id; }; =20 +#define to_mpfs_periph_clk(_hw) container_of(_hw, struct mpfs_periph_hw_cl= ock, hw) + /* - * mpfs_clk_lock prevents anything else from writing to the - * mpfs clk block while a software locked register is being written. + * Protects MSSPLL outputs, since there's two to a register */ static DEFINE_SPINLOCK(mpfs_clk_lock); =20 @@ -219,16 +249,61 @@ static int mpfs_clk_register_msspll_outs(struct devic= e *dev, /* * "CFG" clocks */ +static unsigned long mpfs_cfg_clk_recalc_rate(struct clk_hw *hw, unsigned = long prate) +{ + struct mpfs_cfg_hw_clock *cfg_hw =3D to_mpfs_cfg_clk(hw); + struct mpfs_cfg_clock *cfg =3D &cfg_hw->cfg; + u32 val; =20 -#define CLK_CFG(_id, _name, _parent, _shift, _width, _table, _flags, _offs= et) { \ - .id =3D _id, \ - .cfg.shift =3D _shift, \ - .cfg.width =3D _width, \ - .cfg.table =3D _table, \ - .reg_offset =3D _offset, \ - .cfg.flags =3D _flags, \ - .cfg.hw.init =3D CLK_HW_INIT(_name, _parent, &clk_divider_ops, 0), \ - .cfg.lock =3D &mpfs_clk_lock, \ + regmap_read(cfg->map, cfg->map_offset, &val); + val >>=3D cfg->shift; + val &=3D clk_div_mask(cfg->width); + + return divider_recalc_rate(hw, prate, val, cfg->table, cfg->flags, cfg->w= idth); +} + +static int mpfs_cfg_clk_determine_rate(struct clk_hw *hw, struct clk_rate_= request *req) +{ + struct mpfs_cfg_hw_clock *cfg_hw =3D to_mpfs_cfg_clk(hw); + struct mpfs_cfg_clock *cfg =3D &cfg_hw->cfg; + + return divider_determine_rate(hw, req, cfg->table, cfg->width, 0); +} + +static int mpfs_cfg_clk_set_rate(struct clk_hw *hw, unsigned long rate, un= signed long prate) +{ + struct mpfs_cfg_hw_clock *cfg_hw =3D to_mpfs_cfg_clk(hw); + struct mpfs_cfg_clock *cfg =3D &cfg_hw->cfg; + int divider_setting; + u32 val; + u32 mask; + + divider_setting =3D divider_get_val(rate, prate, cfg->table, cfg->width, = 0); + + if (divider_setting < 0) + return divider_setting; + + mask =3D clk_div_mask(cfg->width) << cfg->shift; + val =3D divider_setting << cfg->shift; + regmap_update_bits(cfg->map, cfg->map_offset, val, mask); + + return 0; +} + +static const struct clk_ops mpfs_clk_cfg_ops =3D { + .recalc_rate =3D mpfs_cfg_clk_recalc_rate, + .determine_rate =3D mpfs_cfg_clk_determine_rate, + .set_rate =3D mpfs_cfg_clk_set_rate, +}; + +#define CLK_CFG(_id, _name, _parent, _shift, _width, _table, _flags, _offs= et) { \ + .id =3D _id, \ + .cfg.shift =3D _shift, \ + .cfg.width =3D _width, \ + .cfg.table =3D _table, \ + .cfg.map_offset =3D _offset, \ + .cfg.flags =3D _flags, \ + .hw.init =3D CLK_HW_INIT(_name, _parent, &mpfs_clk_cfg_ops, 0), \ } =20 #define CLK_CPU_OFFSET 0u @@ -248,10 +323,10 @@ static struct mpfs_cfg_hw_clock mpfs_cfg_clks[] =3D { .cfg.shift =3D 0, .cfg.width =3D 12, .cfg.table =3D mpfs_div_rtcref_table, - .reg_offset =3D REG_RTC_CLOCK_CR, + .cfg.map_offset =3D REG_RTC_CLOCK_CR, .cfg.flags =3D CLK_DIVIDER_ONE_BASED, - .cfg.hw.init =3D - CLK_HW_INIT_PARENTS_DATA("clk_rtcref", mpfs_ext_ref, &clk_divider_ops, = 0), + .hw.init =3D + CLK_HW_INIT_PARENTS_DATA("clk_rtcref", mpfs_ext_ref, &mpfs_clk_cfg_ops,= 0), } }; =20 @@ -264,14 +339,14 @@ static int mpfs_clk_register_cfgs(struct device *dev,= struct mpfs_cfg_hw_clock * for (i =3D 0; i < num_clks; i++) { struct mpfs_cfg_hw_clock *cfg_hw =3D &cfg_hws[i]; =20 - cfg_hw->cfg.reg =3D data->base + cfg_hw->reg_offset; - ret =3D devm_clk_hw_register(dev, &cfg_hw->cfg.hw); + cfg_hw->cfg.map =3D data->regmap; + ret =3D devm_clk_hw_register(dev, &cfg_hw->hw); if (ret) return dev_err_probe(dev, ret, "failed to register clock id: %d\n", cfg_hw->id); =20 id =3D cfg_hw->id; - data->hw_data.hws[id] =3D &cfg_hw->cfg.hw; + data->hw_data.hws[id] =3D &cfg_hw->hw; } =20 return 0; @@ -281,15 +356,50 @@ static int mpfs_clk_register_cfgs(struct device *dev,= struct mpfs_cfg_hw_clock * * peripheral clocks - devices connected to axi or ahb buses. */ =20 -#define CLK_PERIPH(_id, _name, _parent, _shift, _flags) { \ - .id =3D _id, \ - .periph.bit_idx =3D _shift, \ - .periph.hw.init =3D CLK_HW_INIT_HW(_name, _parent, &clk_gate_ops, \ - _flags), \ - .periph.lock =3D &mpfs_clk_lock, \ +static int mpfs_periph_clk_enable(struct clk_hw *hw) +{ + struct mpfs_periph_hw_clock *periph_hw =3D to_mpfs_periph_clk(hw); + struct mpfs_periph_clock *periph =3D &periph_hw->periph; + + regmap_update_bits(periph->map, periph->map_offset, + BIT(periph->shift), BIT(periph->shift)); + + return 0; } =20 -#define PARENT_CLK(PARENT) (&mpfs_cfg_clks[CLK_##PARENT##_OFFSET].cfg.hw) +static void mpfs_periph_clk_disable(struct clk_hw *hw) +{ + struct mpfs_periph_hw_clock *periph_hw =3D to_mpfs_periph_clk(hw); + struct mpfs_periph_clock *periph =3D &periph_hw->periph; + + regmap_update_bits(periph->map, periph->map_offset, BIT(periph->shift), 0= ); +} + +static int mpfs_periph_clk_is_enabled(struct clk_hw *hw) +{ + struct mpfs_periph_hw_clock *periph_hw =3D to_mpfs_periph_clk(hw); + struct mpfs_periph_clock *periph =3D &periph_hw->periph; + u32 val; + + regmap_read(periph->map, periph->map_offset, &val); + + return !!(val & BIT(periph->shift)); +} + +static const struct clk_ops mpfs_periph_clk_ops =3D { + .enable =3D mpfs_periph_clk_enable, + .disable =3D mpfs_periph_clk_disable, + .is_enabled =3D mpfs_periph_clk_is_enabled, +}; + +#define CLK_PERIPH(_id, _name, _parent, _shift, _flags) { \ + .id =3D _id, \ + .periph.map_offset =3D REG_SUBBLK_CLOCK_CR, \ + .periph.shift =3D _shift, \ + .hw.init =3D CLK_HW_INIT_HW(_name, _parent, &mpfs_periph_clk_ops, _flags)= , \ +} + +#define PARENT_CLK(PARENT) (&mpfs_cfg_clks[CLK_##PARENT##_OFFSET].hw) =20 /* * Critical clocks: @@ -346,19 +456,55 @@ static int mpfs_clk_register_periphs(struct device *d= ev, struct mpfs_periph_hw_c for (i =3D 0; i < num_clks; i++) { struct mpfs_periph_hw_clock *periph_hw =3D &periph_hws[i]; =20 - periph_hw->periph.reg =3D data->base + REG_SUBBLK_CLOCK_CR; - ret =3D devm_clk_hw_register(dev, &periph_hw->periph.hw); + periph_hw->periph.map =3D data->regmap; + ret =3D devm_clk_hw_register(dev, &periph_hw->hw); if (ret) return dev_err_probe(dev, ret, "failed to register clock id: %d\n", periph_hw->id); =20 id =3D periph_hws[i].id; - data->hw_data.hws[id] =3D &periph_hw->periph.hw; + data->hw_data.hws[id] =3D &periph_hw->hw; } =20 return 0; } =20 +static inline int mpfs_clk_syscon_probe(struct mpfs_clock_data *clk_data, + struct platform_device *pdev) +{ + clk_data->regmap =3D syscon_regmap_lookup_by_compatible("microchip,mpfs-m= ss-top-sysreg"); + if (IS_ERR(clk_data->regmap)) + return PTR_ERR(clk_data->regmap); + + clk_data->msspll_base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(clk_data->msspll_base)) + return PTR_ERR(clk_data->msspll_base); + + return 0; +} + +static inline int mpfs_clk_old_format_probe(struct mpfs_clock_data *clk_da= ta, + struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + + dev_warn(&pdev->dev, "falling back to old devicetree format"); + + clk_data->base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(clk_data->base)) + return PTR_ERR(clk_data->base); + + clk_data->msspll_base =3D devm_platform_ioremap_resource(pdev, 1); + if (IS_ERR(clk_data->msspll_base)) + return PTR_ERR(clk_data->msspll_base); + + clk_data->regmap =3D devm_regmap_init_mmio(dev, clk_data->base, &mpfs_clk= _regmap_config); + if (IS_ERR(clk_data->regmap)) + return PTR_ERR(clk_data->regmap); + + return mpfs_reset_controller_register(dev, clk_data->base + REG_SUBBLK_RE= SET_CR); +} + static int mpfs_clk_probe(struct platform_device *pdev) { struct device *dev =3D &pdev->dev; @@ -374,13 +520,12 @@ static int mpfs_clk_probe(struct platform_device *pde= v) if (!clk_data) return -ENOMEM; =20 - clk_data->base =3D devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(clk_data->base)) - return PTR_ERR(clk_data->base); - - clk_data->msspll_base =3D devm_platform_ioremap_resource(pdev, 1); - if (IS_ERR(clk_data->msspll_base)) - return PTR_ERR(clk_data->msspll_base); + ret =3D mpfs_clk_syscon_probe(clk_data, pdev); + if (ret) { + ret =3D mpfs_clk_old_format_probe(clk_data, pdev); + if (ret) + return ret; + } =20 clk_data->hw_data.num =3D num_clks; clk_data->dev =3D dev; @@ -406,11 +551,7 @@ static int mpfs_clk_probe(struct platform_device *pdev) if (ret) return ret; =20 - ret =3D devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, &clk_data= ->hw_data); - if (ret) - return ret; - - return mpfs_reset_controller_register(dev, clk_data->base + REG_SUBBLK_RE= SET_CR); + return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, &clk_data-= >hw_data); } =20 static const struct of_device_id mpfs_clk_of_match_table[] =3D { --=20 2.51.0 From nobody Sat Feb 7 13:41:35 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CA8A9345759; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="shL+YnIa" Received: by smtp.kernel.org (Postfix) with ESMTPSA id D989AC4CEF8; Wed, 29 Oct 2025 16:11:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1761754307; bh=yx40n6aW+7axlHFIv+/k4z1XcQ+4QDorszZ6b/jKM44=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=shL+YnIan2zZqQcm7YTriVz713DFPhdH2niLVFZdiWRW4nO2yK9V7sJqSwkLrdaeU 30wlimwKz1xybhPt5ctiYBaJZ0Zm6lx1H2HOUzcd1dglYp8MnMewMg2/b7ik2a9vIh FZCk5zEYSv33GfdwyKV9eHgmxadTkeFdhXZiFXGrIAYy34itjnm0w/4oCh03FYn2/i 6gJVSEPYEjToVkeDk8Klf425qY4BYiwndogt4aWvqoZb9IU8vSse4xnl91pNKt9a3x vRHJO0SkyIfEe/FbRWv/VEoKXikG/b7TXSEaNZUfDdDcHFO6I8CWsQZlXpx3MV0BUv 9vj3BL8KeO1aA== From: Conor Dooley To: claudiu.beznea@tuxon.dev Cc: conor@kernel.org, Conor Dooley , Daire McNamara , pierre-henry.moussay@microchip.com, valentina.fernandezalanis@microchip.com, Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Philipp Zabel , linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 4/7] riscv: dts: microchip: fix mailbox description Date: Wed, 29 Oct 2025 16:11:20 +0000 Message-ID: <20251029-cobbler-unwritten-b907859d048d@spud> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251029-chewing-absolve-c4e6acfe0fa4@spud> References: <20251029-chewing-absolve-c4e6acfe0fa4@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2048; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=CJ93zZ/gwT2VF26tXat2Gljwq2Roq9NVUZwBFI4dODQ=; b=owGbwMvMwCVWscWwfUFT0iXG02pJDJlMNusz1M0/cvfZGng1c7NuXpdx5OO+aHaF2IqGnKU1t pyPb2p0lLIwiHExyIopsiTe7muRWv/HZYdzz1uYOaxMIEMYuDgFYCJn3zMybHtncCWt+N3sea8i xVQSLZemCSVx1R8PWRN21D1hyuavDxj+p9lc2dbM/t7u/gE1nhKHBQHuWdb/Z620FFgVLZSzljm LBQA= X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley When the binding for the mailbox on PolarFire SoC was originally written, and later modified, mistakes were made - and the precise nature of the later modification should have been a giveaway, but alas I was naive at the time. A more correct modelling of the hardware is to use two syscons and have a single reg entry for the mailbox, containing the mailbox region. The two syscons contain the general control/status registers for the mailbox and the interrupt related registers respectively. The reason for two syscons is that the same mailbox is present on the non-SoC version of the FPGA, which has no interrupt controller, and the shared part of the rtl was unchanged between devices. Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/microchip/mpfs.dtsi | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/= microchip/mpfs.dtsi index 9883ca3554c5..f9d6bf08e717 100644 --- a/arch/riscv/boot/dts/microchip/mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi @@ -259,6 +259,11 @@ clkcfg: clkcfg@20002000 { #reset-cells =3D <1>; }; =20 + sysreg_scb: syscon@20003000 { + compatible =3D "microchip,mpfs-sysreg-scb", "syscon"; + reg =3D <0x0 0x20003000 0x0 0x1000>; + }; + ccc_se: clock-controller@38010000 { compatible =3D "microchip,mpfs-ccc"; reg =3D <0x0 0x38010000 0x0 0x1000>, <0x0 0x38020000 0x0 0x1000>, @@ -521,10 +526,14 @@ usb: usb@20201000 { status =3D "disabled"; }; =20 - mbox: mailbox@37020000 { + control_scb: syscon@37020000 { + compatible =3D "microchip,mpfs-control-scb", "syscon"; + reg =3D <0x0 0x37020000 0x0 0x100>; + }; + + mbox: mailbox@37020800 { compatible =3D "microchip,mpfs-mailbox"; - reg =3D <0x0 0x37020000 0x0 0x58>, <0x0 0x2000318C 0x0 0x40>, - <0x0 0x37020800 0x0 0x100>; + reg =3D <0x0 0x37020800 0x0 0x1000>; interrupt-parent =3D <&plic>; interrupts =3D <96>; #mbox-cells =3D <1>; --=20 2.51.0 From nobody Sat Feb 7 13:41:35 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7B1C92EC088; Wed, 29 Oct 2025 16:11:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761754311; cv=none; b=qGJsrMpm+uNSQa3w6KTx7ZbPniO2Gh2WoT+7Cmgn6qHhxFnoJJdQOcj2Hhbl6PLYVd8guDCKh7Yve7FIJoEQaDR0ca0z1UcY95fPeDUNHslyikAOZxzell4evgd5lf/fJAtWjWurllSoDhNz5hWb/Q4755k/t/XTtJMGaSgGg+A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761754311; c=relaxed/simple; bh=o06pwj8GQhduMpl8X9PMCjFDAGlLMLElJucB88tSCYo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=CdvFEkSQ28Rh24DuPo4AhByiRPwLgAVe+GyjJ2Q+nL6afTn7+3GKwolHhU5GsuL+QkqQRFQhzVNKaCbEqjQVIRAI1swvW844jYmIuajW3Wh36ACIOXRJ4iYGXpSObQJUs0aiv7/zKi1fl7C/lyHKTNNj3Icaj2ckOfsMzOaCcig= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=O0gI1KfZ; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="O0gI1KfZ" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 12FEFC4CEF7; Wed, 29 Oct 2025 16:11:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1761754310; bh=o06pwj8GQhduMpl8X9PMCjFDAGlLMLElJucB88tSCYo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=O0gI1KfZlA0/45L4U9eJrx6qpu2IGzA4wsjML93oPVhLNXOYtnWX6CXllgZboqBWY vhyfgBB7crP61m7dAm7gSTWaW2puf4AiUZ0jf2IkEAYPPAsdIeOWZ46byVOAJny4vt vCJBbKeyLaK6wA0nB1rKUpAWQmZh4kYAkvaqM4xicqU5J/X+9ELkj97AtmW2+tIXA1 mOQw9x9JmMJRo7iiaGICMrZLj6sNQ9IweicaszD5IzK59M50W6DfWee2Nm6kQWLMB6 FLvzrC/+KfgsiMu13uEq2OeZqvvKZpp0eFsDRZSnXJak8K7tXoyndkITATDw8434ED dcNcJp4fIBM5g== From: Conor Dooley To: claudiu.beznea@tuxon.dev Cc: conor@kernel.org, Conor Dooley , Daire McNamara , pierre-henry.moussay@microchip.com, valentina.fernandezalanis@microchip.com, Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Philipp Zabel , linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 5/7] riscv: dts: microchip: convert clock and reset to use syscon Date: Wed, 29 Oct 2025 16:11:21 +0000 Message-ID: <20251029-polyester-dubiously-55915f5c7962@spud> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251029-chewing-absolve-c4e6acfe0fa4@spud> References: <20251029-chewing-absolve-c4e6acfe0fa4@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2216; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=+zR8fbMXO9YW4YzwKnjp5SrmA8iRht4FGjwYBRXJ6yY=; b=owGbwMvMwCVWscWwfUFT0iXG02pJDJlMNut3HPy0mnNWf/rhFwWOM+01G8SW19s+mH++M/St6 h4r7aurO0pZGMS4GGTFFFkSb/e1SK3/47LDuectzBxWJpAhDFycAjCR0/EMfwWVq15GmWRs9jj8 +qGyFMu2KuEjAlv03W977glfPo/p5yWGf1qL9SO2Rmddm/bttfaSq9/2h0pYNjKHWDqx8XfUNU7 ezgEA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley The "subblock" clocks and reset registers on PolarFire SoC are located in the mss-top-sysreg region, alongside pinctrl and interrupt control functionality. Re-write the devicetree to describe the sys explicitly, as its own node, rather than as a region of the clock node. Correspondingly, the phandles to the reset controller must be updated to the new provider. The drivers will continue to support the old way of doing things. Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/microchip/mpfs.dtsi | 19 ++++++++++++------- 1 file changed, 12 insertions(+), 7 deletions(-) diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/= microchip/mpfs.dtsi index f9d6bf08e717..5c2963e269b8 100644 --- a/arch/riscv/boot/dts/microchip/mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi @@ -251,11 +251,9 @@ pdma: dma-controller@3000000 { #dma-cells =3D <1>; }; =20 - clkcfg: clkcfg@20002000 { - compatible =3D "microchip,mpfs-clkcfg"; - reg =3D <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0x1000>; - clocks =3D <&refclk>; - #clock-cells =3D <1>; + mss_top_sysreg: syscon@20002000 { + compatible =3D "microchip,mpfs-mss-top-sysreg", "syscon", "simple-mfd"; + reg =3D <0x0 0x20002000 0x0 0x1000>; #reset-cells =3D <1>; }; =20 @@ -452,7 +450,7 @@ mac0: ethernet@20110000 { local-mac-address =3D [00 00 00 00 00 00]; clocks =3D <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>; clock-names =3D "pclk", "hclk"; - resets =3D <&clkcfg CLK_MAC0>; + resets =3D <&mss_top_sysreg CLK_MAC0>; status =3D "disabled"; }; =20 @@ -466,7 +464,7 @@ mac1: ethernet@20112000 { local-mac-address =3D [00 00 00 00 00 00]; clocks =3D <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>; clock-names =3D "pclk", "hclk"; - resets =3D <&clkcfg CLK_MAC1>; + resets =3D <&mss_top_sysreg CLK_MAC1>; status =3D "disabled"; }; =20 @@ -550,5 +548,12 @@ syscontroller_qspi: spi@37020100 { clocks =3D <&scbclk>; status =3D "disabled"; }; + + clkcfg: clkcfg@3e001000 { + compatible =3D "microchip,mpfs-clkcfg"; + reg =3D <0x0 0x3e001000 0x0 0x1000>; + clocks =3D <&refclk>; + #clock-cells =3D <1>; + }; }; }; --=20 2.51.0 From nobody Sat Feb 7 13:41:35 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 794D634AB1F; Wed, 29 Oct 2025 16:11:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Wed, 29 Oct 2025 16:11:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1761754314; bh=E43Z5Y8tSJqRgamwuiELwt0g0OSF4ium8fxWSOTU1R0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=cuTtSTQLMy3fnNiduDQZvyUp5JHLt08l6kcgxU8V9U+NVbB2/rb7/phdVDs89J/BE yYXTm/8RLSbtrTo+Sin6ArdYWC572FSz3vJk30Tf6bJ4twOuyK45LftApfqB0aM0Sl 5ujEYXPhRHzLWnd5RonWzEpIgKTD+w+Y/YhLg8knFxKQCNXN9AJbt+RLZq+/2glumL R6q7YpophojoKXEgngZFcbV4WAQ8CwEuOBJ+geOWjXnWNmyQL7aBk/ZWbf44N8LzHQ aPNiBaBszcZ+Rr8gTOqOWZADHIU2qeTmpQ2r8nftSRuatuvSoKu81J46zk69Tl0tp4 LlMTxpTnRKKsQ== From: Conor Dooley To: claudiu.beznea@tuxon.dev Cc: conor@kernel.org, Conor Dooley , Daire McNamara , pierre-henry.moussay@microchip.com, valentina.fernandezalanis@microchip.com, Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Philipp Zabel , linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 6/7] MAINTAINERS: add new soc drivers to Microchip RISC-V entry Date: Wed, 29 Oct 2025 16:11:22 +0000 Message-ID: <20251029-bonded-uranium-0b985c14a758@spud> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251029-chewing-absolve-c4e6acfe0fa4@spud> References: <20251029-chewing-absolve-c4e6acfe0fa4@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=733; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=gmAo0f4txEXEqIJYVzrDbfZIGVrUbtgonOlTrrMh7lQ=; b=owGbwMvMwCVWscWwfUFT0iXG02pJDJlMNuuPTn7jwGt0ibH5lOFzyWtXUicz7d/c4yDh45s0v 7859c3UjlIWBjEuBlkxRZbE230tUuv/uOxw7nkLM4eVCWQIAxenAEzkFB/DfydvuX9pd5UO6bv4 FT3WU5jU56nCpPpQ1vCDvW/c/yNxLowMb5KfdE202efKZjKz28Bg6c1XZyJ8VNVVTY5ULPa4zHC ZDQA= X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley Add the two new syscon drivers to the RISC-V entry for Microchip platforms. Signed-off-by: Conor Dooley --- MAINTAINERS | 2 ++ 1 file changed, 2 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 46126ce2f968..a28740a7d87a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -22105,6 +22105,8 @@ F: drivers/pci/controller/plda/pcie-microchip-host.c F: drivers/pwm/pwm-microchip-core.c F: drivers/reset/reset-mpfs.c F: drivers/rtc/rtc-mpfs.c +F: drivers/soc/microchip/mpfs-control-scb.c +F: drivers/soc/microchip/mpfs-mss-top-sysreg.c F: drivers/soc/microchip/mpfs-sys-controller.c F: drivers/spi/spi-microchip-core-qspi.c F: drivers/spi/spi-microchip-core.c --=20 2.51.0 From nobody Sat Feb 7 13:41:35 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C479B32E125; Wed, 29 Oct 2025 16:11:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761754317; cv=none; b=HOez2n6yPTYm19pDR4UEhAgwbA4/tqWYEJDswpiHzZp01gLvec6gqYzlDsuyvr029RWmesDzhpMDijHBHZFzsBXnDyF/IuBCBrrSTVwGC/tj8wo9l73nuvyilgA7fS1skEn4ie+jaqO6WjKIveXcub8KXNpODScN75BNcKgp+9g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761754317; c=relaxed/simple; bh=4tliw4UQndH1N9g1/up84eMEVp/xYC+YCAsm2JdOf3U=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Cgk2WyBNi2Gosi3exlP3BGhkuBwHXCjTLjJfUsAz8DOY+poG8KoPCX87vMgFkGDKmno5/UNSpgOdMkkUaQXJJXQaEDPIULf5NJkH/rLuyvqCg26zEkfRrcSTXLXWQCMzTKbP8wGhaRtFRWmpOReMMBVDxwCSEqQjnHXxundRhxI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=DDik67Xj; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="DDik67Xj" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6F9E4C4CEF8; Wed, 29 Oct 2025 16:11:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1761754317; bh=4tliw4UQndH1N9g1/up84eMEVp/xYC+YCAsm2JdOf3U=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=DDik67Xj2g89qtJbhs05ihSJj1yuG8PXOTAlyqGqaHz91XBjOhszwyGqHOVvLB/4U rqmdClAvEu+T4Ct5K8CAGQRCtqcK+N5cDJ0A0SMUOIk4tjw+waLVHy2csrayoOjxyH oYMTQyfA2utC8FJ8FieW2497NYjVTk2G5DRqwGPhzMwy002nKv1gFDhUe+TYZnm/oO BDCVIueC6yO1hzRzl+la8/bEWGwKwzh4rujaN8N3gZSP7ZUZxUs6LGsfuPusMB31Sd uuKme3s/ZEBMq3/KhhFL7nkHX0HZ781nSOhcyZK11GooOwrPFc0OcnHK0qGcIo44X/ PTt6vXAgwIVPQ== From: Conor Dooley To: claudiu.beznea@tuxon.dev Cc: conor@kernel.org, Conor Dooley , Daire McNamara , pierre-henry.moussay@microchip.com, valentina.fernandezalanis@microchip.com, Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Philipp Zabel , linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 7/7] MAINTAINERS: rename Microchip RISC-V entry Date: Wed, 29 Oct 2025 16:11:23 +0000 Message-ID: <20251029-timing-venue-1cd20c3450ac@spud> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251029-chewing-absolve-c4e6acfe0fa4@spud> References: <20251029-chewing-absolve-c4e6acfe0fa4@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=735; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=WjqbuqvJbBVUVn1s3EoLv4wSnU+jVPnRC0yZy4Sseq4=; b=owGbwMvMwCVWscWwfUFT0iXG02pJDJlMNusF9rzrT3y85rnMwW1Ve/sfH/j9ccWcxf3H+mWPe l1pU2na3lHKwiDGxSArpsiSeLuvRWr9H5cdzj1vYeawMoEMYeDiFICJuMUw/K/M3HBAemLkxk2K 9xmmJPQlHLw8ecIbdqcyp2nb/vxOfviekWGGyeEk84JLk3mTV1qoiCc9nKu58tTMxlX6X1dVuKd LcnIDAA== X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley There's now non-FPGA RISC-V SoCs from Microchip, so rename the entry to reflect that. Signed-off-by: Conor Dooley --- MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index a28740a7d87a..24efae3df425 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -22079,7 +22079,7 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/gi= t/iommu/linux.git F: Documentation/devicetree/bindings/iommu/riscv,iommu.yaml F: drivers/iommu/riscv/ =20 -RISC-V MICROCHIP FPGA SUPPORT +RISC-V MICROCHIP SUPPORT M: Conor Dooley M: Daire McNamara L: linux-riscv@lists.infradead.org --=20 2.51.0