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Wed, 29 Oct 2025 14:30:36 -0700 (PDT) From: Peter Griffin Date: Wed, 29 Oct 2025 21:29:22 +0000 Subject: [PATCH v2 1/4] dt-bindings: clock: google,gs101-clock: add samsung,sysreg property as required Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251029-automatic-clocks-v2-1-f8edd3a2d82b@linaro.org> References: <20251029-automatic-clocks-v2-0-f8edd3a2d82b@linaro.org> In-Reply-To: <20251029-automatic-clocks-v2-0-f8edd3a2d82b@linaro.org> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alim Akhtar , =?utf-8?q?Andr=C3=A9_Draszik?= , Tudor Ambarus , Michael Turquette , Stephen Boyd , Sam Protsenko , Sylwester Nawrocki , Chanwoo Choi Cc: Will McVicker , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, kernel-team@android.com, Peter Griffin , Krzysztof Kozlowski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=0EFC8E6F5578750D56B549FCCEE8B8D6023472BA Each CMU (with the exception of cmu_top) has a corresponding sysreg bank that contains the BUSCOMPONENT_DRCG_EN and MEMCLK registers. If present these registers need to be initialised in the clock driver. Update the bindings documentation so that all CMUs (with the exception of gs101-cmu-top) have samsung,sysreg as a required property. Additionally update the DT example to included the correct CMU size as registers in that region are used for auto clock mode. Signed-off-by: Peter Griffin --- v2: * Update commit description as to why the sysreg is required (Krzysztof) * Update commit description regarding updated example (Andre) --- .../bindings/clock/google,gs101-clock.yaml | 23 ++++++++++++++++++= +++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/clock/google,gs101-clock.yam= l b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml index 31e106ef913dead9a038b3b6d8b43b950587f6aa..5ce5ba523110af3a2a7740b8ba2= 8e2271c76bddb 100644 --- a/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml +++ b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml @@ -52,6 +52,11 @@ properties: reg: maxItems: 1 =20 + samsung,sysreg: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to system registers interface. + required: - compatible - "#clock-cells" @@ -166,6 +171,22 @@ allOf: - const: bus - const: ip =20 + - if: + properties: + compatible: + contains: + enum: + - google,gs101-cmu-apm + - google,gs101-cmu-misc + - google,gs101-hsi0 + - google,gs101-cmu-hsi2 + - google,gs101-cmu-peric0 + - google,gs101-cmu-peric1 + + then: + required: + - samsung,sysreg + additionalProperties: false =20 examples: @@ -175,7 +196,7 @@ examples: =20 cmu_top: clock-controller@1e080000 { compatible =3D "google,gs101-cmu-top"; - reg =3D <0x1e080000 0x8000>; + reg =3D <0x1e080000 0x10000>; #clock-cells =3D <1>; clocks =3D <&ext_24_5m>; clock-names =3D "oscclk"; --=20 2.51.1.851.g4ebd6896fd-goog