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Wed, 29 Oct 2025 14:30:36 -0700 (PDT) From: Peter Griffin Date: Wed, 29 Oct 2025 21:29:22 +0000 Subject: [PATCH v2 1/4] dt-bindings: clock: google,gs101-clock: add samsung,sysreg property as required Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251029-automatic-clocks-v2-1-f8edd3a2d82b@linaro.org> References: <20251029-automatic-clocks-v2-0-f8edd3a2d82b@linaro.org> In-Reply-To: <20251029-automatic-clocks-v2-0-f8edd3a2d82b@linaro.org> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alim Akhtar , =?utf-8?q?Andr=C3=A9_Draszik?= , Tudor Ambarus , Michael Turquette , Stephen Boyd , Sam Protsenko , Sylwester Nawrocki , Chanwoo Choi Cc: Will McVicker , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, kernel-team@android.com, Peter Griffin , Krzysztof Kozlowski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=0EFC8E6F5578750D56B549FCCEE8B8D6023472BA Each CMU (with the exception of cmu_top) has a corresponding sysreg bank that contains the BUSCOMPONENT_DRCG_EN and MEMCLK registers. If present these registers need to be initialised in the clock driver. Update the bindings documentation so that all CMUs (with the exception of gs101-cmu-top) have samsung,sysreg as a required property. Additionally update the DT example to included the correct CMU size as registers in that region are used for auto clock mode. Signed-off-by: Peter Griffin --- v2: * Update commit description as to why the sysreg is required (Krzysztof) * Update commit description regarding updated example (Andre) --- .../bindings/clock/google,gs101-clock.yaml | 23 ++++++++++++++++++= +++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/clock/google,gs101-clock.yam= l b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml index 31e106ef913dead9a038b3b6d8b43b950587f6aa..5ce5ba523110af3a2a7740b8ba2= 8e2271c76bddb 100644 --- a/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml +++ b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml @@ -52,6 +52,11 @@ properties: reg: maxItems: 1 =20 + samsung,sysreg: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to system registers interface. + required: - compatible - "#clock-cells" @@ -166,6 +171,22 @@ allOf: - const: bus - const: ip =20 + - if: + properties: + compatible: + contains: + enum: + - google,gs101-cmu-apm + - google,gs101-cmu-misc + - google,gs101-hsi0 + - google,gs101-cmu-hsi2 + - google,gs101-cmu-peric0 + - google,gs101-cmu-peric1 + + then: + required: + - samsung,sysreg + additionalProperties: false =20 examples: @@ -175,7 +196,7 @@ examples: =20 cmu_top: clock-controller@1e080000 { compatible =3D "google,gs101-cmu-top"; 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Wed, 29 Oct 2025 14:30:38 -0700 (PDT) From: Peter Griffin Date: Wed, 29 Oct 2025 21:29:23 +0000 Subject: [PATCH v2 2/4] arm64: dts: exynos: gs101: add samsung,sysreg property to CMU nodes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251029-automatic-clocks-v2-2-f8edd3a2d82b@linaro.org> References: <20251029-automatic-clocks-v2-0-f8edd3a2d82b@linaro.org> In-Reply-To: <20251029-automatic-clocks-v2-0-f8edd3a2d82b@linaro.org> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alim Akhtar , =?utf-8?q?Andr=C3=A9_Draszik?= , Tudor Ambarus , Michael Turquette , Stephen Boyd , Sam Protsenko , Sylwester Nawrocki , Chanwoo Choi Cc: Will McVicker , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, kernel-team@android.com, Peter Griffin , Krzysztof Kozlowski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=0EFC8E6F5578750D56B549FCCEE8B8D6023472BA sysreg bank contains BUSCOMPONENT_DRCG_EN and MEMCLK clock registers that need to be initialized in the CMU clock driver. Signed-off-by: Peter Griffin --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot= /dts/exynos/google/gs101.dtsi index d06d1d05f36408137a8acd98e43d48ea7d4f4292..c39ca4c4508f046ca16ae86be42= 468c7245561b8 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -578,6 +578,7 @@ cmu_misc: clock-controller@10010000 { clocks =3D <&cmu_top CLK_DOUT_CMU_MISC_BUS>, <&cmu_top CLK_DOUT_CMU_MISC_SSS>; clock-names =3D "bus", "sss"; + samsung,sysreg =3D <&sysreg_misc>; }; =20 sysreg_misc: syscon@10030000 { @@ -662,6 +663,7 @@ cmu_peric0: clock-controller@10800000 { <&cmu_top CLK_DOUT_CMU_PERIC0_BUS>, <&cmu_top CLK_DOUT_CMU_PERIC0_IP>; clock-names =3D "oscclk", "bus", "ip"; + samsung,sysreg =3D <&sysreg_peric0>; }; =20 sysreg_peric0: syscon@10820000 { @@ -1208,6 +1210,7 @@ cmu_peric1: clock-controller@10c00000 { <&cmu_top CLK_DOUT_CMU_PERIC1_BUS>, <&cmu_top CLK_DOUT_CMU_PERIC1_IP>; clock-names =3D "oscclk", "bus", "ip"; + samsung,sysreg =3D <&sysreg_peric1>; }; =20 sysreg_peric1: syscon@10c20000 { @@ -1566,6 +1569,7 @@ cmu_hsi0: clock-controller@11000000 { <&cmu_top CLK_DOUT_CMU_HSI0_USBDPDBG>; clock-names =3D "oscclk", "bus", "dpgtc", "usb31drd", "usbdpdbg"; + samsung,sysreg =3D <&sysreg_hsi0>; }; =20 sysreg_hsi0: syscon@11020000 { @@ -1637,6 +1641,7 @@ cmu_hsi2: clock-controller@14400000 { <&cmu_top CLK_DOUT_CMU_HSI2_UFS_EMBD>, <&cmu_top CLK_DOUT_CMU_HSI2_MMC_CARD>; clock-names =3D "oscclk", "bus", "pcie", "ufs", "mmc"; + samsung,sysreg =3D <&sysreg_hsi2>; }; =20 sysreg_hsi2: syscon@14420000 { @@ -1697,6 +1702,7 @@ cmu_apm: clock-controller@17400000 { =20 clocks =3D <&ext_24_5m>; clock-names =3D "oscclk"; + samsung,sysreg =3D <&sysreg_apm>; }; =20 sysreg_apm: syscon@17420000 { --=20 2.51.1.851.g4ebd6896fd-goog From nobody Sun Dec 14 11:14:00 2025 Received: from mail-wm1-f50.google.com (mail-wm1-f50.google.com [209.85.128.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 96A8631A567 for ; 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a=openpgp; fpr=0EFC8E6F5578750D56B549FCCEE8B8D6023472BA Update exynos_arm64_init_clocks() so that it enables the automatic clock mode bits in the CMU option register if the auto_clock_gate flag and option_offset fields are set for the CMU. To ensure compatibility with older DTs (that specified an incorrect CMU reg size), detect this and fallback to manual clock gate mode as the auto clock mode feature depends on registers in this area. The CMU option register bits are global and effect every clock component in the CMU, as such clearing the GATE_ENABLE_HWACG bit and setting GATE_MANUAL bit on every gate register is only required if auto_clock_gate is false. Additionally if auto_clock_gate is enabled the dynamic root clock gating and memclk registers will be configured in the corresponding CMUs sysreg bank. These registers are exposed via syscon, so the register samsung_clk_save/restore paths are updated to also take a regmap. As many gates for various Samsung SoCs are already exposed in the Samsung clock drivers a new samsung_auto_clk_gate_ops is implemented. This uses some CMU debug registers to report whether clocks are enabled or disabled when operating in automatic mode. This allows /sys/kernel/debug/clk/clk_summary to still dump the entire clock tree and correctly report the status of each clock in the system. Signed-off-by: Peter Griffin --- Changes in v2 * Fallback to manual clock gate mode for old DTs with incorrect CMU size (added samsung_is_auto_capable()) (Krzysztof) * Rename OPT_UNKNOWN bit to OPT_EN_LAYER2_CTRL (Andre) * Rename OPT_EN_MEM_PM_GATING to OPT_EN_MEM_PWR_GATING (Andre) * Reverse Option bit definitions LSB -> MSB (Krzysztof) * Update kerneldoc init_clk_regs comment (Andre) * Fix space on various comments (Andre) * Fix regmap typo on samsung_clk_save/restore calls (Andre) * Include error code in pr_err message (Andre) * Add macros for dcrg and memclk (Andre) * Avoid confusing !IS_ERR_OR_NULL(ctx->sysreg) test (Krzysztof) * Update kerneldoc to mention drcg_offset & memclk_offset are in sysreg (An= dre) * Fix intel 0 day randconfig warning * Update clk-s5pv210 and clk-s3c64xx.c samsung_clk_sleep_init call sites (P= eter) --- drivers/clk/samsung/clk-exynos-arm64.c | 62 ++++++++-- drivers/clk/samsung/clk-exynos4.c | 12 +- drivers/clk/samsung/clk-exynos4412-isp.c | 4 +- drivers/clk/samsung/clk-exynos5250.c | 2 +- drivers/clk/samsung/clk-exynos5420.c | 4 +- drivers/clk/samsung/clk-s3c64xx.c | 4 +- drivers/clk/samsung/clk-s5pv210.c | 2 +- drivers/clk/samsung/clk.c | 199 +++++++++++++++++++++++++++= +--- drivers/clk/samsung/clk.h | 55 ++++++++- 9 files changed, 301 insertions(+), 43 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos-arm64.c b/drivers/clk/samsung/c= lk-exynos-arm64.c index bf7de21f329ec89069dcf817ca578fcf9b2d9809..11e4d49f2390ba714eff5a329bb= 1f427cd6437b9 100644 --- a/drivers/clk/samsung/clk-exynos-arm64.c +++ b/drivers/clk/samsung/clk-exynos-arm64.c @@ -24,6 +24,16 @@ #define GATE_MANUAL BIT(20) #define GATE_ENABLE_HWACG BIT(28) =20 +/* Option register bits */ +#define OPT_EN_MEM_PWR_GATING BIT(24) +#define OPT_EN_AUTO_GATING BIT(28) +#define OPT_EN_PWR_MANAGEMENT BIT(29) +#define OPT_EN_LAYER2_CTRL BIT(30) +#define OPT_EN_DBG BIT(31) + +#define CMU_OPT_GLOBAL_EN_AUTO_GATING (OPT_EN_DBG | OPT_EN_LAYER2_CTRL | \ + OPT_EN_PWR_MANAGEMENT | OPT_EN_AUTO_GATING | OPT_EN_MEM_PWR_GATING) + /* PLL_CONx_PLL register offsets range */ #define PLL_CON_OFF_START 0x100 #define PLL_CON_OFF_END 0x600 @@ -37,6 +47,8 @@ struct exynos_arm64_cmu_data { unsigned int nr_clk_save; const struct samsung_clk_reg_dump *clk_suspend; unsigned int nr_clk_suspend; + struct samsung_clk_reg_dump *clk_sysreg_save; + unsigned int nr_clk_sysreg; =20 struct clk *clk; struct clk **pclks; @@ -76,19 +88,41 @@ static void __init exynos_arm64_init_clocks(struct devi= ce_node *np, const unsigned long *reg_offs =3D cmu->clk_regs; size_t reg_offs_len =3D cmu->nr_clk_regs; void __iomem *reg_base; + bool init_auto; size_t i; =20 reg_base =3D of_iomap(np, 0); if (!reg_base) panic("%s: failed to map registers\n", __func__); =20 + /* ensure compatibility with older DTs */ + if (cmu->auto_clock_gate && samsung_is_auto_capable(np)) + init_auto =3D true; + else + init_auto =3D false; + + if (cmu->option_offset && init_auto) { + /* + * Enable the global automatic mode for the entire CMU. + * This overrides the individual HWACG bits in each of the + * individual gate, mux and qch registers. + */ + writel(CMU_OPT_GLOBAL_EN_AUTO_GATING, + reg_base + cmu->option_offset); + } + for (i =3D 0; i < reg_offs_len; ++i) { void __iomem *reg =3D reg_base + reg_offs[i]; u32 val; =20 if (cmu->manual_plls && is_pll_con1_reg(reg_offs[i])) { writel(PLL_CON1_MANUAL, reg); - } else if (is_gate_reg(reg_offs[i])) { + } else if (is_gate_reg(reg_offs[i]) && !init_auto) { + /* + * Setting GATE_MANUAL bit (which is described in TRM as + * reserved!) overrides the global CMU automatic mode + * option. + */ val =3D readl(reg); val |=3D GATE_MANUAL; val &=3D ~GATE_ENABLE_HWACG; @@ -210,8 +244,8 @@ void __init exynos_arm64_register_cmu(struct device *de= v, /** * exynos_arm64_register_cmu_pm - Register Exynos CMU domain with PM suppo= rt * - * @pdev: Platform device object - * @set_manual: If true, set gate clocks to manual mode + * @pdev: Platform device object + * @init_clk_regs: If true, initialize CMU registers * * It's a version of exynos_arm64_register_cmu() with PM support. Should be * called from probe function of platform driver. @@ -219,7 +253,7 @@ void __init exynos_arm64_register_cmu(struct device *de= v, * Return: 0 on success, or negative error code on error. */ int __init exynos_arm64_register_cmu_pm(struct platform_device *pdev, - bool set_manual) + bool init_clk_regs) { const struct samsung_cmu_info *cmu; struct device *dev =3D &pdev->dev; @@ -249,7 +283,7 @@ int __init exynos_arm64_register_cmu_pm(struct platform= _device *pdev, dev_err(dev, "%s: could not enable bus clock %s; err =3D %d\n", __func__, cmu->clk_name, ret); =20 - if (set_manual) + if (init_clk_regs) exynos_arm64_init_clocks(np, cmu); =20 reg_base =3D devm_platform_ioremap_resource(pdev, 0); @@ -268,8 +302,10 @@ int __init exynos_arm64_register_cmu_pm(struct platfor= m_device *pdev, pm_runtime_set_active(dev); pm_runtime_enable(dev); =20 - samsung_cmu_register_clocks(data->ctx, cmu); + samsung_cmu_register_clocks(data->ctx, cmu, np); samsung_clk_of_add_provider(dev->of_node, data->ctx); + /* sysreg DT nodes reference a clock in this CMU */ + samsung_en_dyn_root_clk_gating(np, data->ctx, cmu); pm_runtime_put_sync(dev); =20 return 0; @@ -280,14 +316,17 @@ int exynos_arm64_cmu_suspend(struct device *dev) struct exynos_arm64_cmu_data *data =3D dev_get_drvdata(dev); int i; =20 - samsung_clk_save(data->ctx->reg_base, data->clk_save, + samsung_clk_save(data->ctx->reg_base, NULL, data->clk_save, data->nr_clk_save); =20 + samsung_clk_save(NULL, data->ctx->sysreg, data->clk_sysreg_save, + data->nr_clk_sysreg); + for (i =3D 0; i < data->nr_pclks; i++) clk_prepare_enable(data->pclks[i]); =20 /* For suspend some registers have to be set to certain values */ - samsung_clk_restore(data->ctx->reg_base, data->clk_suspend, + samsung_clk_restore(data->ctx->reg_base, NULL, data->clk_suspend, data->nr_clk_suspend); =20 for (i =3D 0; i < data->nr_pclks; i++) @@ -308,9 +347,14 @@ int exynos_arm64_cmu_resume(struct device *dev) for (i =3D 0; i < data->nr_pclks; i++) clk_prepare_enable(data->pclks[i]); =20 - samsung_clk_restore(data->ctx->reg_base, data->clk_save, + samsung_clk_restore(data->ctx->reg_base, NULL, data->clk_save, data->nr_clk_save); =20 + if (data->ctx->sysreg) + samsung_clk_restore(NULL, data->ctx->sysreg, + data->clk_sysreg_save, + data->nr_clk_sysreg); + for (i =3D 0; i < data->nr_pclks; i++) clk_disable_unprepare(data->pclks[i]); =20 diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-ex= ynos4.c index cc5c1644c41c08b27bc48d809a08cd8a006cbe8f..246bd28bac2d577a58a7b9e0e93= b700548370a36 100644 --- a/drivers/clk/samsung/clk-exynos4.c +++ b/drivers/clk/samsung/clk-exynos4.c @@ -1361,12 +1361,12 @@ static void __init exynos4_clk_init(struct device_n= ode *np, ARRAY_SIZE(exynos4x12_plls)); } =20 - samsung_cmu_register_clocks(ctx, &cmu_info_exynos4); + samsung_cmu_register_clocks(ctx, &cmu_info_exynos4, np); =20 if (exynos4_soc =3D=3D EXYNOS4210) { - samsung_cmu_register_clocks(ctx, &cmu_info_exynos4210); + samsung_cmu_register_clocks(ctx, &cmu_info_exynos4210, np); } else { - samsung_cmu_register_clocks(ctx, &cmu_info_exynos4x12); + samsung_cmu_register_clocks(ctx, &cmu_info_exynos4x12, np); if (soc =3D=3D EXYNOS4412) samsung_clk_register_cpu(ctx, exynos4412_cpu_clks, ARRAY_SIZE(exynos4412_cpu_clks)); @@ -1378,15 +1378,15 @@ static void __init exynos4_clk_init(struct device_n= ode *np, if (soc =3D=3D EXYNOS4212 || soc =3D=3D EXYNOS4412) exynos4x12_core_down_clock(); =20 - samsung_clk_extended_sleep_init(reg_base, + samsung_clk_extended_sleep_init(reg_base, NULL, exynos4_clk_regs, ARRAY_SIZE(exynos4_clk_regs), src_mask_suspend, ARRAY_SIZE(src_mask_suspend)); if (exynos4_soc =3D=3D EXYNOS4210) - samsung_clk_extended_sleep_init(reg_base, + samsung_clk_extended_sleep_init(reg_base, NULL, exynos4210_clk_save, ARRAY_SIZE(exynos4210_clk_save), src_mask_suspend_e4210, ARRAY_SIZE(src_mask_suspend_e4210)); else - samsung_clk_sleep_init(reg_base, exynos4x12_clk_save, + samsung_clk_sleep_init(reg_base, NULL, exynos4x12_clk_save, ARRAY_SIZE(exynos4x12_clk_save)); =20 samsung_clk_of_add_provider(np, ctx); diff --git a/drivers/clk/samsung/clk-exynos4412-isp.c b/drivers/clk/samsung= /clk-exynos4412-isp.c index fa915057e109e0008ebe0b1b5d1652fd5804e82b..772bc18a1e686f23b11bf160b80= 3becff6279637 100644 --- a/drivers/clk/samsung/clk-exynos4412-isp.c +++ b/drivers/clk/samsung/clk-exynos4412-isp.c @@ -94,7 +94,7 @@ static int __maybe_unused exynos4x12_isp_clk_suspend(stru= ct device *dev) { struct samsung_clk_provider *ctx =3D dev_get_drvdata(dev); =20 - samsung_clk_save(ctx->reg_base, exynos4x12_save_isp, + samsung_clk_save(ctx->reg_base, NULL, exynos4x12_save_isp, ARRAY_SIZE(exynos4x12_clk_isp_save)); return 0; } @@ -103,7 +103,7 @@ static int __maybe_unused exynos4x12_isp_clk_resume(str= uct device *dev) { struct samsung_clk_provider *ctx =3D dev_get_drvdata(dev); =20 - samsung_clk_restore(ctx->reg_base, exynos4x12_save_isp, + samsung_clk_restore(ctx->reg_base, NULL, exynos4x12_save_isp, ARRAY_SIZE(exynos4x12_clk_isp_save)); return 0; } diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk= -exynos5250.c index e90d3a0848cbc24b2709c10795f6affcda404567..f97f30b29be7317db8186bac39c= f52e1893eb106 100644 --- a/drivers/clk/samsung/clk-exynos5250.c +++ b/drivers/clk/samsung/clk-exynos5250.c @@ -854,7 +854,7 @@ static void __init exynos5250_clk_init(struct device_no= de *np) PWR_CTRL2_CORE2_UP_RATIO | PWR_CTRL2_CORE1_UP_RATIO); __raw_writel(tmp, reg_base + PWR_CTRL2); =20 - samsung_clk_sleep_init(reg_base, exynos5250_clk_regs, + samsung_clk_sleep_init(reg_base, NULL, exynos5250_clk_regs, ARRAY_SIZE(exynos5250_clk_regs)); exynos5_subcmus_init(ctx, ARRAY_SIZE(exynos5250_subcmus), exynos5250_subcmus); diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk= -exynos5420.c index a9df4e6db82fa7831d4e5c7210b0163d7d301ec1..1982e0751ceec7e57f9e82d96dc= badce1f691092 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -1649,12 +1649,12 @@ static void __init exynos5x_clk_init(struct device_= node *np, ARRAY_SIZE(exynos5800_cpu_clks)); } =20 - samsung_clk_extended_sleep_init(reg_base, + samsung_clk_extended_sleep_init(reg_base, NULL, exynos5x_clk_regs, ARRAY_SIZE(exynos5x_clk_regs), exynos5420_set_clksrc, ARRAY_SIZE(exynos5420_set_clksrc)); =20 if (soc =3D=3D EXYNOS5800) { - samsung_clk_sleep_init(reg_base, exynos5800_clk_regs, + samsung_clk_sleep_init(reg_base, NULL, exynos5800_clk_regs, ARRAY_SIZE(exynos5800_clk_regs)); =20 exynos5_subcmus_init(ctx, ARRAY_SIZE(exynos5800_subcmus), diff --git a/drivers/clk/samsung/clk-s3c64xx.c b/drivers/clk/samsung/clk-s3= c64xx.c index 397a057af5d1e704e7ead7ba04b477fdc28c45bf..5a2d5a5703ffc5ed48b9a18a20c= 39be2de827920 100644 --- a/drivers/clk/samsung/clk-s3c64xx.c +++ b/drivers/clk/samsung/clk-s3c64xx.c @@ -449,10 +449,10 @@ void __init s3c64xx_clk_init(struct device_node *np, = unsigned long xtal_f, samsung_clk_register_alias(ctx, s3c64xx_clock_aliases, ARRAY_SIZE(s3c64xx_clock_aliases)); =20 - samsung_clk_sleep_init(reg_base, s3c64xx_clk_regs, + samsung_clk_sleep_init(reg_base, NULL, s3c64xx_clk_regs, ARRAY_SIZE(s3c64xx_clk_regs)); if (!is_s3c6400) - samsung_clk_sleep_init(reg_base, s3c6410_clk_regs, + samsung_clk_sleep_init(reg_base, NULL, s3c6410_clk_regs, ARRAY_SIZE(s3c6410_clk_regs)); =20 samsung_clk_of_add_provider(np, ctx); diff --git a/drivers/clk/samsung/clk-s5pv210.c b/drivers/clk/samsung/clk-s5= pv210.c index 9a4217cc1908aa60ebbe51b2b5c841138cc46ef3..4ee4f2b5efbc1d4770fefff22de= 21f7d4e5e9506 100644 --- a/drivers/clk/samsung/clk-s5pv210.c +++ b/drivers/clk/samsung/clk-s5pv210.c @@ -782,7 +782,7 @@ static void __init __s5pv210_clk_init(struct device_nod= e *np, samsung_clk_register_alias(ctx, s5pv210_aliases, ARRAY_SIZE(s5pv210_aliases)); =20 - samsung_clk_sleep_init(reg_base, s5pv210_clk_regs, + samsung_clk_sleep_init(reg_base, NULL, s5pv210_clk_regs, ARRAY_SIZE(s5pv210_clk_regs)); =20 samsung_clk_of_add_provider(np, ctx); diff --git a/drivers/clk/samsung/clk.c b/drivers/clk/samsung/clk.c index dbc9925ca8f46e951dfb5d391c0e744ca370abcc..6554ea02e29c495da83bfffe1a9= d3f523fe8c73e 100644 --- a/drivers/clk/samsung/clk.c +++ b/drivers/clk/samsung/clk.c @@ -12,8 +12,10 @@ #include #include #include +#include #include #include +#include #include =20 #include "clk.h" @@ -21,19 +23,29 @@ static LIST_HEAD(clock_reg_cache_list); =20 void samsung_clk_save(void __iomem *base, + struct regmap *regmap, struct samsung_clk_reg_dump *rd, unsigned int num_regs) { - for (; num_regs > 0; --num_regs, ++rd) - rd->value =3D readl(base + rd->offset); + for (; num_regs > 0; --num_regs, ++rd) { + if (base) + rd->value =3D readl(base + rd->offset); + else if (regmap) + regmap_read(regmap, rd->offset, &rd->value); + } } =20 void samsung_clk_restore(void __iomem *base, + struct regmap *regmap, const struct samsung_clk_reg_dump *rd, unsigned int num_regs) { - for (; num_regs > 0; --num_regs, ++rd) - writel(rd->value, base + rd->offset); + for (; num_regs > 0; --num_regs, ++rd) { + if (base) + writel(rd->value, base + rd->offset); + else if (regmap) + regmap_write(regmap, rd->offset, rd->value); + } } =20 struct samsung_clk_reg_dump *samsung_clk_alloc_reg_dump( @@ -227,6 +239,103 @@ void __init samsung_clk_register_div(struct samsung_c= lk_provider *ctx, } } =20 +/* + * Some older DT's have an incorrect CMU resource size which is incompatib= le + * with the auto clock mode feature. In such cases we switch back to manual + * clock gating mode. + */ +bool samsung_is_auto_capable(struct device_node *np) +{ + struct resource res; + resource_size_t size; + + if (of_address_to_resource(np, 0, &res)) + return false; + + size =3D resource_size(&res); + if (size !=3D 0x10000) { + pr_warn("%pOF: incorrect res size for automatic clocks\n", np); + return false; + } + return true; +} + +#define ACG_MSK GENMASK(6, 4) +#define CLK_IDLE GENMASK(5, 4) +static int samsung_auto_clk_gate_is_en(struct clk_hw *hw) +{ + u32 reg; + struct clk_gate *gate =3D to_clk_gate(hw); + + reg =3D readl(gate->reg); + return ((reg & ACG_MSK) =3D=3D CLK_IDLE) ? 0 : 1; +} + +/* enable and disable are nops in automatic clock mode */ +static int samsung_auto_clk_gate_en(struct clk_hw *hw) +{ + return 0; +} + +static void samsung_auto_clk_gate_dis(struct clk_hw *hw) +{ +} + +static const struct clk_ops samsung_auto_clk_gate_ops =3D { + .enable =3D samsung_auto_clk_gate_en, + .disable =3D samsung_auto_clk_gate_dis, + .is_enabled =3D samsung_auto_clk_gate_is_en, +}; + +struct clk_hw *samsung_register_auto_gate(struct device *dev, + struct device_node *np, const char *name, + const char *parent_name, const struct clk_hw *parent_hw, + const struct clk_parent_data *parent_data, + unsigned long flags, + void __iomem *reg, u8 bit_idx, + u8 clk_gate_flags, spinlock_t *lock) +{ + struct clk_gate *gate; + struct clk_hw *hw; + struct clk_init_data init =3D {}; + int ret =3D -EINVAL; + + /* allocate the gate */ + gate =3D kzalloc(sizeof(*gate), GFP_KERNEL); + if (!gate) + return ERR_PTR(-ENOMEM); + + init.name =3D name; + init.ops =3D &samsung_auto_clk_gate_ops; + init.flags =3D flags; + init.parent_names =3D parent_name ? &parent_name : NULL; + init.parent_hws =3D parent_hw ? &parent_hw : NULL; + init.parent_data =3D parent_data; + if (parent_name || parent_hw || parent_data) + init.num_parents =3D 1; + else + init.num_parents =3D 0; + + /* struct clk_gate assignments */ + gate->reg =3D reg; + gate->bit_idx =3D bit_idx; + gate->flags =3D clk_gate_flags; + gate->lock =3D lock; + gate->hw.init =3D &init; + + hw =3D &gate->hw; + if (dev || !np) + ret =3D clk_hw_register(dev, hw); + else if (np) + ret =3D of_clk_hw_register(np, hw); + if (ret) { + kfree(gate); + hw =3D ERR_PTR(ret); + } + + return hw; +} + /* register a list of gate clocks */ void __init samsung_clk_register_gate(struct samsung_clk_provider *ctx, const struct samsung_gate_clock *list, @@ -234,14 +343,24 @@ void __init samsung_clk_register_gate(struct samsung_= clk_provider *ctx, { struct clk_hw *clk_hw; unsigned int idx; + void __iomem *reg_offs; =20 for (idx =3D 0; idx < nr_clk; idx++, list++) { - clk_hw =3D clk_hw_register_gate(ctx->dev, list->name, list->parent_name, - list->flags, ctx->reg_base + list->offset, + reg_offs =3D ctx->reg_base + list->offset; + + if (ctx->auto_clock_gate && ctx->gate_dbg_offset) + clk_hw =3D samsung_register_auto_gate(ctx->dev, NULL, + list->name, list->parent_name, NULL, NULL, + list->flags, reg_offs + ctx->gate_dbg_offset, list->bit_idx, list->gate_flags, &ctx->lock); + else + clk_hw =3D clk_hw_register_gate(ctx->dev, list->name, + list->parent_name, list->flags, + ctx->reg_base + list->offset, list->bit_idx, + list->gate_flags, &ctx->lock); if (IS_ERR(clk_hw)) { - pr_err("%s: failed to register clock %s\n", __func__, - list->name); + pr_err("%s: failed to register clock %s: %ld\n", __func__, + list->name, PTR_ERR(clk_hw)); continue; } =20 @@ -276,10 +395,11 @@ static int samsung_clk_suspend(void) struct samsung_clock_reg_cache *reg_cache; =20 list_for_each_entry(reg_cache, &clock_reg_cache_list, node) { - samsung_clk_save(reg_cache->reg_base, reg_cache->rdump, - reg_cache->rd_num); - samsung_clk_restore(reg_cache->reg_base, reg_cache->rsuspend, - reg_cache->rsuspend_num); + samsung_clk_save(reg_cache->reg_base, reg_cache->sysreg, + reg_cache->rdump, reg_cache->rd_num); + samsung_clk_restore(reg_cache->reg_base, reg_cache->sysreg, + reg_cache->rsuspend, + reg_cache->rsuspend_num); } return 0; } @@ -289,8 +409,8 @@ static void samsung_clk_resume(void) struct samsung_clock_reg_cache *reg_cache; =20 list_for_each_entry(reg_cache, &clock_reg_cache_list, node) - samsung_clk_restore(reg_cache->reg_base, reg_cache->rdump, - reg_cache->rd_num); + samsung_clk_restore(reg_cache->reg_base, reg_cache->sysreg, + reg_cache->rdump, reg_cache->rd_num); } =20 static struct syscore_ops samsung_clk_syscore_ops =3D { @@ -299,6 +419,7 @@ static struct syscore_ops samsung_clk_syscore_ops =3D { }; =20 void samsung_clk_extended_sleep_init(void __iomem *reg_base, + struct regmap *sysreg, const unsigned long *rdump, unsigned long nr_rdump, const struct samsung_clk_reg_dump *rsuspend, @@ -319,6 +440,7 @@ void samsung_clk_extended_sleep_init(void __iomem *reg_= base, register_syscore_ops(&samsung_clk_syscore_ops); =20 reg_cache->reg_base =3D reg_base; + reg_cache->sysreg =3D sysreg; reg_cache->rd_num =3D nr_rdump; reg_cache->rsuspend =3D rsuspend; reg_cache->rsuspend_num =3D nr_rsuspend; @@ -332,8 +454,17 @@ void samsung_clk_extended_sleep_init(void __iomem *reg= _base, * @cmu: CMU object with clocks to register */ void __init samsung_cmu_register_clocks(struct samsung_clk_provider *ctx, - const struct samsung_cmu_info *cmu) + const struct samsung_cmu_info *cmu, + struct device_node *np) { + if (samsung_is_auto_capable(np) && cmu->auto_clock_gate) + ctx->auto_clock_gate =3D cmu->auto_clock_gate; + + ctx->gate_dbg_offset =3D cmu->gate_dbg_offset; + ctx->option_offset =3D cmu->option_offset; + ctx->drcg_offset =3D cmu->drcg_offset; + ctx->memclk_offset =3D cmu->memclk_offset; + if (cmu->pll_clks) samsung_clk_register_pll(ctx, cmu->pll_clks, cmu->nr_pll_clks); if (cmu->mux_clks) @@ -353,6 +484,37 @@ void __init samsung_cmu_register_clocks(struct samsung= _clk_provider *ctx, samsung_clk_register_cpu(ctx, cmu->cpu_clks, cmu->nr_cpu_clks); } =20 +/* Each bit enable/disables DRCG of a bus component */ +#define DRCG_EN_MSK GENMASK(31, 0) +#define MEMCLK_EN BIT(0) + +/* Enable Dynamic Root Clock Gating (DRCG) of bus components */ +void samsung_en_dyn_root_clk_gating(struct device_node *np, + struct samsung_clk_provider *ctx, + const struct samsung_cmu_info *cmu) +{ + if (!ctx->auto_clock_gate) + return; + + ctx->sysreg =3D syscon_regmap_lookup_by_phandle(np, "samsung,sysreg"); + if (IS_ERR(ctx->sysreg)) { + pr_warn("%pOF: Unable to get CMU sysreg\n", np); + ctx->sysreg =3D NULL; + } else { + /* Enable DRCG for all bus components */ + regmap_write(ctx->sysreg, ctx->drcg_offset, DRCG_EN_MSK); + /* Enable memclk gate (not present on all sysreg) */ + if (ctx->memclk_offset) + regmap_write_bits(ctx->sysreg, ctx->memclk_offset, + MEMCLK_EN, 0x0); + + samsung_clk_extended_sleep_init(NULL, ctx->sysreg, + cmu->sysreg_clk_regs, + cmu->nr_sysreg_clk_regs, + NULL, 0); + } +} + /* * Common function which registers plls, muxes, dividers and gates * for each CMU. It also add CMU register list to register cache. @@ -371,14 +533,17 @@ struct samsung_clk_provider * __init samsung_cmu_regi= ster_one( } =20 ctx =3D samsung_clk_init(NULL, reg_base, cmu->nr_clk_ids); - samsung_cmu_register_clocks(ctx, cmu); + samsung_cmu_register_clocks(ctx, cmu, np); =20 if (cmu->clk_regs) - samsung_clk_extended_sleep_init(reg_base, + samsung_clk_extended_sleep_init(reg_base, NULL, cmu->clk_regs, cmu->nr_clk_regs, cmu->suspend_regs, cmu->nr_suspend_regs); =20 samsung_clk_of_add_provider(np, ctx); =20 + /* sysreg DT nodes reference a clock in this CMU */ + samsung_en_dyn_root_clk_gating(np, ctx, cmu); + return ctx; } diff --git a/drivers/clk/samsung/clk.h b/drivers/clk/samsung/clk.h index 18660c1ac6f0106b17b9efc9c6b3cd62d46f7b82..a56aa3be54d817cd24bf2bc2942= 7e783a1a9a859 100644 --- a/drivers/clk/samsung/clk.h +++ b/drivers/clk/samsung/clk.h @@ -12,6 +12,7 @@ =20 #include #include +#include #include "clk-pll.h" #include "clk-cpu.h" =20 @@ -19,13 +20,25 @@ * struct samsung_clk_provider - information about clock provider * @reg_base: virtual address for the register base * @dev: clock provider device needed for runtime PM + * @sysreg: syscon regmap for clock-provider sysreg controller * @lock: maintains exclusion between callbacks for a given clock-provider + * @auto_clock_gate: enable auto clk mode for all clocks in clock-provider + * @gate_dbg_offset: gate debug reg offset. Used for all gates in auto clk= mode + * @option_offset: option reg offset. Enables auto mode for clock-provider + * @drcg_offset: dynamic root clk gate enable register offset in sysreg + * @memclk_offset: memclk enable register offset in sysreg * @clk_data: holds clock related data like clk_hw* and number of clocks */ struct samsung_clk_provider { void __iomem *reg_base; struct device *dev; + struct regmap *sysreg; spinlock_t lock; + bool auto_clock_gate; + u32 gate_dbg_offset; + u32 option_offset; + u32 drcg_offset; + u32 memclk_offset; /* clk_data must be the last entry due to variable length 'hws' array */ struct clk_hw_onecell_data clk_data; }; @@ -310,6 +323,7 @@ struct samsung_cpu_clock { struct samsung_clock_reg_cache { struct list_head node; void __iomem *reg_base; + struct regmap *sysreg; struct samsung_clk_reg_dump *rdump; unsigned int rd_num; const struct samsung_clk_reg_dump *rsuspend; @@ -338,7 +352,14 @@ struct samsung_clock_reg_cache { * @suspend_regs: list of clock registers to set before suspend * @nr_suspend_regs: count of clock registers in @suspend_regs * @clk_name: name of the parent clock needed for CMU register access + * @sysreg_clk_regs: list of sysreg clock registers + * @nr_sysreg_clk_regs: count of clock registers in @sysreg_clk_regs * @manual_plls: Enable manual control for PLL clocks + * @auto_clock_gate: enable auto clock mode for all components in CMU + * @gate_dbg_offset: gate debug reg offset. Used by all gates in auto clk = mode + * @option_offset: option reg offset. Enables auto clk mode for entire CMU + * @drcg_offset: dynamic root clk gate enable register offset in sysreg + * @memclk_offset: memclk enable register offset in sysreg */ struct samsung_cmu_info { const struct samsung_pll_clock *pll_clks; @@ -364,8 +385,16 @@ struct samsung_cmu_info { unsigned int nr_suspend_regs; const char *clk_name; =20 + const unsigned long *sysreg_clk_regs; + unsigned int nr_sysreg_clk_regs; + /* ARM64 Exynos CMUs */ bool manual_plls; + bool auto_clock_gate; + u32 gate_dbg_offset; + u32 option_offset; + u32 drcg_offset; + u32 memclk_offset; }; =20 struct samsung_clk_provider *samsung_clk_init(struct device *dev, @@ -408,35 +437,55 @@ void samsung_clk_register_cpu(struct samsung_clk_prov= ider *ctx, const struct samsung_cpu_clock *list, unsigned int nr_clk); =20 void samsung_cmu_register_clocks(struct samsung_clk_provider *ctx, - const struct samsung_cmu_info *cmu); + const struct samsung_cmu_info *cmu, + struct device_node *np); struct samsung_clk_provider *samsung_cmu_register_one( struct device_node *, const struct samsung_cmu_info *); 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a=openpgp; fpr=0EFC8E6F5578750D56B549FCCEE8B8D6023472BA Enable auto clock mode, and define the additional fields which are used when this mode is enabled. /sys/kernel/debug/clk/clk_summary now reports approximately 308 running clocks and 298 disabled clocks. Prior to this commit 586 clocks were running and 17 disabled. Signed-off-by: Peter Griffin --- drivers/clk/samsung/clk-gs101.c | 56 +++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 56 insertions(+) diff --git a/drivers/clk/samsung/clk-gs101.c b/drivers/clk/samsung/clk-gs10= 1.c index 70b26db9b95ad0b376d23f637c7683fbc8c8c600..68c5ed8f0fe1cac5169313b6ec7= 05f9eec44ff53 100644 --- a/drivers/clk/samsung/clk-gs101.c +++ b/drivers/clk/samsung/clk-gs101.c @@ -9,6 +9,7 @@ #include #include #include +#include #include =20 #include @@ -26,6 +27,10 @@ #define CLKS_NR_PERIC0 (CLK_GOUT_PERIC0_SYSREG_PERIC0_PCLK + 1) #define CLKS_NR_PERIC1 (CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK + 1) =20 +#define GS101_GATE_DBG_OFFSET 0x4000 +#define GS101_DRCG_EN_OFFSET 0x104 +#define GS101_MEMCLK_OFFSET 0x108 + /* ---- CMU_TOP ----------------------------------------------------------= --- */ =20 /* Register Offset definitions for CMU_TOP (0x1e080000) */ @@ -1433,6 +1438,9 @@ static const struct samsung_cmu_info top_cmu_info __i= nitconst =3D { .nr_clk_ids =3D CLKS_NR_TOP, .clk_regs =3D cmu_top_clk_regs, .nr_clk_regs =3D ARRAY_SIZE(cmu_top_clk_regs), + .auto_clock_gate =3D true, + .gate_dbg_offset =3D GS101_GATE_DBG_OFFSET, + .option_offset =3D CMU_CMU_TOP_CONTROLLER_OPTION, }; =20 static void __init gs101_cmu_top_init(struct device_node *np) @@ -1900,6 +1908,11 @@ static const struct samsung_gate_clock apm_gate_clks= [] __initconst =3D { CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK, 21, CLK_IS_C= RITICAL, 0), }; =20 +static const unsigned long dcrg_memclk_sysreg[] __initconst =3D { + GS101_DRCG_EN_OFFSET, + GS101_MEMCLK_OFFSET, +}; + static const struct samsung_cmu_info apm_cmu_info __initconst =3D { .mux_clks =3D apm_mux_clks, .nr_mux_clks =3D ARRAY_SIZE(apm_mux_clks), @@ -1912,6 +1925,12 @@ static const struct samsung_cmu_info apm_cmu_info __= initconst =3D { .nr_clk_ids =3D CLKS_NR_APM, .clk_regs =3D apm_clk_regs, .nr_clk_regs =3D ARRAY_SIZE(apm_clk_regs), + .sysreg_clk_regs =3D dcrg_memclk_sysreg, + .nr_sysreg_clk_regs =3D ARRAY_SIZE(dcrg_memclk_sysreg), + .auto_clock_gate =3D true, + .gate_dbg_offset =3D GS101_GATE_DBG_OFFSET, + .drcg_offset =3D GS101_DRCG_EN_OFFSET, + .memclk_offset =3D GS101_MEMCLK_OFFSET, }; =20 /* ---- CMU_HSI0 ---------------------------------------------------------= --- */ @@ -2375,7 +2394,14 @@ static const struct samsung_cmu_info hsi0_cmu_info _= _initconst =3D { .nr_clk_ids =3D CLKS_NR_HSI0, .clk_regs =3D hsi0_clk_regs, .nr_clk_regs =3D ARRAY_SIZE(hsi0_clk_regs), + .sysreg_clk_regs =3D dcrg_memclk_sysreg, + .nr_sysreg_clk_regs =3D ARRAY_SIZE(dcrg_memclk_sysreg), .clk_name =3D "bus", + .auto_clock_gate =3D true, + .gate_dbg_offset =3D GS101_GATE_DBG_OFFSET, + .option_offset =3D HSI0_CMU_HSI0_CONTROLLER_OPTION, + .drcg_offset =3D GS101_DRCG_EN_OFFSET, + .memclk_offset =3D GS101_MEMCLK_OFFSET, }; =20 /* ---- CMU_HSI2 ---------------------------------------------------------= --- */ @@ -2863,7 +2889,14 @@ static const struct samsung_cmu_info hsi2_cmu_info _= _initconst =3D { .nr_clk_ids =3D CLKS_NR_HSI2, .clk_regs =3D cmu_hsi2_clk_regs, .nr_clk_regs =3D ARRAY_SIZE(cmu_hsi2_clk_regs), + .sysreg_clk_regs =3D dcrg_memclk_sysreg, + .nr_sysreg_clk_regs =3D ARRAY_SIZE(dcrg_memclk_sysreg), .clk_name =3D "bus", + .auto_clock_gate =3D true, + .gate_dbg_offset =3D GS101_GATE_DBG_OFFSET, + .option_offset =3D HSI2_CMU_HSI2_CONTROLLER_OPTION, + .drcg_offset =3D GS101_DRCG_EN_OFFSET, + .memclk_offset =3D GS101_MEMCLK_OFFSET, }; =20 /* ---- CMU_MISC ---------------------------------------------------------= --- */ @@ -3423,7 +3456,14 @@ static const struct samsung_cmu_info misc_cmu_info _= _initconst =3D { .nr_clk_ids =3D CLKS_NR_MISC, .clk_regs =3D misc_clk_regs, .nr_clk_regs =3D ARRAY_SIZE(misc_clk_regs), + .sysreg_clk_regs =3D dcrg_memclk_sysreg, + .nr_sysreg_clk_regs =3D ARRAY_SIZE(dcrg_memclk_sysreg), .clk_name =3D "bus", + .auto_clock_gate =3D true, + .gate_dbg_offset =3D GS101_GATE_DBG_OFFSET, + .option_offset =3D MISC_CMU_MISC_CONTROLLER_OPTION, + .drcg_offset =3D GS101_DRCG_EN_OFFSET, + .memclk_offset =3D GS101_MEMCLK_OFFSET, }; =20 static void __init gs101_cmu_misc_init(struct device_node *np) @@ -4010,6 +4050,10 @@ static const struct samsung_gate_clock peric0_gate_c= lks[] __initconst =3D { 21, 0, 0), }; =20 +static const unsigned long dcrg_sysreg[] __initconst =3D { + GS101_DRCG_EN_OFFSET, +}; + static const struct samsung_cmu_info peric0_cmu_info __initconst =3D { .mux_clks =3D peric0_mux_clks, .nr_mux_clks =3D ARRAY_SIZE(peric0_mux_clks), @@ -4020,7 +4064,13 @@ static const struct samsung_cmu_info peric0_cmu_info= __initconst =3D { .nr_clk_ids =3D CLKS_NR_PERIC0, .clk_regs =3D peric0_clk_regs, .nr_clk_regs =3D ARRAY_SIZE(peric0_clk_regs), + .sysreg_clk_regs =3D dcrg_sysreg, + .nr_sysreg_clk_regs =3D ARRAY_SIZE(dcrg_sysreg), .clk_name =3D "bus", + .auto_clock_gate =3D true, + .gate_dbg_offset =3D GS101_GATE_DBG_OFFSET, + .option_offset =3D PERIC0_CMU_PERIC0_CONTROLLER_OPTION, + .drcg_offset =3D GS101_DRCG_EN_OFFSET, }; =20 /* ---- CMU_PERIC1 -------------------------------------------------------= --- */ @@ -4368,7 +4418,13 @@ static const struct samsung_cmu_info peric1_cmu_info= __initconst =3D { .nr_clk_ids =3D CLKS_NR_PERIC1, .clk_regs =3D peric1_clk_regs, .nr_clk_regs =3D ARRAY_SIZE(peric1_clk_regs), + .sysreg_clk_regs =3D dcrg_sysreg, + .nr_sysreg_clk_regs =3D ARRAY_SIZE(dcrg_sysreg), .clk_name =3D "bus", + .auto_clock_gate =3D true, + .gate_dbg_offset =3D GS101_GATE_DBG_OFFSET, + .option_offset =3D PERIC1_CMU_PERIC1_CONTROLLER_OPTION, + .drcg_offset =3D GS101_DRCG_EN_OFFSET, }; =20 /* ---- platform_driver --------------------------------------------------= --- */ --=20 2.51.1.851.g4ebd6896fd-goog