From nobody Mon Dec 15 18:54:00 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 24AEA31E0EA; Wed, 29 Oct 2025 08:06:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761725185; cv=none; b=YF9KDDDO7c0S7Wcz4qw/IBFZJ3f9ejMlanmDlvJogN2y+sxpeDg/BSts4fgXDwI16599nxWCTVJYJ4+n77QIbSTsJarRz0R4225S3URzhdJQP/kYs/qZ653yREaXFadSeVefpLLyAX+1pSnYR4kJgdlmKTC9Iu/vrXUSAJHuILU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761725185; c=relaxed/simple; bh=/oVMgoN0d3ixwVotycgrVVjswd5DG6nEvx4SH9if1No=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=sCfYTtMQ5fj2mj3qd8prBZyKLBMtswPLH/FpLRg/5y2QpbhzvQ7cZ/XDiPWWHjF+YT3ZSKqUsgfPXD/5BYSgC14Nng4qDtPna9MSCKbuOPWgcH6PO8oJhH0Jxcw+mgV5qoirBY+4TBC4EyOUQ6hYpr2assCzHWizJUv1ZemXmQY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ZsaO2cFj; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ZsaO2cFj" Received: by smtp.kernel.org (Postfix) with ESMTPS id CB132C116B1; Wed, 29 Oct 2025 08:06:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1761725184; bh=/oVMgoN0d3ixwVotycgrVVjswd5DG6nEvx4SH9if1No=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=ZsaO2cFji1crgWSeRKwYEYPtaAyrNGg2KkSsQbSog66qVsns1ISiARgeHk9cMNtbM /uFFf5LBnetXjXQDgJJRLZDjptJqNVnjU9vxXMq8b1hlA1qzHO2iEuyuaTIiQr9qwD 6HnTUdCc090XoWit4TBk5nf5sP8TLMolwO99C8Yd+ek4evLsiEaJQcasWB+sgsPRPb IUsLp7aC7f8N/XVsTtJoMCZd+DV+6zMI/ghfnQbP2vjPsn3HyVjMlJ87w7p3psbi7O UJOOmJeQUD7Nn/XKIEEjUSbs/x4dEWvm3CLWb9tXXVUoG201S7vtgsNJWVgGvu9dfk Ho6jPrCK4IvOg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id B929DCCF9E9; Wed, 29 Oct 2025 08:06:24 +0000 (UTC) From: Rohan G Thomas via B4 Relay Date: Wed, 29 Oct 2025 16:06:13 +0800 Subject: [PATCH net-next 1/4] net: stmmac: socfpga: Agilex5 EMAC platform configuration Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251029-agilex5_ext-v1-1-1931132d77d6@altera.com> References: <20251029-agilex5_ext-v1-0-1931132d77d6@altera.com> In-Reply-To: <20251029-agilex5_ext-v1-0-1931132d77d6@altera.com> To: Maxime Chevallier , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Alexandre Torgue , Richard Cochran , Steffen Trumtrar Cc: netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rohan G Thomas X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1761725182; l=4008; i=rohan.g.thomas@altera.com; s=20250815; h=from:subject:message-id; bh=fqpheFKts6+7OsBqsj9xRO/POu9s39bQIp1U3z6E4Sk=; b=YohBBb/PJcQ7AlroGARqRd4AYmGE4QmSVQzy2BMDhtBTSq+CR5nGjCP4j5YphFG2mIhAp7T9/ qCSWpLuHYEDAORQd7rU9kKLKkHWQhfhPffjsdxoTfsCfP7J9wp1rmSS X-Developer-Key: i=rohan.g.thomas@altera.com; a=ed25519; pk=5yZXkXswhfUILKAQwoIn7m6uSblwgV5oppxqde4g4TY= X-Endpoint-Received: by B4 Relay for rohan.g.thomas@altera.com/20250815 with auth_id=494 X-Original-From: Rohan G Thomas Reply-To: rohan.g.thomas@altera.com From: Rohan G Thomas Agilex5 HPS EMAC uses the dwxgmac-3.10a IP, unlike previous socfpga platforms which use dwmac1000 IP. Due to differences in platform configuration, Agilex5 requires a distinct setup. Introduce a setup_plat_dat() callback in socfpga_dwmac_ops to handle platform-specific setup. This callback is invoked before stmmac_dvr_probe() to ensure the platform data is correctly configured. Also, implemented separate setup_plat_dat() callback for current socfpga platforms and Agilex5. Signed-off-by: Rohan G Thomas Reviewed-by: Maxime Chevallier Tested-by: Maxime Chevallier --- .../net/ethernet/stmicro/stmmac/dwmac-socfpga.c | 53 ++++++++++++++++++= ---- 1 file changed, 43 insertions(+), 10 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c b/drivers/= net/ethernet/stmicro/stmmac/dwmac-socfpga.c index 2ff5db6d41ca08a1652d57f3eb73923b9a9558bf..3dae4f3c103802ed1c2cd390634= bd5473192d4ee 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c @@ -44,6 +44,7 @@ struct socfpga_dwmac; struct socfpga_dwmac_ops { int (*set_phy_mode)(struct socfpga_dwmac *dwmac_priv); + void (*setup_plat_dat)(struct socfpga_dwmac *dwmac_priv); }; =20 struct socfpga_dwmac { @@ -441,6 +442,39 @@ static int socfpga_dwmac_init(struct platform_device *= pdev, void *bsp_priv) return dwmac->ops->set_phy_mode(dwmac); } =20 +static void socfpga_common_plat_dat(struct socfpga_dwmac *dwmac) +{ + struct plat_stmmacenet_data *plat_dat =3D dwmac->plat_dat; + + plat_dat->bsp_priv =3D dwmac; + plat_dat->fix_mac_speed =3D socfpga_dwmac_fix_mac_speed; + plat_dat->init =3D socfpga_dwmac_init; + plat_dat->pcs_init =3D socfpga_dwmac_pcs_init; + plat_dat->pcs_exit =3D socfpga_dwmac_pcs_exit; + plat_dat->select_pcs =3D socfpga_dwmac_select_pcs; +} + +static void socfpga_gen5_setup_plat_dat(struct socfpga_dwmac *dwmac) +{ + struct plat_stmmacenet_data *plat_dat =3D dwmac->plat_dat; + + socfpga_common_plat_dat(dwmac); + + plat_dat->core_type =3D DWMAC_CORE_GMAC; + + /* Rx watchdog timer in dwmac is buggy in this hw */ + plat_dat->riwt_off =3D 1; +} + +static void socfpga_agilex5_setup_plat_dat(struct socfpga_dwmac *dwmac) +{ + struct plat_stmmacenet_data *plat_dat =3D dwmac->plat_dat; + + socfpga_common_plat_dat(dwmac); + + plat_dat->core_type =3D DWMAC_CORE_XGMAC; +} + static int socfpga_dwmac_probe(struct platform_device *pdev) { struct plat_stmmacenet_data *plat_dat; @@ -491,31 +525,30 @@ static int socfpga_dwmac_probe(struct platform_device= *pdev) dwmac->ops =3D ops; dwmac->plat_dat =3D plat_dat; =20 - plat_dat->bsp_priv =3D dwmac; - plat_dat->fix_mac_speed =3D socfpga_dwmac_fix_mac_speed; - plat_dat->init =3D socfpga_dwmac_init; - plat_dat->pcs_init =3D socfpga_dwmac_pcs_init; - plat_dat->pcs_exit =3D socfpga_dwmac_pcs_exit; - plat_dat->select_pcs =3D socfpga_dwmac_select_pcs; - plat_dat->core_type =3D DWMAC_CORE_GMAC; - - plat_dat->riwt_off =3D 1; + ops->setup_plat_dat(dwmac); =20 return devm_stmmac_pltfr_probe(pdev, plat_dat, &stmmac_res); } =20 static const struct socfpga_dwmac_ops socfpga_gen5_ops =3D { .set_phy_mode =3D socfpga_gen5_set_phy_mode, + .setup_plat_dat =3D socfpga_gen5_setup_plat_dat, }; =20 static const struct socfpga_dwmac_ops socfpga_gen10_ops =3D { .set_phy_mode =3D socfpga_gen10_set_phy_mode, + .setup_plat_dat =3D socfpga_gen5_setup_plat_dat, +}; + +static const struct socfpga_dwmac_ops socfpga_agilex5_ops =3D { + .set_phy_mode =3D socfpga_gen10_set_phy_mode, + .setup_plat_dat =3D socfpga_agilex5_setup_plat_dat, }; =20 static const struct of_device_id socfpga_dwmac_match[] =3D { { .compatible =3D "altr,socfpga-stmmac", .data =3D &socfpga_gen5_ops }, { .compatible =3D "altr,socfpga-stmmac-a10-s10", .data =3D &socfpga_gen10= _ops }, - { .compatible =3D "altr,socfpga-stmmac-agilex5", .data =3D &socfpga_gen10= _ops }, + { .compatible =3D "altr,socfpga-stmmac-agilex5", .data =3D &socfpga_agile= x5_ops }, { } }; MODULE_DEVICE_TABLE(of, socfpga_dwmac_match); --=20 2.43.7 From nobody Mon Dec 15 18:54:00 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 24B68320380; Wed, 29 Oct 2025 08:06:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761725185; cv=none; b=PexS3Cl1hH4ToSo3wvt2sxYOMpzoY9pLAUDe/twUKI72cqflgDYOwbHhxHKPjjdN4cI8N5ab6FXiMjPSp8QQh7Dsdlt4Z/ptyMPBaBzoDB9X5rMqQ5whbZ7UiZh8EbtsMfAjfmsSF/+DtYnanZEFZ5hpK3tBwLx6/DPUxeuXkUY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761725185; c=relaxed/simple; bh=nWVHnfvQBRA6ZVCql74XqpzDCs6ZKXaKNS1r6cUtQN8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; 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Wed, 29 Oct 2025 08:06:24 +0000 (UTC) From: Rohan G Thomas via B4 Relay Date: Wed, 29 Oct 2025 16:06:14 +0800 Subject: [PATCH net-next 2/4] net: stmmac: socfpga: Enable TBS support for Agilex5 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251029-agilex5_ext-v1-2-1931132d77d6@altera.com> References: <20251029-agilex5_ext-v1-0-1931132d77d6@altera.com> In-Reply-To: <20251029-agilex5_ext-v1-0-1931132d77d6@altera.com> To: Maxime Chevallier , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Alexandre Torgue , Richard Cochran , Steffen Trumtrar Cc: netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rohan G Thomas X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1761725182; l=1189; i=rohan.g.thomas@altera.com; s=20250815; h=from:subject:message-id; bh=xSJKSpzgBUj6X7SaRiqPgyeJfwi6PIzrINgCzQeog7s=; b=8SDkbxGig66XtJrELUxq38wXz640VIOzsR/gO+kkHJvQzQZVfXdl5J7m1gsIdbdgDYQZiKbl0 cKATRITmZzNDbB6AewGNQndYuQwl85NB0G5Y9LEWVUbJ0LywdZ8FRxM X-Developer-Key: i=rohan.g.thomas@altera.com; a=ed25519; pk=5yZXkXswhfUILKAQwoIn7m6uSblwgV5oppxqde4g4TY= X-Endpoint-Received: by B4 Relay for rohan.g.thomas@altera.com/20250815 with auth_id=494 X-Original-From: Rohan G Thomas Reply-To: rohan.g.thomas@altera.com From: Rohan G Thomas Agilex5 supports Time-Based Scheduling(TBS) for Tx queue 6 and Tx queue 7. This commit enables TBS support for these queues. Signed-off-by: Rohan G Thomas --- drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c b/drivers/= net/ethernet/stmicro/stmmac/dwmac-socfpga.c index 3dae4f3c103802ed1c2cd390634bd5473192d4ee..c02e6fa715bbea2f703bcdeee9d= 7a41be51ce91c 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c @@ -473,6 +473,19 @@ static void socfpga_agilex5_setup_plat_dat(struct socf= pga_dwmac *dwmac) socfpga_common_plat_dat(dwmac); =20 plat_dat->core_type =3D DWMAC_CORE_XGMAC; + + /* Enable TBS */ + switch (plat_dat->tx_queues_to_use) { + case 8: + plat_dat->tx_queues_cfg[7].tbs_en =3D true; + fallthrough; + case 7: + plat_dat->tx_queues_cfg[6].tbs_en =3D true; + break; + default: + /* Tx Queues 0 - 5 doesn't support TBS on Agilex5 */ + break; + } } =20 static int socfpga_dwmac_probe(struct platform_device *pdev) --=20 2.43.7 From nobody Mon Dec 15 18:54:00 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3914E320A0F; Wed, 29 Oct 2025 08:06:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761725185; cv=none; b=J6FhX9M803HZxqtp7oovanRr7JTYzgy17uROKEaT2/EEGPXHYgXo+83JreH4yF56yJu1N9AjEXX9std5enbc19UPpTq0hP0LYzVDF2ZpDtJXwr7FC9mfC357r7mLYNmnXJduDeJ5zKu+iGr7lcwbp1tXA1T2SBY9CRcBX5ZlxR8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761725185; c=relaxed/simple; bh=EILhiXwSG8mnsP3WGsVKBzN2WcZ7wKbqmXj+1wrNFzc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=mb1IuplpP8LgCiP/jqtZIxjxFhZISSwOOIdZ4ncu1xInUWcPBL52YwjIpkhHyuFMHcMqT6tgATgZQ2Cfk1AR9nbMOY83npz1YcwX/gpy5Qq41e+n9EpPV8zju1/WpG4z8mgcf3i8qTg2pOlRsbx98X4N10G+p92VgPUjs5TPQv0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=HIlPSwP9; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="HIlPSwP9" Received: by smtp.kernel.org (Postfix) with ESMTPS id E4E36C116C6; Wed, 29 Oct 2025 08:06:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1761725185; bh=EILhiXwSG8mnsP3WGsVKBzN2WcZ7wKbqmXj+1wrNFzc=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=HIlPSwP91NTIR8DUNPxOnv/QWitRD5UCo3NK/LPNUYywq319bFSleyjDrASLyZOET EyIg0r/E+LHUX9/Hq+kfNL+Bos3HAlc31jpPtpI8ebdy1KmvlWbpeevQy/Ea0m+MsE CZxtVAHJ/EZkb4P+nKtVgKgkFcVUPxK8S7u3BT4icP5l9DzyGjLdGSKdp93YlfQpxM A7gXBhn4zDD0LE6oqsKQVGXdxN1R/kNNxiO48BnxfFr9jKfR/pla2chJzOGgRZwPjX q2cO7hiXVFPHEOKIR6bAtvg3xGjatE25cb+zcJGNTO3LMtqDlcnP6GoljUjd61a2N9 knbmbYWBeMLEw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id D9E74CCF9F3; Wed, 29 Oct 2025 08:06:24 +0000 (UTC) From: Rohan G Thomas via B4 Relay Date: Wed, 29 Oct 2025 16:06:15 +0800 Subject: [PATCH net-next 3/4] net: stmmac: socfpga: Enable TSO for Agilex5 platform Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251029-agilex5_ext-v1-3-1931132d77d6@altera.com> References: <20251029-agilex5_ext-v1-0-1931132d77d6@altera.com> In-Reply-To: <20251029-agilex5_ext-v1-0-1931132d77d6@altera.com> To: Maxime Chevallier , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Alexandre Torgue , Richard Cochran , Steffen Trumtrar Cc: netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rohan G Thomas X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1761725182; l=898; i=rohan.g.thomas@altera.com; s=20250815; h=from:subject:message-id; bh=p2uWSKKuLwxCOpiNDSbfDTRN7HWTGIFC7QoK3weEpGc=; b=zvAEVmt+YCzpgZzoyQtINmkYcMh3/hMOKUNLU/c2tHXcq3h/po36vCnYfNbJL7FRIrYsYIqLa yFsbzkbCYp7Bbvx1f8salXZIKI48J2OoZKGS74Dg5MPOSyLxdweez8P X-Developer-Key: i=rohan.g.thomas@altera.com; a=ed25519; pk=5yZXkXswhfUILKAQwoIn7m6uSblwgV5oppxqde4g4TY= X-Endpoint-Received: by B4 Relay for rohan.g.thomas@altera.com/20250815 with auth_id=494 X-Original-From: Rohan G Thomas Reply-To: rohan.g.thomas@altera.com From: Rohan G Thomas Agilex5 supports TCP Segmentation Offload(TSO). This commit enables TSO for Agilex5 socfpga platforms. Signed-off-by: Rohan G Thomas --- drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c b/drivers/= net/ethernet/stmicro/stmmac/dwmac-socfpga.c index c02e6fa715bbea2f703bcdeee9d7a41be51ce91c..37fcf272a46920d1d97a4b651a4= 69767609373b4 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c @@ -474,6 +474,9 @@ static void socfpga_agilex5_setup_plat_dat(struct socfp= ga_dwmac *dwmac) =20 plat_dat->core_type =3D DWMAC_CORE_XGMAC; =20 + /* Enable TSO */ + plat_dat->flags |=3D STMMAC_FLAG_TSO_EN; + /* Enable TBS */ switch (plat_dat->tx_queues_to_use) { case 8: --=20 2.43.7 From nobody Mon Dec 15 18:54:00 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 390CB31B10D; Wed, 29 Oct 2025 08:06:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761725185; cv=none; b=SevEnlHF1DkmVQvY5y08hE5EcbsdWBTn2T8kb0nq9L3wlPv/tvkt7q6t8PeRqpZUCcHD0J1ZFvWnc0l+PxZ66F6lTemUGBk+CSjquwr46xPbgfJmDeY2q81wauXncFiahoBsp9AzPn1bNTlC9VFaZjsb1La9WGJo+e9VvcK/K+c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761725185; c=relaxed/simple; bh=h6Poh04xfjup8bHK1NHe1ZEcNsz2wld/VP/Vdn6DDTQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Ftk6lzXtx8jzfxinL35N1I2W/Y0GeMco2S9rrBw+PpP67eAolp17ZPOuT4eA7t5ipO4/E4RXcPwvyHAB3SfTEgXmQERdJ1sAOUZPz97DyaG2RDbTJt+x+oSuIMg37DqQuT2pzk5kXt75DMp5qDWVu4sQPIui23+2jV8kirFxkT0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=HVY7K9p9; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="HVY7K9p9" Received: by smtp.kernel.org (Postfix) with ESMTPS id 02A62C19421; Wed, 29 Oct 2025 08:06:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1761725185; bh=h6Poh04xfjup8bHK1NHe1ZEcNsz2wld/VP/Vdn6DDTQ=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=HVY7K9p9MOH1ueZGbZafRkY7ixs02cP3wBU3IT4TKvkuAXYT8idv9p7FC8YDih0vh KkB0O1wkxIXMxknUz6y8+pI2wL2m7PZF+wpTVaLbSl5nGB9NTjMgrADaHeWuJFfQCK 535lm9CpwCvsJbf4H5Wxk9lqLCaKQmgPwJAgkbgT4jSwzw03NtqzO/CD42llR2cXKb jaHWEwHNx3eDvdV6vh0Q5lngVoofHS+7ZAQ3TK7gm7FBeHEwICZmy1BB/2mXOEe9cF pJwsEDdaxUB/2M0mVaVgfYiwfLumsMDEsvFWyFEWjW/iuUdWe6fV4oFr3sWYj08iCH lf2Ltn5pX92iQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id EA253CCF9EE; Wed, 29 Oct 2025 08:06:24 +0000 (UTC) From: Rohan G Thomas via B4 Relay Date: Wed, 29 Oct 2025 16:06:16 +0800 Subject: [PATCH net-next 4/4] net: stmmac: socfpga: Add hardware supported cross-timestamp Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251029-agilex5_ext-v1-4-1931132d77d6@altera.com> References: <20251029-agilex5_ext-v1-0-1931132d77d6@altera.com> In-Reply-To: <20251029-agilex5_ext-v1-0-1931132d77d6@altera.com> To: Maxime Chevallier , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Alexandre Torgue , Richard Cochran , Steffen Trumtrar Cc: netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rohan G Thomas X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1761725182; l=7260; i=rohan.g.thomas@altera.com; s=20250815; h=from:subject:message-id; bh=tUV/L7I6pOGEG38MdWI+75TwNmBVsKyEDIuFz1TUCgU=; b=/smYeDjK8rwqYcgfEOpvuMUFqL6IEZpzQmRyCLPGablCq+W4zvn+KYPaTwBit++QgjOUr83wd rfffrHawDlaCV0cK2KiOjCLsdGsKnFSX58w84U23PMwor8COayGh/+U X-Developer-Key: i=rohan.g.thomas@altera.com; a=ed25519; pk=5yZXkXswhfUILKAQwoIn7m6uSblwgV5oppxqde4g4TY= X-Endpoint-Received: by B4 Relay for rohan.g.thomas@altera.com/20250815 with auth_id=494 X-Original-From: Rohan G Thomas Reply-To: rohan.g.thomas@altera.com From: Rohan G Thomas Cross timestamping is supported on Agilex5 platform with Synchronized Multidrop Timestamp Gathering(SMTG) IP. The hardware cross-timestamp result is made available the applications through the ioctl call PTP_SYS_OFFSET_PRECISE, which inturn calls stmmac_getcrosststamp(). Device time is stored in the MAC Auxiliary register. The 64-bit System time (ARM_ARCH_COUNTER) is stored in SMTG IP. SMTG IP is an MDIO device with 0xC - 0xF MDIO register space holds 64-bit system time. This commit is similar to following commit for Intel platforms: Commit 341f67e424e5 ("net: stmmac: Add hardware supported cross-timestamp") Signed-off-by: Rohan G Thomas --- .../net/ethernet/stmicro/stmmac/dwmac-socfpga.c | 125 +++++++++++++++++= ++++ drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h | 5 + 2 files changed, 130 insertions(+) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c b/drivers/= net/ethernet/stmicro/stmmac/dwmac-socfpga.c index 37fcf272a46920d1d97a4b651a469767609373b4..d36c9b77003ef4ad3ac598929fe= e3f7a8b94b9bc 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c @@ -5,6 +5,7 @@ */ =20 #include +#include #include #include #include @@ -15,8 +16,10 @@ #include #include =20 +#include "dwxgmac2.h" #include "stmmac.h" #include "stmmac_platform.h" +#include "stmmac_ptp.h" =20 #define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII 0x0 #define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII 0x1 @@ -41,6 +44,13 @@ #define SGMII_ADAPTER_ENABLE 0x0000 #define SGMII_ADAPTER_DISABLE 0x0001 =20 +#define SMTG_MDIO_ADDR 0x15 +#define SMTG_TSC_WORD0 0xC +#define SMTG_TSC_WORD1 0xD +#define SMTG_TSC_WORD2 0xE +#define SMTG_TSC_WORD3 0xF +#define SMTG_TSC_SHIFT 16 + struct socfpga_dwmac; struct socfpga_dwmac_ops { int (*set_phy_mode)(struct socfpga_dwmac *dwmac_priv); @@ -269,6 +279,117 @@ static int socfpga_set_phy_mode_common(int phymode, u= 32 *val) return 0; } =20 +static void get_smtgtime(struct mii_bus *mii, int smtg_addr, u64 *smtg_tim= e) +{ + u64 ns; + + ns =3D mdiobus_read(mii, smtg_addr, SMTG_TSC_WORD3); + ns <<=3D SMTG_TSC_SHIFT; + ns |=3D mdiobus_read(mii, smtg_addr, SMTG_TSC_WORD2); + ns <<=3D SMTG_TSC_SHIFT; + ns |=3D mdiobus_read(mii, smtg_addr, SMTG_TSC_WORD1); + ns <<=3D SMTG_TSC_SHIFT; + ns |=3D mdiobus_read(mii, smtg_addr, SMTG_TSC_WORD0); + + *smtg_time =3D ns; +} + +static int dwxgmac_cross_ts_isr(struct stmmac_priv *priv) +{ + return (readl(priv->ioaddr + XGMAC_INT_STATUS) & XGMAC_INT_TSIS); +} + +static int smtg_crosststamp(ktime_t *device, struct system_counterval_t *s= ystem, + void *ctx) +{ + struct stmmac_priv *priv =3D (struct stmmac_priv *)ctx; + u32 num_snapshot, gpio_value, acr_value; + void __iomem *ptpaddr =3D priv->ptpaddr; + void __iomem *ioaddr =3D priv->hw->pcsr; + unsigned long flags; + u64 smtg_time =3D 0; + u64 ptp_time =3D 0; + int i, ret; + + /* Both internal crosstimestamping and external triggered event + * timestamping cannot be run concurrently. + */ + if (priv->plat->flags & STMMAC_FLAG_EXT_SNAPSHOT_EN) + return -EBUSY; + + mutex_lock(&priv->aux_ts_lock); + /* Enable Internal snapshot trigger */ + acr_value =3D readl(ptpaddr + PTP_ACR); + acr_value &=3D ~PTP_ACR_MASK; + switch (priv->plat->int_snapshot_num) { + case AUX_SNAPSHOT0: + acr_value |=3D PTP_ACR_ATSEN0; + break; + case AUX_SNAPSHOT1: + acr_value |=3D PTP_ACR_ATSEN1; + break; + case AUX_SNAPSHOT2: + acr_value |=3D PTP_ACR_ATSEN2; + break; + case AUX_SNAPSHOT3: + acr_value |=3D PTP_ACR_ATSEN3; + break; + default: + mutex_unlock(&priv->aux_ts_lock); + return -EINVAL; + } + writel(acr_value, ptpaddr + PTP_ACR); + + /* Clear FIFO */ + acr_value =3D readl(ptpaddr + PTP_ACR); + acr_value |=3D PTP_ACR_ATSFC; + writel(acr_value, ptpaddr + PTP_ACR); + /* Release the mutex */ + mutex_unlock(&priv->aux_ts_lock); + + /* Trigger Internal snapshot signal. Create a rising edge by just toggle + * the GPO0 to low and back to high. + */ + gpio_value =3D readl(ioaddr + XGMAC_GPIO_STATUS); + gpio_value &=3D ~XGMAC_GPIO_GPO0; + writel(gpio_value, ioaddr + XGMAC_GPIO_STATUS); + gpio_value |=3D XGMAC_GPIO_GPO0; + writel(gpio_value, ioaddr + XGMAC_GPIO_STATUS); + + /* Time sync done Indication - Interrupt method */ + if (!wait_event_interruptible_timeout(priv->tstamp_busy_wait, + dwxgmac_cross_ts_isr(priv), + HZ / 100)) { + priv->plat->flags &=3D ~STMMAC_FLAG_INT_SNAPSHOT_EN; + return -ETIMEDOUT; + } + + *system =3D (struct system_counterval_t) { + .cycles =3D 0, + .cs_id =3D CSID_ARM_ARCH_COUNTER, + .use_nsecs =3D true, + }; + + num_snapshot =3D (readl(ioaddr + XGMAC_TIMESTAMP_STATUS) & + XGMAC_TIMESTAMP_ATSNS_MASK) >> + XGMAC_TIMESTAMP_ATSNS_SHIFT; + + /* Repeat until the timestamps are from the FIFO last segment */ + for (i =3D 0; i < num_snapshot; i++) { + read_lock_irqsave(&priv->ptp_lock, flags); + stmmac_get_ptptime(priv, ptpaddr, &ptp_time); + *device =3D ns_to_ktime(ptp_time); + read_unlock_irqrestore(&priv->ptp_lock, flags); + } + + get_smtgtime(priv->mii, SMTG_MDIO_ADDR, &smtg_time); + system->cycles =3D smtg_time; + + priv->plat->flags &=3D ~STMMAC_FLAG_INT_SNAPSHOT_EN; + + return ret; +} + static int socfpga_gen5_set_phy_mode(struct socfpga_dwmac *dwmac) { struct regmap *sys_mgr_base_addr =3D dwmac->sys_mgr_base_addr; @@ -489,6 +610,10 @@ static void socfpga_agilex5_setup_plat_dat(struct socf= pga_dwmac *dwmac) /* Tx Queues 0 - 5 doesn't support TBS on Agilex5 */ break; } + + /* Hw supported cross-timestamp */ + plat_dat->int_snapshot_num =3D AUX_SNAPSHOT0; + plat_dat->crosststamp =3D smtg_crosststamp; } =20 static int socfpga_dwmac_probe(struct platform_device *pdev) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h b/drivers/net/e= thernet/stmicro/stmmac/dwxgmac2.h index 0d408ee17f337851502cbcba8e82d2b839b9db02..e48cfa05000c07ed9194de786ef= a530a61a9dbfa 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h +++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h @@ -79,6 +79,7 @@ #define XGMAC_PSRQ(x) GENMASK((x) * 8 + 7, (x) * 8) #define XGMAC_PSRQ_SHIFT(x) ((x) * 8) #define XGMAC_INT_STATUS 0x000000b0 +#define XGMAC_INT_TSIS BIT(12) #define XGMAC_LPIIS BIT(5) #define XGMAC_PMTIS BIT(4) #define XGMAC_INT_EN 0x000000b4 @@ -173,6 +174,8 @@ #define XGMAC_MDIO_ADDR 0x00000200 #define XGMAC_MDIO_DATA 0x00000204 #define XGMAC_MDIO_C22P 0x00000220 +#define XGMAC_GPIO_STATUS 0x0000027c +#define XGMAC_GPIO_GPO0 BIT(16) #define XGMAC_ADDRx_HIGH(x) (0x00000300 + (x) * 0x8) #define XGMAC_ADDR_MAX 32 #define XGMAC_AE BIT(31) @@ -220,6 +223,8 @@ #define XGMAC_OB BIT(0) #define XGMAC_RSS_DATA 0x00000c8c #define XGMAC_TIMESTAMP_STATUS 0x00000d20 +#define XGMAC_TIMESTAMP_ATSNS_MASK GENMASK(29, 25) +#define XGMAC_TIMESTAMP_ATSNS_SHIFT 25 #define XGMAC_TXTSC BIT(15) #define XGMAC_TXTIMESTAMP_NSEC 0x00000d30 #define XGMAC_TXTSSTSLO GENMASK(30, 0) --=20 2.43.7