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([2401:4900:1c06:77f0:168f:479e:bf92:ce93]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-29498cf3410sm125713005ad.8.2025.10.28.10.55.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Oct 2025 10:55:13 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v2 1/5] arm64: dts: renesas: r9a09g077: Add ETHSS node Date: Tue, 28 Oct 2025 17:54:54 +0000 Message-ID: <20251028175458.1037397-2-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251028175458.1037397-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20251028175458.1037397-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Add an Ethernet Switch Subsystem (ETHSS) device node to the RZ/T2H (R9A09G077) SoC. The ETHSS IP block is responsible for handling MII pass-through or conversion to RMII/RGMII. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven --- v1->v2 changes: - No changes. --- arch/arm64/boot/dts/renesas/r9a09g077.dtsi | 37 ++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi b/arch/arm64/boot/d= ts/renesas/r9a09g077.dtsi index 2acca4bc1d3a..8a530c12a6dc 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi @@ -270,6 +270,43 @@ i2c2: i2c@81008000 { status =3D "disabled"; }; =20 + ethss: ethss@80110000 { + compatible =3D "renesas,r9a09g077-miic"; + reg =3D <0 0x80110000 0 0x10000>; + clocks =3D <&cpg CPG_CORE R9A09G077_ETCLKE>, + <&cpg CPG_CORE R9A09G077_ETCLKB>, + <&cpg CPG_CORE R9A09G077_ETCLKD>, + <&cpg CPG_MOD 403>; + clock-names =3D "mii_ref", "rgmii_ref", "rmii_ref", "hclk"; + resets =3D <&cpg 405>, <&cpg 406>; + reset-names =3D "rst", "crst"; + power-domains =3D <&cpg>; + status =3D "disabled"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + mii_conv0: mii-conv@0 { + reg =3D <0>; + status =3D "disabled"; + }; + + mii_conv1: mii-conv@1 { + reg =3D <1>; + status =3D "disabled"; + }; + + mii_conv2: mii-conv@2 { + reg =3D <2>; + status =3D "disabled"; + }; + + mii_conv3: mii-conv@3 { + reg =3D <3>; + status =3D "disabled"; + }; + }; + cpg: clock-controller@80280000 { compatible =3D "renesas,r9a09g077-cpg-mssr"; reg =3D <0 0x80280000 0 0x1000>, --=20 2.43.0 From nobody Mon Feb 9 12:54:52 2026 Received: from mail-pg1-f172.google.com (mail-pg1-f172.google.com [209.85.215.172]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9067C34C9A3 for ; Tue, 28 Oct 2025 17:55:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.215.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761674122; cv=none; b=dyYhxegoc+xUyo+Tv+MpDyTbNUn8+7reqTxCY4MwSk3iLVo9+99qlxEsh9FbtocnTC4kvHHpEGbNpLb7UEKNqHBNxQPrxiS10w7yKbhJWoh3VADVycq+0KHv+tcyvly32C5Yj461TcoJBrfCmm3t2NawG9M+5Bb5f+bL19z8gfQ= ARC-Message-Signature: i=1; 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([2401:4900:1c06:77f0:168f:479e:bf92:ce93]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-29498cf3410sm125713005ad.8.2025.10.28.10.55.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Oct 2025 10:55:18 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v2 2/5] arm64: dts: renesas: r9a09g087: Add ETHSS node Date: Tue, 28 Oct 2025 17:54:55 +0000 Message-ID: <20251028175458.1037397-3-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251028175458.1037397-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20251028175458.1037397-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Add an Ethernet Switch Subsystem (ETHSS) device node to the RZ/N2H (R9A09G087) SoC. The ETHSS IP block is responsible for handling MII pass-through or conversion to RMII/RGMII. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven --- v1->v2 changes: - No changes. --- arch/arm64/boot/dts/renesas/r9a09g087.dtsi | 37 ++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi b/arch/arm64/boot/d= ts/renesas/r9a09g087.dtsi index 3ece794fb0a7..fe0087a7d4b4 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi @@ -270,6 +270,43 @@ i2c2: i2c@81008000 { status =3D "disabled"; }; =20 + ethss: ethss@80110000 { + compatible =3D "renesas,r9a09g087-miic", "renesas,r9a09g077-miic"; + reg =3D <0 0x80110000 0 0x10000>; + clocks =3D <&cpg CPG_CORE R9A09G087_ETCLKE>, + <&cpg CPG_CORE R9A09G087_ETCLKB>, + <&cpg CPG_CORE R9A09G087_ETCLKD>, + <&cpg CPG_MOD 403>; + clock-names =3D "mii_ref", "rgmii_ref", "rmii_ref", "hclk"; + resets =3D <&cpg 405>, <&cpg 406>; + reset-names =3D "rst", "crst"; + power-domains =3D <&cpg>; + status =3D "disabled"; + + #address-cells =3D <1>; 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([2401:4900:1c06:77f0:168f:479e:bf92:ce93]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-29498cf3410sm125713005ad.8.2025.10.28.10.55.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Oct 2025 10:55:23 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v2 3/5] arm64: dts: renesas: r9a09g077: Add GMAC nodes Date: Tue, 28 Oct 2025 17:54:56 +0000 Message-ID: <20251028175458.1037397-4-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251028175458.1037397-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20251028175458.1037397-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Add Ethernet MAC (GMAC) device nodes to the RZ/T2H (R9A09G077) SoC DTSI. The RZ/T2H integrates three GMAC interfaces based on the Synopsys DesignWare MAC (version 5.20). Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven --- v1->v2 changes: - No changes. --- arch/arm64/boot/dts/renesas/r9a09g077.dtsi | 445 +++++++++++++++++++++ 1 file changed, 445 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi b/arch/arm64/boot/d= ts/renesas/r9a09g077.dtsi index 8a530c12a6dc..f5fa6ca06409 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi @@ -270,6 +270,444 @@ i2c2: i2c@81008000 { status =3D "disabled"; }; =20 + gmac0: ethernet@80100000 { + compatible =3D "renesas,r9a09g077-gbeth", "snps,dwmac-5.20"; + reg =3D <0 0x80100000 0 0x10000>; + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names =3D "macirq", "eth_wake_irq", "eth_lpi", + "rx-queue-0", "rx-queue-1", "rx-queue-2", + "rx-queue-3", "rx-queue-4", "rx-queue-5", + "rx-queue-6", "rx-queue-7", "tx-queue-0", + "tx-queue-1", "tx-queue-2", "tx-queue-3", + "tx-queue-4", "tx-queue-5", "tx-queue-6", + "tx-queue-7"; + clocks =3D <&cpg CPG_MOD 400>, + <&cpg CPG_CORE R9A09G077_CLK_PCLKH>, + <&cpg CPG_CORE R9A09G077_ETCLKB>; + clock-names =3D "stmmaceth", "pclk", "tx"; + resets =3D <&cpg 400>, <&cpg 401>; + reset-names =3D "stmmaceth", "ahb"; + power-domains =3D <&cpg>; + snps,multicast-filter-bins =3D <256>; + snps,perfect-filter-entries =3D <32>; + rx-fifo-depth =3D <8192>; + tx-fifo-depth =3D <8192>; + snps,fixed-burst; + snps,no-pbl-x8; + snps,force_thresh_dma_mode; + snps,axi-config =3D <&stmmac_axi_setup>; + snps,mtl-rx-config =3D <&mtl_rx_setup0>; + snps,mtl-tx-config =3D <&mtl_tx_setup0>; + snps,txpbl =3D <16>; + snps,rxpbl =3D <16>; + status =3D "disabled"; + + mdio0: mdio { + compatible =3D "snps,dwmac-mdio"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + mtl_rx_setup0: rx-queues-config { + snps,rx-queues-to-use =3D <8>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,priority =3D <0x1>; + snps,map-to-dma-channel =3D <0>; + }; + + queue1 { + snps,dcb-algorithm; + snps,priority =3D <0x2>; + snps,map-to-dma-channel =3D <1>; + }; + + queue2 { + snps,dcb-algorithm; + snps,priority =3D <0x4>; + snps,map-to-dma-channel =3D <2>; + }; + + queue3 { + snps,dcb-algorithm; + snps,priority =3D <0x8>; + snps,map-to-dma-channel =3D <3>; + }; + + queue4 { + snps,dcb-algorithm; + snps,priority =3D <0x10>; + snps,map-to-dma-channel =3D <4>; + }; + + queue5 { + snps,dcb-algorithm; + snps,priority =3D <0x20>; + snps,map-to-dma-channel =3D <5>; + }; + + queue6 { + snps,dcb-algorithm; + snps,priority =3D <0x40>; + snps,map-to-dma-channel =3D <6>; + }; + + queue7 { + snps,dcb-algorithm; + snps,priority =3D <0x80>; + snps,map-to-dma-channel =3D <7>; + }; + }; + + mtl_tx_setup0: tx-queues-config { + snps,tx-queues-to-use =3D <8>; + + queue0 { + snps,dcb-algorithm; + }; + + queue1 { + snps,dcb-algorithm; + }; + + queue2 { + snps,dcb-algorithm; + }; + + queue3 { + snps,dcb-algorithm; + }; + + queue4 { + snps,dcb-algorithm; + }; + + queue5 { + snps,dcb-algorithm; + }; + + queue6 { + snps,dcb-algorithm; + }; + + queue7 { + snps,dcb-algorithm; + }; + }; + }; + + gmac1: ethernet@92000000 { + compatible =3D "renesas,r9a09g077-gbeth", "snps,dwmac-5.20"; + reg =3D <0 0x92000000 0 0x10000>; + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names =3D "macirq", "eth_wake_irq", "eth_lpi", + "rx-queue-0", "rx-queue-1", "rx-queue-2", + "rx-queue-3", "rx-queue-4", "rx-queue-5", + "rx-queue-6", "rx-queue-7", "tx-queue-0", + "tx-queue-1", "tx-queue-2", "tx-queue-3", + "tx-queue-4", "tx-queue-5", "tx-queue-6", + "tx-queue-7"; + clocks =3D <&cpg CPG_MOD 416>, + <&cpg CPG_CORE R9A09G077_CLK_PCLKAH>, + <&cpg CPG_CORE R9A09G077_ETCLKB>; + clock-names =3D "stmmaceth", "pclk", "tx"; + resets =3D <&cpg 416>, <&cpg 417>; + reset-names =3D "stmmaceth", "ahb"; + power-domains =3D <&cpg>; + snps,multicast-filter-bins =3D <256>; + snps,perfect-filter-entries =3D <32>; + rx-fifo-depth =3D <8192>; + tx-fifo-depth =3D <8192>; + snps,fixed-burst; + snps,no-pbl-x8; + snps,force_thresh_dma_mode; + snps,axi-config =3D <&stmmac_axi_setup>; + snps,mtl-rx-config =3D <&mtl_rx_setup1>; + snps,mtl-tx-config =3D <&mtl_tx_setup1>; + snps,txpbl =3D <16>; + snps,rxpbl =3D <16>; + status =3D "disabled"; + + mdio1: mdio { + compatible =3D "snps,dwmac-mdio"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + mtl_rx_setup1: rx-queues-config { + snps,rx-queues-to-use =3D <8>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,priority =3D <0x1>; + snps,map-to-dma-channel =3D <0>; + }; + + queue1 { + snps,dcb-algorithm; + snps,priority =3D <0x2>; + snps,map-to-dma-channel =3D <1>; + }; + + queue2 { + snps,dcb-algorithm; + snps,priority =3D <0x4>; + snps,map-to-dma-channel =3D <2>; + }; + + queue3 { + snps,dcb-algorithm; + snps,priority =3D <0x8>; + snps,map-to-dma-channel =3D <3>; + }; + + queue4 { + snps,dcb-algorithm; + snps,priority =3D <0x10>; + snps,map-to-dma-channel =3D <4>; + }; + + queue5 { + snps,dcb-algorithm; + snps,priority =3D <0x20>; + snps,map-to-dma-channel =3D <5>; + }; + + queue6 { + snps,dcb-algorithm; + snps,priority =3D <0x40>; + snps,map-to-dma-channel =3D <6>; + }; + + queue7 { + snps,dcb-algorithm; + snps,priority =3D <0x80>; + snps,map-to-dma-channel =3D <7>; + }; + }; + + mtl_tx_setup1: tx-queues-config { + snps,tx-queues-to-use =3D <8>; + + queue0 { + snps,dcb-algorithm; + }; + + queue1 { + snps,dcb-algorithm; + }; + + queue2 { + snps,dcb-algorithm; + }; + + queue3 { + snps,dcb-algorithm; + }; + + queue4 { + snps,dcb-algorithm; + }; + + queue5 { + snps,dcb-algorithm; + }; + + queue6 { + snps,dcb-algorithm; + }; + + queue7 { + snps,dcb-algorithm; + }; + }; + }; + + gmac2: ethernet@92010000 { + compatible =3D "renesas,r9a09g077-gbeth", "snps,dwmac-5.20"; + reg =3D <0 0x92010000 0 0x10000>; + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names =3D "macirq", "eth_wake_irq", "eth_lpi", + "rx-queue-0", "rx-queue-1", "rx-queue-2", + "rx-queue-3", "rx-queue-4", "rx-queue-5", + "rx-queue-6", "rx-queue-7", "tx-queue-0", + "tx-queue-1", "tx-queue-2", "tx-queue-3", + "tx-queue-4", "tx-queue-5", "tx-queue-6", + "tx-queue-7"; + clocks =3D <&cpg CPG_MOD 417>, + <&cpg CPG_CORE R9A09G077_CLK_PCLKAH>, + <&cpg CPG_CORE R9A09G077_ETCLKB>; + clock-names =3D "stmmaceth", "pclk", "tx"; + resets =3D <&cpg 418>, <&cpg 419>; + reset-names =3D "stmmaceth", "ahb"; + power-domains =3D <&cpg>; + snps,multicast-filter-bins =3D <256>; + snps,perfect-filter-entries =3D <32>; + rx-fifo-depth =3D <8192>; + tx-fifo-depth =3D <8192>; + snps,fixed-burst; + snps,no-pbl-x8; + snps,force_thresh_dma_mode; + snps,axi-config =3D <&stmmac_axi_setup>; + snps,mtl-rx-config =3D <&mtl_rx_setup2>; + snps,mtl-tx-config =3D <&mtl_tx_setup2>; + snps,txpbl =3D <16>; + snps,rxpbl =3D <16>; + status =3D "disabled"; + + mdio2: mdio { + compatible =3D "snps,dwmac-mdio"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + mtl_rx_setup2: rx-queues-config { + snps,rx-queues-to-use =3D <8>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,priority =3D <0x1>; + snps,map-to-dma-channel =3D <0>; + }; + + queue1 { + snps,dcb-algorithm; + snps,priority =3D <0x2>; + snps,map-to-dma-channel =3D <1>; + }; + + queue2 { + snps,dcb-algorithm; + snps,priority =3D <0x4>; + snps,map-to-dma-channel =3D <2>; + }; + + queue3 { + snps,dcb-algorithm; + snps,priority =3D <0x8>; + snps,map-to-dma-channel =3D <3>; + }; + + queue4 { + snps,dcb-algorithm; + snps,priority =3D <0x10>; + snps,map-to-dma-channel =3D <4>; + }; + + queue5 { + snps,dcb-algorithm; + snps,priority =3D <0x20>; + snps,map-to-dma-channel =3D <5>; + }; + + queue6 { + snps,dcb-algorithm; + snps,priority =3D <0x40>; + snps,map-to-dma-channel =3D <6>; + }; + + queue7 { + snps,dcb-algorithm; + snps,priority =3D <0x80>; + snps,map-to-dma-channel =3D <7>; + }; + }; + + mtl_tx_setup2: tx-queues-config { + snps,tx-queues-to-use =3D <8>; + + queue0 { + snps,dcb-algorithm; + }; + + queue1 { + snps,dcb-algorithm; + }; + + queue2 { + snps,dcb-algorithm; + }; + + queue3 { + snps,dcb-algorithm; + }; + + queue4 { + snps,dcb-algorithm; + }; + + queue5 { + snps,dcb-algorithm; + }; + + queue6 { + snps,dcb-algorithm; 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([2401:4900:1c06:77f0:168f:479e:bf92:ce93]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-29498cf3410sm125713005ad.8.2025.10.28.10.55.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Oct 2025 10:55:28 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v2 4/5] arm64: dts: renesas: r9a09g087: Add GMAC nodes Date: Tue, 28 Oct 2025 17:54:57 +0000 Message-ID: <20251028175458.1037397-5-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251028175458.1037397-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20251028175458.1037397-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Add Ethernet MAC (GMAC) device nodes to the RZ/N2H (R9A09G087) SoC DTSI. The RZ/T2H integrates three GMAC interfaces based on the Synopsys DesignWare MAC (version 5.20). Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven --- v1->v2 changes: - No changes. --- arch/arm64/boot/dts/renesas/r9a09g087.dtsi | 448 +++++++++++++++++++++ 1 file changed, 448 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi b/arch/arm64/boot/d= ts/renesas/r9a09g087.dtsi index fe0087a7d4b4..361a9235f00d 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi @@ -270,6 +270,447 @@ i2c2: i2c@81008000 { status =3D "disabled"; }; =20 + gmac0: ethernet@80100000 { + compatible =3D "renesas,r9a09g087-gbeth", "renesas,r9a09g077-gbeth", + "snps,dwmac-5.20"; + reg =3D <0 0x80100000 0 0x10000>; + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names =3D "macirq", "eth_wake_irq", "eth_lpi", + "rx-queue-0", "rx-queue-1", "rx-queue-2", + "rx-queue-3", "rx-queue-4", "rx-queue-5", + "rx-queue-6", "rx-queue-7", "tx-queue-0", + "tx-queue-1", "tx-queue-2", "tx-queue-3", + "tx-queue-4", "tx-queue-5", "tx-queue-6", + "tx-queue-7"; + clocks =3D <&cpg CPG_MOD 400>, + <&cpg CPG_CORE R9A09G087_CLK_PCLKH>, + <&cpg CPG_CORE R9A09G087_ETCLKB>; + clock-names =3D "stmmaceth", "pclk", "tx"; + resets =3D <&cpg 400>, <&cpg 401>; + reset-names =3D "stmmaceth", "ahb"; + power-domains =3D <&cpg>; + snps,multicast-filter-bins =3D <256>; + snps,perfect-filter-entries =3D <32>; + rx-fifo-depth =3D <8192>; + tx-fifo-depth =3D <8192>; + snps,fixed-burst; + snps,no-pbl-x8; + snps,force_thresh_dma_mode; + snps,axi-config =3D <&stmmac_axi_setup>; + snps,mtl-rx-config =3D <&mtl_rx_setup0>; + snps,mtl-tx-config =3D <&mtl_tx_setup0>; + snps,txpbl =3D <16>; + snps,rxpbl =3D <16>; + status =3D "disabled"; + + mdio0: mdio { + compatible =3D "snps,dwmac-mdio"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + mtl_rx_setup0: rx-queues-config { + snps,rx-queues-to-use =3D <8>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,priority =3D <0x1>; + snps,map-to-dma-channel =3D <0>; + }; + + queue1 { + snps,dcb-algorithm; + snps,priority =3D <0x2>; + snps,map-to-dma-channel =3D <1>; + }; + + queue2 { + snps,dcb-algorithm; + snps,priority =3D <0x4>; + snps,map-to-dma-channel =3D <2>; + }; + + queue3 { + snps,dcb-algorithm; + snps,priority =3D <0x8>; + snps,map-to-dma-channel =3D <3>; + }; + + queue4 { + snps,dcb-algorithm; + snps,priority =3D <0x10>; + snps,map-to-dma-channel =3D <4>; + }; + + queue5 { + snps,dcb-algorithm; + snps,priority =3D <0x20>; + snps,map-to-dma-channel =3D <5>; + }; + + queue6 { + snps,dcb-algorithm; + snps,priority =3D <0x40>; + snps,map-to-dma-channel =3D <6>; + }; + + queue7 { + snps,dcb-algorithm; + snps,priority =3D <0x80>; + snps,map-to-dma-channel =3D <7>; + }; + }; + + mtl_tx_setup0: tx-queues-config { + snps,tx-queues-to-use =3D <8>; + + queue0 { + snps,dcb-algorithm; + }; + + queue1 { + snps,dcb-algorithm; + }; + + queue2 { + snps,dcb-algorithm; + }; + + queue3 { + snps,dcb-algorithm; + }; + + queue4 { + snps,dcb-algorithm; + }; + + queue5 { + snps,dcb-algorithm; + }; + + queue6 { + snps,dcb-algorithm; + }; + + queue7 { + snps,dcb-algorithm; + }; + }; + }; + + gmac1: ethernet@92000000 { + compatible =3D "renesas,r9a09g087-gbeth", "renesas,r9a09g077-gbeth", + "snps,dwmac-5.20"; + reg =3D <0 0x92000000 0 0x10000>; + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names =3D "macirq", "eth_wake_irq", "eth_lpi", + "rx-queue-0", "rx-queue-1", "rx-queue-2", + "rx-queue-3", "rx-queue-4", "rx-queue-5", + "rx-queue-6", "rx-queue-7", "tx-queue-0", + "tx-queue-1", "tx-queue-2", "tx-queue-3", + "tx-queue-4", "tx-queue-5", "tx-queue-6", + "tx-queue-7"; + clocks =3D <&cpg CPG_MOD 416>, + <&cpg CPG_CORE R9A09G087_CLK_PCLKAH>, + <&cpg CPG_CORE R9A09G087_ETCLKB>; + clock-names =3D "stmmaceth", "pclk", "tx"; + resets =3D <&cpg 416>, <&cpg 417>; + reset-names =3D "stmmaceth", "ahb"; + power-domains =3D <&cpg>; + snps,multicast-filter-bins =3D <256>; + snps,perfect-filter-entries =3D <32>; + rx-fifo-depth =3D <8192>; + tx-fifo-depth =3D <8192>; + snps,fixed-burst; + snps,no-pbl-x8; + snps,force_thresh_dma_mode; + snps,axi-config =3D <&stmmac_axi_setup>; + snps,mtl-rx-config =3D <&mtl_rx_setup1>; + snps,mtl-tx-config =3D <&mtl_tx_setup1>; + snps,txpbl =3D <16>; + snps,rxpbl =3D <16>; + status =3D "disabled"; + + mdio1: mdio { + compatible =3D "snps,dwmac-mdio"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + mtl_rx_setup1: rx-queues-config { + snps,rx-queues-to-use =3D <8>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,priority =3D <0x1>; + snps,map-to-dma-channel =3D <0>; + }; + + queue1 { + snps,dcb-algorithm; + snps,priority =3D <0x2>; + snps,map-to-dma-channel =3D <1>; + }; + + queue2 { + snps,dcb-algorithm; + snps,priority =3D <0x4>; + snps,map-to-dma-channel =3D <2>; + }; + + queue3 { + snps,dcb-algorithm; + snps,priority =3D <0x8>; + snps,map-to-dma-channel =3D <3>; + }; + + queue4 { + snps,dcb-algorithm; + snps,priority =3D <0x10>; + snps,map-to-dma-channel =3D <4>; + }; + + queue5 { + snps,dcb-algorithm; + snps,priority =3D <0x20>; + snps,map-to-dma-channel =3D <5>; + }; + + queue6 { + snps,dcb-algorithm; + snps,priority =3D <0x40>; + snps,map-to-dma-channel =3D <6>; + }; + + queue7 { + snps,dcb-algorithm; + snps,priority =3D <0x80>; + snps,map-to-dma-channel =3D <7>; + }; + }; + + mtl_tx_setup1: tx-queues-config { + snps,tx-queues-to-use =3D <8>; + + queue0 { + snps,dcb-algorithm; + }; + + queue1 { + snps,dcb-algorithm; + }; + + queue2 { + snps,dcb-algorithm; + }; + + queue3 { + snps,dcb-algorithm; + }; + + queue4 { + snps,dcb-algorithm; + }; + + queue5 { + snps,dcb-algorithm; + }; + + queue6 { + snps,dcb-algorithm; + }; + + queue7 { + snps,dcb-algorithm; + }; + }; + }; + + gmac2: ethernet@92010000 { + compatible =3D "renesas,r9a09g087-gbeth", "renesas,r9a09g077-gbeth", + "snps,dwmac-5.20"; + reg =3D <0 0x92010000 0 0x10000>; + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names =3D "macirq", "eth_wake_irq", "eth_lpi", + "rx-queue-0", "rx-queue-1", "rx-queue-2", + "rx-queue-3", "rx-queue-4", "rx-queue-5", + "rx-queue-6", "rx-queue-7", "tx-queue-0", + "tx-queue-1", "tx-queue-2", "tx-queue-3", + "tx-queue-4", "tx-queue-5", "tx-queue-6", + "tx-queue-7"; + clocks =3D <&cpg CPG_MOD 417>, + <&cpg CPG_CORE R9A09G087_CLK_PCLKAH>, + <&cpg CPG_CORE R9A09G087_ETCLKB>; + clock-names =3D "stmmaceth", "pclk", "tx"; + resets =3D <&cpg 418>, <&cpg 419>; + reset-names =3D "stmmaceth", "ahb"; + power-domains =3D <&cpg>; + snps,multicast-filter-bins =3D <256>; + snps,perfect-filter-entries =3D <32>; + rx-fifo-depth =3D <8192>; + tx-fifo-depth =3D <8192>; + snps,fixed-burst; + snps,no-pbl-x8; + snps,force_thresh_dma_mode; + snps,axi-config =3D <&stmmac_axi_setup>; + snps,mtl-rx-config =3D <&mtl_rx_setup2>; + snps,mtl-tx-config =3D <&mtl_tx_setup2>; + snps,txpbl =3D <16>; + snps,rxpbl =3D <16>; + status =3D "disabled"; + + mdio2: mdio { + compatible =3D "snps,dwmac-mdio"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + mtl_rx_setup2: rx-queues-config { + snps,rx-queues-to-use =3D <8>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,priority =3D <0x1>; + snps,map-to-dma-channel =3D <0>; + }; + + queue1 { + snps,dcb-algorithm; + snps,priority =3D <0x2>; + snps,map-to-dma-channel =3D <1>; + }; + + queue2 { + snps,dcb-algorithm; + snps,priority =3D <0x4>; + snps,map-to-dma-channel =3D <2>; + }; + + queue3 { + snps,dcb-algorithm; + snps,priority =3D <0x8>; + snps,map-to-dma-channel =3D <3>; + }; + + queue4 { + snps,dcb-algorithm; + snps,priority =3D <0x10>; + snps,map-to-dma-channel =3D <4>; + }; + + queue5 { + snps,dcb-algorithm; + snps,priority =3D <0x20>; + snps,map-to-dma-channel =3D <5>; + }; + + queue6 { + snps,dcb-algorithm; + snps,priority =3D <0x40>; + snps,map-to-dma-channel =3D <6>; + }; + + queue7 { + snps,dcb-algorithm; + snps,priority =3D <0x80>; + snps,map-to-dma-channel =3D <7>; + }; + }; + + mtl_tx_setup2: tx-queues-config { + snps,tx-queues-to-use =3D <8>; + + queue0 { + snps,dcb-algorithm; + }; + + queue1 { + snps,dcb-algorithm; + }; + + queue2 { + snps,dcb-algorithm; + }; + + queue3 { + snps,dcb-algorithm; + }; + + queue4 { + snps,dcb-algorithm; + }; + + queue5 { + snps,dcb-algorithm; + }; + + queue6 { + snps,dcb-algorithm; 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([2401:4900:1c06:77f0:168f:479e:bf92:ce93]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-29498cf3410sm125713005ad.8.2025.10.28.10.55.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Oct 2025 10:55:33 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v2 5/5] arm64: dts: renesas: rzt2h-n2h-evk: Enable Ethernet support Date: Tue, 28 Oct 2025 17:54:58 +0000 Message-ID: <20251028175458.1037397-6-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251028175458.1037397-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20251028175458.1037397-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Enable Ethernet support on the RZ/T2H and RZ/N2H EVKs. Configure the MIIC converter in mode 0x6: Port 0 <-> ETHSW Port 0 Port 1 <-> ETHSW Port 1 Port 2 <-> GMAC2 Port 3 <-> GMAC1 Enable the ETHSS, GMAC1 and GMAC2 nodes. ETHSW support will be added once the switch driver is available. Configure the MIIC converters to map ports according to the selected switching mode, with converters 0 and 1 mapped to switch ports and converters 2 and 3 mapped to GMAC ports. Signed-off-by: Lad Prabhakar --- v1->v2 changes: - Dropped *skew-psec properties which are not needed for VSC8541 PHYs. --- .../dts/renesas/r9a09g077m44-rzt2h-evk.dts | 70 ++++++++++++++++ .../dts/renesas/r9a09g087m44-rzn2h-evk.dts | 79 +++++++++++++++++++ .../dts/renesas/rzt2h-n2h-evk-common.dtsi | 70 ++++++++++++++++ 3 files changed, 219 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts b/arch/= arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts index 799c58afd6fe..33cbf74933de 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts @@ -149,7 +149,77 @@ &i2c1 { status =3D "okay"; }; =20 +&phy2 { + /* + * PHY2 Reset Configuration: + * + * SW6[1] =3D OFF; SW6[2] =3D ON; SW6[3] =3D OFF; + * P17_5 is used as GMAC_RESETOUT2# + */ + reset-gpios =3D <&pinctrl RZT2H_GPIO(17, 5) GPIO_ACTIVE_LOW>; +}; + +&phy3 { + reset-gpios =3D <&pinctrl RZT2H_GPIO(32, 3) GPIO_ACTIVE_LOW>; +}; + &pinctrl { + /* + * ETH2 Pin Configuration: + * + * SW2[6] =3D OFF: MDC and MDIO of Ethernet port 2 are connected to GMAC2 + * SW2[7] =3D ON: Pins P29_1-P29_7, P30_0-P30_4, and P31_2-P31_5 are use= d for Ethernet port 2 + */ + eth2_pins: eth2-pins { + pinmux =3D , /* ETH2_TXCLK */ + , /* ETH2_TXD[0] */ + , /* ETH2_TXD[1] */ + , /* ETH2_TXD[2] */ + , /* ETH2_TXD[3] */ + , /* ETH2_TXEN */ + , /* ETH2_RXCLK */ + , /* ETH2_RXD[0] */ + , /* ETH2_RXD[1] */ + , /* ETH2_RXD[2] */ + , /* ETH2_RXD[3] */ + , /* ETH2_RXDV */ + , /* ETH2_TXER */ + , /* ETH2_RXER */ + , /* ETH2_CRS */ + , /* ETH2_COL */ + , /* ETH2_MDC */ + , /* ETH2_MDIO */ + ; /* ETH2_REFCLK */ + }; + + /* + * ETH3 Pin Configuration: + * + * SW2[8] =3D ON, P27_2, P33_2-P33_7, P34_0-P34_5, P34_7 and P35_0-P35_5 + * are used for Ethernet port 3 + */ + eth3_pins: eth3-pins { + pinmux =3D , /* ETH3_TXCLK */ + , /* ETH3_TXD[0] */ + , /* ETH3_TXD[1] */ + , /* ETH3_TXD[2] */ + , /* ETH3_TXD[3] */ + , /* ETH3_TXEN */ + , /* ETH3_RXCLK */ + , /* ETH3_RXD[0] */ + , /* ETH3_RXD[1] */ + , /* ETH3_RXD[2] */ + , /* ETH3_RXD[3] */ + , /* ETH3_RXDV */ + , /* ETH3_TXER */ + , /* ETH3_RXER */ + , /* ETH3_CRS */ + , /* ETH3_COL */ + , /* ETH3_MDC */ + , /* ETH3_MDIO */ + ; /* ETH3_REFCLK */ + }; + /* * I2C0 Pin Configuration: * ------------------------ diff --git a/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts b/arch/= arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts index d698b6368ee7..7ebc89bafaf1 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts @@ -186,7 +186,86 @@ &i2c1 { status =3D "okay"; }; =20 +&phy2 { + /* + * PHY2 Reset Configuration: + * + * DSW8[1] =3D ON; DSW8[2] =3D OFF + * DSW12[7] =3D OFF; DSW12[8] =3D ON + * P03_1 is used as GMAC_RESETOUT2# + */ + reset-gpios =3D <&pinctrl RZT2H_GPIO(3, 1) GPIO_ACTIVE_LOW>; +}; + +&phy3 { + /* + * PHY3 Reset Configuration: + * + * DSW12[5] =3D OFF; DSW12[6] =3D ON + * P03_2 is used as GMAC_RESETOUT3# + */ + reset-gpios =3D <&pinctrl RZT2H_GPIO(3, 2) GPIO_ACTIVE_LOW>; +}; + &pinctrl { + /* + * ETH2 Pin Configuration: + * + * DSW5[6] =3D OFF, P21_4-P21_5 are used for Ethernet port 2 + * DSW5[7] =3D ON, P29_1-P29_7, P30_0-P30_4, P30_7, P31_2, P31_4 + * and P31_5 are used for Ethernet port 2 + */ + eth2_pins: eth2-pins { + pinmux =3D , /* ETH2_TXCLK */ + , /* ETH2_TXD[0] */ + , /* ETH2_TXD[1] */ + , /* ETH2_TXD[2] */ + , /* ETH2_TXD[3] */ + , /* ETH2_TXEN */ + , /* ETH2_RXCLK */ + , /* ETH2_RXD[0] */ + , /* ETH2_RXD[1] */ + , /* ETH2_RXD[2] */ + , /* ETH2_RXD[3] */ + , /* ETH2_RXDV */ + , /* ETH2_TXER */ + , /* ETH2_RXER */ + , /* ETH2_CRS */ + , /* ETH2_COL */ + , /* ETH2_MDC */ + , /* ETH2_MDIO */ + ; /* ETH2_REFCLK */ + + }; + + /* + * ETH3 Pin Configuration: + * + * DSW5[8] =3D ON, P00_0-P00_2, P33_2-P33_7, P34_0-P34_6, are used for Et= hernet port 3 + * DSW12[1] =3D OFF;DSW12[2] =3D ON, P00_3 is used for Ethernet port 3 + */ + eth3_pins: eth3-pins { + pinmux =3D , /* ETH3_TXCLK */ + , /* ETH3_TXD[0] */ + , /* ETH3_TXD[1] */ + , /* ETH3_TXD[2] */ + , /* ETH3_TXD[3] */ + , /* ETH3_TXEN */ + , /* ETH3_RXCLK */ + , /* ETH3_RXD[0] */ + , /* ETH3_RXD[1] */ + , /* ETH3_RXD[2] */ + , /* ETH3_RXD[3] */ + , /* ETH3_RXDV */ + , /* ETH3_TXER */ + , /* ETH3_RXER */ + , /* ETH3_CRS */ + , /* ETH3_COL */ + , /* ETH3_MDC */ + , /* ETH3_MDIO */ + ; /* ETH3_REFCLK */ + }; + /* * I2C0 Pin Configuration: * ------------------------ diff --git a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi b/arch/a= rm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi index 924a38c6cb0f..c608d97586ff 100644 --- a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi +++ b/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi @@ -7,10 +7,14 @@ =20 #include #include +#include +#include #include =20 / { aliases { + ethernet0 =3D &gmac1; + ethernet1 =3D &gmac2; i2c0 =3D &i2c0; i2c1 =3D &i2c1; mmc0 =3D &sdhi0; @@ -70,10 +74,34 @@ &ehci { status =3D "okay"; }; =20 +ðss { + status =3D "okay"; + + renesas,miic-switch-portin =3D ; +}; + &extal_clk { clock-frequency =3D <25000000>; }; =20 +&gmac1 { + pinctrl-0 =3D <ð3_pins>; + pinctrl-names =3D "default"; + phy-handle =3D <&phy3>; + phy-mode =3D "rgmii-id"; + pcs-handle =3D <&mii_conv3>; + status =3D "okay"; +}; + +&gmac2 { + pinctrl-0 =3D <ð2_pins>; + pinctrl-names =3D "default"; + phy-handle =3D <&phy2>; + phy-mode =3D "rgmii-id"; + pcs-handle =3D <&mii_conv2>; + status =3D "okay"; +}; + &hsusb { dr_mode =3D "otg"; status =3D "okay"; @@ -87,6 +115,48 @@ eeprom: eeprom@50 { }; }; =20 +&mdio1 { + phy3: ethernet-phy@3 { + compatible =3D "ethernet-phy-id0007.0772", "ethernet-phy-ieee802.3-c22"; + reg =3D <3>; + vsc8531,led-0-mode =3D ; + vsc8531,led-1-mode =3D ; + reset-assert-us =3D <2000>; + reset-deassert-us =3D <15000>; + }; +}; + +&mdio2 { + phy2: ethernet-phy@2 { + compatible =3D "ethernet-phy-id0007.0772", "ethernet-phy-ieee802.3-c22"; + reg =3D <2>; + vsc8531,led-0-mode =3D ; + vsc8531,led-1-mode =3D ; + reset-assert-us =3D <2000>; + reset-deassert-us =3D <15000>; + }; +}; + +&mii_conv0 { + renesas,miic-input =3D ; + status =3D "okay"; +}; + +&mii_conv1 { + renesas,miic-input =3D ; + status =3D "okay"; +}; + +&mii_conv2 { + renesas,miic-input =3D ; + status =3D "okay"; +}; + +&mii_conv3 { + renesas,miic-input =3D ; + status =3D "okay"; +}; + &ohci { dr_mode =3D "otg"; status =3D "okay"; --=20 2.43.0