From nobody Mon Feb 9 08:28:08 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 934B234575E; Tue, 28 Oct 2025 17:36:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761672995; cv=none; b=Up/kFdHq9XTcSTXfq1tS6orXB59TJSAHMbBHKNK+qvzdle9R6kyGcVCIaRbVOrRUDbOSTAYGKSNabv2i63GWxYXfLXRQ0iklEQNueQkkUAjI1NqH+xpxfMWBLjmW1zDtg81RDoEHxpadB5yja1RDmxa6FUO2marrlw0Cya9zyYw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761672995; c=relaxed/simple; bh=0f8W0WS6inYfd0WkJ0SCn94YCCu0EJVcm13WAGscUSY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=tGa+U89vKy6owy+O6ZxPl1Pp++zJamRwUgFgdnmCZunSaVL4VlABz/80z/d4zJ+T+zPLf4NDspKPXaOzulks2IGAAO88vfW8biT8jOVoKL1WOn9uae5TIvZrKZmpIYO7XMi6czBoxKAJFL6sv5EvTUsInANGysG51VkyfaD7slA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Y/2T3wYs; arc=none smtp.client-ip=192.198.163.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Y/2T3wYs" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1761672994; x=1793208994; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=0f8W0WS6inYfd0WkJ0SCn94YCCu0EJVcm13WAGscUSY=; b=Y/2T3wYsHMLQKjDaGa4teDMkj4eWICCNiN6Hny9h3rKBSpdxQf3PYWbJ mj0j6401BgyyIxbm2Qq3EVVYf4XPpMquxdjxME2sMQX58hFI0hOyF9psV P8kDWLC6XUVTfltwkE3nFh+0E2xg3zB4xSjU5nnIvx+Dw1YGtfBSA6Tr0 Ssx4eWK/SallzqN4LAxWWNJdS5IsNGv7aCwsJGkJAfOL+Gvrl1SOPSwAs NEkgI2igvxYmyukLnnRfhcsB93jj5b1f06rukjPC8z///uxWigylRS/fA TCYRV/t/b+ioR835Ho8hISGXLgezF7QUH54oYkU2bf5SnfFDlfnyBuEc5 w==; X-CSE-ConnectionGUID: R4ldLjvFTPCOBZDOUB9oWQ== X-CSE-MsgGUID: Xh6pTJw4TJCRKE8O4JC+NA== X-IronPort-AV: E=McAfee;i="6800,10657,11586"; a="62987773" X-IronPort-AV: E=Sophos;i="6.19,261,1754982000"; d="scan'208";a="62987773" Received: from orviesa004.jf.intel.com ([10.64.159.144]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Oct 2025 10:36:33 -0700 X-CSE-ConnectionGUID: fPiIVu8uQjeY/dUHTMbs1A== X-CSE-MsgGUID: hGQY3DAKR4OnG7nLFGuSzQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.19,261,1754982000"; d="scan'208";a="189730127" Received: from ijarvine-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.244.182]) by orviesa004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Oct 2025 10:36:26 -0700 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= To: =?UTF-8?q?Alex=20Benn=C3=A9e?= , Simon Richter , Lucas De Marchi , Alex Deucher , amd-gfx@lists.freedesktop.org, Bjorn Helgaas , David Airlie , dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, Jani Nikula , Joonas Lahtinen , linux-pci@vger.kernel.org, Rodrigo Vivi , Simona Vetter , Tvrtko Ursulin , =?UTF-8?q?Christian=20K=C3=B6nig?= , =?UTF-8?q?Thomas=20Hellstr=C3=B6m?= , =?UTF-8?q?Micha=C5=82=20Winiarski?= , linux-kernel@vger.kernel.org Cc: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Subject: [PATCH 2/9] PCI/IOV: Adjust ->barsz[] when changing BAR size Date: Tue, 28 Oct 2025 19:35:44 +0200 Message-Id: <20251028173551.22578-3-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20251028173551.22578-1-ilpo.jarvinen@linux.intel.com> References: <20251028173551.22578-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable pci_rebar_set_size() adjusts BAR size for both normal and IOV BARs. The struct pci_srvio keeps a cached copy of BAR size in unit of resource_size_t in ->barsz[] which is not adjusted by pci_rebar_set_size() but by pci_iov_resource_set_size(). pci_iov_resource_set_size() is called also from pci_resize_resource_set_size(). The current arrangement is problematic once BAR resize algorithm starts to roll back changes properly in case of a failure. The normal resource fitting algorithm rolls back resource size using the struct pci_dev_resource easily but having to call also pci_resize_resource_set_size() or pci_iov_resource_set_size() to roll back BAR size would be an extra burden, whereas combining ->barsz[] update with pci_rebar_set_size() naturally rolls back it when restoring the old BAR size on a different layer of the BAR resize operation. Thus, rework pci_rebar_set_size() to also update ->barsz[]. Signed-off-by: Ilpo J=C3=A4rvinen --- drivers/pci/iov.c | 15 ++++----------- drivers/pci/pci.c | 4 ++++ drivers/pci/pci.h | 5 ++--- drivers/pci/setup-res.c | 10 ++++------ 4 files changed, 14 insertions(+), 20 deletions(-) diff --git a/drivers/pci/iov.c b/drivers/pci/iov.c index 77dee43b7858..04b675e90963 100644 --- a/drivers/pci/iov.c +++ b/drivers/pci/iov.c @@ -158,8 +158,7 @@ resource_size_t pci_iov_resource_size(struct pci_dev *d= ev, int resno) return dev->sriov->barsz[pci_resource_num_to_vf_bar(resno)]; } =20 -void pci_iov_resource_set_size(struct pci_dev *dev, int resno, - resource_size_t size) +void pci_iov_resource_set_size(struct pci_dev *dev, int resno, int size) { if (!pci_resource_is_iov(resno)) { pci_warn(dev, "%s is not an IOV resource\n", @@ -167,7 +166,8 @@ void pci_iov_resource_set_size(struct pci_dev *dev, int= resno, return; } =20 - dev->sriov->barsz[pci_resource_num_to_vf_bar(resno)] =3D size; + resno =3D pci_resource_num_to_vf_bar(resno); + dev->sriov->barsz[resno] =3D pci_rebar_size_to_bytes(size); } =20 bool pci_iov_is_memory_decoding_enabled(struct pci_dev *dev) @@ -1340,7 +1340,6 @@ EXPORT_SYMBOL_GPL(pci_sriov_configure_simple); int pci_iov_vf_bar_set_size(struct pci_dev *dev, int resno, int size) { u32 sizes; - int ret; =20 if (!pci_resource_is_iov(resno)) return -EINVAL; @@ -1355,13 +1354,7 @@ int pci_iov_vf_bar_set_size(struct pci_dev *dev, int= resno, int size) if (!(sizes & BIT(size))) return -EINVAL; =20 - ret =3D pci_rebar_set_size(dev, resno, size); - if (ret) - return ret; - - pci_iov_resource_set_size(dev, resno, pci_rebar_size_to_bytes(size)); - - return 0; + return pci_rebar_set_size(dev, resno, size); } EXPORT_SYMBOL_GPL(pci_iov_vf_bar_set_size); =20 diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index b14dd064006c..7dfc58b0e55e 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -3803,6 +3803,10 @@ int pci_rebar_set_size(struct pci_dev *pdev, int bar= , int size) ctrl &=3D ~PCI_REBAR_CTRL_BAR_SIZE; ctrl |=3D FIELD_PREP(PCI_REBAR_CTRL_BAR_SIZE, size); pci_write_config_dword(pdev, pos + PCI_REBAR_CTRL, ctrl); + + if (pci_resource_is_iov(bar)) + pci_iov_resource_set_size(pdev, bar, size); + return 0; } =20 diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 4492b809094b..bf1a577e9623 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -808,8 +808,7 @@ void pci_iov_update_resource(struct pci_dev *dev, int r= esno); resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resn= o); void pci_restore_iov_state(struct pci_dev *dev); int pci_iov_bus_range(struct pci_bus *bus); -void pci_iov_resource_set_size(struct pci_dev *dev, int resno, - resource_size_t size); +void pci_iov_resource_set_size(struct pci_dev *dev, int resno, int size); bool pci_iov_is_memory_decoding_enabled(struct pci_dev *dev); static inline u16 pci_iov_vf_rebar_cap(struct pci_dev *dev) { @@ -851,7 +850,7 @@ static inline int pci_iov_bus_range(struct pci_bus *bus) return 0; } static inline void pci_iov_resource_set_size(struct pci_dev *dev, int resn= o, - resource_size_t size) { } + int size) { } static inline bool pci_iov_is_memory_decoding_enabled(struct pci_dev *dev) { return false; diff --git a/drivers/pci/setup-res.c b/drivers/pci/setup-res.c index c3ba4ccecd43..3d0b0b3f60c4 100644 --- a/drivers/pci/setup-res.c +++ b/drivers/pci/setup-res.c @@ -450,12 +450,10 @@ static void pci_resize_resource_set_size(struct pci_d= ev *dev, int resno, resource_size_t res_size =3D pci_rebar_size_to_bytes(size); struct resource *res =3D pci_resource_n(dev, resno); =20 - if (!pci_resource_is_iov(resno)) { - resource_set_size(res, res_size); - } else { - resource_set_size(res, res_size * pci_sriov_get_totalvfs(dev)); - pci_iov_resource_set_size(dev, resno, res_size); - } + if (pci_resource_is_iov(resno)) + res_size *=3D pci_sriov_get_totalvfs(dev); + + resource_set_size(res, res_size); } =20 int pci_resize_resource(struct pci_dev *dev, int resno, int size) --=20 2.39.5